[llvm] 1ea7b9c - [DAG] matchRotateSub - set demanded bits to the shift amount type size, not the shift result size.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-07-26T17:58:51+01:00
New Revision: 1ea7b9c6ee6420dd6e87489534f44b92e1b6f220

URL: https://github.com/llvm/llvm-project/commit/1ea7b9c6ee6420dd6e87489534f44b92e1b6f220
DIFF: https://github.com/llvm/llvm-project/commit/1ea7b9c6ee6420dd6e87489534f44b92e1b6f220.diff

LOG: [DAG] matchRotateSub - set demanded bits to the shift amount type size, not the shift result size.

This should fix a report on D130251 of an assert due to a bitwidth mismatch in APInt::isSubSetOf

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 21bad736bc46..654879115ff9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7301,7 +7301,8 @@ static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize,
   unsigned MaskLoBits = 0;
   if (IsRotate && isPowerOf2_64(EltSize)) {
     unsigned Bits = Log2_64(EltSize);
-    APInt DemandedBits = APInt::getLowBitsSet(EltSize, Bits);
+    APInt DemandedBits =
+        APInt::getLowBitsSet(Neg.getScalarValueSizeInBits(), Bits);
     if (SDValue Inner =
             TLI.SimplifyMultipleUseDemandedBits(Neg, DemandedBits, DAG)) {
       Neg = Inner;
@@ -7321,7 +7322,8 @@ static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize,
   // affect Mask's demanded bits, just replace Pos with Pos'. These operations
   // are redundant for the purpose of the equality.
   if (MaskLoBits) {
-    APInt DemandedBits = APInt::getLowBitsSet(EltSize, MaskLoBits);
+    APInt DemandedBits =
+        APInt::getLowBitsSet(Pos.getScalarValueSizeInBits(), MaskLoBits);
     if (SDValue Inner =
             TLI.SimplifyMultipleUseDemandedBits(Pos, DemandedBits, DAG)) {
       Pos = Inner;