[llvm] ae16b2e - [llvm-objdump,ARM] Fix a lot more tests.

Tue Jul 26 02:22:26 PDT 2022

Author: Simon Tatham
Date: 2022-07-26T10:22:02+01:00
New Revision: ae16b2ed9871b5624fdcb4286fbd0d6ddfd88961

URL: https://github.com/llvm/llvm-project/commit/ae16b2ed9871b5624fdcb4286fbd0d6ddfd88961
DIFF: https://github.com/llvm/llvm-project/commit/ae16b2ed9871b5624fdcb4286fbd0d6ddfd88961.diff

LOG: [llvm-objdump,ARM] Fix a lot more tests.

When I changed the output format of llvm-objdump for Arm and AArch64
in D130358, I hadn't realised llvm-objdump was used so much in the
plain MC tests as well as tests of itself and lld. Sorry!

Added: 
    

Modified: 
    llvm/test/MC/AArch64/SME/addha-u32.s
    llvm/test/MC/AArch64/SME/addha-u64.s
    llvm/test/MC/AArch64/SME/addspl.s
    llvm/test/MC/AArch64/SME/addsvl.s
    llvm/test/MC/AArch64/SME/addva-u32.s
    llvm/test/MC/AArch64/SME/addva-u64.s
    llvm/test/MC/AArch64/SME/bfmopa.s
    llvm/test/MC/AArch64/SME/bfmops.s
    llvm/test/MC/AArch64/SME/fmopa-fp64.s
    llvm/test/MC/AArch64/SME/fmopa.s
    llvm/test/MC/AArch64/SME/fmops-fp64.s
    llvm/test/MC/AArch64/SME/fmops.s
    llvm/test/MC/AArch64/SME/ld1b.s
    llvm/test/MC/AArch64/SME/ld1d.s
    llvm/test/MC/AArch64/SME/ld1h.s
    llvm/test/MC/AArch64/SME/ld1q.s
    llvm/test/MC/AArch64/SME/ld1w.s
    llvm/test/MC/AArch64/SME/ldr.s
    llvm/test/MC/AArch64/SME/mova.s
    llvm/test/MC/AArch64/SME/psel.s
    llvm/test/MC/AArch64/SME/rdsvl.s
    llvm/test/MC/AArch64/SME/revd.s
    llvm/test/MC/AArch64/SME/sclamp.s
    llvm/test/MC/AArch64/SME/smopa-32.s
    llvm/test/MC/AArch64/SME/smopa-64.s
    llvm/test/MC/AArch64/SME/smops-32.s
    llvm/test/MC/AArch64/SME/smops-64.s
    llvm/test/MC/AArch64/SME/smstart.s
    llvm/test/MC/AArch64/SME/smstop.s
    llvm/test/MC/AArch64/SME/st1b.s
    llvm/test/MC/AArch64/SME/st1d.s
    llvm/test/MC/AArch64/SME/st1h.s
    llvm/test/MC/AArch64/SME/st1q.s
    llvm/test/MC/AArch64/SME/st1w.s
    llvm/test/MC/AArch64/SME/str.s
    llvm/test/MC/AArch64/SME/sumopa-32.s
    llvm/test/MC/AArch64/SME/sumopa-64.s
    llvm/test/MC/AArch64/SME/sumops-32.s
    llvm/test/MC/AArch64/SME/sumops-64.s
    llvm/test/MC/AArch64/SME/system-regs-mpam.s
    llvm/test/MC/AArch64/SME/system-regs.s
    llvm/test/MC/AArch64/SME/uclamp.s
    llvm/test/MC/AArch64/SME/umopa-32.s
    llvm/test/MC/AArch64/SME/umopa-64.s
    llvm/test/MC/AArch64/SME/umops-32.s
    llvm/test/MC/AArch64/SME/umops-64.s
    llvm/test/MC/AArch64/SME/usmopa-32.s
    llvm/test/MC/AArch64/SME/usmopa-64.s
    llvm/test/MC/AArch64/SME/usmops-32.s
    llvm/test/MC/AArch64/SME/usmops-64.s
    llvm/test/MC/AArch64/SME/zero.s
    llvm/test/MC/AArch64/SVE/abs.s
    llvm/test/MC/AArch64/SVE/add.s
    llvm/test/MC/AArch64/SVE/addpl.s
    llvm/test/MC/AArch64/SVE/addvl.s
    llvm/test/MC/AArch64/SVE/adr.s
    llvm/test/MC/AArch64/SVE/and.s
    llvm/test/MC/AArch64/SVE/ands.s
    llvm/test/MC/AArch64/SVE/andv.s
    llvm/test/MC/AArch64/SVE/asr.s
    llvm/test/MC/AArch64/SVE/asrd.s
    llvm/test/MC/AArch64/SVE/asrr.s
    llvm/test/MC/AArch64/SVE/bic.s
    llvm/test/MC/AArch64/SVE/bics.s
    llvm/test/MC/AArch64/SVE/brka.s
    llvm/test/MC/AArch64/SVE/brkas.s
    llvm/test/MC/AArch64/SVE/brkb.s
    llvm/test/MC/AArch64/SVE/brkbs.s
    llvm/test/MC/AArch64/SVE/brkn.s
    llvm/test/MC/AArch64/SVE/brkns.s
    llvm/test/MC/AArch64/SVE/brkpa.s
    llvm/test/MC/AArch64/SVE/brkpas.s
    llvm/test/MC/AArch64/SVE/brkpb.s
    llvm/test/MC/AArch64/SVE/brkpbs.s
    llvm/test/MC/AArch64/SVE/clasta.s
    llvm/test/MC/AArch64/SVE/clastb.s
    llvm/test/MC/AArch64/SVE/cls.s
    llvm/test/MC/AArch64/SVE/clz.s
    llvm/test/MC/AArch64/SVE/cmpeq.s
    llvm/test/MC/AArch64/SVE/cmpge.s
    llvm/test/MC/AArch64/SVE/cmpgt.s
    llvm/test/MC/AArch64/SVE/cmphi.s
    llvm/test/MC/AArch64/SVE/cmphs.s
    llvm/test/MC/AArch64/SVE/cmple.s
    llvm/test/MC/AArch64/SVE/cmplo.s
    llvm/test/MC/AArch64/SVE/cmpls.s
    llvm/test/MC/AArch64/SVE/cmplt.s
    llvm/test/MC/AArch64/SVE/cmpne.s
    llvm/test/MC/AArch64/SVE/cnot.s
    llvm/test/MC/AArch64/SVE/cnt.s
    llvm/test/MC/AArch64/SVE/cntb.s
    llvm/test/MC/AArch64/SVE/cntd.s
    llvm/test/MC/AArch64/SVE/cnth.s
    llvm/test/MC/AArch64/SVE/cntp.s
    llvm/test/MC/AArch64/SVE/cntw.s
    llvm/test/MC/AArch64/SVE/compact.s
    llvm/test/MC/AArch64/SVE/cpy.s
    llvm/test/MC/AArch64/SVE/ctermeq.s
    llvm/test/MC/AArch64/SVE/ctermne.s
    llvm/test/MC/AArch64/SVE/decb.s
    llvm/test/MC/AArch64/SVE/decd.s
    llvm/test/MC/AArch64/SVE/dech.s
    llvm/test/MC/AArch64/SVE/decp.s
    llvm/test/MC/AArch64/SVE/decw.s
    llvm/test/MC/AArch64/SVE/dup.s
    llvm/test/MC/AArch64/SVE/dupm.s
    llvm/test/MC/AArch64/SVE/eon.s
    llvm/test/MC/AArch64/SVE/eor.s
    llvm/test/MC/AArch64/SVE/eors.s
    llvm/test/MC/AArch64/SVE/eorv.s
    llvm/test/MC/AArch64/SVE/ext.s
    llvm/test/MC/AArch64/SVE/fabd.s
    llvm/test/MC/AArch64/SVE/fabs.s
    llvm/test/MC/AArch64/SVE/facge.s
    llvm/test/MC/AArch64/SVE/facgt.s
    llvm/test/MC/AArch64/SVE/facle.s
    llvm/test/MC/AArch64/SVE/faclt.s
    llvm/test/MC/AArch64/SVE/fadd.s
    llvm/test/MC/AArch64/SVE/fadda.s
    llvm/test/MC/AArch64/SVE/faddv.s
    llvm/test/MC/AArch64/SVE/fcadd.s
    llvm/test/MC/AArch64/SVE/fcmeq.s
    llvm/test/MC/AArch64/SVE/fcmge.s
    llvm/test/MC/AArch64/SVE/fcmgt.s
    llvm/test/MC/AArch64/SVE/fcmla.s
    llvm/test/MC/AArch64/SVE/fcmle.s
    llvm/test/MC/AArch64/SVE/fcmlt.s
    llvm/test/MC/AArch64/SVE/fcmne.s
    llvm/test/MC/AArch64/SVE/fcmuo.s
    llvm/test/MC/AArch64/SVE/fcpy.s
    llvm/test/MC/AArch64/SVE/fcvt.s
    llvm/test/MC/AArch64/SVE/fcvtzs.s
    llvm/test/MC/AArch64/SVE/fcvtzu.s
    llvm/test/MC/AArch64/SVE/fdiv.s
    llvm/test/MC/AArch64/SVE/fdivr.s
    llvm/test/MC/AArch64/SVE/fdup.s
    llvm/test/MC/AArch64/SVE/fexpa.s
    llvm/test/MC/AArch64/SVE/fmad.s
    llvm/test/MC/AArch64/SVE/fmax.s
    llvm/test/MC/AArch64/SVE/fmaxnm.s
    llvm/test/MC/AArch64/SVE/fmaxnmv.s
    llvm/test/MC/AArch64/SVE/fmaxv.s
    llvm/test/MC/AArch64/SVE/fmin.s
    llvm/test/MC/AArch64/SVE/fminnm.s
    llvm/test/MC/AArch64/SVE/fminnmv.s
    llvm/test/MC/AArch64/SVE/fminv.s
    llvm/test/MC/AArch64/SVE/fmla.s
    llvm/test/MC/AArch64/SVE/fmls.s
    llvm/test/MC/AArch64/SVE/fmov.s
    llvm/test/MC/AArch64/SVE/fmsb.s
    llvm/test/MC/AArch64/SVE/fmul.s
    llvm/test/MC/AArch64/SVE/fmulx.s
    llvm/test/MC/AArch64/SVE/fneg.s
    llvm/test/MC/AArch64/SVE/fnmad.s
    llvm/test/MC/AArch64/SVE/fnmla.s
    llvm/test/MC/AArch64/SVE/fnmls.s
    llvm/test/MC/AArch64/SVE/fnmsb.s
    llvm/test/MC/AArch64/SVE/frecpe.s
    llvm/test/MC/AArch64/SVE/frecps.s
    llvm/test/MC/AArch64/SVE/frecpx.s
    llvm/test/MC/AArch64/SVE/frinta.s
    llvm/test/MC/AArch64/SVE/frinti.s
    llvm/test/MC/AArch64/SVE/frintm.s
    llvm/test/MC/AArch64/SVE/frintn.s
    llvm/test/MC/AArch64/SVE/frintp.s
    llvm/test/MC/AArch64/SVE/frintx.s
    llvm/test/MC/AArch64/SVE/frintz.s
    llvm/test/MC/AArch64/SVE/frsqrte.s
    llvm/test/MC/AArch64/SVE/frsqrts.s
    llvm/test/MC/AArch64/SVE/fscale.s
    llvm/test/MC/AArch64/SVE/fsqrt.s
    llvm/test/MC/AArch64/SVE/fsub.s
    llvm/test/MC/AArch64/SVE/fsubr.s
    llvm/test/MC/AArch64/SVE/ftmad.s
    llvm/test/MC/AArch64/SVE/ftsmul.s
    llvm/test/MC/AArch64/SVE/ftssel.s
    llvm/test/MC/AArch64/SVE/incb.s
    llvm/test/MC/AArch64/SVE/incd.s
    llvm/test/MC/AArch64/SVE/inch.s
    llvm/test/MC/AArch64/SVE/incp.s
    llvm/test/MC/AArch64/SVE/incw.s
    llvm/test/MC/AArch64/SVE/index.s
    llvm/test/MC/AArch64/SVE/insr.s
    llvm/test/MC/AArch64/SVE/lasta.s
    llvm/test/MC/AArch64/SVE/lastb.s
    llvm/test/MC/AArch64/SVE/ld1b-sve-only.s
    llvm/test/MC/AArch64/SVE/ld1b.s
    llvm/test/MC/AArch64/SVE/ld1d-sve-only.s
    llvm/test/MC/AArch64/SVE/ld1d.s
    llvm/test/MC/AArch64/SVE/ld1h-sve-only.s
    llvm/test/MC/AArch64/SVE/ld1h.s
    llvm/test/MC/AArch64/SVE/ld1rb.s
    llvm/test/MC/AArch64/SVE/ld1rd.s
    llvm/test/MC/AArch64/SVE/ld1rh.s
    llvm/test/MC/AArch64/SVE/ld1rqb.s
    llvm/test/MC/AArch64/SVE/ld1rqd.s
    llvm/test/MC/AArch64/SVE/ld1rqh.s
    llvm/test/MC/AArch64/SVE/ld1rqw.s
    llvm/test/MC/AArch64/SVE/ld1rsb.s
    llvm/test/MC/AArch64/SVE/ld1rsh.s
    llvm/test/MC/AArch64/SVE/ld1rsw.s
    llvm/test/MC/AArch64/SVE/ld1rw.s
    llvm/test/MC/AArch64/SVE/ld1sb-sve-only.s
    llvm/test/MC/AArch64/SVE/ld1sb.s
    llvm/test/MC/AArch64/SVE/ld1sh-sve-only.s
    llvm/test/MC/AArch64/SVE/ld1sh.s
    llvm/test/MC/AArch64/SVE/ld1sw-sve-only.s
    llvm/test/MC/AArch64/SVE/ld1sw.s
    llvm/test/MC/AArch64/SVE/ld1w-sve-only.s
    llvm/test/MC/AArch64/SVE/ld1w.s
    llvm/test/MC/AArch64/SVE/ld2b.s
    llvm/test/MC/AArch64/SVE/ld2d.s
    llvm/test/MC/AArch64/SVE/ld2h.s
    llvm/test/MC/AArch64/SVE/ld2w.s
    llvm/test/MC/AArch64/SVE/ld3b.s
    llvm/test/MC/AArch64/SVE/ld3d.s
    llvm/test/MC/AArch64/SVE/ld3h.s
    llvm/test/MC/AArch64/SVE/ld3w.s
    llvm/test/MC/AArch64/SVE/ld4b.s
    llvm/test/MC/AArch64/SVE/ld4d.s
    llvm/test/MC/AArch64/SVE/ld4h.s
    llvm/test/MC/AArch64/SVE/ld4w.s
    llvm/test/MC/AArch64/SVE/ldff1b.s
    llvm/test/MC/AArch64/SVE/ldff1d.s
    llvm/test/MC/AArch64/SVE/ldff1h.s
    llvm/test/MC/AArch64/SVE/ldff1sb.s
    llvm/test/MC/AArch64/SVE/ldff1sh.s
    llvm/test/MC/AArch64/SVE/ldff1sw.s
    llvm/test/MC/AArch64/SVE/ldff1w.s
    llvm/test/MC/AArch64/SVE/ldnf1b.s
    llvm/test/MC/AArch64/SVE/ldnf1d.s
    llvm/test/MC/AArch64/SVE/ldnf1h.s
    llvm/test/MC/AArch64/SVE/ldnf1sb.s
    llvm/test/MC/AArch64/SVE/ldnf1sh.s
    llvm/test/MC/AArch64/SVE/ldnf1sw.s
    llvm/test/MC/AArch64/SVE/ldnf1w.s
    llvm/test/MC/AArch64/SVE/ldnt1b.s
    llvm/test/MC/AArch64/SVE/ldnt1d.s
    llvm/test/MC/AArch64/SVE/ldnt1h.s
    llvm/test/MC/AArch64/SVE/ldnt1w.s
    llvm/test/MC/AArch64/SVE/ldr.s
    llvm/test/MC/AArch64/SVE/lsl.s
    llvm/test/MC/AArch64/SVE/lslr.s
    llvm/test/MC/AArch64/SVE/lsr.s
    llvm/test/MC/AArch64/SVE/lsrr.s
    llvm/test/MC/AArch64/SVE/mad.s
    llvm/test/MC/AArch64/SVE/matrix-multiply-fp32.s
    llvm/test/MC/AArch64/SVE/matrix-multiply-fp64.s
    llvm/test/MC/AArch64/SVE/matrix-multiply-int8.s
    llvm/test/MC/AArch64/SVE/mla.s
    llvm/test/MC/AArch64/SVE/mls.s
    llvm/test/MC/AArch64/SVE/mov.s
    llvm/test/MC/AArch64/SVE/movprfx.s
    llvm/test/MC/AArch64/SVE/movs.s
    llvm/test/MC/AArch64/SVE/msb.s
    llvm/test/MC/AArch64/SVE/mul.s
    llvm/test/MC/AArch64/SVE/nand.s
    llvm/test/MC/AArch64/SVE/nands.s
    llvm/test/MC/AArch64/SVE/neg.s
    llvm/test/MC/AArch64/SVE/nor.s
    llvm/test/MC/AArch64/SVE/nors.s
    llvm/test/MC/AArch64/SVE/not.s
    llvm/test/MC/AArch64/SVE/nots.s
    llvm/test/MC/AArch64/SVE/orn.s
    llvm/test/MC/AArch64/SVE/orns.s
    llvm/test/MC/AArch64/SVE/orr.s
    llvm/test/MC/AArch64/SVE/orrs.s
    llvm/test/MC/AArch64/SVE/orv.s
    llvm/test/MC/AArch64/SVE/pfalse.s
    llvm/test/MC/AArch64/SVE/pfirst.s
    llvm/test/MC/AArch64/SVE/pnext.s
    llvm/test/MC/AArch64/SVE/prfb-sve-only.s
    llvm/test/MC/AArch64/SVE/prfb.s
    llvm/test/MC/AArch64/SVE/prfd-sve-only.s
    llvm/test/MC/AArch64/SVE/prfd.s
    llvm/test/MC/AArch64/SVE/prfh-sve-only.s
    llvm/test/MC/AArch64/SVE/prfh.s
    llvm/test/MC/AArch64/SVE/prfw-sve-only.s
    llvm/test/MC/AArch64/SVE/prfw.s
    llvm/test/MC/AArch64/SVE/ptest.s
    llvm/test/MC/AArch64/SVE/ptrue.s
    llvm/test/MC/AArch64/SVE/ptrues.s
    llvm/test/MC/AArch64/SVE/punpkhi.s
    llvm/test/MC/AArch64/SVE/punpklo.s
    llvm/test/MC/AArch64/SVE/rbit.s
    llvm/test/MC/AArch64/SVE/rdffr.s
    llvm/test/MC/AArch64/SVE/rdffrs.s
    llvm/test/MC/AArch64/SVE/rdvl.s
    llvm/test/MC/AArch64/SVE/rev.s
    llvm/test/MC/AArch64/SVE/revb.s
    llvm/test/MC/AArch64/SVE/revh.s
    llvm/test/MC/AArch64/SVE/revw.s
    llvm/test/MC/AArch64/SVE/sabd.s
    llvm/test/MC/AArch64/SVE/saddv.s
    llvm/test/MC/AArch64/SVE/scvtf.s
    llvm/test/MC/AArch64/SVE/sdiv.s
    llvm/test/MC/AArch64/SVE/sdivr.s
    llvm/test/MC/AArch64/SVE/sdot.s
    llvm/test/MC/AArch64/SVE/sel.s
    llvm/test/MC/AArch64/SVE/setffr.s
    llvm/test/MC/AArch64/SVE/smax.s
    llvm/test/MC/AArch64/SVE/smaxv.s
    llvm/test/MC/AArch64/SVE/smin.s
    llvm/test/MC/AArch64/SVE/sminv.s
    llvm/test/MC/AArch64/SVE/smulh.s
    llvm/test/MC/AArch64/SVE/splice.s
    llvm/test/MC/AArch64/SVE/sqadd.s
    llvm/test/MC/AArch64/SVE/sqdecb.s
    llvm/test/MC/AArch64/SVE/sqdecd.s
    llvm/test/MC/AArch64/SVE/sqdech.s
    llvm/test/MC/AArch64/SVE/sqdecp.s
    llvm/test/MC/AArch64/SVE/sqdecw.s
    llvm/test/MC/AArch64/SVE/sqincb.s
    llvm/test/MC/AArch64/SVE/sqincd.s
    llvm/test/MC/AArch64/SVE/sqinch.s
    llvm/test/MC/AArch64/SVE/sqincp.s
    llvm/test/MC/AArch64/SVE/sqincw.s
    llvm/test/MC/AArch64/SVE/sqsub.s
    llvm/test/MC/AArch64/SVE/st1b-sve-only.s
    llvm/test/MC/AArch64/SVE/st1b.s
    llvm/test/MC/AArch64/SVE/st1d-sve-only.s
    llvm/test/MC/AArch64/SVE/st1d.s
    llvm/test/MC/AArch64/SVE/st1h-sve-only.s
    llvm/test/MC/AArch64/SVE/st1h.s
    llvm/test/MC/AArch64/SVE/st1w-sve-only.s
    llvm/test/MC/AArch64/SVE/st1w.s
    llvm/test/MC/AArch64/SVE/st2b.s
    llvm/test/MC/AArch64/SVE/st2d.s
    llvm/test/MC/AArch64/SVE/st2h.s
    llvm/test/MC/AArch64/SVE/st2w.s
    llvm/test/MC/AArch64/SVE/st3b.s
    llvm/test/MC/AArch64/SVE/st3d.s
    llvm/test/MC/AArch64/SVE/st3h.s
    llvm/test/MC/AArch64/SVE/st3w.s
    llvm/test/MC/AArch64/SVE/st4b.s
    llvm/test/MC/AArch64/SVE/st4d.s
    llvm/test/MC/AArch64/SVE/st4h.s
    llvm/test/MC/AArch64/SVE/st4w.s
    llvm/test/MC/AArch64/SVE/stnt1b.s
    llvm/test/MC/AArch64/SVE/stnt1d.s
    llvm/test/MC/AArch64/SVE/stnt1h.s
    llvm/test/MC/AArch64/SVE/stnt1w.s
    llvm/test/MC/AArch64/SVE/str.s
    llvm/test/MC/AArch64/SVE/sub.s
    llvm/test/MC/AArch64/SVE/subr.s
    llvm/test/MC/AArch64/SVE/sunpkhi.s
    llvm/test/MC/AArch64/SVE/sunpklo.s
    llvm/test/MC/AArch64/SVE/sxtb.s
    llvm/test/MC/AArch64/SVE/sxth.s
    llvm/test/MC/AArch64/SVE/sxtw.s
    llvm/test/MC/AArch64/SVE/system-regs.s
    llvm/test/MC/AArch64/SVE/tbl.s
    llvm/test/MC/AArch64/SVE/trn1.s
    llvm/test/MC/AArch64/SVE/trn2.s
    llvm/test/MC/AArch64/SVE/uabd.s
    llvm/test/MC/AArch64/SVE/uaddv.s
    llvm/test/MC/AArch64/SVE/ucvtf.s
    llvm/test/MC/AArch64/SVE/udiv.s
    llvm/test/MC/AArch64/SVE/udivr.s
    llvm/test/MC/AArch64/SVE/udot.s
    llvm/test/MC/AArch64/SVE/umax.s
    llvm/test/MC/AArch64/SVE/umaxv.s
    llvm/test/MC/AArch64/SVE/umin.s
    llvm/test/MC/AArch64/SVE/uminv.s
    llvm/test/MC/AArch64/SVE/umulh.s
    llvm/test/MC/AArch64/SVE/uqadd.s
    llvm/test/MC/AArch64/SVE/uqdecb.s
    llvm/test/MC/AArch64/SVE/uqdecd.s
    llvm/test/MC/AArch64/SVE/uqdech.s
    llvm/test/MC/AArch64/SVE/uqdecp.s
    llvm/test/MC/AArch64/SVE/uqdecw.s
    llvm/test/MC/AArch64/SVE/uqincb.s
    llvm/test/MC/AArch64/SVE/uqincd.s
    llvm/test/MC/AArch64/SVE/uqinch.s
    llvm/test/MC/AArch64/SVE/uqincp.s
    llvm/test/MC/AArch64/SVE/uqincw.s
    llvm/test/MC/AArch64/SVE/uqsub.s
    llvm/test/MC/AArch64/SVE/uunpkhi.s
    llvm/test/MC/AArch64/SVE/uunpklo.s
    llvm/test/MC/AArch64/SVE/uxtb.s
    llvm/test/MC/AArch64/SVE/uxth.s
    llvm/test/MC/AArch64/SVE/uxtw.s
    llvm/test/MC/AArch64/SVE/uzp1.s
    llvm/test/MC/AArch64/SVE/uzp2.s
    llvm/test/MC/AArch64/SVE/whilele.s
    llvm/test/MC/AArch64/SVE/whilelo.s
    llvm/test/MC/AArch64/SVE/whilels.s
    llvm/test/MC/AArch64/SVE/whilelt.s
    llvm/test/MC/AArch64/SVE/wrffr.s
    llvm/test/MC/AArch64/SVE/zip1.s
    llvm/test/MC/AArch64/SVE/zip2.s
    llvm/test/MC/AArch64/SVE2/adclb.s
    llvm/test/MC/AArch64/SVE2/adclt.s
    llvm/test/MC/AArch64/SVE2/addhnb.s
    llvm/test/MC/AArch64/SVE2/addhnt.s
    llvm/test/MC/AArch64/SVE2/addp.s
    llvm/test/MC/AArch64/SVE2/aesd.s
    llvm/test/MC/AArch64/SVE2/aese.s
    llvm/test/MC/AArch64/SVE2/aesimc.s
    llvm/test/MC/AArch64/SVE2/aesmc.s
    llvm/test/MC/AArch64/SVE2/bcax.s
    llvm/test/MC/AArch64/SVE2/bdep.s
    llvm/test/MC/AArch64/SVE2/bext.s
    llvm/test/MC/AArch64/SVE2/bgrp.s
    llvm/test/MC/AArch64/SVE2/bsl.s
    llvm/test/MC/AArch64/SVE2/bsl1n.s
    llvm/test/MC/AArch64/SVE2/bsl2n.s
    llvm/test/MC/AArch64/SVE2/cadd.s
    llvm/test/MC/AArch64/SVE2/cdot.s
    llvm/test/MC/AArch64/SVE2/cmla.s
    llvm/test/MC/AArch64/SVE2/eor3.s
    llvm/test/MC/AArch64/SVE2/eorbt.s
    llvm/test/MC/AArch64/SVE2/eortb.s
    llvm/test/MC/AArch64/SVE2/ext.s
    llvm/test/MC/AArch64/SVE2/faddp.s
    llvm/test/MC/AArch64/SVE2/fcvtlt.s
    llvm/test/MC/AArch64/SVE2/fcvtnt.s
    llvm/test/MC/AArch64/SVE2/fcvtx.s
    llvm/test/MC/AArch64/SVE2/fcvtxnt.s
    llvm/test/MC/AArch64/SVE2/flogb.s
    llvm/test/MC/AArch64/SVE2/fmaxnmp.s
    llvm/test/MC/AArch64/SVE2/fmaxp.s
    llvm/test/MC/AArch64/SVE2/fminnmp.s
    llvm/test/MC/AArch64/SVE2/fminp.s
    llvm/test/MC/AArch64/SVE2/fmlalb.s
    llvm/test/MC/AArch64/SVE2/fmlalt.s
    llvm/test/MC/AArch64/SVE2/fmlslb.s
    llvm/test/MC/AArch64/SVE2/fmlslt.s
    llvm/test/MC/AArch64/SVE2/histcnt.s
    llvm/test/MC/AArch64/SVE2/histseg.s
    llvm/test/MC/AArch64/SVE2/ldnt1b.s
    llvm/test/MC/AArch64/SVE2/ldnt1d.s
    llvm/test/MC/AArch64/SVE2/ldnt1h.s
    llvm/test/MC/AArch64/SVE2/ldnt1sb.s
    llvm/test/MC/AArch64/SVE2/ldnt1sh.s
    llvm/test/MC/AArch64/SVE2/ldnt1sw.s
    llvm/test/MC/AArch64/SVE2/ldnt1w.s
    llvm/test/MC/AArch64/SVE2/match.s
    llvm/test/MC/AArch64/SVE2/mla.s
    llvm/test/MC/AArch64/SVE2/mls.s
    llvm/test/MC/AArch64/SVE2/mul.s
    llvm/test/MC/AArch64/SVE2/nbsl.s
    llvm/test/MC/AArch64/SVE2/nmatch.s
    llvm/test/MC/AArch64/SVE2/pmul.s
    llvm/test/MC/AArch64/SVE2/pmullb-128.s
    llvm/test/MC/AArch64/SVE2/pmullb.s
    llvm/test/MC/AArch64/SVE2/pmullt-128.s
    llvm/test/MC/AArch64/SVE2/pmullt.s
    llvm/test/MC/AArch64/SVE2/raddhnb.s
    llvm/test/MC/AArch64/SVE2/raddhnt.s
    llvm/test/MC/AArch64/SVE2/rax1.s
    llvm/test/MC/AArch64/SVE2/rshrnb.s
    llvm/test/MC/AArch64/SVE2/rshrnt.s
    llvm/test/MC/AArch64/SVE2/rsubhnb.s
    llvm/test/MC/AArch64/SVE2/rsubhnt.s
    llvm/test/MC/AArch64/SVE2/saba.s
    llvm/test/MC/AArch64/SVE2/sabalb.s
    llvm/test/MC/AArch64/SVE2/sabalt.s
    llvm/test/MC/AArch64/SVE2/sabdlb.s
    llvm/test/MC/AArch64/SVE2/sabdlt.s
    llvm/test/MC/AArch64/SVE2/sadalp.s
    llvm/test/MC/AArch64/SVE2/saddlb.s
    llvm/test/MC/AArch64/SVE2/saddlbt.s
    llvm/test/MC/AArch64/SVE2/saddlt.s
    llvm/test/MC/AArch64/SVE2/saddwb.s
    llvm/test/MC/AArch64/SVE2/saddwt.s
    llvm/test/MC/AArch64/SVE2/sbclb.s
    llvm/test/MC/AArch64/SVE2/sbclt.s
    llvm/test/MC/AArch64/SVE2/shadd.s
    llvm/test/MC/AArch64/SVE2/shrnb.s
    llvm/test/MC/AArch64/SVE2/shrnt.s
    llvm/test/MC/AArch64/SVE2/shsub.s
    llvm/test/MC/AArch64/SVE2/shsubr.s
    llvm/test/MC/AArch64/SVE2/sli.s
    llvm/test/MC/AArch64/SVE2/sm4e.s
    llvm/test/MC/AArch64/SVE2/sm4ekey.s
    llvm/test/MC/AArch64/SVE2/smaxp.s
    llvm/test/MC/AArch64/SVE2/sminp.s
    llvm/test/MC/AArch64/SVE2/smlalb.s
    llvm/test/MC/AArch64/SVE2/smlalt.s
    llvm/test/MC/AArch64/SVE2/smlslb.s
    llvm/test/MC/AArch64/SVE2/smlslt.s
    llvm/test/MC/AArch64/SVE2/smulh.s
    llvm/test/MC/AArch64/SVE2/smullb.s
    llvm/test/MC/AArch64/SVE2/smullt.s
    llvm/test/MC/AArch64/SVE2/splice.s
    llvm/test/MC/AArch64/SVE2/sqabs.s
    llvm/test/MC/AArch64/SVE2/sqadd.s
    llvm/test/MC/AArch64/SVE2/sqcadd.s
    llvm/test/MC/AArch64/SVE2/sqdmlalb.s
    llvm/test/MC/AArch64/SVE2/sqdmlalbt.s
    llvm/test/MC/AArch64/SVE2/sqdmlalt.s
    llvm/test/MC/AArch64/SVE2/sqdmlslb.s
    llvm/test/MC/AArch64/SVE2/sqdmlslbt.s
    llvm/test/MC/AArch64/SVE2/sqdmlslt.s
    llvm/test/MC/AArch64/SVE2/sqdmulh.s
    llvm/test/MC/AArch64/SVE2/sqdmullb.s
    llvm/test/MC/AArch64/SVE2/sqdmullt.s
    llvm/test/MC/AArch64/SVE2/sqneg.s
    llvm/test/MC/AArch64/SVE2/sqrdcmlah.s
    llvm/test/MC/AArch64/SVE2/sqrdmlah.s
    llvm/test/MC/AArch64/SVE2/sqrdmlsh.s
    llvm/test/MC/AArch64/SVE2/sqrdmulh.s
    llvm/test/MC/AArch64/SVE2/sqrshl.s
    llvm/test/MC/AArch64/SVE2/sqrshlr.s
    llvm/test/MC/AArch64/SVE2/sqrshrnb.s
    llvm/test/MC/AArch64/SVE2/sqrshrnt.s
    llvm/test/MC/AArch64/SVE2/sqrshrunb.s
    llvm/test/MC/AArch64/SVE2/sqrshrunt.s
    llvm/test/MC/AArch64/SVE2/sqshl.s
    llvm/test/MC/AArch64/SVE2/sqshlr.s
    llvm/test/MC/AArch64/SVE2/sqshlu.s
    llvm/test/MC/AArch64/SVE2/sqshrnb.s
    llvm/test/MC/AArch64/SVE2/sqshrnt.s
    llvm/test/MC/AArch64/SVE2/sqshrunb.s
    llvm/test/MC/AArch64/SVE2/sqshrunt.s
    llvm/test/MC/AArch64/SVE2/sqsub.s
    llvm/test/MC/AArch64/SVE2/sqsubr.s
    llvm/test/MC/AArch64/SVE2/sqxtnb.s
    llvm/test/MC/AArch64/SVE2/sqxtnt.s
    llvm/test/MC/AArch64/SVE2/sqxtunb.s
    llvm/test/MC/AArch64/SVE2/sqxtunt.s
    llvm/test/MC/AArch64/SVE2/srhadd.s
    llvm/test/MC/AArch64/SVE2/sri.s
    llvm/test/MC/AArch64/SVE2/srshl.s
    llvm/test/MC/AArch64/SVE2/srshlr.s
    llvm/test/MC/AArch64/SVE2/srshr.s
    llvm/test/MC/AArch64/SVE2/srsra.s
    llvm/test/MC/AArch64/SVE2/sshllb.s
    llvm/test/MC/AArch64/SVE2/sshllt.s
    llvm/test/MC/AArch64/SVE2/ssra.s
    llvm/test/MC/AArch64/SVE2/ssublb.s
    llvm/test/MC/AArch64/SVE2/ssublbt.s
    llvm/test/MC/AArch64/SVE2/ssublt.s
    llvm/test/MC/AArch64/SVE2/ssubltb.s
    llvm/test/MC/AArch64/SVE2/ssubwb.s
    llvm/test/MC/AArch64/SVE2/ssubwt.s
    llvm/test/MC/AArch64/SVE2/stnt1b.s
    llvm/test/MC/AArch64/SVE2/stnt1d.s
    llvm/test/MC/AArch64/SVE2/stnt1h.s
    llvm/test/MC/AArch64/SVE2/stnt1w.s
    llvm/test/MC/AArch64/SVE2/subhnb.s
    llvm/test/MC/AArch64/SVE2/subhnt.s
    llvm/test/MC/AArch64/SVE2/suqadd.s
    llvm/test/MC/AArch64/SVE2/tbl.s
    llvm/test/MC/AArch64/SVE2/tbx.s
    llvm/test/MC/AArch64/SVE2/uaba.s
    llvm/test/MC/AArch64/SVE2/uabalb.s
    llvm/test/MC/AArch64/SVE2/uabalt.s
    llvm/test/MC/AArch64/SVE2/uabdlb.s
    llvm/test/MC/AArch64/SVE2/uabdlt.s
    llvm/test/MC/AArch64/SVE2/uadalp.s
    llvm/test/MC/AArch64/SVE2/uaddlb.s
    llvm/test/MC/AArch64/SVE2/uaddlt.s
    llvm/test/MC/AArch64/SVE2/uaddwb.s
    llvm/test/MC/AArch64/SVE2/uaddwt.s
    llvm/test/MC/AArch64/SVE2/uhadd.s
    llvm/test/MC/AArch64/SVE2/uhsub.s
    llvm/test/MC/AArch64/SVE2/uhsubr.s
    llvm/test/MC/AArch64/SVE2/umaxp.s
    llvm/test/MC/AArch64/SVE2/uminp.s
    llvm/test/MC/AArch64/SVE2/umlalb.s
    llvm/test/MC/AArch64/SVE2/umlalt.s
    llvm/test/MC/AArch64/SVE2/umlslb.s
    llvm/test/MC/AArch64/SVE2/umlslt.s
    llvm/test/MC/AArch64/SVE2/umulh.s
    llvm/test/MC/AArch64/SVE2/umullb.s
    llvm/test/MC/AArch64/SVE2/umullt.s
    llvm/test/MC/AArch64/SVE2/uqadd.s
    llvm/test/MC/AArch64/SVE2/uqrshl.s
    llvm/test/MC/AArch64/SVE2/uqrshlr.s
    llvm/test/MC/AArch64/SVE2/uqrshrnb.s
    llvm/test/MC/AArch64/SVE2/uqrshrnt.s
    llvm/test/MC/AArch64/SVE2/uqshl.s
    llvm/test/MC/AArch64/SVE2/uqshlr.s
    llvm/test/MC/AArch64/SVE2/uqshrnb.s
    llvm/test/MC/AArch64/SVE2/uqshrnt.s
    llvm/test/MC/AArch64/SVE2/uqsub.s
    llvm/test/MC/AArch64/SVE2/uqsubr.s
    llvm/test/MC/AArch64/SVE2/uqxtnb.s
    llvm/test/MC/AArch64/SVE2/uqxtnt.s
    llvm/test/MC/AArch64/SVE2/urecpe.s
    llvm/test/MC/AArch64/SVE2/urhadd.s
    llvm/test/MC/AArch64/SVE2/urshl.s
    llvm/test/MC/AArch64/SVE2/urshlr.s
    llvm/test/MC/AArch64/SVE2/urshr.s
    llvm/test/MC/AArch64/SVE2/ursqrte.s
    llvm/test/MC/AArch64/SVE2/ursra.s
    llvm/test/MC/AArch64/SVE2/ushllb.s
    llvm/test/MC/AArch64/SVE2/ushllt.s
    llvm/test/MC/AArch64/SVE2/usqadd.s
    llvm/test/MC/AArch64/SVE2/usra.s
    llvm/test/MC/AArch64/SVE2/usublb.s
    llvm/test/MC/AArch64/SVE2/usublt.s
    llvm/test/MC/AArch64/SVE2/usubwb.s
    llvm/test/MC/AArch64/SVE2/usubwt.s
    llvm/test/MC/AArch64/SVE2/whilege.s
    llvm/test/MC/AArch64/SVE2/whilegt.s
    llvm/test/MC/AArch64/SVE2/whilehi.s
    llvm/test/MC/AArch64/SVE2/whilehs.s
    llvm/test/MC/AArch64/SVE2/whilerw.s
    llvm/test/MC/AArch64/SVE2/whilewr.s
    llvm/test/MC/AArch64/SVE2/xar.s
    llvm/test/MC/AArch64/align.s
    llvm/test/MC/AArch64/coff-relocations-offset.s
    llvm/test/MC/AArch64/coff-relocations.s
    llvm/test/MC/AArch64/coff-separator.s
    llvm/test/MC/AArch64/darwin-reloc-addsubimm.s
    llvm/test/MC/AArch64/elf-reloc-addsubimm.s
    llvm/test/MC/AArch64/inst-directive-other.s
    llvm/test/MC/ARM/Windows/literals-comments.s
    llvm/test/MC/ARM/Windows/mov32t-range.s
    llvm/test/MC/ARM/align_arm_2_thumb.s
    llvm/test/MC/ARM/align_thumb_2_arm.s
    llvm/test/MC/ARM/elf-movt.s
    llvm/test/MC/ARM/inst-directive-other.s
    llvm/test/MC/ARM/thumb1-relax-bcc.s
    llvm/test/MC/ARM/thumb1-relax-br.s
    llvm/test/MC/ARM/thumb2-cbn-to-next-inst.s
    llvm/test/MC/Disassembler/AArch64/udf.txt

Removed: 
    


################################################################################
diff  --git a/llvm/test/MC/AArch64/SME/addha-u32.s b/llvm/test/MC/AArch64/SME/addha-u32.s
index 80c4eabce5c94..d999b5a473c3e 100644

--- a/llvm/test/MC/AArch64/SME/addha-u32.s
+++ b/llvm/test/MC/AArch64/SME/addha-u32.s
@@ -16,70 +16,70 @@ addha   za0.s, p0/m, p0/m, z0.s
 // CHECK-INST: addha   za0.s, p0/m, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0x00,0x90,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 90 c0 <unknown>
+// CHECK-UNKNOWN: c0900000 <unknown>
 
 addha   za1.s, p5/m, p2/m, z10.s
 // CHECK-INST: addha   za1.s, p5/m, p2/m, z10.s
 // CHECK-ENCODING: [0x41,0x55,0x90,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 41 55 90 c0 <unknown>
+// CHECK-UNKNOWN: c0905541 <unknown>
 
 addha   za3.s, p3/m, p7/m, z13.s
 // CHECK-INST: addha   za3.s, p3/m, p7/m, z13.s
 // CHECK-ENCODING: [0xa3,0xed,0x90,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a3 ed 90 c0 <unknown>
+// CHECK-UNKNOWN: c090eda3 <unknown>
 
 addha   za3.s, p7/m, p7/m, z31.s
 // CHECK-INST: addha   za3.s, p7/m, p7/m, z31.s
 // CHECK-ENCODING: [0xe3,0xff,0x90,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: e3 ff 90 c0 <unknown>
+// CHECK-UNKNOWN: c090ffe3 <unknown>
 
 addha   za1.s, p3/m, p0/m, z17.s
 // CHECK-INST: addha   za1.s, p3/m, p0/m, z17.s
 // CHECK-ENCODING: [0x21,0x0e,0x90,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 0e 90 c0 <unknown>
+// CHECK-UNKNOWN: c0900e21 <unknown>
 
 addha   za1.s, p1/m, p4/m, z1.s
 // CHECK-INST: addha   za1.s, p1/m, p4/m, z1.s
 // CHECK-ENCODING: [0x21,0x84,0x90,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 90 c0 <unknown>
+// CHECK-UNKNOWN: c0908421 <unknown>
 
 addha   za0.s, p5/m, p2/m, z19.s
 // CHECK-INST: addha   za0.s, p5/m, p2/m, z19.s
 // CHECK-ENCODING: [0x60,0x56,0x90,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 60 56 90 c0 <unknown>
+// CHECK-UNKNOWN: c0905660 <unknown>
 
 addha   za0.s, p6/m, p0/m, z12.s
 // CHECK-INST: addha   za0.s, p6/m, p0/m, z12.s
 // CHECK-ENCODING: [0x80,0x19,0x90,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 90 c0 <unknown>
+// CHECK-UNKNOWN: c0901980 <unknown>
 
 addha   za1.s, p2/m, p6/m, z1.s
 // CHECK-INST: addha   za1.s, p2/m, p6/m, z1.s
 // CHECK-ENCODING: [0x21,0xc8,0x90,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 90 c0 <unknown>
+// CHECK-UNKNOWN: c090c821 <unknown>
 
 addha   za1.s, p2/m, p0/m, z22.s
 // CHECK-INST: addha   za1.s, p2/m, p0/m, z22.s
 // CHECK-ENCODING: [0xc1,0x0a,0x90,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: c1 0a 90 c0 <unknown>
+// CHECK-UNKNOWN: c0900ac1 <unknown>
 
 addha   za2.s, p5/m, p7/m, z9.s
 // CHECK-INST: addha   za2.s, p5/m, p7/m, z9.s
 // CHECK-ENCODING: [0x22,0xf5,0x90,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 90 c0 <unknown>
+// CHECK-UNKNOWN: c090f522 <unknown>
 
 addha   za3.s, p2/m, p5/m, z12.s
 // CHECK-INST: addha   za3.s, p2/m, p5/m, z12.s
 // CHECK-ENCODING: [0x83,0xa9,0x90,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 83 a9 90 c0 <unknown>
+// CHECK-UNKNOWN: c090a983 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/addha-u64.s b/llvm/test/MC/AArch64/SME/addha-u64.s
index 1cb4c92f03efa..c5b077a5e1e2e 100644
--- a/llvm/test/MC/AArch64/SME/addha-u64.s
+++ b/llvm/test/MC/AArch64/SME/addha-u64.s
@@ -16,70 +16,70 @@ addha   za0.d, p0/m, p0/m, z0.d
 // CHECK-INST: addha   za0.d, p0/m, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0x00,0xd0,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 00 00 d0 c0 <unknown>
+// CHECK-UNKNOWN: c0d00000 <unknown>
 
 addha   za5.d, p5/m, p2/m, z10.d
 // CHECK-INST: addha   za5.d, p5/m, p2/m, z10.d
 // CHECK-ENCODING: [0x45,0x55,0xd0,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 45 55 d0 c0 <unknown>
+// CHECK-UNKNOWN: c0d05545 <unknown>
 
 addha   za7.d, p3/m, p7/m, z13.d
 // CHECK-INST: addha   za7.d, p3/m, p7/m, z13.d
 // CHECK-ENCODING: [0xa7,0xed,0xd0,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: a7 ed d0 c0 <unknown>
+// CHECK-UNKNOWN: c0d0eda7 <unknown>
 
 addha   za7.d, p7/m, p7/m, z31.d
 // CHECK-INST: addha   za7.d, p7/m, p7/m, z31.d
 // CHECK-ENCODING: [0xe7,0xff,0xd0,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: e7 ff d0 c0 <unknown>
+// CHECK-UNKNOWN: c0d0ffe7 <unknown>
 
 addha   za5.d, p3/m, p0/m, z17.d
 // CHECK-INST: addha   za5.d, p3/m, p0/m, z17.d
 // CHECK-ENCODING: [0x25,0x0e,0xd0,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 25 0e d0 c0 <unknown>
+// CHECK-UNKNOWN: c0d00e25 <unknown>
 
 addha   za1.d, p1/m, p4/m, z1.d
 // CHECK-INST: addha   za1.d, p1/m, p4/m, z1.d
 // CHECK-ENCODING: [0x21,0x84,0xd0,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 21 84 d0 c0 <unknown>
+// CHECK-UNKNOWN: c0d08421 <unknown>
 
 addha   za0.d, p5/m, p2/m, z19.d
 // CHECK-INST: addha   za0.d, p5/m, p2/m, z19.d
 // CHECK-ENCODING: [0x60,0x56,0xd0,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 60 56 d0 c0 <unknown>
+// CHECK-UNKNOWN: c0d05660 <unknown>
 
 addha   za0.d, p6/m, p0/m, z12.d
 // CHECK-INST: addha   za0.d, p6/m, p0/m, z12.d
 // CHECK-ENCODING: [0x80,0x19,0xd0,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 80 19 d0 c0 <unknown>
+// CHECK-UNKNOWN: c0d01980 <unknown>
 
 addha   za1.d, p2/m, p6/m, z1.d
 // CHECK-INST: addha   za1.d, p2/m, p6/m, z1.d
 // CHECK-ENCODING: [0x21,0xc8,0xd0,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 21 c8 d0 c0 <unknown>
+// CHECK-UNKNOWN: c0d0c821 <unknown>
 
 addha   za5.d, p2/m, p0/m, z22.d
 // CHECK-INST: addha   za5.d, p2/m, p0/m, z22.d
 // CHECK-ENCODING: [0xc5,0x0a,0xd0,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: c5 0a d0 c0 <unknown>
+// CHECK-UNKNOWN: c0d00ac5 <unknown>
 
 addha   za2.d, p5/m, p7/m, z9.d
 // CHECK-INST: addha   za2.d, p5/m, p7/m, z9.d
 // CHECK-ENCODING: [0x22,0xf5,0xd0,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 22 f5 d0 c0 <unknown>
+// CHECK-UNKNOWN: c0d0f522 <unknown>
 
 addha   za7.d, p2/m, p5/m, z12.d
 // CHECK-INST: addha   za7.d, p2/m, p5/m, z12.d
 // CHECK-ENCODING: [0x87,0xa9,0xd0,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 87 a9 d0 c0 <unknown>
+// CHECK-UNKNOWN: c0d0a987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/addspl.s b/llvm/test/MC/AArch64/SME/addspl.s
index 04f0449b45310..da5b7e6aec21d 100644
--- a/llvm/test/MC/AArch64/SME/addspl.s
+++ b/llvm/test/MC/AArch64/SME/addspl.s
@@ -11,22 +11,22 @@ addspl   x21, x21, #0
 // CHECK-INST: addspl   x21, x21, #0
 // CHECK-ENCODING: [0x15,0x58,0x75,0x04]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 15 58 75 04 <unknown>
+// CHECK-UNKNOWN: 04755815 <unknown>
 
 addspl   x23, x8, #-1
 // CHECK-INST: addspl   x23, x8, #-1
 // CHECK-ENCODING: [0xf7,0x5f,0x68,0x04]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: f7 5f 68 04 <unknown>
+// CHECK-UNKNOWN: 04685ff7 <unknown>
 
 addspl   sp, sp, #31
 // CHECK-INST: addspl   sp, sp, #31
 // CHECK-ENCODING: [0xff,0x5b,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 5b 7f 04 <unknown>
+// CHECK-UNKNOWN: 047f5bff <unknown>
 
 addspl   x0, x0, #-32
 // CHECK-INST: addspl   x0, x0, #-32
 // CHECK-ENCODING: [0x00,0x5c,0x60,0x04]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 5c 60 04 <unknown>
+// CHECK-UNKNOWN: 04605c00 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/addsvl.s b/llvm/test/MC/AArch64/SME/addsvl.s
index c24c02b7deb39..efa646ff35955 100644
--- a/llvm/test/MC/AArch64/SME/addsvl.s
+++ b/llvm/test/MC/AArch64/SME/addsvl.s
@@ -11,22 +11,22 @@ addsvl   x21, x21, #0
 // CHECK-INST: addsvl   x21, x21, #0
 // CHECK-ENCODING: [0x15,0x58,0x35,0x04]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 15 58 35 04 <unknown>
+// CHECK-UNKNOWN: 04355815 <unknown>
 
 addsvl   x23, x8, #-1
 // CHECK-INST: addsvl   x23, x8, #-1
 // CHECK-ENCODING: [0xf7,0x5f,0x28,0x04]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: f7 5f 28 04 <unknown>
+// CHECK-UNKNOWN: 04285ff7 <unknown>
 
 addsvl   sp, sp, #31
 // CHECK-INST: addsvl   sp, sp, #31
 // CHECK-ENCODING: [0xff,0x5b,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 5b 3f 04 <unknown>
+// CHECK-UNKNOWN: 043f5bff <unknown>
 
 addsvl   x0, x0, #-32
 // CHECK-INST: addsvl   x0, x0, #-32
 // CHECK-ENCODING: [0x00,0x5c,0x20,0x04]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 5c 20 04 <unknown>
+// CHECK-UNKNOWN: 04205c00 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/addva-u32.s b/llvm/test/MC/AArch64/SME/addva-u32.s
index 98d706fb05293..18326659ecc04 100644
--- a/llvm/test/MC/AArch64/SME/addva-u32.s
+++ b/llvm/test/MC/AArch64/SME/addva-u32.s
@@ -16,70 +16,70 @@ addva   za0.s, p0/m, p0/m, z0.s
 // CHECK-INST: addva   za0.s, p0/m, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0x00,0x91,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 91 c0 <unknown>
+// CHECK-UNKNOWN: c0910000 <unknown>
 
 addva   za1.s, p5/m, p2/m, z10.s
 // CHECK-INST: addva   za1.s, p5/m, p2/m, z10.s
 // CHECK-ENCODING: [0x41,0x55,0x91,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 41 55 91 c0 <unknown>
+// CHECK-UNKNOWN: c0915541 <unknown>
 
 addva   za3.s, p3/m, p7/m, z13.s
 // CHECK-INST: addva   za3.s, p3/m, p7/m, z13.s
 // CHECK-ENCODING: [0xa3,0xed,0x91,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a3 ed 91 c0 <unknown>
+// CHECK-UNKNOWN: c091eda3 <unknown>
 
 addva   za3.s, p7/m, p7/m, z31.s
 // CHECK-INST: addva   za3.s, p7/m, p7/m, z31.s
 // CHECK-ENCODING: [0xe3,0xff,0x91,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: e3 ff 91 c0 <unknown>
+// CHECK-UNKNOWN: c091ffe3 <unknown>
 
 addva   za1.s, p3/m, p0/m, z17.s
 // CHECK-INST: addva   za1.s, p3/m, p0/m, z17.s
 // CHECK-ENCODING: [0x21,0x0e,0x91,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 0e 91 c0 <unknown>
+// CHECK-UNKNOWN: c0910e21 <unknown>
 
 addva   za1.s, p1/m, p4/m, z1.s
 // CHECK-INST: addva   za1.s, p1/m, p4/m, z1.s
 // CHECK-ENCODING: [0x21,0x84,0x91,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 91 c0 <unknown>
+// CHECK-UNKNOWN: c0918421 <unknown>
 
 addva   za0.s, p5/m, p2/m, z19.s
 // CHECK-INST: addva   za0.s, p5/m, p2/m, z19.s
 // CHECK-ENCODING: [0x60,0x56,0x91,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 60 56 91 c0 <unknown>
+// CHECK-UNKNOWN: c0915660 <unknown>
 
 addva   za0.s, p6/m, p0/m, z12.s
 // CHECK-INST: addva   za0.s, p6/m, p0/m, z12.s
 // CHECK-ENCODING: [0x80,0x19,0x91,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 91 c0 <unknown>
+// CHECK-UNKNOWN: c0911980 <unknown>
 
 addva   za1.s, p2/m, p6/m, z1.s
 // CHECK-INST: addva   za1.s, p2/m, p6/m, z1.s
 // CHECK-ENCODING: [0x21,0xc8,0x91,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 91 c0 <unknown>
+// CHECK-UNKNOWN: c091c821 <unknown>
 
 addva   za1.s, p2/m, p0/m, z22.s
 // CHECK-INST: addva   za1.s, p2/m, p0/m, z22.s
 // CHECK-ENCODING: [0xc1,0x0a,0x91,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: c1 0a 91 c0 <unknown>
+// CHECK-UNKNOWN: c0910ac1 <unknown>
 
 addva   za2.s, p5/m, p7/m, z9.s
 // CHECK-INST: addva   za2.s, p5/m, p7/m, z9.s
 // CHECK-ENCODING: [0x22,0xf5,0x91,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 91 c0 <unknown>
+// CHECK-UNKNOWN: c091f522 <unknown>
 
 addva   za3.s, p2/m, p5/m, z12.s
 // CHECK-INST: addva   za3.s, p2/m, p5/m, z12.s
 // CHECK-ENCODING: [0x83,0xa9,0x91,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 83 a9 91 c0 <unknown>
+// CHECK-UNKNOWN: c091a983 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/addva-u64.s b/llvm/test/MC/AArch64/SME/addva-u64.s
index d9686548cef09..48d0c3dff28ee 100644
--- a/llvm/test/MC/AArch64/SME/addva-u64.s
+++ b/llvm/test/MC/AArch64/SME/addva-u64.s
@@ -16,70 +16,70 @@ addva   za0.d, p0/m, p0/m, z0.d
 // CHECK-INST: addva   za0.d, p0/m, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0x00,0xd1,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 00 00 d1 c0 <unknown>
+// CHECK-UNKNOWN: c0d10000 <unknown>
 
 addva   za5.d, p5/m, p2/m, z10.d
 // CHECK-INST: addva   za5.d, p5/m, p2/m, z10.d
 // CHECK-ENCODING: [0x45,0x55,0xd1,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 45 55 d1 c0 <unknown>
+// CHECK-UNKNOWN: c0d15545 <unknown>
 
 addva   za7.d, p3/m, p7/m, z13.d
 // CHECK-INST: addva   za7.d, p3/m, p7/m, z13.d
 // CHECK-ENCODING: [0xa7,0xed,0xd1,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: a7 ed d1 c0 <unknown>
+// CHECK-UNKNOWN: c0d1eda7 <unknown>
 
 addva   za7.d, p7/m, p7/m, z31.d
 // CHECK-INST: addva   za7.d, p7/m, p7/m, z31.d
 // CHECK-ENCODING: [0xe7,0xff,0xd1,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: e7 ff d1 c0 <unknown>
+// CHECK-UNKNOWN: c0d1ffe7 <unknown>
 
 addva   za5.d, p3/m, p0/m, z17.d
 // CHECK-INST: addva   za5.d, p3/m, p0/m, z17.d
 // CHECK-ENCODING: [0x25,0x0e,0xd1,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 25 0e d1 c0 <unknown>
+// CHECK-UNKNOWN: c0d10e25 <unknown>
 
 addva   za1.d, p1/m, p4/m, z1.d
 // CHECK-INST: addva   za1.d, p1/m, p4/m, z1.d
 // CHECK-ENCODING: [0x21,0x84,0xd1,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 21 84 d1 c0 <unknown>
+// CHECK-UNKNOWN: c0d18421 <unknown>
 
 addva   za0.d, p5/m, p2/m, z19.d
 // CHECK-INST: addva   za0.d, p5/m, p2/m, z19.d
 // CHECK-ENCODING: [0x60,0x56,0xd1,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 60 56 d1 c0 <unknown>
+// CHECK-UNKNOWN: c0d15660 <unknown>
 
 addva   za0.d, p6/m, p0/m, z12.d
 // CHECK-INST: addva   za0.d, p6/m, p0/m, z12.d
 // CHECK-ENCODING: [0x80,0x19,0xd1,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 80 19 d1 c0 <unknown>
+// CHECK-UNKNOWN: c0d11980 <unknown>
 
 addva   za1.d, p2/m, p6/m, z1.d
 // CHECK-INST: addva   za1.d, p2/m, p6/m, z1.d
 // CHECK-ENCODING: [0x21,0xc8,0xd1,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 21 c8 d1 c0 <unknown>
+// CHECK-UNKNOWN: c0d1c821 <unknown>
 
 addva   za5.d, p2/m, p0/m, z22.d
 // CHECK-INST: addva   za5.d, p2/m, p0/m, z22.d
 // CHECK-ENCODING: [0xc5,0x0a,0xd1,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: c5 0a d1 c0 <unknown>
+// CHECK-UNKNOWN: c0d10ac5 <unknown>
 
 addva   za2.d, p5/m, p7/m, z9.d
 // CHECK-INST: addva   za2.d, p5/m, p7/m, z9.d
 // CHECK-ENCODING: [0x22,0xf5,0xd1,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 22 f5 d1 c0 <unknown>
+// CHECK-UNKNOWN: c0d1f522 <unknown>
 
 addva   za7.d, p2/m, p5/m, z12.d
 // CHECK-INST: addva   za7.d, p2/m, p5/m, z12.d
 // CHECK-ENCODING: [0x87,0xa9,0xd1,0xc0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 87 a9 d1 c0 <unknown>
+// CHECK-UNKNOWN: c0d1a987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/bfmopa.s b/llvm/test/MC/AArch64/SME/bfmopa.s
index a155aa643bbf4..b8b4d6c50562b 100644
--- a/llvm/test/MC/AArch64/SME/bfmopa.s
+++ b/llvm/test/MC/AArch64/SME/bfmopa.s
@@ -16,71 +16,71 @@ bfmopa  za0.s, p0/m, p0/m, z0.h, z0.h
 // CHECK-INST: bfmopa  za0.s, p0/m, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x00,0x80,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 80 81 <unknown>
+// CHECK-UNKNOWN: 81800000 <unknown>
 
 bfmopa  za1.s, p5/m, p2/m, z10.h, z21.h
 // CHECK-INST: bfmopa  za1.s, p5/m, p2/m, z10.h, z21.h
 // CHECK-ENCODING: [0x41,0x55,0x95,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 41 55 95 81 <unknown>
+// CHECK-UNKNOWN: 81955541 <unknown>
 
 bfmopa  za3.s, p3/m, p7/m, z13.h, z8.h
 // CHECK-INST: bfmopa  za3.s, p3/m, p7/m, z13.h, z8.h
 // CHECK-ENCODING: [0xa3,0xed,0x88,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a3 ed 88 81 <unknown>
+// CHECK-UNKNOWN: 8188eda3 <unknown>
 
 bfmopa  za3.s, p7/m, p7/m, z31.h, z31.h
 // CHECK-INST: bfmopa  za3.s, p7/m, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xe3,0xff,0x9f,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: e3 ff 9f 81 <unknown>
+// CHECK-UNKNOWN: 819fffe3 <unknown>
 
 bfmopa  za1.s, p3/m, p0/m, z17.h, z16.h
 // CHECK-INST: bfmopa  za1.s, p3/m, p0/m, z17.h, z16.h
 // CHECK-ENCODING: [0x21,0x0e,0x90,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 0e 90 81 <unknown>
+// CHECK-UNKNOWN: 81900e21 <unknown>
 
 bfmopa  za1.s, p1/m, p4/m, z1.h, z30.h
 // CHECK-INST: bfmopa  za1.s, p1/m, p4/m, z1.h, z30.h
 // CHECK-ENCODING: [0x21,0x84,0x9e,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 9e 81 <unknown>
+// CHECK-UNKNOWN: 819e8421 <unknown>
 
 bfmopa  za0.s, p5/m, p2/m, z19.h, z20.h
 // CHECK-INST: bfmopa  za0.s, p5/m, p2/m, z19.h, z20.h
 // CHECK-ENCODING: [0x60,0x56,0x94,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 60 56 94 81 <unknown>
+// CHECK-UNKNOWN: 81945660 <unknown>
 
 bfmopa  za0.s, p6/m, p0/m, z12.h, z2.h
 // CHECK-INST: bfmopa  za0.s, p6/m, p0/m, z12.h, z2.h
 // CHECK-ENCODING: [0x80,0x19,0x82,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 82 81 <unknown>
+// CHECK-UNKNOWN: 81821980 <unknown>
 
 bfmopa  za1.s, p2/m, p6/m, z1.h, z26.h
 // CHECK-INST: bfmopa  za1.s, p2/m, p6/m, z1.h, z26.h
 // CHECK-ENCODING: [0x21,0xc8,0x9a,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 9a 81 <unknown>
+// CHECK-UNKNOWN: 819ac821 <unknown>
 
 bfmopa  za1.s, p2/m, p0/m, z22.h, z30.h
 // CHECK-INST: bfmopa  za1.s, p2/m, p0/m, z22.h, z30.h
 // CHECK-ENCODING: [0xc1,0x0a,0x9e,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: c1 0a 9e 81 <unknown>
+// CHECK-UNKNOWN: 819e0ac1 <unknown>
 
 bfmopa  za2.s, p5/m, p7/m, z9.h, z1.h
 // CHECK-INST: bfmopa  za2.s, p5/m, p7/m, z9.h, z1.h
 // CHECK-ENCODING: [0x22,0xf5,0x81,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 81 81 <unknown>
+// CHECK-UNKNOWN: 8181f522 <unknown>
 
 bfmopa  za3.s, p2/m, p5/m, z12.h, z11.h
 // CHECK-INST: bfmopa  za3.s, p2/m, p5/m, z12.h, z11.h
 // CHECK-ENCODING: [0x83,0xa9,0x8b,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 83 a9 8b 81 <unknown>
+// CHECK-UNKNOWN: 818ba983 <unknown>
 

diff  --git a/llvm/test/MC/AArch64/SME/bfmops.s b/llvm/test/MC/AArch64/SME/bfmops.s
index 103db8ae9b2d3..2f93765f26f5e 100644
--- a/llvm/test/MC/AArch64/SME/bfmops.s
+++ b/llvm/test/MC/AArch64/SME/bfmops.s
@@ -16,71 +16,71 @@ bfmops  za0.s, p0/m, p0/m, z0.h, z0.h
 // CHECK-INST: bfmops  za0.s, p0/m, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x10,0x00,0x80,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 10 00 80 81 <unknown>
+// CHECK-UNKNOWN: 81800010 <unknown>
 
 bfmops  za1.s, p5/m, p2/m, z10.h, z21.h
 // CHECK-INST: bfmops  za1.s, p5/m, p2/m, z10.h, z21.h
 // CHECK-ENCODING: [0x51,0x55,0x95,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 51 55 95 81 <unknown>
+// CHECK-UNKNOWN: 81955551 <unknown>
 
 bfmops  za3.s, p3/m, p7/m, z13.h, z8.h
 // CHECK-INST: bfmops  za3.s, p3/m, p7/m, z13.h, z8.h
 // CHECK-ENCODING: [0xb3,0xed,0x88,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b3 ed 88 81 <unknown>
+// CHECK-UNKNOWN: 8188edb3 <unknown>
 
 bfmops  za3.s, p7/m, p7/m, z31.h, z31.h
 // CHECK-INST: bfmops  za3.s, p7/m, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xf3,0xff,0x9f,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: f3 ff 9f 81 <unknown>
+// CHECK-UNKNOWN: 819ffff3 <unknown>
 
 bfmops  za1.s, p3/m, p0/m, z17.h, z16.h
 // CHECK-INST: bfmops  za1.s, p3/m, p0/m, z17.h, z16.h
 // CHECK-ENCODING: [0x31,0x0e,0x90,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 0e 90 81 <unknown>
+// CHECK-UNKNOWN: 81900e31 <unknown>
 
 bfmops  za1.s, p1/m, p4/m, z1.h, z30.h
 // CHECK-INST: bfmops  za1.s, p1/m, p4/m, z1.h, z30.h
 // CHECK-ENCODING: [0x31,0x84,0x9e,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 84 9e 81 <unknown>
+// CHECK-UNKNOWN: 819e8431 <unknown>
 
 bfmops  za0.s, p5/m, p2/m, z19.h, z20.h
 // CHECK-INST: bfmops  za0.s, p5/m, p2/m, z19.h, z20.h
 // CHECK-ENCODING: [0x70,0x56,0x94,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 70 56 94 81 <unknown>
+// CHECK-UNKNOWN: 81945670 <unknown>
 
 bfmops  za0.s, p6/m, p0/m, z12.h, z2.h
 // CHECK-INST: bfmops  za0.s, p6/m, p0/m, z12.h, z2.h
 // CHECK-ENCODING: [0x90,0x19,0x82,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 90 19 82 81 <unknown>
+// CHECK-UNKNOWN: 81821990 <unknown>
 
 bfmops  za1.s, p2/m, p6/m, z1.h, z26.h
 // CHECK-INST: bfmops  za1.s, p2/m, p6/m, z1.h, z26.h
 // CHECK-ENCODING: [0x31,0xc8,0x9a,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 9a 81 <unknown>
+// CHECK-UNKNOWN: 819ac831 <unknown>
 
 bfmops  za1.s, p2/m, p0/m, z22.h, z30.h
 // CHECK-INST: bfmops  za1.s, p2/m, p0/m, z22.h, z30.h
 // CHECK-ENCODING: [0xd1,0x0a,0x9e,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: d1 0a 9e 81 <unknown>
+// CHECK-UNKNOWN: 819e0ad1 <unknown>
 
 bfmops  za2.s, p5/m, p7/m, z9.h, z1.h
 // CHECK-INST: bfmops  za2.s, p5/m, p7/m, z9.h, z1.h
 // CHECK-ENCODING: [0x32,0xf5,0x81,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 32 f5 81 81 <unknown>
+// CHECK-UNKNOWN: 8181f532 <unknown>
 
 bfmops  za3.s, p2/m, p5/m, z12.h, z11.h
 // CHECK-INST: bfmops  za3.s, p2/m, p5/m, z12.h, z11.h
 // CHECK-ENCODING: [0x93,0xa9,0x8b,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 93 a9 8b 81 <unknown>
+// CHECK-UNKNOWN: 818ba993 <unknown>
 

diff  --git a/llvm/test/MC/AArch64/SME/fmopa-fp64.s b/llvm/test/MC/AArch64/SME/fmopa-fp64.s
index 4272e47ca211e..089487d0c6a7d 100644
--- a/llvm/test/MC/AArch64/SME/fmopa-fp64.s
+++ b/llvm/test/MC/AArch64/SME/fmopa-fp64.s
@@ -19,70 +19,70 @@ fmopa   za0.d, p0/m, p0/m, z0.d, z0.d
 // CHECK-INST: fmopa   za0.d, p0/m, p0/m, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x00,0xc0,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 00 00 c0 80 <unknown>
+// CHECK-UNKNOWN: 80c00000 <unknown>
 
 fmopa   za5.d, p5/m, p2/m, z10.d, z21.d
 // CHECK-INST: fmopa   za5.d, p5/m, p2/m, z10.d, z21.d
 // CHECK-ENCODING: [0x45,0x55,0xd5,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 45 55 d5 80 <unknown>
+// CHECK-UNKNOWN: 80d55545 <unknown>
 
 fmopa   za7.d, p3/m, p7/m, z13.d, z8.d
 // CHECK-INST: fmopa   za7.d, p3/m, p7/m, z13.d, z8.d
 // CHECK-ENCODING: [0xa7,0xed,0xc8,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: a7 ed c8 80 <unknown>
+// CHECK-UNKNOWN: 80c8eda7 <unknown>
 
 fmopa   za7.d, p7/m, p7/m, z31.d, z31.d
 // CHECK-INST: fmopa   za7.d, p7/m, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xe7,0xff,0xdf,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: e7 ff df 80 <unknown>
+// CHECK-UNKNOWN: 80dfffe7 <unknown>
 
 fmopa   za5.d, p3/m, p0/m, z17.d, z16.d
 // CHECK-INST: fmopa   za5.d, p3/m, p0/m, z17.d, z16.d
 // CHECK-ENCODING: [0x25,0x0e,0xd0,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 25 0e d0 80 <unknown>
+// CHECK-UNKNOWN: 80d00e25 <unknown>
 
 fmopa   za1.d, p1/m, p4/m, z1.d, z30.d
 // CHECK-INST: fmopa   za1.d, p1/m, p4/m, z1.d, z30.d
 // CHECK-ENCODING: [0x21,0x84,0xde,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 21 84 de 80 <unknown>
+// CHECK-UNKNOWN: 80de8421 <unknown>
 
 fmopa   za0.d, p5/m, p2/m, z19.d, z20.d
 // CHECK-INST: fmopa   za0.d, p5/m, p2/m, z19.d, z20.d
 // CHECK-ENCODING: [0x60,0x56,0xd4,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 60 56 d4 80 <unknown>
+// CHECK-UNKNOWN: 80d45660 <unknown>
 
 fmopa   za0.d, p6/m, p0/m, z12.d, z2.d
 // CHECK-INST: fmopa   za0.d, p6/m, p0/m, z12.d, z2.d
 // CHECK-ENCODING: [0x80,0x19,0xc2,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 80 19 c2 80 <unknown>
+// CHECK-UNKNOWN: 80c21980 <unknown>
 
 fmopa   za1.d, p2/m, p6/m, z1.d, z26.d
 // CHECK-INST: fmopa   za1.d, p2/m, p6/m, z1.d, z26.d
 // CHECK-ENCODING: [0x21,0xc8,0xda,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 21 c8 da 80 <unknown>
+// CHECK-UNKNOWN: 80dac821 <unknown>
 
 fmopa   za5.d, p2/m, p0/m, z22.d, z30.d
 // CHECK-INST: fmopa   za5.d, p2/m, p0/m, z22.d, z30.d
 // CHECK-ENCODING: [0xc5,0x0a,0xde,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: c5 0a de 80 <unknown>
+// CHECK-UNKNOWN: 80de0ac5 <unknown>
 
 fmopa   za2.d, p5/m, p7/m, z9.d, z1.d
 // CHECK-INST: fmopa   za2.d, p5/m, p7/m, z9.d, z1.d
 // CHECK-ENCODING: [0x22,0xf5,0xc1,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 22 f5 c1 80 <unknown>
+// CHECK-UNKNOWN: 80c1f522 <unknown>
 
 fmopa   za7.d, p2/m, p5/m, z12.d, z11.d
 // CHECK-INST: fmopa   za7.d, p2/m, p5/m, z12.d, z11.d
 // CHECK-ENCODING: [0x87,0xa9,0xcb,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 87 a9 cb 80 <unknown>
+// CHECK-UNKNOWN: 80cba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/fmopa.s b/llvm/test/MC/AArch64/SME/fmopa.s
index b0423c5029634..ca9d71f3beed8 100644
--- a/llvm/test/MC/AArch64/SME/fmopa.s
+++ b/llvm/test/MC/AArch64/SME/fmopa.s
@@ -19,73 +19,73 @@ fmopa   za0.s, p0/m, p0/m, z0.h, z0.h
 // CHECK-INST: fmopa   za0.s, p0/m, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x00,0xa0,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 a0 81 <unknown>
+// CHECK-UNKNOWN: 81a00000 <unknown>
 
 fmopa   za1.s, p5/m, p2/m, z10.h, z21.h
 // CHECK-INST: fmopa   za1.s, p5/m, p2/m, z10.h, z21.h
 // CHECK-ENCODING: [0x41,0x55,0xb5,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 41 55 b5 81 <unknown>
+// CHECK-UNKNOWN: 81b55541 <unknown>
 
 fmopa   za3.s, p3/m, p7/m, z13.h, z8.h
 // CHECK-INST: fmopa   za3.s, p3/m, p7/m, z13.h, z8.h
 // CHECK-ENCODING: [0xa3,0xed,0xa8,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a3 ed a8 81 <unknown>
+// CHECK-UNKNOWN: 81a8eda3 <unknown>
 
 fmopa   za3.s, p7/m, p7/m, z31.h, z31.h
 // CHECK-INST: fmopa   za3.s, p7/m, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xe3,0xff,0xbf,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: e3 ff bf 81 <unknown>
+// CHECK-UNKNOWN: 81bfffe3 <unknown>
 
 fmopa   za1.s, p3/m, p0/m, z17.h, z16.h
 // CHECK-INST: fmopa   za1.s, p3/m, p0/m, z17.h, z16.h
 // CHECK-ENCODING: [0x21,0x0e,0xb0,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 0e b0 81 <unknown>
+// CHECK-UNKNOWN: 81b00e21 <unknown>
 
 fmopa   za1.s, p1/m, p4/m, z1.h, z30.h
 // CHECK-INST: fmopa   za1.s, p1/m, p4/m, z1.h, z30.h
 // CHECK-ENCODING: [0x21,0x84,0xbe,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 be 81 <unknown>
+// CHECK-UNKNOWN: 81be8421 <unknown>
 
 fmopa   za0.s, p5/m, p2/m, z19.h, z20.h
 // CHECK-INST: fmopa   za0.s, p5/m, p2/m, z19.h, z20.h
 // CHECK-ENCODING: [0x60,0x56,0xb4,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 60 56 b4 81 <unknown>
+// CHECK-UNKNOWN: 81b45660 <unknown>
 
 fmopa   za0.s, p6/m, p0/m, z12.h, z2.h
 // CHECK-INST: fmopa   za0.s, p6/m, p0/m, z12.h, z2.h
 // CHECK-ENCODING: [0x80,0x19,0xa2,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 a2 81 <unknown>
+// CHECK-UNKNOWN: 81a21980 <unknown>
 
 fmopa   za1.s, p2/m, p6/m, z1.h, z26.h
 // CHECK-INST: fmopa   za1.s, p2/m, p6/m, z1.h, z26.h
 // CHECK-ENCODING: [0x21,0xc8,0xba,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 ba 81 <unknown>
+// CHECK-UNKNOWN: 81bac821 <unknown>
 
 fmopa   za1.s, p2/m, p0/m, z22.h, z30.h
 // CHECK-INST: fmopa   za1.s, p2/m, p0/m, z22.h, z30.h
 // CHECK-ENCODING: [0xc1,0x0a,0xbe,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: c1 0a be 81 <unknown>
+// CHECK-UNKNOWN: 81be0ac1 <unknown>
 
 fmopa   za2.s, p5/m, p7/m, z9.h, z1.h
 // CHECK-INST: fmopa   za2.s, p5/m, p7/m, z9.h, z1.h
 // CHECK-ENCODING: [0x22,0xf5,0xa1,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 a1 81 <unknown>
+// CHECK-UNKNOWN: 81a1f522 <unknown>
 
 fmopa   za3.s, p2/m, p5/m, z12.h, z11.h
 // CHECK-INST: fmopa   za3.s, p2/m, p5/m, z12.h, z11.h
 // CHECK-ENCODING: [0x83,0xa9,0xab,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 83 a9 ab 81 <unknown>
+// CHECK-UNKNOWN: 81aba983 <unknown>
 
 // --------------------------------------------------------------------------//
 // Non-widening (single-precision)
@@ -94,70 +94,70 @@ fmopa   za0.s, p0/m, p0/m, z0.s, z0.s
 // CHECK-INST: fmopa   za0.s, p0/m, p0/m, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x00,0x80,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 80 80 <unknown>
+// CHECK-UNKNOWN: 80800000 <unknown>
 
 fmopa   za1.s, p5/m, p2/m, z10.s, z21.s
 // CHECK-INST: fmopa   za1.s, p5/m, p2/m, z10.s, z21.s
 // CHECK-ENCODING: [0x41,0x55,0x95,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 41 55 95 80 <unknown>
+// CHECK-UNKNOWN: 80955541 <unknown>
 
 fmopa   za3.s, p3/m, p7/m, z13.s, z8.s
 // CHECK-INST: fmopa   za3.s, p3/m, p7/m, z13.s, z8.s
 // CHECK-ENCODING: [0xa3,0xed,0x88,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a3 ed 88 80 <unknown>
+// CHECK-UNKNOWN: 8088eda3 <unknown>
 
 fmopa   za3.s, p7/m, p7/m, z31.s, z31.s
 // CHECK-INST: fmopa   za3.s, p7/m, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xe3,0xff,0x9f,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: e3 ff 9f 80 <unknown>
+// CHECK-UNKNOWN: 809fffe3 <unknown>
 
 fmopa   za1.s, p3/m, p0/m, z17.s, z16.s
 // CHECK-INST: fmopa   za1.s, p3/m, p0/m, z17.s, z16.s
 // CHECK-ENCODING: [0x21,0x0e,0x90,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 0e 90 80 <unknown>
+// CHECK-UNKNOWN: 80900e21 <unknown>
 
 fmopa   za1.s, p1/m, p4/m, z1.s, z30.s
 // CHECK-INST: fmopa   za1.s, p1/m, p4/m, z1.s, z30.s
 // CHECK-ENCODING: [0x21,0x84,0x9e,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 9e 80 <unknown>
+// CHECK-UNKNOWN: 809e8421 <unknown>
 
 fmopa   za0.s, p5/m, p2/m, z19.s, z20.s
 // CHECK-INST: fmopa   za0.s, p5/m, p2/m, z19.s, z20.s
 // CHECK-ENCODING: [0x60,0x56,0x94,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 60 56 94 80 <unknown>
+// CHECK-UNKNOWN: 80945660 <unknown>
 
 fmopa   za0.s, p6/m, p0/m, z12.s, z2.s
 // CHECK-INST: fmopa   za0.s, p6/m, p0/m, z12.s, z2.s
 // CHECK-ENCODING: [0x80,0x19,0x82,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 82 80 <unknown>
+// CHECK-UNKNOWN: 80821980 <unknown>
 
 fmopa   za1.s, p2/m, p6/m, z1.s, z26.s
 // CHECK-INST: fmopa   za1.s, p2/m, p6/m, z1.s, z26.s
 // CHECK-ENCODING: [0x21,0xc8,0x9a,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 9a 80 <unknown>
+// CHECK-UNKNOWN: 809ac821 <unknown>
 
 fmopa   za1.s, p2/m, p0/m, z22.s, z30.s
 // CHECK-INST: fmopa   za1.s, p2/m, p0/m, z22.s, z30.s
 // CHECK-ENCODING: [0xc1,0x0a,0x9e,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: c1 0a 9e 80 <unknown>
+// CHECK-UNKNOWN: 809e0ac1 <unknown>
 
 fmopa   za2.s, p5/m, p7/m, z9.s, z1.s
 // CHECK-INST: fmopa   za2.s, p5/m, p7/m, z9.s, z1.s
 // CHECK-ENCODING: [0x22,0xf5,0x81,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 81 80 <unknown>
+// CHECK-UNKNOWN: 8081f522 <unknown>
 
 fmopa   za3.s, p2/m, p5/m, z12.s, z11.s
 // CHECK-INST: fmopa   za3.s, p2/m, p5/m, z12.s, z11.s
 // CHECK-ENCODING: [0x83,0xa9,0x8b,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 83 a9 8b 80 <unknown>
+// CHECK-UNKNOWN: 808ba983 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/fmops-fp64.s b/llvm/test/MC/AArch64/SME/fmops-fp64.s
index 8c077439a1ed8..f2e5831739b3e 100644
--- a/llvm/test/MC/AArch64/SME/fmops-fp64.s
+++ b/llvm/test/MC/AArch64/SME/fmops-fp64.s
@@ -19,70 +19,70 @@ fmops   za0.d, p0/m, p0/m, z0.d, z0.d
 // CHECK-INST: fmops   za0.d, p0/m, p0/m, z0.d, z0.d
 // CHECK-ENCODING: [0x10,0x00,0xc0,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 10 00 c0 80 <unknown>
+// CHECK-UNKNOWN: 80c00010 <unknown>
 
 fmops   za5.d, p5/m, p2/m, z10.d, z21.d
 // CHECK-INST: fmops   za5.d, p5/m, p2/m, z10.d, z21.d
 // CHECK-ENCODING: [0x55,0x55,0xd5,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 55 55 d5 80 <unknown>
+// CHECK-UNKNOWN: 80d55555 <unknown>
 
 fmops   za7.d, p3/m, p7/m, z13.d, z8.d
 // CHECK-INST: fmops   za7.d, p3/m, p7/m, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0xed,0xc8,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: b7 ed c8 80 <unknown>
+// CHECK-UNKNOWN: 80c8edb7 <unknown>
 
 fmops   za7.d, p7/m, p7/m, z31.d, z31.d
 // CHECK-INST: fmops   za7.d, p7/m, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xf7,0xff,0xdf,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: f7 ff df 80 <unknown>
+// CHECK-UNKNOWN: 80dffff7 <unknown>
 
 fmops   za5.d, p3/m, p0/m, z17.d, z16.d
 // CHECK-INST: fmops   za5.d, p3/m, p0/m, z17.d, z16.d
 // CHECK-ENCODING: [0x35,0x0e,0xd0,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 35 0e d0 80 <unknown>
+// CHECK-UNKNOWN: 80d00e35 <unknown>
 
 fmops   za1.d, p1/m, p4/m, z1.d, z30.d
 // CHECK-INST: fmops   za1.d, p1/m, p4/m, z1.d, z30.d
 // CHECK-ENCODING: [0x31,0x84,0xde,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 31 84 de 80 <unknown>
+// CHECK-UNKNOWN: 80de8431 <unknown>
 
 fmops   za0.d, p5/m, p2/m, z19.d, z20.d
 // CHECK-INST: fmops   za0.d, p5/m, p2/m, z19.d, z20.d
 // CHECK-ENCODING: [0x70,0x56,0xd4,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 70 56 d4 80 <unknown>
+// CHECK-UNKNOWN: 80d45670 <unknown>
 
 fmops   za0.d, p6/m, p0/m, z12.d, z2.d
 // CHECK-INST: fmops   za0.d, p6/m, p0/m, z12.d, z2.d
 // CHECK-ENCODING: [0x90,0x19,0xc2,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 90 19 c2 80 <unknown>
+// CHECK-UNKNOWN: 80c21990 <unknown>
 
 fmops   za1.d, p2/m, p6/m, z1.d, z26.d
 // CHECK-INST: fmops   za1.d, p2/m, p6/m, z1.d, z26.d
 // CHECK-ENCODING: [0x31,0xc8,0xda,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 31 c8 da 80 <unknown>
+// CHECK-UNKNOWN: 80dac831 <unknown>
 
 fmops   za5.d, p2/m, p0/m, z22.d, z30.d
 // CHECK-INST: fmops   za5.d, p2/m, p0/m, z22.d, z30.d
 // CHECK-ENCODING: [0xd5,0x0a,0xde,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: d5 0a de 80 <unknown>
+// CHECK-UNKNOWN: 80de0ad5 <unknown>
 
 fmops   za2.d, p5/m, p7/m, z9.d, z1.d
 // CHECK-INST: fmops   za2.d, p5/m, p7/m, z9.d, z1.d
 // CHECK-ENCODING: [0x32,0xf5,0xc1,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 32 f5 c1 80 <unknown>
+// CHECK-UNKNOWN: 80c1f532 <unknown>
 
 fmops   za7.d, p2/m, p5/m, z12.d, z11.d
 // CHECK-INST: fmops   za7.d, p2/m, p5/m, z12.d, z11.d
 // CHECK-ENCODING: [0x97,0xa9,0xcb,0x80]
 // CHECK-ERROR: instruction requires: sme-f64
-// CHECK-UNKNOWN: 97 a9 cb 80 <unknown>
+// CHECK-UNKNOWN: 80cba997 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/fmops.s b/llvm/test/MC/AArch64/SME/fmops.s
index 9a3a2cb634b0b..bc8936b290c8b 100644
--- a/llvm/test/MC/AArch64/SME/fmops.s
+++ b/llvm/test/MC/AArch64/SME/fmops.s
@@ -19,73 +19,73 @@ fmops   za0.s, p0/m, p0/m, z0.h, z0.h
 // CHECK-INST: fmops   za0.s, p0/m, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x10,0x00,0xa0,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 10 00 a0 81 <unknown>
+// CHECK-UNKNOWN: 81a00010 <unknown>
 
 fmops   za1.s, p5/m, p2/m, z10.h, z21.h
 // CHECK-INST: fmops   za1.s, p5/m, p2/m, z10.h, z21.h
 // CHECK-ENCODING: [0x51,0x55,0xb5,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 51 55 b5 81 <unknown>
+// CHECK-UNKNOWN: 81b55551 <unknown>
 
 fmops   za3.s, p3/m, p7/m, z13.h, z8.h
 // CHECK-INST: fmops   za3.s, p3/m, p7/m, z13.h, z8.h
 // CHECK-ENCODING: [0xb3,0xed,0xa8,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b3 ed a8 81 <unknown>
+// CHECK-UNKNOWN: 81a8edb3 <unknown>
 
 fmops   za3.s, p7/m, p7/m, z31.h, z31.h
 // CHECK-INST: fmops   za3.s, p7/m, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xf3,0xff,0xbf,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: f3 ff bf 81 <unknown>
+// CHECK-UNKNOWN: 81bffff3 <unknown>
 
 fmops   za1.s, p3/m, p0/m, z17.h, z16.h
 // CHECK-INST: fmops   za1.s, p3/m, p0/m, z17.h, z16.h
 // CHECK-ENCODING: [0x31,0x0e,0xb0,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 0e b0 81 <unknown>
+// CHECK-UNKNOWN: 81b00e31 <unknown>
 
 fmops   za1.s, p1/m, p4/m, z1.h, z30.h
 // CHECK-INST: fmops   za1.s, p1/m, p4/m, z1.h, z30.h
 // CHECK-ENCODING: [0x31,0x84,0xbe,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 84 be 81 <unknown>
+// CHECK-UNKNOWN: 81be8431 <unknown>
 
 fmops   za0.s, p5/m, p2/m, z19.h, z20.h
 // CHECK-INST: fmops   za0.s, p5/m, p2/m, z19.h, z20.h
 // CHECK-ENCODING: [0x70,0x56,0xb4,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 70 56 b4 81 <unknown>
+// CHECK-UNKNOWN: 81b45670 <unknown>
 
 fmops   za0.s, p6/m, p0/m, z12.h, z2.h
 // CHECK-INST: fmops   za0.s, p6/m, p0/m, z12.h, z2.h
 // CHECK-ENCODING: [0x90,0x19,0xa2,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 90 19 a2 81 <unknown>
+// CHECK-UNKNOWN: 81a21990 <unknown>
 
 fmops   za1.s, p2/m, p6/m, z1.h, z26.h
 // CHECK-INST: fmops   za1.s, p2/m, p6/m, z1.h, z26.h
 // CHECK-ENCODING: [0x31,0xc8,0xba,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 ba 81 <unknown>
+// CHECK-UNKNOWN: 81bac831 <unknown>
 
 fmops   za1.s, p2/m, p0/m, z22.h, z30.h
 // CHECK-INST: fmops   za1.s, p2/m, p0/m, z22.h, z30.h
 // CHECK-ENCODING: [0xd1,0x0a,0xbe,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: d1 0a be 81 <unknown>
+// CHECK-UNKNOWN: 81be0ad1 <unknown>
 
 fmops   za2.s, p5/m, p7/m, z9.h, z1.h
 // CHECK-INST: fmops   za2.s, p5/m, p7/m, z9.h, z1.h
 // CHECK-ENCODING: [0x32,0xf5,0xa1,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 32 f5 a1 81 <unknown>
+// CHECK-UNKNOWN: 81a1f532 <unknown>
 
 fmops   za3.s, p2/m, p5/m, z12.h, z11.h
 // CHECK-INST: fmops   za3.s, p2/m, p5/m, z12.h, z11.h
 // CHECK-ENCODING: [0x93,0xa9,0xab,0x81]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 93 a9 ab 81 <unknown>
+// CHECK-UNKNOWN: 81aba993 <unknown>
 
 // --------------------------------------------------------------------------//
 // Non-widening (single-precision)
@@ -94,70 +94,70 @@ fmops   za0.s, p0/m, p0/m, z0.s, z0.s
 // CHECK-INST: fmops   za0.s, p0/m, p0/m, z0.s, z0.s
 // CHECK-ENCODING: [0x10,0x00,0x80,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 10 00 80 80 <unknown>
+// CHECK-UNKNOWN: 80800010 <unknown>
 
 fmops   za1.s, p5/m, p2/m, z10.s, z21.s
 // CHECK-INST: fmops   za1.s, p5/m, p2/m, z10.s, z21.s
 // CHECK-ENCODING: [0x51,0x55,0x95,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 51 55 95 80 <unknown>
+// CHECK-UNKNOWN: 80955551 <unknown>
 
 fmops   za3.s, p3/m, p7/m, z13.s, z8.s
 // CHECK-INST: fmops   za3.s, p3/m, p7/m, z13.s, z8.s
 // CHECK-ENCODING: [0xb3,0xed,0x88,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b3 ed 88 80 <unknown>
+// CHECK-UNKNOWN: 8088edb3 <unknown>
 
 fmops   za3.s, p7/m, p7/m, z31.s, z31.s
 // CHECK-INST: fmops   za3.s, p7/m, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xf3,0xff,0x9f,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: f3 ff 9f 80 <unknown>
+// CHECK-UNKNOWN: 809ffff3 <unknown>
 
 fmops   za1.s, p3/m, p0/m, z17.s, z16.s
 // CHECK-INST: fmops   za1.s, p3/m, p0/m, z17.s, z16.s
 // CHECK-ENCODING: [0x31,0x0e,0x90,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 0e 90 80 <unknown>
+// CHECK-UNKNOWN: 80900e31 <unknown>
 
 fmops   za1.s, p1/m, p4/m, z1.s, z30.s
 // CHECK-INST: fmops   za1.s, p1/m, p4/m, z1.s, z30.s
 // CHECK-ENCODING: [0x31,0x84,0x9e,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 84 9e 80 <unknown>
+// CHECK-UNKNOWN: 809e8431 <unknown>
 
 fmops   za0.s, p5/m, p2/m, z19.s, z20.s
 // CHECK-INST: fmops   za0.s, p5/m, p2/m, z19.s, z20.s
 // CHECK-ENCODING: [0x70,0x56,0x94,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 70 56 94 80 <unknown>
+// CHECK-UNKNOWN: 80945670 <unknown>
 
 fmops   za0.s, p6/m, p0/m, z12.s, z2.s
 // CHECK-INST: fmops   za0.s, p6/m, p0/m, z12.s, z2.s
 // CHECK-ENCODING: [0x90,0x19,0x82,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 90 19 82 80 <unknown>
+// CHECK-UNKNOWN: 80821990 <unknown>
 
 fmops   za1.s, p2/m, p6/m, z1.s, z26.s
 // CHECK-INST: fmops   za1.s, p2/m, p6/m, z1.s, z26.s
 // CHECK-ENCODING: [0x31,0xc8,0x9a,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 9a 80 <unknown>
+// CHECK-UNKNOWN: 809ac831 <unknown>
 
 fmops   za1.s, p2/m, p0/m, z22.s, z30.s
 // CHECK-INST: fmops   za1.s, p2/m, p0/m, z22.s, z30.s
 // CHECK-ENCODING: [0xd1,0x0a,0x9e,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: d1 0a 9e 80 <unknown>
+// CHECK-UNKNOWN: 809e0ad1 <unknown>
 
 fmops   za2.s, p5/m, p7/m, z9.s, z1.s
 // CHECK-INST: fmops   za2.s, p5/m, p7/m, z9.s, z1.s
 // CHECK-ENCODING: [0x32,0xf5,0x81,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 32 f5 81 80 <unknown>
+// CHECK-UNKNOWN: 8081f532 <unknown>
 
 fmops   za3.s, p2/m, p5/m, z12.s, z11.s
 // CHECK-INST: fmops   za3.s, p2/m, p5/m, z12.s, z11.s
 // CHECK-ENCODING: [0x93,0xa9,0x8b,0x80]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 93 a9 8b 80 <unknown>
+// CHECK-UNKNOWN: 808ba993 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/ld1b.s b/llvm/test/MC/AArch64/SME/ld1b.s
index 8ce68313922df..ed011a7d9090e 100644
--- a/llvm/test/MC/AArch64/SME/ld1b.s
+++ b/llvm/test/MC/AArch64/SME/ld1b.s
@@ -19,145 +19,145 @@ ld1b    {za0h.b[w12, 0]}, p0/z, [x0, x0]
 // CHECK-INST: ld1b    {za0h.b[w12, 0]}, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x00,0x00,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 00 e0 <unknown>
+// CHECK-UNKNOWN: e0000000 <unknown>
 
 ld1b    {za0h.b[w14, 5]}, p5/z, [x10, x21]
 // CHECK-INST: ld1b    {za0h.b[w14, 5]}, p5/z, [x10, x21]
 // CHECK-ENCODING: [0x45,0x55,0x15,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 15 e0 <unknown>
+// CHECK-UNKNOWN: e0155545 <unknown>
 
 ld1b    {za0h.b[w15, 7]}, p3/z, [x13, x8]
 // CHECK-INST: ld1b    {za0h.b[w15, 7]}, p3/z, [x13, x8]
 // CHECK-ENCODING: [0xa7,0x6d,0x08,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 08 e0 <unknown>
+// CHECK-UNKNOWN: e0086da7 <unknown>
 
 ld1b    {za0h.b[w15, 15]}, p7/z, [sp]
 // CHECK-INST: ld1b    {za0h.b[w15, 15]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0x1f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 1f e0 <unknown>
+// CHECK-UNKNOWN: e01f7fef <unknown>
 
 ld1b    {za0h.b[w12, 5]}, p3/z, [x17, x16]
 // CHECK-INST: ld1b    {za0h.b[w12, 5]}, p3/z, [x17, x16]
 // CHECK-ENCODING: [0x25,0x0e,0x10,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 10 e0 <unknown>
+// CHECK-UNKNOWN: e0100e25 <unknown>
 
 ld1b    {za0h.b[w12, 1]}, p1/z, [x1, x30]
 // CHECK-INST: ld1b    {za0h.b[w12, 1]}, p1/z, [x1, x30]
 // CHECK-ENCODING: [0x21,0x04,0x1e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 1e e0 <unknown>
+// CHECK-UNKNOWN: e01e0421 <unknown>
 
 ld1b    {za0h.b[w14, 8]}, p5/z, [x19, x20]
 // CHECK-INST: ld1b    {za0h.b[w14, 8]}, p5/z, [x19, x20]
 // CHECK-ENCODING: [0x68,0x56,0x14,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 14 e0 <unknown>
+// CHECK-UNKNOWN: e0145668 <unknown>
 
 ld1b    {za0h.b[w12, 0]}, p6/z, [x12, x2]
 // CHECK-INST: ld1b    {za0h.b[w12, 0]}, p6/z, [x12, x2]
 // CHECK-ENCODING: [0x80,0x19,0x02,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 02 e0 <unknown>
+// CHECK-UNKNOWN: e0021980 <unknown>
 
 ld1b    {za0h.b[w14, 1]}, p2/z, [x1, x26]
 // CHECK-INST: ld1b    {za0h.b[w14, 1]}, p2/z, [x1, x26]
 // CHECK-ENCODING: [0x21,0x48,0x1a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 1a e0 <unknown>
+// CHECK-UNKNOWN: e01a4821 <unknown>
 
 ld1b    {za0h.b[w12, 13]}, p2/z, [x22, x30]
 // CHECK-INST: ld1b    {za0h.b[w12, 13]}, p2/z, [x22, x30]
 // CHECK-ENCODING: [0xcd,0x0a,0x1e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 1e e0 <unknown>
+// CHECK-UNKNOWN: e01e0acd <unknown>
 
 ld1b    {za0h.b[w15, 2]}, p5/z, [x9, x1]
 // CHECK-INST: ld1b    {za0h.b[w15, 2]}, p5/z, [x9, x1]
 // CHECK-ENCODING: [0x22,0x75,0x01,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 01 e0 <unknown>
+// CHECK-UNKNOWN: e0017522 <unknown>
 
 ld1b    {za0h.b[w13, 7]}, p2/z, [x12, x11]
 // CHECK-INST: ld1b    {za0h.b[w13, 7]}, p2/z, [x12, x11]
 // CHECK-ENCODING: [0x87,0x29,0x0b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 0b e0 <unknown>
+// CHECK-UNKNOWN: e00b2987 <unknown>
 
 ld1b    za0h.b[w12, 0], p0/z, [x0, x0]
 // CHECK-INST: ld1b    {za0h.b[w12, 0]}, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x00,0x00,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 00 e0 <unknown>
+// CHECK-UNKNOWN: e0000000 <unknown>
 
 ld1b    za0h.b[w14, 5], p5/z, [x10, x21]
 // CHECK-INST: ld1b    {za0h.b[w14, 5]}, p5/z, [x10, x21]
 // CHECK-ENCODING: [0x45,0x55,0x15,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 15 e0 <unknown>
+// CHECK-UNKNOWN: e0155545 <unknown>
 
 ld1b    za0h.b[w15, 7], p3/z, [x13, x8]
 // CHECK-INST: ld1b    {za0h.b[w15, 7]}, p3/z, [x13, x8]
 // CHECK-ENCODING: [0xa7,0x6d,0x08,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 08 e0 <unknown>
+// CHECK-UNKNOWN: e0086da7 <unknown>
 
 ld1b    za0h.b[w15, 15], p7/z, [sp]
 // CHECK-INST: ld1b    {za0h.b[w15, 15]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0x1f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 1f e0 <unknown>
+// CHECK-UNKNOWN: e01f7fef <unknown>
 
 ld1b    za0h.b[w12, 5], p3/z, [x17, x16]
 // CHECK-INST: ld1b    {za0h.b[w12, 5]}, p3/z, [x17, x16]
 // CHECK-ENCODING: [0x25,0x0e,0x10,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 10 e0 <unknown>
+// CHECK-UNKNOWN: e0100e25 <unknown>
 
 ld1b    za0h.b[w12, 1], p1/z, [x1, x30]
 // CHECK-INST: ld1b    {za0h.b[w12, 1]}, p1/z, [x1, x30]
 // CHECK-ENCODING: [0x21,0x04,0x1e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 1e e0 <unknown>
+// CHECK-UNKNOWN: e01e0421 <unknown>
 
 ld1b    za0h.b[w14, 8], p5/z, [x19, x20]
 // CHECK-INST: ld1b    {za0h.b[w14, 8]}, p5/z, [x19, x20]
 // CHECK-ENCODING: [0x68,0x56,0x14,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 14 e0 <unknown>
+// CHECK-UNKNOWN: e0145668 <unknown>
 
 ld1b    za0h.b[w12, 0], p6/z, [x12, x2]
 // CHECK-INST: ld1b    {za0h.b[w12, 0]}, p6/z, [x12, x2]
 // CHECK-ENCODING: [0x80,0x19,0x02,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 02 e0 <unknown>
+// CHECK-UNKNOWN: e0021980 <unknown>
 
 ld1b    za0h.b[w14, 1], p2/z, [x1, x26]
 // CHECK-INST: ld1b    {za0h.b[w14, 1]}, p2/z, [x1, x26]
 // CHECK-ENCODING: [0x21,0x48,0x1a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 1a e0 <unknown>
+// CHECK-UNKNOWN: e01a4821 <unknown>
 
 ld1b    za0h.b[w12, 13], p2/z, [x22, x30]
 // CHECK-INST: ld1b    {za0h.b[w12, 13]}, p2/z, [x22, x30]
 // CHECK-ENCODING: [0xcd,0x0a,0x1e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 1e e0 <unknown>
+// CHECK-UNKNOWN: e01e0acd <unknown>
 
 ld1b    za0h.b[w15, 2], p5/z, [x9, x1]
 // CHECK-INST: ld1b    {za0h.b[w15, 2]}, p5/z, [x9, x1]
 // CHECK-ENCODING: [0x22,0x75,0x01,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 01 e0 <unknown>
+// CHECK-UNKNOWN: e0017522 <unknown>
 
 ld1b    za0h.b[w13, 7], p2/z, [x12, x11]
 // CHECK-INST: ld1b    {za0h.b[w13, 7]}, p2/z, [x12, x11]
 // CHECK-ENCODING: [0x87,0x29,0x0b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 0b e0 <unknown>
+// CHECK-UNKNOWN: e00b2987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Vertical
@@ -166,142 +166,142 @@ ld1b    {za0v.b[w12, 0]}, p0/z, [x0, x0]
 // CHECK-INST: ld1b    {za0v.b[w12, 0]}, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x80,0x00,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 00 e0 <unknown>
+// CHECK-UNKNOWN: e0008000 <unknown>
 
 ld1b    {za0v.b[w14, 5]}, p5/z, [x10, x21]
 // CHECK-INST: ld1b    {za0v.b[w14, 5]}, p5/z, [x10, x21]
 // CHECK-ENCODING: [0x45,0xd5,0x15,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 15 e0 <unknown>
+// CHECK-UNKNOWN: e015d545 <unknown>
 
 ld1b    {za0v.b[w15, 7]}, p3/z, [x13, x8]
 // CHECK-INST: ld1b    {za0v.b[w15, 7]}, p3/z, [x13, x8]
 // CHECK-ENCODING: [0xa7,0xed,0x08,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 08 e0 <unknown>
+// CHECK-UNKNOWN: e008eda7 <unknown>
 
 ld1b    {za0v.b[w15, 15]}, p7/z, [sp]
 // CHECK-INST: ld1b    {za0v.b[w15, 15]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0xff,0x1f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 1f e0 <unknown>
+// CHECK-UNKNOWN: e01fffef <unknown>
 
 ld1b    {za0v.b[w12, 5]}, p3/z, [x17, x16]
 // CHECK-INST: ld1b    {za0v.b[w12, 5]}, p3/z, [x17, x16]
 // CHECK-ENCODING: [0x25,0x8e,0x10,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 10 e0 <unknown>
+// CHECK-UNKNOWN: e0108e25 <unknown>
 
 ld1b    {za0v.b[w12, 1]}, p1/z, [x1, x30]
 // CHECK-INST: ld1b    {za0v.b[w12, 1]}, p1/z, [x1, x30]
 // CHECK-ENCODING: [0x21,0x84,0x1e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 1e e0 <unknown>
+// CHECK-UNKNOWN: e01e8421 <unknown>
 
 ld1b    {za0v.b[w14, 8]}, p5/z, [x19, x20]
 // CHECK-INST: ld1b    {za0v.b[w14, 8]}, p5/z, [x19, x20]
 // CHECK-ENCODING: [0x68,0xd6,0x14,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 14 e0 <unknown>
+// CHECK-UNKNOWN: e014d668 <unknown>
 
 ld1b    {za0v.b[w12, 0]}, p6/z, [x12, x2]
 // CHECK-INST: ld1b    {za0v.b[w12, 0]}, p6/z, [x12, x2]
 // CHECK-ENCODING: [0x80,0x99,0x02,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 02 e0 <unknown>
+// CHECK-UNKNOWN: e0029980 <unknown>
 
 ld1b    {za0v.b[w14, 1]}, p2/z, [x1, x26]
 // CHECK-INST: ld1b    {za0v.b[w14, 1]}, p2/z, [x1, x26]
 // CHECK-ENCODING: [0x21,0xc8,0x1a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 1a e0 <unknown>
+// CHECK-UNKNOWN: e01ac821 <unknown>
 
 ld1b    {za0v.b[w12, 13]}, p2/z, [x22, x30]
 // CHECK-INST: ld1b    {za0v.b[w12, 13]}, p2/z, [x22, x30]
 // CHECK-ENCODING: [0xcd,0x8a,0x1e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 1e e0 <unknown>
+// CHECK-UNKNOWN: e01e8acd <unknown>
 
 ld1b    {za0v.b[w15, 2]}, p5/z, [x9, x1]
 // CHECK-INST: ld1b    {za0v.b[w15, 2]}, p5/z, [x9, x1]
 // CHECK-ENCODING: [0x22,0xf5,0x01,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 01 e0 <unknown>
+// CHECK-UNKNOWN: e001f522 <unknown>
 
 ld1b    {za0v.b[w13, 7]}, p2/z, [x12, x11]
 // CHECK-INST: ld1b    {za0v.b[w13, 7]}, p2/z, [x12, x11]
 // CHECK-ENCODING: [0x87,0xa9,0x0b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 0b e0 <unknown>
+// CHECK-UNKNOWN: e00ba987 <unknown>
 
 ld1b    za0v.b[w12, 0], p0/z, [x0, x0]
 // CHECK-INST: ld1b    {za0v.b[w12, 0]}, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x80,0x00,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 00 e0 <unknown>
+// CHECK-UNKNOWN: e0008000 <unknown>
 
 ld1b    za0v.b[w14, 5], p5/z, [x10, x21]
 // CHECK-INST: ld1b    {za0v.b[w14, 5]}, p5/z, [x10, x21]
 // CHECK-ENCODING: [0x45,0xd5,0x15,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 15 e0 <unknown>
+// CHECK-UNKNOWN: e015d545 <unknown>
 
 ld1b    za0v.b[w15, 7], p3/z, [x13, x8]
 // CHECK-INST: ld1b    {za0v.b[w15, 7]}, p3/z, [x13, x8]
 // CHECK-ENCODING: [0xa7,0xed,0x08,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 08 e0 <unknown>
+// CHECK-UNKNOWN: e008eda7 <unknown>
 
 ld1b    za0v.b[w15, 15], p7/z, [sp]
 // CHECK-INST: ld1b    {za0v.b[w15, 15]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0xff,0x1f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 1f e0 <unknown>
+// CHECK-UNKNOWN: e01fffef <unknown>
 
 ld1b    za0v.b[w12, 5], p3/z, [x17, x16]
 // CHECK-INST: ld1b    {za0v.b[w12, 5]}, p3/z, [x17, x16]
 // CHECK-ENCODING: [0x25,0x8e,0x10,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 10 e0 <unknown>
+// CHECK-UNKNOWN: e0108e25 <unknown>
 
 ld1b    za0v.b[w12, 1], p1/z, [x1, x30]
 // CHECK-INST: ld1b    {za0v.b[w12, 1]}, p1/z, [x1, x30]
 // CHECK-ENCODING: [0x21,0x84,0x1e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 1e e0 <unknown>
+// CHECK-UNKNOWN: e01e8421 <unknown>
 
 ld1b    za0v.b[w14, 8], p5/z, [x19, x20]
 // CHECK-INST: ld1b    {za0v.b[w14, 8]}, p5/z, [x19, x20]
 // CHECK-ENCODING: [0x68,0xd6,0x14,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 14 e0 <unknown>
+// CHECK-UNKNOWN: e014d668 <unknown>
 
 ld1b    za0v.b[w12, 0], p6/z, [x12, x2]
 // CHECK-INST: ld1b    {za0v.b[w12, 0]}, p6/z, [x12, x2]
 // CHECK-ENCODING: [0x80,0x99,0x02,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 02 e0 <unknown>
+// CHECK-UNKNOWN: e0029980 <unknown>
 
 ld1b    za0v.b[w14, 1], p2/z, [x1, x26]
 // CHECK-INST: ld1b    {za0v.b[w14, 1]}, p2/z, [x1, x26]
 // CHECK-ENCODING: [0x21,0xc8,0x1a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 1a e0 <unknown>
+// CHECK-UNKNOWN: e01ac821 <unknown>
 
 ld1b    za0v.b[w12, 13], p2/z, [x22, x30]
 // CHECK-INST: ld1b    {za0v.b[w12, 13]}, p2/z, [x22, x30]
 // CHECK-ENCODING: [0xcd,0x8a,0x1e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 1e e0 <unknown>
+// CHECK-UNKNOWN: e01e8acd <unknown>
 
 ld1b    za0v.b[w15, 2], p5/z, [x9, x1]
 // CHECK-INST: ld1b    {za0v.b[w15, 2]}, p5/z, [x9, x1]
 // CHECK-ENCODING: [0x22,0xf5,0x01,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 01 e0 <unknown>
+// CHECK-UNKNOWN: e001f522 <unknown>
 
 ld1b    za0v.b[w13, 7], p2/z, [x12, x11]
 // CHECK-INST: ld1b    {za0v.b[w13, 7]}, p2/z, [x12, x11]
 // CHECK-ENCODING: [0x87,0xa9,0x0b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 0b e0 <unknown>
+// CHECK-UNKNOWN: e00ba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/ld1d.s b/llvm/test/MC/AArch64/SME/ld1d.s
index 24d9c3c16412c..12c9a4d4c6bd8 100644
--- a/llvm/test/MC/AArch64/SME/ld1d.s
+++ b/llvm/test/MC/AArch64/SME/ld1d.s
@@ -19,145 +19,145 @@ ld1d    {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
 // CHECK-INST: ld1d    {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x00,0xc0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 c0 e0 <unknown>
+// CHECK-UNKNOWN: e0c00000 <unknown>
 
 ld1d    {za2h.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
 // CHECK-INST: ld1d    {za2h.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
 // CHECK-ENCODING: [0x45,0x55,0xd5,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 d5 e0 <unknown>
+// CHECK-UNKNOWN: e0d55545 <unknown>
 
 ld1d    {za3h.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
 // CHECK-INST: ld1d    {za3h.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
 // CHECK-ENCODING: [0xa7,0x6d,0xc8,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d c8 e0 <unknown>
+// CHECK-UNKNOWN: e0c86da7 <unknown>
 
 ld1d    {za7h.d[w15, 1]}, p7/z, [sp]
 // CHECK-INST: ld1d    {za7h.d[w15, 1]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0xdf,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f df e0 <unknown>
+// CHECK-UNKNOWN: e0df7fef <unknown>
 
 ld1d    {za2h.d[w12, 1]}, p3/z, [x17, x16, lsl #3]
 // CHECK-INST: ld1d    {za2h.d[w12, 1]}, p3/z, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0x0e,0xd0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e d0 e0 <unknown>
+// CHECK-UNKNOWN: e0d00e25 <unknown>
 
 ld1d    {za0h.d[w12, 1]}, p1/z, [x1, x30, lsl #3]
 // CHECK-INST: ld1d    {za0h.d[w12, 1]}, p1/z, [x1, x30, lsl #3]
 // CHECK-ENCODING: [0x21,0x04,0xde,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 de e0 <unknown>
+// CHECK-UNKNOWN: e0de0421 <unknown>
 
 ld1d    {za4h.d[w14, 0]}, p5/z, [x19, x20, lsl #3]
 // CHECK-INST: ld1d    {za4h.d[w14, 0]}, p5/z, [x19, x20, lsl #3]
 // CHECK-ENCODING: [0x68,0x56,0xd4,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 d4 e0 <unknown>
+// CHECK-UNKNOWN: e0d45668 <unknown>
 
 ld1d    {za0h.d[w12, 0]}, p6/z, [x12, x2, lsl #3]
 // CHECK-INST: ld1d    {za0h.d[w12, 0]}, p6/z, [x12, x2, lsl #3]
 // CHECK-ENCODING: [0x80,0x19,0xc2,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 c2 e0 <unknown>
+// CHECK-UNKNOWN: e0c21980 <unknown>
 
 ld1d    {za0h.d[w14, 1]}, p2/z, [x1, x26, lsl #3]
 // CHECK-INST: ld1d    {za0h.d[w14, 1]}, p2/z, [x1, x26, lsl #3]
 // CHECK-ENCODING: [0x21,0x48,0xda,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 da e0 <unknown>
+// CHECK-UNKNOWN: e0da4821 <unknown>
 
 ld1d    {za6h.d[w12, 1]}, p2/z, [x22, x30, lsl #3]
 // CHECK-INST: ld1d    {za6h.d[w12, 1]}, p2/z, [x22, x30, lsl #3]
 // CHECK-ENCODING: [0xcd,0x0a,0xde,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a de e0 <unknown>
+// CHECK-UNKNOWN: e0de0acd <unknown>
 
 ld1d    {za1h.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
 // CHECK-INST: ld1d    {za1h.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
 // CHECK-ENCODING: [0x22,0x75,0xc1,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 c1 e0 <unknown>
+// CHECK-UNKNOWN: e0c17522 <unknown>
 
 ld1d    {za3h.d[w13, 1]}, p2/z, [x12, x11, lsl #3]
 // CHECK-INST: ld1d    {za3h.d[w13, 1]}, p2/z, [x12, x11, lsl #3]
 // CHECK-ENCODING: [0x87,0x29,0xcb,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 cb e0 <unknown>
+// CHECK-UNKNOWN: e0cb2987 <unknown>
 
 ld1d    za0h.d[w12, 0], p0/z, [x0, x0, lsl #3]
 // CHECK-INST: ld1d    {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x00,0xc0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 c0 e0 <unknown>
+// CHECK-UNKNOWN: e0c00000 <unknown>
 
 ld1d    za2h.d[w14, 1], p5/z, [x10, x21, lsl #3]
 // CHECK-INST: ld1d    {za2h.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
 // CHECK-ENCODING: [0x45,0x55,0xd5,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 d5 e0 <unknown>
+// CHECK-UNKNOWN: e0d55545 <unknown>
 
 ld1d    za3h.d[w15, 1], p3/z, [x13, x8, lsl #3]
 // CHECK-INST: ld1d    {za3h.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
 // CHECK-ENCODING: [0xa7,0x6d,0xc8,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d c8 e0 <unknown>
+// CHECK-UNKNOWN: e0c86da7 <unknown>
 
 ld1d    za7h.d[w15, 1], p7/z, [sp]
 // CHECK-INST: ld1d    {za7h.d[w15, 1]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0xdf,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f df e0 <unknown>
+// CHECK-UNKNOWN: e0df7fef <unknown>
 
 ld1d    za2h.d[w12, 1], p3/z, [x17, x16, lsl #3]
 // CHECK-INST: ld1d    {za2h.d[w12, 1]}, p3/z, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0x0e,0xd0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e d0 e0 <unknown>
+// CHECK-UNKNOWN: e0d00e25 <unknown>
 
 ld1d    za0h.d[w12, 1], p1/z, [x1, x30, lsl #3]
 // CHECK-INST: ld1d    {za0h.d[w12, 1]}, p1/z, [x1, x30, lsl #3]
 // CHECK-ENCODING: [0x21,0x04,0xde,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 de e0 <unknown>
+// CHECK-UNKNOWN: e0de0421 <unknown>
 
 ld1d    za4h.d[w14, 0], p5/z, [x19, x20, lsl #3]
 // CHECK-INST: ld1d    {za4h.d[w14, 0]}, p5/z, [x19, x20, lsl #3]
 // CHECK-ENCODING: [0x68,0x56,0xd4,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 d4 e0 <unknown>
+// CHECK-UNKNOWN: e0d45668 <unknown>
 
 ld1d    za0h.d[w12, 0], p6/z, [x12, x2, lsl #3]
 // CHECK-INST: ld1d    {za0h.d[w12, 0]}, p6/z, [x12, x2, lsl #3]
 // CHECK-ENCODING: [0x80,0x19,0xc2,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 c2 e0 <unknown>
+// CHECK-UNKNOWN: e0c21980 <unknown>
 
 ld1d    za0h.d[w14, 1], p2/z, [x1, x26, lsl #3]
 // CHECK-INST: ld1d    {za0h.d[w14, 1]}, p2/z, [x1, x26, lsl #3]
 // CHECK-ENCODING: [0x21,0x48,0xda,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 da e0 <unknown>
+// CHECK-UNKNOWN: e0da4821 <unknown>
 
 ld1d    za6h.d[w12, 1], p2/z, [x22, x30, lsl #3]
 // CHECK-INST: ld1d    {za6h.d[w12, 1]}, p2/z, [x22, x30, lsl #3]
 // CHECK-ENCODING: [0xcd,0x0a,0xde,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a de e0 <unknown>
+// CHECK-UNKNOWN: e0de0acd <unknown>
 
 ld1d    za1h.d[w15, 0], p5/z, [x9, x1, lsl #3]
 // CHECK-INST: ld1d    {za1h.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
 // CHECK-ENCODING: [0x22,0x75,0xc1,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 c1 e0 <unknown>
+// CHECK-UNKNOWN: e0c17522 <unknown>
 
 ld1d    za3h.d[w13, 1], p2/z, [x12, x11, lsl #3]
 // CHECK-INST: ld1d    {za3h.d[w13, 1]}, p2/z, [x12, x11, lsl #3]
 // CHECK-ENCODING: [0x87,0x29,0xcb,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 cb e0 <unknown>
+// CHECK-UNKNOWN: e0cb2987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Vertical
@@ -166,142 +166,142 @@ ld1d    {za0v.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
 // CHECK-INST: ld1d    {za0v.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x80,0xc0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 c0 e0 <unknown>
+// CHECK-UNKNOWN: e0c08000 <unknown>
 
 ld1d    {za2v.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
 // CHECK-INST: ld1d    {za2v.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
 // CHECK-ENCODING: [0x45,0xd5,0xd5,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 d5 e0 <unknown>
+// CHECK-UNKNOWN: e0d5d545 <unknown>
 
 ld1d    {za3v.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
 // CHECK-INST: ld1d    {za3v.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
 // CHECK-ENCODING: [0xa7,0xed,0xc8,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed c8 e0 <unknown>
+// CHECK-UNKNOWN: e0c8eda7 <unknown>
 
 ld1d    {za7v.d[w15, 1]}, p7/z, [sp]
 // CHECK-INST: ld1d    {za7v.d[w15, 1]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0xff,0xdf,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff df e0 <unknown>
+// CHECK-UNKNOWN: e0dfffef <unknown>
 
 ld1d    {za2v.d[w12, 1]}, p3/z, [x17, x16, lsl #3]
 // CHECK-INST: ld1d    {za2v.d[w12, 1]}, p3/z, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0x8e,0xd0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e d0 e0 <unknown>
+// CHECK-UNKNOWN: e0d08e25 <unknown>
 
 ld1d    {za0v.d[w12, 1]}, p1/z, [x1, x30, lsl #3]
 // CHECK-INST: ld1d    {za0v.d[w12, 1]}, p1/z, [x1, x30, lsl #3]
 // CHECK-ENCODING: [0x21,0x84,0xde,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 de e0 <unknown>
+// CHECK-UNKNOWN: e0de8421 <unknown>
 
 ld1d    {za4v.d[w14, 0]}, p5/z, [x19, x20, lsl #3]
 // CHECK-INST: ld1d    {za4v.d[w14, 0]}, p5/z, [x19, x20, lsl #3]
 // CHECK-ENCODING: [0x68,0xd6,0xd4,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 d4 e0 <unknown>
+// CHECK-UNKNOWN: e0d4d668 <unknown>
 
 ld1d    {za0v.d[w12, 0]}, p6/z, [x12, x2, lsl #3]
 // CHECK-INST: ld1d    {za0v.d[w12, 0]}, p6/z, [x12, x2, lsl #3]
 // CHECK-ENCODING: [0x80,0x99,0xc2,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 c2 e0 <unknown>
+// CHECK-UNKNOWN: e0c29980 <unknown>
 
 ld1d    {za0v.d[w14, 1]}, p2/z, [x1, x26, lsl #3]
 // CHECK-INST: ld1d    {za0v.d[w14, 1]}, p2/z, [x1, x26, lsl #3]
 // CHECK-ENCODING: [0x21,0xc8,0xda,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 da e0 <unknown>
+// CHECK-UNKNOWN: e0dac821 <unknown>
 
 ld1d    {za6v.d[w12, 1]}, p2/z, [x22, x30, lsl #3]
 // CHECK-INST: ld1d    {za6v.d[w12, 1]}, p2/z, [x22, x30, lsl #3]
 // CHECK-ENCODING: [0xcd,0x8a,0xde,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a de e0 <unknown>
+// CHECK-UNKNOWN: e0de8acd <unknown>
 
 ld1d    {za1v.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
 // CHECK-INST: ld1d    {za1v.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
 // CHECK-ENCODING: [0x22,0xf5,0xc1,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 c1 e0 <unknown>
+// CHECK-UNKNOWN: e0c1f522 <unknown>
 
 ld1d    {za3v.d[w13, 1]}, p2/z, [x12, x11, lsl #3]
 // CHECK-INST: ld1d    {za3v.d[w13, 1]}, p2/z, [x12, x11, lsl #3]
 // CHECK-ENCODING: [0x87,0xa9,0xcb,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 cb e0 <unknown>
+// CHECK-UNKNOWN: e0cba987 <unknown>
 
 ld1d    za0v.d[w12, 0], p0/z, [x0, x0, lsl #3]
 // CHECK-INST: ld1d    {za0v.d[w12, 0]}, p0/z, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x80,0xc0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 c0 e0 <unknown>
+// CHECK-UNKNOWN: e0c08000 <unknown>
 
 ld1d    za2v.d[w14, 1], p5/z, [x10, x21, lsl #3]
 // CHECK-INST: ld1d    {za2v.d[w14, 1]}, p5/z, [x10, x21, lsl #3]
 // CHECK-ENCODING: [0x45,0xd5,0xd5,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 d5 e0 <unknown>
+// CHECK-UNKNOWN: e0d5d545 <unknown>
 
 ld1d    za3v.d[w15, 1], p3/z, [x13, x8, lsl #3]
 // CHECK-INST: ld1d    {za3v.d[w15, 1]}, p3/z, [x13, x8, lsl #3]
 // CHECK-ENCODING: [0xa7,0xed,0xc8,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed c8 e0 <unknown>
+// CHECK-UNKNOWN: e0c8eda7 <unknown>
 
 ld1d    za7v.d[w15, 1], p7/z, [sp]
 // CHECK-INST: ld1d    {za7v.d[w15, 1]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0xff,0xdf,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff df e0 <unknown>
+// CHECK-UNKNOWN: e0dfffef <unknown>
 
 ld1d    za2v.d[w12, 1], p3/z, [x17, x16, lsl #3]
 // CHECK-INST: ld1d    {za2v.d[w12, 1]}, p3/z, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0x8e,0xd0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e d0 e0 <unknown>
+// CHECK-UNKNOWN: e0d08e25 <unknown>
 
 ld1d    za0v.d[w12, 1], p1/z, [x1, x30, lsl #3]
 // CHECK-INST: ld1d    {za0v.d[w12, 1]}, p1/z, [x1, x30, lsl #3]
 // CHECK-ENCODING: [0x21,0x84,0xde,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 de e0 <unknown>
+// CHECK-UNKNOWN: e0de8421 <unknown>
 
 ld1d    za4v.d[w14, 0], p5/z, [x19, x20, lsl #3]
 // CHECK-INST: ld1d    {za4v.d[w14, 0]}, p5/z, [x19, x20, lsl #3]
 // CHECK-ENCODING: [0x68,0xd6,0xd4,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 d4 e0 <unknown>
+// CHECK-UNKNOWN: e0d4d668 <unknown>
 
 ld1d    za0v.d[w12, 0], p6/z, [x12, x2, lsl #3]
 // CHECK-INST: ld1d    {za0v.d[w12, 0]}, p6/z, [x12, x2, lsl #3]
 // CHECK-ENCODING: [0x80,0x99,0xc2,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 c2 e0 <unknown>
+// CHECK-UNKNOWN: e0c29980 <unknown>
 
 ld1d    za0v.d[w14, 1], p2/z, [x1, x26, lsl #3]
 // CHECK-INST: ld1d    {za0v.d[w14, 1]}, p2/z, [x1, x26, lsl #3]
 // CHECK-ENCODING: [0x21,0xc8,0xda,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 da e0 <unknown>
+// CHECK-UNKNOWN: e0dac821 <unknown>
 
 ld1d    za6v.d[w12, 1], p2/z, [x22, x30, lsl #3]
 // CHECK-INST: ld1d    {za6v.d[w12, 1]}, p2/z, [x22, x30, lsl #3]
 // CHECK-ENCODING: [0xcd,0x8a,0xde,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a de e0 <unknown>
+// CHECK-UNKNOWN: e0de8acd <unknown>
 
 ld1d    za1v.d[w15, 0], p5/z, [x9, x1, lsl #3]
 // CHECK-INST: ld1d    {za1v.d[w15, 0]}, p5/z, [x9, x1, lsl #3]
 // CHECK-ENCODING: [0x22,0xf5,0xc1,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 c1 e0 <unknown>
+// CHECK-UNKNOWN: e0c1f522 <unknown>
 
 ld1d    za3v.d[w13, 1], p2/z, [x12, x11, lsl #3]
 // CHECK-INST: ld1d    {za3v.d[w13, 1]}, p2/z, [x12, x11, lsl #3]
 // CHECK-ENCODING: [0x87,0xa9,0xcb,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 cb e0 <unknown>
+// CHECK-UNKNOWN: e0cba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/ld1h.s b/llvm/test/MC/AArch64/SME/ld1h.s
index 1de76c1a4e83d..a476b41d75b9d 100644
--- a/llvm/test/MC/AArch64/SME/ld1h.s
+++ b/llvm/test/MC/AArch64/SME/ld1h.s
@@ -19,145 +19,145 @@ ld1h    {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x00,0x40,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 40 e0 <unknown>
+// CHECK-UNKNOWN: e0400000 <unknown>
 
 ld1h    {za0h.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
 // CHECK-ENCODING: [0x45,0x55,0x55,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 55 e0 <unknown>
+// CHECK-UNKNOWN: e0555545 <unknown>
 
 ld1h    {za0h.h[w15, 7]}, p3/z, [x13, x8, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w15, 7]}, p3/z, [x13, x8, lsl #1]
 // CHECK-ENCODING: [0xa7,0x6d,0x48,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 48 e0 <unknown>
+// CHECK-UNKNOWN: e0486da7 <unknown>
 
 ld1h    {za1h.h[w15, 7]}, p7/z, [sp]
 // CHECK-INST: ld1h    {za1h.h[w15, 7]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0x5f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 5f e0 <unknown>
+// CHECK-UNKNOWN: e05f7fef <unknown>
 
 ld1h    {za0h.h[w12, 5]}, p3/z, [x17, x16, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w12, 5]}, p3/z, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x0e,0x50,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 50 e0 <unknown>
+// CHECK-UNKNOWN: e0500e25 <unknown>
 
 ld1h    {za0h.h[w12, 1]}, p1/z, [x1, x30, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w12, 1]}, p1/z, [x1, x30, lsl #1]
 // CHECK-ENCODING: [0x21,0x04,0x5e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 5e e0 <unknown>
+// CHECK-UNKNOWN: e05e0421 <unknown>
 
 ld1h    {za1h.h[w14, 0]}, p5/z, [x19, x20, lsl #1]
 // CHECK-INST: ld1h    {za1h.h[w14, 0]}, p5/z, [x19, x20, lsl #1]
 // CHECK-ENCODING: [0x68,0x56,0x54,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 54 e0 <unknown>
+// CHECK-UNKNOWN: e0545668 <unknown>
 
 ld1h    {za0h.h[w12, 0]}, p6/z, [x12, x2, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w12, 0]}, p6/z, [x12, x2, lsl #1]
 // CHECK-ENCODING: [0x80,0x19,0x42,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 42 e0 <unknown>
+// CHECK-UNKNOWN: e0421980 <unknown>
 
 ld1h    {za0h.h[w14, 1]}, p2/z, [x1, x26, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w14, 1]}, p2/z, [x1, x26, lsl #1]
 // CHECK-ENCODING: [0x21,0x48,0x5a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 5a e0 <unknown>
+// CHECK-UNKNOWN: e05a4821 <unknown>
 
 ld1h    {za1h.h[w12, 5]}, p2/z, [x22, x30, lsl #1]
 // CHECK-INST: ld1h    {za1h.h[w12, 5]}, p2/z, [x22, x30, lsl #1]
 // CHECK-ENCODING: [0xcd,0x0a,0x5e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 5e e0 <unknown>
+// CHECK-UNKNOWN: e05e0acd <unknown>
 
 ld1h    {za0h.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
 // CHECK-ENCODING: [0x22,0x75,0x41,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 41 e0 <unknown>
+// CHECK-UNKNOWN: e0417522 <unknown>
 
 ld1h    {za0h.h[w13, 7]}, p2/z, [x12, x11, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w13, 7]}, p2/z, [x12, x11, lsl #1]
 // CHECK-ENCODING: [0x87,0x29,0x4b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 4b e0 <unknown>
+// CHECK-UNKNOWN: e04b2987 <unknown>
 
 ld1h    za0h.h[w12, 0], p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x00,0x40,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 40 e0 <unknown>
+// CHECK-UNKNOWN: e0400000 <unknown>
 
 ld1h    za0h.h[w14, 5], p5/z, [x10, x21, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
 // CHECK-ENCODING: [0x45,0x55,0x55,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 55 e0 <unknown>
+// CHECK-UNKNOWN: e0555545 <unknown>
 
 ld1h    za0h.h[w15, 7], p3/z, [x13, x8, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w15, 7]}, p3/z, [x13, x8, lsl #1]
 // CHECK-ENCODING: [0xa7,0x6d,0x48,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 48 e0 <unknown>
+// CHECK-UNKNOWN: e0486da7 <unknown>
 
 ld1h    za1h.h[w15, 7], p7/z, [sp]
 // CHECK-INST: ld1h    {za1h.h[w15, 7]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0x5f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 5f e0 <unknown>
+// CHECK-UNKNOWN: e05f7fef <unknown>
 
 ld1h    za0h.h[w12, 5], p3/z, [x17, x16, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w12, 5]}, p3/z, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x0e,0x50,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 50 e0 <unknown>
+// CHECK-UNKNOWN: e0500e25 <unknown>
 
 ld1h    za0h.h[w12, 1], p1/z, [x1, x30, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w12, 1]}, p1/z, [x1, x30, lsl #1]
 // CHECK-ENCODING: [0x21,0x04,0x5e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 5e e0 <unknown>
+// CHECK-UNKNOWN: e05e0421 <unknown>
 
 ld1h    za1h.h[w14, 0], p5/z, [x19, x20, lsl #1]
 // CHECK-INST: ld1h    {za1h.h[w14, 0]}, p5/z, [x19, x20, lsl #1]
 // CHECK-ENCODING: [0x68,0x56,0x54,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 54 e0 <unknown>
+// CHECK-UNKNOWN: e0545668 <unknown>
 
 ld1h    za0h.h[w12, 0], p6/z, [x12, x2, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w12, 0]}, p6/z, [x12, x2, lsl #1]
 // CHECK-ENCODING: [0x80,0x19,0x42,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 42 e0 <unknown>
+// CHECK-UNKNOWN: e0421980 <unknown>
 
 ld1h    za0h.h[w14, 1], p2/z, [x1, x26, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w14, 1]}, p2/z, [x1, x26, lsl #1]
 // CHECK-ENCODING: [0x21,0x48,0x5a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 5a e0 <unknown>
+// CHECK-UNKNOWN: e05a4821 <unknown>
 
 ld1h    za1h.h[w12, 5], p2/z, [x22, x30, lsl #1]
 // CHECK-INST: ld1h    {za1h.h[w12, 5]}, p2/z, [x22, x30, lsl #1]
 // CHECK-ENCODING: [0xcd,0x0a,0x5e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 5e e0 <unknown>
+// CHECK-UNKNOWN: e05e0acd <unknown>
 
 ld1h    za0h.h[w15, 2], p5/z, [x9, x1, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
 // CHECK-ENCODING: [0x22,0x75,0x41,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 41 e0 <unknown>
+// CHECK-UNKNOWN: e0417522 <unknown>
 
 ld1h    za0h.h[w13, 7], p2/z, [x12, x11, lsl #1]
 // CHECK-INST: ld1h    {za0h.h[w13, 7]}, p2/z, [x12, x11, lsl #1]
 // CHECK-ENCODING: [0x87,0x29,0x4b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 4b e0 <unknown>
+// CHECK-UNKNOWN: e04b2987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Vertical
@@ -166,142 +166,142 @@ ld1h    {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x80,0x40,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 40 e0 <unknown>
+// CHECK-UNKNOWN: e0408000 <unknown>
 
 ld1h    {za0v.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
 // CHECK-ENCODING: [0x45,0xd5,0x55,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 55 e0 <unknown>
+// CHECK-UNKNOWN: e055d545 <unknown>
 
 ld1h    {za0v.h[w15, 7]}, p3/z, [x13, x8, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w15, 7]}, p3/z, [x13, x8, lsl #1]
 // CHECK-ENCODING: [0xa7,0xed,0x48,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 48 e0 <unknown>
+// CHECK-UNKNOWN: e048eda7 <unknown>
 
 ld1h    {za1v.h[w15, 7]}, p7/z, [sp]
 // CHECK-INST: ld1h    {za1v.h[w15, 7]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0xff,0x5f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 5f e0 <unknown>
+// CHECK-UNKNOWN: e05fffef <unknown>
 
 ld1h    {za0v.h[w12, 5]}, p3/z, [x17, x16, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w12, 5]}, p3/z, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x8e,0x50,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 50 e0 <unknown>
+// CHECK-UNKNOWN: e0508e25 <unknown>
 
 ld1h    {za0v.h[w12, 1]}, p1/z, [x1, x30, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w12, 1]}, p1/z, [x1, x30, lsl #1]
 // CHECK-ENCODING: [0x21,0x84,0x5e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 5e e0 <unknown>
+// CHECK-UNKNOWN: e05e8421 <unknown>
 
 ld1h    {za1v.h[w14, 0]}, p5/z, [x19, x20, lsl #1]
 // CHECK-INST: ld1h    {za1v.h[w14, 0]}, p5/z, [x19, x20, lsl #1]
 // CHECK-ENCODING: [0x68,0xd6,0x54,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 54 e0 <unknown>
+// CHECK-UNKNOWN: e054d668 <unknown>
 
 ld1h    {za0v.h[w12, 0]}, p6/z, [x12, x2, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w12, 0]}, p6/z, [x12, x2, lsl #1]
 // CHECK-ENCODING: [0x80,0x99,0x42,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 42 e0 <unknown>
+// CHECK-UNKNOWN: e0429980 <unknown>
 
 ld1h    {za0v.h[w14, 1]}, p2/z, [x1, x26, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w14, 1]}, p2/z, [x1, x26, lsl #1]
 // CHECK-ENCODING: [0x21,0xc8,0x5a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 5a e0 <unknown>
+// CHECK-UNKNOWN: e05ac821 <unknown>
 
 ld1h    {za1v.h[w12, 5]}, p2/z, [x22, x30, lsl #1]
 // CHECK-INST: ld1h    {za1v.h[w12, 5]}, p2/z, [x22, x30, lsl #1]
 // CHECK-ENCODING: [0xcd,0x8a,0x5e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 5e e0 <unknown>
+// CHECK-UNKNOWN: e05e8acd <unknown>
 
 ld1h    {za0v.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
 // CHECK-ENCODING: [0x22,0xf5,0x41,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 41 e0 <unknown>
+// CHECK-UNKNOWN: e041f522 <unknown>
 
 ld1h    {za0v.h[w13, 7]}, p2/z, [x12, x11, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w13, 7]}, p2/z, [x12, x11, lsl #1]
 // CHECK-ENCODING: [0x87,0xa9,0x4b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 4b e0 <unknown>
+// CHECK-UNKNOWN: e04ba987 <unknown>
 
 ld1h    za0v.h[w12, 0], p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x80,0x40,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 40 e0 <unknown>
+// CHECK-UNKNOWN: e0408000 <unknown>
 
 ld1h    za0v.h[w14, 5], p5/z, [x10, x21, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w14, 5]}, p5/z, [x10, x21, lsl #1]
 // CHECK-ENCODING: [0x45,0xd5,0x55,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 55 e0 <unknown>
+// CHECK-UNKNOWN: e055d545 <unknown>
 
 ld1h    za0v.h[w15, 7], p3/z, [x13, x8, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w15, 7]}, p3/z, [x13, x8, lsl #1]
 // CHECK-ENCODING: [0xa7,0xed,0x48,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 48 e0 <unknown>
+// CHECK-UNKNOWN: e048eda7 <unknown>
 
 ld1h    za1v.h[w15, 7], p7/z, [sp]
 // CHECK-INST: ld1h    {za1v.h[w15, 7]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0xff,0x5f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 5f e0 <unknown>
+// CHECK-UNKNOWN: e05fffef <unknown>
 
 ld1h    za0v.h[w12, 5], p3/z, [x17, x16, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w12, 5]}, p3/z, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x8e,0x50,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 50 e0 <unknown>
+// CHECK-UNKNOWN: e0508e25 <unknown>
 
 ld1h    za0v.h[w12, 1], p1/z, [x1, x30, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w12, 1]}, p1/z, [x1, x30, lsl #1]
 // CHECK-ENCODING: [0x21,0x84,0x5e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 5e e0 <unknown>
+// CHECK-UNKNOWN: e05e8421 <unknown>
 
 ld1h    za1v.h[w14, 0], p5/z, [x19, x20, lsl #1]
 // CHECK-INST: ld1h    {za1v.h[w14, 0]}, p5/z, [x19, x20, lsl #1]
 // CHECK-ENCODING: [0x68,0xd6,0x54,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 54 e0 <unknown>
+// CHECK-UNKNOWN: e054d668 <unknown>
 
 ld1h    za0v.h[w12, 0], p6/z, [x12, x2, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w12, 0]}, p6/z, [x12, x2, lsl #1]
 // CHECK-ENCODING: [0x80,0x99,0x42,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 42 e0 <unknown>
+// CHECK-UNKNOWN: e0429980 <unknown>
 
 ld1h    za0v.h[w14, 1], p2/z, [x1, x26, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w14, 1]}, p2/z, [x1, x26, lsl #1]
 // CHECK-ENCODING: [0x21,0xc8,0x5a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 5a e0 <unknown>
+// CHECK-UNKNOWN: e05ac821 <unknown>
 
 ld1h    za1v.h[w12, 5], p2/z, [x22, x30, lsl #1]
 // CHECK-INST: ld1h    {za1v.h[w12, 5]}, p2/z, [x22, x30, lsl #1]
 // CHECK-ENCODING: [0xcd,0x8a,0x5e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 5e e0 <unknown>
+// CHECK-UNKNOWN: e05e8acd <unknown>
 
 ld1h    za0v.h[w15, 2], p5/z, [x9, x1, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w15, 2]}, p5/z, [x9, x1, lsl #1]
 // CHECK-ENCODING: [0x22,0xf5,0x41,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 41 e0 <unknown>
+// CHECK-UNKNOWN: e041f522 <unknown>
 
 ld1h    za0v.h[w13, 7], p2/z, [x12, x11, lsl #1]
 // CHECK-INST: ld1h    {za0v.h[w13, 7]}, p2/z, [x12, x11, lsl #1]
 // CHECK-ENCODING: [0x87,0xa9,0x4b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 4b e0 <unknown>
+// CHECK-UNKNOWN: e04ba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/ld1q.s b/llvm/test/MC/AArch64/SME/ld1q.s
index b3072ad22074b..ea4aeebd798fe 100644
--- a/llvm/test/MC/AArch64/SME/ld1q.s
+++ b/llvm/test/MC/AArch64/SME/ld1q.s
@@ -19,145 +19,145 @@ ld1q    {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
 // CHECK-INST: ld1q    {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
 // CHECK-ENCODING: [0x00,0x00,0xc0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 c0 e1 <unknown>
+// CHECK-UNKNOWN: e1c00000 <unknown>
 
 ld1q    {za5h.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
 // CHECK-INST: ld1q    {za5h.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
 // CHECK-ENCODING: [0x45,0x55,0xd5,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 d5 e1 <unknown>
+// CHECK-UNKNOWN: e1d55545 <unknown>
 
 ld1q    {za7h.q[w15, 0]}, p3/z, [x13, x8, lsl #4]
 // CHECK-INST: ld1q    {za7h.q[w15, 0]}, p3/z, [x13, x8, lsl #4]
 // CHECK-ENCODING: [0xa7,0x6d,0xc8,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d c8 e1 <unknown>
+// CHECK-UNKNOWN: e1c86da7 <unknown>
 
 ld1q    {za15h.q[w15, 0]}, p7/z, [sp]
 // CHECK-INST: ld1q    {za15h.q[w15, 0]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0xdf,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f df e1 <unknown>
+// CHECK-UNKNOWN: e1df7fef <unknown>
 
 ld1q    {za5h.q[w12, 0]}, p3/z, [x17, x16, lsl #4]
 // CHECK-INST: ld1q    {za5h.q[w12, 0]}, p3/z, [x17, x16, lsl #4]
 // CHECK-ENCODING: [0x25,0x0e,0xd0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e d0 e1 <unknown>
+// CHECK-UNKNOWN: e1d00e25 <unknown>
 
 ld1q    {za1h.q[w12, 0]}, p1/z, [x1, x30, lsl #4]
 // CHECK-INST: ld1q    {za1h.q[w12, 0]}, p1/z, [x1, x30, lsl #4]
 // CHECK-ENCODING: [0x21,0x04,0xde,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 de e1 <unknown>
+// CHECK-UNKNOWN: e1de0421 <unknown>
 
 ld1q    {za8h.q[w14, 0]}, p5/z, [x19, x20, lsl #4]
 // CHECK-INST: ld1q    {za8h.q[w14, 0]}, p5/z, [x19, x20, lsl #4]
 // CHECK-ENCODING: [0x68,0x56,0xd4,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 d4 e1 <unknown>
+// CHECK-UNKNOWN: e1d45668 <unknown>
 
 ld1q    {za0h.q[w12, 0]}, p6/z, [x12, x2, lsl #4]
 // CHECK-INST: ld1q    {za0h.q[w12, 0]}, p6/z, [x12, x2, lsl #4]
 // CHECK-ENCODING: [0x80,0x19,0xc2,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 c2 e1 <unknown>
+// CHECK-UNKNOWN: e1c21980 <unknown>
 
 ld1q    {za1h.q[w14, 0]}, p2/z, [x1, x26, lsl #4]
 // CHECK-INST: ld1q    {za1h.q[w14, 0]}, p2/z, [x1, x26, lsl #4]
 // CHECK-ENCODING: [0x21,0x48,0xda,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 da e1 <unknown>
+// CHECK-UNKNOWN: e1da4821 <unknown>
 
 ld1q    {za13h.q[w12, 0]}, p2/z, [x22, x30, lsl #4]
 // CHECK-INST: ld1q    {za13h.q[w12, 0]}, p2/z, [x22, x30, lsl #4]
 // CHECK-ENCODING: [0xcd,0x0a,0xde,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a de e1 <unknown>
+// CHECK-UNKNOWN: e1de0acd <unknown>
 
 ld1q    {za2h.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
 // CHECK-INST: ld1q    {za2h.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
 // CHECK-ENCODING: [0x22,0x75,0xc1,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 c1 e1 <unknown>
+// CHECK-UNKNOWN: e1c17522 <unknown>
 
 ld1q    {za7h.q[w13, 0]}, p2/z, [x12, x11, lsl #4]
 // CHECK-INST: ld1q    {za7h.q[w13, 0]}, p2/z, [x12, x11, lsl #4]
 // CHECK-ENCODING: [0x87,0x29,0xcb,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 cb e1 <unknown>
+// CHECK-UNKNOWN: e1cb2987 <unknown>
 
 ld1q    za0h.q[w12, 0], p0/z, [x0, x0, lsl #4]
 // CHECK-INST: ld1q    {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
 // CHECK-ENCODING: [0x00,0x00,0xc0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 c0 e1 <unknown>
+// CHECK-UNKNOWN: e1c00000 <unknown>
 
 ld1q    za5h.q[w14, 0], p5/z, [x10, x21, lsl #4]
 // CHECK-INST: ld1q    {za5h.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
 // CHECK-ENCODING: [0x45,0x55,0xd5,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 d5 e1 <unknown>
+// CHECK-UNKNOWN: e1d55545 <unknown>
 
 ld1q    za7h.q[w15, 0], p3/z, [x13, x8, lsl #4]
 // CHECK-INST: ld1q    {za7h.q[w15, 0]}, p3/z, [x13, x8, lsl #4]
 // CHECK-ENCODING: [0xa7,0x6d,0xc8,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d c8 e1 <unknown>
+// CHECK-UNKNOWN: e1c86da7 <unknown>
 
 ld1q    za15h.q[w15, 0], p7/z, [sp]
 // CHECK-INST: ld1q    {za15h.q[w15, 0]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0xdf,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f df e1 <unknown>
+// CHECK-UNKNOWN: e1df7fef <unknown>
 
 ld1q    za5h.q[w12, 0], p3/z, [x17, x16, lsl #4]
 // CHECK-INST: ld1q    {za5h.q[w12, 0]}, p3/z, [x17, x16, lsl #4]
 // CHECK-ENCODING: [0x25,0x0e,0xd0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e d0 e1 <unknown>
+// CHECK-UNKNOWN: e1d00e25 <unknown>
 
 ld1q    za1h.q[w12, 0], p1/z, [x1, x30, lsl #4]
 // CHECK-INST: ld1q    {za1h.q[w12, 0]}, p1/z, [x1, x30, lsl #4]
 // CHECK-ENCODING: [0x21,0x04,0xde,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 de e1 <unknown>
+// CHECK-UNKNOWN: e1de0421 <unknown>
 
 ld1q    za8h.q[w14, 0], p5/z, [x19, x20, lsl #4]
 // CHECK-INST: ld1q    {za8h.q[w14, 0]}, p5/z, [x19, x20, lsl #4]
 // CHECK-ENCODING: [0x68,0x56,0xd4,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 d4 e1 <unknown>
+// CHECK-UNKNOWN: e1d45668 <unknown>
 
 ld1q    za0h.q[w12, 0], p6/z, [x12, x2, lsl #4]
 // CHECK-INST: ld1q    {za0h.q[w12, 0]}, p6/z, [x12, x2, lsl #4]
 // CHECK-ENCODING: [0x80,0x19,0xc2,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 c2 e1 <unknown>
+// CHECK-UNKNOWN: e1c21980 <unknown>
 
 ld1q    za1h.q[w14, 0], p2/z, [x1, x26, lsl #4]
 // CHECK-INST: ld1q    {za1h.q[w14, 0]}, p2/z, [x1, x26, lsl #4]
 // CHECK-ENCODING: [0x21,0x48,0xda,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 da e1 <unknown>
+// CHECK-UNKNOWN: e1da4821 <unknown>
 
 ld1q    za13h.q[w12, 0], p2/z, [x22, x30, lsl #4]
 // CHECK-INST: ld1q    {za13h.q[w12, 0]}, p2/z, [x22, x30, lsl #4]
 // CHECK-ENCODING: [0xcd,0x0a,0xde,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a de e1 <unknown>
+// CHECK-UNKNOWN: e1de0acd <unknown>
 
 ld1q    za2h.q[w15, 0], p5/z, [x9, x1, lsl #4]
 // CHECK-INST: ld1q    {za2h.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
 // CHECK-ENCODING: [0x22,0x75,0xc1,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 c1 e1 <unknown>
+// CHECK-UNKNOWN: e1c17522 <unknown>
 
 ld1q    za7h.q[w13, 0], p2/z, [x12, x11, lsl #4]
 // CHECK-INST: ld1q    {za7h.q[w13, 0]}, p2/z, [x12, x11, lsl #4]
 // CHECK-ENCODING: [0x87,0x29,0xcb,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 cb e1 <unknown>
+// CHECK-UNKNOWN: e1cb2987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Vertical
@@ -166,142 +166,142 @@ ld1q    {za0v.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
 // CHECK-INST: ld1q    {za0v.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
 // CHECK-ENCODING: [0x00,0x80,0xc0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 c0 e1 <unknown>
+// CHECK-UNKNOWN: e1c08000 <unknown>
 
 ld1q    {za5v.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
 // CHECK-INST: ld1q    {za5v.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
 // CHECK-ENCODING: [0x45,0xd5,0xd5,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 d5 e1 <unknown>
+// CHECK-UNKNOWN: e1d5d545 <unknown>
 
 ld1q    {za7v.q[w15, 0]}, p3/z, [x13, x8, lsl #4]
 // CHECK-INST: ld1q    {za7v.q[w15, 0]}, p3/z, [x13, x8, lsl #4]
 // CHECK-ENCODING: [0xa7,0xed,0xc8,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed c8 e1 <unknown>
+// CHECK-UNKNOWN: e1c8eda7 <unknown>
 
 ld1q    {za15v.q[w15, 0]}, p7/z, [sp]
 // CHECK-INST: ld1q    {za15v.q[w15, 0]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0xff,0xdf,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff df e1 <unknown>
+// CHECK-UNKNOWN: e1dfffef <unknown>
 
 ld1q    {za5v.q[w12, 0]}, p3/z, [x17, x16, lsl #4]
 // CHECK-INST: ld1q    {za5v.q[w12, 0]}, p3/z, [x17, x16, lsl #4]
 // CHECK-ENCODING: [0x25,0x8e,0xd0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e d0 e1 <unknown>
+// CHECK-UNKNOWN: e1d08e25 <unknown>
 
 ld1q    {za1v.q[w12, 0]}, p1/z, [x1, x30, lsl #4]
 // CHECK-INST: ld1q    {za1v.q[w12, 0]}, p1/z, [x1, x30, lsl #4]
 // CHECK-ENCODING: [0x21,0x84,0xde,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 de e1 <unknown>
+// CHECK-UNKNOWN: e1de8421 <unknown>
 
 ld1q    {za8v.q[w14, 0]}, p5/z, [x19, x20, lsl #4]
 // CHECK-INST: ld1q    {za8v.q[w14, 0]}, p5/z, [x19, x20, lsl #4]
 // CHECK-ENCODING: [0x68,0xd6,0xd4,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 d4 e1 <unknown>
+// CHECK-UNKNOWN: e1d4d668 <unknown>
 
 ld1q    {za0v.q[w12, 0]}, p6/z, [x12, x2, lsl #4]
 // CHECK-INST: ld1q    {za0v.q[w12, 0]}, p6/z, [x12, x2, lsl #4]
 // CHECK-ENCODING: [0x80,0x99,0xc2,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 c2 e1 <unknown>
+// CHECK-UNKNOWN: e1c29980 <unknown>
 
 ld1q    {za1v.q[w14, 0]}, p2/z, [x1, x26, lsl #4]
 // CHECK-INST: ld1q    {za1v.q[w14, 0]}, p2/z, [x1, x26, lsl #4]
 // CHECK-ENCODING: [0x21,0xc8,0xda,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 da e1 <unknown>
+// CHECK-UNKNOWN: e1dac821 <unknown>
 
 ld1q    {za13v.q[w12, 0]}, p2/z, [x22, x30, lsl #4]
 // CHECK-INST: ld1q    {za13v.q[w12, 0]}, p2/z, [x22, x30, lsl #4]
 // CHECK-ENCODING: [0xcd,0x8a,0xde,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a de e1 <unknown>
+// CHECK-UNKNOWN: e1de8acd <unknown>
 
 ld1q    {za2v.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
 // CHECK-INST: ld1q    {za2v.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
 // CHECK-ENCODING: [0x22,0xf5,0xc1,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 c1 e1 <unknown>
+// CHECK-UNKNOWN: e1c1f522 <unknown>
 
 ld1q    {za7v.q[w13, 0]}, p2/z, [x12, x11, lsl #4]
 // CHECK-INST: ld1q    {za7v.q[w13, 0]}, p2/z, [x12, x11, lsl #4]
 // CHECK-ENCODING: [0x87,0xa9,0xcb,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 cb e1 <unknown>
+// CHECK-UNKNOWN: e1cba987 <unknown>
 
 ld1q    za0v.q[w12, 0], p0/z, [x0, x0, lsl #4]
 // CHECK-INST: ld1q    {za0v.q[w12, 0]}, p0/z, [x0, x0, lsl #4]
 // CHECK-ENCODING: [0x00,0x80,0xc0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 c0 e1 <unknown>
+// CHECK-UNKNOWN: e1c08000 <unknown>
 
 ld1q    za5v.q[w14, 0], p5/z, [x10, x21, lsl #4]
 // CHECK-INST: ld1q    {za5v.q[w14, 0]}, p5/z, [x10, x21, lsl #4]
 // CHECK-ENCODING: [0x45,0xd5,0xd5,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 d5 e1 <unknown>
+// CHECK-UNKNOWN: e1d5d545 <unknown>
 
 ld1q    za7v.q[w15, 0], p3/z, [x13, x8, lsl #4]
 // CHECK-INST: ld1q    {za7v.q[w15, 0]}, p3/z, [x13, x8, lsl #4]
 // CHECK-ENCODING: [0xa7,0xed,0xc8,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed c8 e1 <unknown>
+// CHECK-UNKNOWN: e1c8eda7 <unknown>
 
 ld1q    za15v.q[w15, 0], p7/z, [sp]
 // CHECK-INST: ld1q    {za15v.q[w15, 0]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0xff,0xdf,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff df e1 <unknown>
+// CHECK-UNKNOWN: e1dfffef <unknown>
 
 ld1q    za5v.q[w12, 0], p3/z, [x17, x16, lsl #4]
 // CHECK-INST: ld1q    {za5v.q[w12, 0]}, p3/z, [x17, x16, lsl #4]
 // CHECK-ENCODING: [0x25,0x8e,0xd0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e d0 e1 <unknown>
+// CHECK-UNKNOWN: e1d08e25 <unknown>
 
 ld1q    za1v.q[w12, 0], p1/z, [x1, x30, lsl #4]
 // CHECK-INST: ld1q    {za1v.q[w12, 0]}, p1/z, [x1, x30, lsl #4]
 // CHECK-ENCODING: [0x21,0x84,0xde,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 de e1 <unknown>
+// CHECK-UNKNOWN: e1de8421 <unknown>
 
 ld1q    za8v.q[w14, 0], p5/z, [x19, x20, lsl #4]
 // CHECK-INST: ld1q    {za8v.q[w14, 0]}, p5/z, [x19, x20, lsl #4]
 // CHECK-ENCODING: [0x68,0xd6,0xd4,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 d4 e1 <unknown>
+// CHECK-UNKNOWN: e1d4d668 <unknown>
 
 ld1q    za0v.q[w12, 0], p6/z, [x12, x2, lsl #4]
 // CHECK-INST: ld1q    {za0v.q[w12, 0]}, p6/z, [x12, x2, lsl #4]
 // CHECK-ENCODING: [0x80,0x99,0xc2,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 c2 e1 <unknown>
+// CHECK-UNKNOWN: e1c29980 <unknown>
 
 ld1q    za1v.q[w14, 0], p2/z, [x1, x26, lsl #4]
 // CHECK-INST: ld1q    {za1v.q[w14, 0]}, p2/z, [x1, x26, lsl #4]
 // CHECK-ENCODING: [0x21,0xc8,0xda,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 da e1 <unknown>
+// CHECK-UNKNOWN: e1dac821 <unknown>
 
 ld1q    za13v.q[w12, 0], p2/z, [x22, x30, lsl #4]
 // CHECK-INST: ld1q    {za13v.q[w12, 0]}, p2/z, [x22, x30, lsl #4]
 // CHECK-ENCODING: [0xcd,0x8a,0xde,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a de e1 <unknown>
+// CHECK-UNKNOWN: e1de8acd <unknown>
 
 ld1q    za2v.q[w15, 0], p5/z, [x9, x1, lsl #4]
 // CHECK-INST: ld1q    {za2v.q[w15, 0]}, p5/z, [x9, x1, lsl #4]
 // CHECK-ENCODING: [0x22,0xf5,0xc1,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 c1 e1 <unknown>
+// CHECK-UNKNOWN: e1c1f522 <unknown>
 
 ld1q    za7v.q[w13, 0], p2/z, [x12, x11, lsl #4]
 // CHECK-INST: ld1q    {za7v.q[w13, 0]}, p2/z, [x12, x11, lsl #4]
 // CHECK-ENCODING: [0x87,0xa9,0xcb,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 cb e1 <unknown>
+// CHECK-UNKNOWN: e1cba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/ld1w.s b/llvm/test/MC/AArch64/SME/ld1w.s
index 1a76c621d297e..099f439849576 100644
--- a/llvm/test/MC/AArch64/SME/ld1w.s
+++ b/llvm/test/MC/AArch64/SME/ld1w.s
@@ -19,145 +19,145 @@ ld1w    {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ld1w    {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x00,0x80,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 80 e0 <unknown>
+// CHECK-UNKNOWN: e0800000 <unknown>
 
 ld1w    {za1h.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
 // CHECK-INST: ld1w    {za1h.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
 // CHECK-ENCODING: [0x45,0x55,0x95,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 95 e0 <unknown>
+// CHECK-UNKNOWN: e0955545 <unknown>
 
 ld1w    {za1h.s[w15, 3]}, p3/z, [x13, x8, lsl #2]
 // CHECK-INST: ld1w    {za1h.s[w15, 3]}, p3/z, [x13, x8, lsl #2]
 // CHECK-ENCODING: [0xa7,0x6d,0x88,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 88 e0 <unknown>
+// CHECK-UNKNOWN: e0886da7 <unknown>
 
 ld1w    {za3h.s[w15, 3]}, p7/z, [sp]
 // CHECK-INST: ld1w    {za3h.s[w15, 3]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0x9f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 9f e0 <unknown>
+// CHECK-UNKNOWN: e09f7fef <unknown>
 
 ld1w    {za1h.s[w12, 1]}, p3/z, [x17, x16, lsl #2]
 // CHECK-INST: ld1w    {za1h.s[w12, 1]}, p3/z, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0x0e,0x90,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 90 e0 <unknown>
+// CHECK-UNKNOWN: e0900e25 <unknown>
 
 ld1w    {za0h.s[w12, 1]}, p1/z, [x1, x30, lsl #2]
 // CHECK-INST: ld1w    {za0h.s[w12, 1]}, p1/z, [x1, x30, lsl #2]
 // CHECK-ENCODING: [0x21,0x04,0x9e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 9e e0 <unknown>
+// CHECK-UNKNOWN: e09e0421 <unknown>
 
 ld1w    {za2h.s[w14, 0]}, p5/z, [x19, x20, lsl #2]
 // CHECK-INST: ld1w    {za2h.s[w14, 0]}, p5/z, [x19, x20, lsl #2]
 // CHECK-ENCODING: [0x68,0x56,0x94,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 94 e0 <unknown>
+// CHECK-UNKNOWN: e0945668 <unknown>
 
 ld1w    {za0h.s[w12, 0]}, p6/z, [x12, x2, lsl #2]
 // CHECK-INST: ld1w    {za0h.s[w12, 0]}, p6/z, [x12, x2, lsl #2]
 // CHECK-ENCODING: [0x80,0x19,0x82,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 82 e0 <unknown>
+// CHECK-UNKNOWN: e0821980 <unknown>
 
 ld1w    {za0h.s[w14, 1]}, p2/z, [x1, x26, lsl #2]
 // CHECK-INST: ld1w    {za0h.s[w14, 1]}, p2/z, [x1, x26, lsl #2]
 // CHECK-ENCODING: [0x21,0x48,0x9a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 9a e0 <unknown>
+// CHECK-UNKNOWN: e09a4821 <unknown>
 
 ld1w    {za3h.s[w12, 1]}, p2/z, [x22, x30, lsl #2]
 // CHECK-INST: ld1w    {za3h.s[w12, 1]}, p2/z, [x22, x30, lsl #2]
 // CHECK-ENCODING: [0xcd,0x0a,0x9e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 9e e0 <unknown>
+// CHECK-UNKNOWN: e09e0acd <unknown>
 
 ld1w    {za0h.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
 // CHECK-INST: ld1w    {za0h.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
 // CHECK-ENCODING: [0x22,0x75,0x81,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 81 e0 <unknown>
+// CHECK-UNKNOWN: e0817522 <unknown>
 
 ld1w    {za1h.s[w13, 3]}, p2/z, [x12, x11, lsl #2]
 // CHECK-INST: ld1w    {za1h.s[w13, 3]}, p2/z, [x12, x11, lsl #2]
 // CHECK-ENCODING: [0x87,0x29,0x8b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 8b e0 <unknown>
+// CHECK-UNKNOWN: e08b2987 <unknown>
 
 ld1w    za0h.s[w12, 0], p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ld1w    {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x00,0x80,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 80 e0 <unknown>
+// CHECK-UNKNOWN: e0800000 <unknown>
 
 ld1w    za1h.s[w14, 1], p5/z, [x10, x21, lsl #2]
 // CHECK-INST: ld1w    {za1h.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
 // CHECK-ENCODING: [0x45,0x55,0x95,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 95 e0 <unknown>
+// CHECK-UNKNOWN: e0955545 <unknown>
 
 ld1w    za1h.s[w15, 3], p3/z, [x13, x8, lsl #2]
 // CHECK-INST: ld1w    {za1h.s[w15, 3]}, p3/z, [x13, x8, lsl #2]
 // CHECK-ENCODING: [0xa7,0x6d,0x88,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 88 e0 <unknown>
+// CHECK-UNKNOWN: e0886da7 <unknown>
 
 ld1w    za3h.s[w15, 3], p7/z, [sp]
 // CHECK-INST: ld1w    {za3h.s[w15, 3]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0x9f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 9f e0 <unknown>
+// CHECK-UNKNOWN: e09f7fef <unknown>
 
 ld1w    za1h.s[w12, 1], p3/z, [x17, x16, lsl #2]
 // CHECK-INST: ld1w    {za1h.s[w12, 1]}, p3/z, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0x0e,0x90,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 90 e0 <unknown>
+// CHECK-UNKNOWN: e0900e25 <unknown>
 
 ld1w    za0h.s[w12, 1], p1/z, [x1, x30, lsl #2]
 // CHECK-INST: ld1w    {za0h.s[w12, 1]}, p1/z, [x1, x30, lsl #2]
 // CHECK-ENCODING: [0x21,0x04,0x9e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 9e e0 <unknown>
+// CHECK-UNKNOWN: e09e0421 <unknown>
 
 ld1w    za2h.s[w14, 0], p5/z, [x19, x20, lsl #2]
 // CHECK-INST: ld1w    {za2h.s[w14, 0]}, p5/z, [x19, x20, lsl #2]
 // CHECK-ENCODING: [0x68,0x56,0x94,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 94 e0 <unknown>
+// CHECK-UNKNOWN: e0945668 <unknown>
 
 ld1w    za0h.s[w12, 0], p6/z, [x12, x2, lsl #2]
 // CHECK-INST: ld1w    {za0h.s[w12, 0]}, p6/z, [x12, x2, lsl #2]
 // CHECK-ENCODING: [0x80,0x19,0x82,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 82 e0 <unknown>
+// CHECK-UNKNOWN: e0821980 <unknown>
 
 ld1w    za0h.s[w14, 1], p2/z, [x1, x26, lsl #2]
 // CHECK-INST: ld1w    {za0h.s[w14, 1]}, p2/z, [x1, x26, lsl #2]
 // CHECK-ENCODING: [0x21,0x48,0x9a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 9a e0 <unknown>
+// CHECK-UNKNOWN: e09a4821 <unknown>
 
 ld1w    za3h.s[w12, 1], p2/z, [x22, x30, lsl #2]
 // CHECK-INST: ld1w    {za3h.s[w12, 1]}, p2/z, [x22, x30, lsl #2]
 // CHECK-ENCODING: [0xcd,0x0a,0x9e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 9e e0 <unknown>
+// CHECK-UNKNOWN: e09e0acd <unknown>
 
 ld1w    za0h.s[w15, 2], p5/z, [x9, x1, lsl #2]
 // CHECK-INST: ld1w    {za0h.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
 // CHECK-ENCODING: [0x22,0x75,0x81,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 81 e0 <unknown>
+// CHECK-UNKNOWN: e0817522 <unknown>
 
 ld1w    za1h.s[w13, 3], p2/z, [x12, x11, lsl #2]
 // CHECK-INST: ld1w    {za1h.s[w13, 3]}, p2/z, [x12, x11, lsl #2]
 // CHECK-ENCODING: [0x87,0x29,0x8b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 8b e0 <unknown>
+// CHECK-UNKNOWN: e08b2987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Vertical
@@ -166,142 +166,142 @@ ld1w    {za0v.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ld1w    {za0v.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x80,0x80,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 80 e0 <unknown>
+// CHECK-UNKNOWN: e0808000 <unknown>
 
 ld1w    {za1v.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
 // CHECK-INST: ld1w    {za1v.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
 // CHECK-ENCODING: [0x45,0xd5,0x95,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 95 e0 <unknown>
+// CHECK-UNKNOWN: e095d545 <unknown>
 
 ld1w    {za1v.s[w15, 3]}, p3/z, [x13, x8, lsl #2]
 // CHECK-INST: ld1w    {za1v.s[w15, 3]}, p3/z, [x13, x8, lsl #2]
 // CHECK-ENCODING: [0xa7,0xed,0x88,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 88 e0 <unknown>
+// CHECK-UNKNOWN: e088eda7 <unknown>
 
 ld1w    {za3v.s[w15, 3]}, p7/z, [sp]
 // CHECK-INST: ld1w    {za3v.s[w15, 3]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0xff,0x9f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 9f e0 <unknown>
+// CHECK-UNKNOWN: e09fffef <unknown>
 
 ld1w    {za1v.s[w12, 1]}, p3/z, [x17, x16, lsl #2]
 // CHECK-INST: ld1w    {za1v.s[w12, 1]}, p3/z, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0x8e,0x90,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 90 e0 <unknown>
+// CHECK-UNKNOWN: e0908e25 <unknown>
 
 ld1w    {za0v.s[w12, 1]}, p1/z, [x1, x30, lsl #2]
 // CHECK-INST: ld1w    {za0v.s[w12, 1]}, p1/z, [x1, x30, lsl #2]
 // CHECK-ENCODING: [0x21,0x84,0x9e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 9e e0 <unknown>
+// CHECK-UNKNOWN: e09e8421 <unknown>
 
 ld1w    {za2v.s[w14, 0]}, p5/z, [x19, x20, lsl #2]
 // CHECK-INST: ld1w    {za2v.s[w14, 0]}, p5/z, [x19, x20, lsl #2]
 // CHECK-ENCODING: [0x68,0xd6,0x94,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 94 e0 <unknown>
+// CHECK-UNKNOWN: e094d668 <unknown>
 
 ld1w    {za0v.s[w12, 0]}, p6/z, [x12, x2, lsl #2]
 // CHECK-INST: ld1w    {za0v.s[w12, 0]}, p6/z, [x12, x2, lsl #2]
 // CHECK-ENCODING: [0x80,0x99,0x82,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 82 e0 <unknown>
+// CHECK-UNKNOWN: e0829980 <unknown>
 
 ld1w    {za0v.s[w14, 1]}, p2/z, [x1, x26, lsl #2]
 // CHECK-INST: ld1w    {za0v.s[w14, 1]}, p2/z, [x1, x26, lsl #2]
 // CHECK-ENCODING: [0x21,0xc8,0x9a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 9a e0 <unknown>
+// CHECK-UNKNOWN: e09ac821 <unknown>
 
 ld1w    {za3v.s[w12, 1]}, p2/z, [x22, x30, lsl #2]
 // CHECK-INST: ld1w    {za3v.s[w12, 1]}, p2/z, [x22, x30, lsl #2]
 // CHECK-ENCODING: [0xcd,0x8a,0x9e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 9e e0 <unknown>
+// CHECK-UNKNOWN: e09e8acd <unknown>
 
 ld1w    {za0v.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
 // CHECK-INST: ld1w    {za0v.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
 // CHECK-ENCODING: [0x22,0xf5,0x81,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 81 e0 <unknown>
+// CHECK-UNKNOWN: e081f522 <unknown>
 
 ld1w    {za1v.s[w13, 3]}, p2/z, [x12, x11, lsl #2]
 // CHECK-INST: ld1w    {za1v.s[w13, 3]}, p2/z, [x12, x11, lsl #2]
 // CHECK-ENCODING: [0x87,0xa9,0x8b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 8b e0 <unknown>
+// CHECK-UNKNOWN: e08ba987 <unknown>
 
 ld1w    za0v.s[w12, 0], p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ld1w    {za0v.s[w12, 0]}, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x80,0x80,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 80 e0 <unknown>
+// CHECK-UNKNOWN: e0808000 <unknown>
 
 ld1w    za1v.s[w14, 1], p5/z, [x10, x21, lsl #2]
 // CHECK-INST: ld1w    {za1v.s[w14, 1]}, p5/z, [x10, x21, lsl #2]
 // CHECK-ENCODING: [0x45,0xd5,0x95,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 95 e0 <unknown>
+// CHECK-UNKNOWN: e095d545 <unknown>
 
 ld1w    za1v.s[w15, 3], p3/z, [x13, x8, lsl #2]
 // CHECK-INST: ld1w    {za1v.s[w15, 3]}, p3/z, [x13, x8, lsl #2]
 // CHECK-ENCODING: [0xa7,0xed,0x88,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 88 e0 <unknown>
+// CHECK-UNKNOWN: e088eda7 <unknown>
 
 ld1w    za3v.s[w15, 3], p7/z, [sp]
 // CHECK-INST: ld1w    {za3v.s[w15, 3]}, p7/z, [sp]
 // CHECK-ENCODING: [0xef,0xff,0x9f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 9f e0 <unknown>
+// CHECK-UNKNOWN: e09fffef <unknown>
 
 ld1w    za1v.s[w12, 1], p3/z, [x17, x16, lsl #2]
 // CHECK-INST: ld1w    {za1v.s[w12, 1]}, p3/z, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0x8e,0x90,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 90 e0 <unknown>
+// CHECK-UNKNOWN: e0908e25 <unknown>
 
 ld1w    za0v.s[w12, 1], p1/z, [x1, x30, lsl #2]
 // CHECK-INST: ld1w    {za0v.s[w12, 1]}, p1/z, [x1, x30, lsl #2]
 // CHECK-ENCODING: [0x21,0x84,0x9e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 9e e0 <unknown>
+// CHECK-UNKNOWN: e09e8421 <unknown>
 
 ld1w    za2v.s[w14, 0], p5/z, [x19, x20, lsl #2]
 // CHECK-INST: ld1w    {za2v.s[w14, 0]}, p5/z, [x19, x20, lsl #2]
 // CHECK-ENCODING: [0x68,0xd6,0x94,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 94 e0 <unknown>
+// CHECK-UNKNOWN: e094d668 <unknown>
 
 ld1w    za0v.s[w12, 0], p6/z, [x12, x2, lsl #2]
 // CHECK-INST: ld1w    {za0v.s[w12, 0]}, p6/z, [x12, x2, lsl #2]
 // CHECK-ENCODING: [0x80,0x99,0x82,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 82 e0 <unknown>
+// CHECK-UNKNOWN: e0829980 <unknown>
 
 ld1w    za0v.s[w14, 1], p2/z, [x1, x26, lsl #2]
 // CHECK-INST: ld1w    {za0v.s[w14, 1]}, p2/z, [x1, x26, lsl #2]
 // CHECK-ENCODING: [0x21,0xc8,0x9a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 9a e0 <unknown>
+// CHECK-UNKNOWN: e09ac821 <unknown>
 
 ld1w    za3v.s[w12, 1], p2/z, [x22, x30, lsl #2]
 // CHECK-INST: ld1w    {za3v.s[w12, 1]}, p2/z, [x22, x30, lsl #2]
 // CHECK-ENCODING: [0xcd,0x8a,0x9e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 9e e0 <unknown>
+// CHECK-UNKNOWN: e09e8acd <unknown>
 
 ld1w    za0v.s[w15, 2], p5/z, [x9, x1, lsl #2]
 // CHECK-INST: ld1w    {za0v.s[w15, 2]}, p5/z, [x9, x1, lsl #2]
 // CHECK-ENCODING: [0x22,0xf5,0x81,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 81 e0 <unknown>
+// CHECK-UNKNOWN: e081f522 <unknown>
 
 ld1w    za1v.s[w13, 3], p2/z, [x12, x11, lsl #2]
 // CHECK-INST: ld1w    {za1v.s[w13, 3]}, p2/z, [x12, x11, lsl #2]
 // CHECK-ENCODING: [0x87,0xa9,0x8b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 8b e0 <unknown>
+// CHECK-UNKNOWN: e08ba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/ldr.s b/llvm/test/MC/AArch64/SME/ldr.s
index 411f3edea5d00..ac55a20a9f146 100644
--- a/llvm/test/MC/AArch64/SME/ldr.s
+++ b/llvm/test/MC/AArch64/SME/ldr.s
@@ -16,70 +16,70 @@ ldr     za[w12, 0], [x0]
 // CHECK-INST: ldr     za[w12, 0], [x0]
 // CHECK-ENCODING: [0x00,0x00,0x00,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 00 e1 <unknown>
+// CHECK-UNKNOWN: e1000000 <unknown>
 
 ldr     za[w14, 5], [x10, #5, mul vl]
 // CHECK-INST: ldr     za[w14, 5], [x10, #5, mul vl]
 // CHECK-ENCODING: [0x45,0x41,0x00,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 41 00 e1 <unknown>
+// CHECK-UNKNOWN: e1004145 <unknown>
 
 ldr     za[w15, 7], [x13, #7, mul vl]
 // CHECK-INST: ldr     za[w15, 7], [x13, #7, mul vl]
 // CHECK-ENCODING: [0xa7,0x61,0x00,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 61 00 e1 <unknown>
+// CHECK-UNKNOWN: e10061a7 <unknown>
 
 ldr     za[w15, 15], [sp, #15, mul vl]
 // CHECK-INST: ldr     za[w15, 15], [sp, #15, mul vl]
 // CHECK-ENCODING: [0xef,0x63,0x00,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 63 00 e1 <unknown>
+// CHECK-UNKNOWN: e10063ef <unknown>
 
 ldr     za[w12, 5], [x17, #5, mul vl]
 // CHECK-INST: ldr     za[w12, 5], [x17, #5, mul vl]
 // CHECK-ENCODING: [0x25,0x02,0x00,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 02 00 e1 <unknown>
+// CHECK-UNKNOWN: e1000225 <unknown>
 
 ldr     za[w12, 1], [x1, #1, mul vl]
 // CHECK-INST: ldr     za[w12, 1], [x1, #1, mul vl]
 // CHECK-ENCODING: [0x21,0x00,0x00,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 00 00 e1 <unknown>
+// CHECK-UNKNOWN: e1000021 <unknown>
 
 ldr     za[w14, 8], [x19, #8, mul vl]
 // CHECK-INST: ldr     za[w14, 8], [x19, #8, mul vl]
 // CHECK-ENCODING: [0x68,0x42,0x00,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 42 00 e1 <unknown>
+// CHECK-UNKNOWN: e1004268 <unknown>
 
 ldr     za[w12, 0], [x12]
 // CHECK-INST: ldr     za[w12, 0], [x12]
 // CHECK-ENCODING: [0x80,0x01,0x00,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 01 00 e1 <unknown>
+// CHECK-UNKNOWN: e1000180 <unknown>
 
 ldr     za[w14, 1], [x1, #1, mul vl]
 // CHECK-INST: ldr     za[w14, 1], [x1, #1, mul vl]
 // CHECK-ENCODING: [0x21,0x40,0x00,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 40 00 e1 <unknown>
+// CHECK-UNKNOWN: e1004021 <unknown>
 
 ldr     za[w12, 13], [x22, #13, mul vl]
 // CHECK-INST: ldr     za[w12, 13], [x22, #13, mul vl]
 // CHECK-ENCODING: [0xcd,0x02,0x00,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 02 00 e1 <unknown>
+// CHECK-UNKNOWN: e10002cd <unknown>
 
 ldr     za[w15, 2], [x9, #2, mul vl]
 // CHECK-INST: ldr     za[w15, 2], [x9, #2, mul vl]
 // CHECK-ENCODING: [0x22,0x61,0x00,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 61 00 e1 <unknown>
+// CHECK-UNKNOWN: e1006122 <unknown>
 
 ldr     za[w13, 7], [x12, #7, mul vl]
 // CHECK-INST: ldr     za[w13, 7], [x12, #7, mul vl]
 // CHECK-ENCODING: [0x87,0x21,0x00,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 21 00 e1 <unknown>
+// CHECK-UNKNOWN: e1002187 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/mova.s b/llvm/test/MC/AArch64/SME/mova.s
index 1ab0b2eac44b3..07522ebd83055 100644
--- a/llvm/test/MC/AArch64/SME/mova.s
+++ b/llvm/test/MC/AArch64/SME/mova.s
@@ -19,73 +19,73 @@ mova    z0.b, p0/m, za0h.b[w12, 0]
 // CHECK-INST: mov     z0.b, p0/m, za0h.b[w12, 0]
 // CHECK-ENCODING: [0x00,0x00,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 02 c0 <unknown>
+// CHECK-UNKNOWN: c0020000 <unknown>
 
 mova    z21.b, p5/m, za0h.b[w14, 10]
 // CHECK-INST: mov     z21.b, p5/m, za0h.b[w14, 10]
 // CHECK-ENCODING: [0x55,0x55,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 55 02 c0 <unknown>
+// CHECK-UNKNOWN: c0025555 <unknown>
 
 mova    z23.b, p3/m, za0h.b[w15, 13]
 // CHECK-INST: mov     z23.b, p3/m, za0h.b[w15, 13]
 // CHECK-ENCODING: [0xb7,0x6d,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 6d 02 c0 <unknown>
+// CHECK-UNKNOWN: c0026db7 <unknown>
 
 mova    z31.b, p7/m, za0h.b[w15, 15]
 // CHECK-INST: mov     z31.b, p7/m, za0h.b[w15, 15]
 // CHECK-ENCODING: [0xff,0x7d,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 7d 02 c0 <unknown>
+// CHECK-UNKNOWN: c0027dff <unknown>
 
 mova    z5.b, p3/m, za0h.b[w12, 1]
 // CHECK-INST: mov     z5.b, p3/m, za0h.b[w12, 1]
 // CHECK-ENCODING: [0x25,0x0c,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0c 02 c0 <unknown>
+// CHECK-UNKNOWN: c0020c25 <unknown>
 
 mova    z1.b, p1/m, za0h.b[w12, 1]
 // CHECK-INST: mov     z1.b, p1/m, za0h.b[w12, 1]
 // CHECK-ENCODING: [0x21,0x04,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 02 c0 <unknown>
+// CHECK-UNKNOWN: c0020421 <unknown>
 
 mova    z24.b, p5/m, za0h.b[w14, 3]
 // CHECK-INST: mov     z24.b, p5/m, za0h.b[w14, 3]
 // CHECK-ENCODING: [0x78,0x54,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 54 02 c0 <unknown>
+// CHECK-UNKNOWN: c0025478 <unknown>
 
 mova    z0.b, p6/m, za0h.b[w12, 12]
 // CHECK-INST: mov     z0.b, p6/m, za0h.b[w12, 12]
 // CHECK-ENCODING: [0x80,0x19,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 02 c0 <unknown>
+// CHECK-UNKNOWN: c0021980 <unknown>
 
 mova    z17.b, p2/m, za0h.b[w14, 1]
 // CHECK-INST: mov     z17.b, p2/m, za0h.b[w14, 1]
 // CHECK-ENCODING: [0x31,0x48,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 48 02 c0 <unknown>
+// CHECK-UNKNOWN: c0024831 <unknown>
 
 mova    z29.b, p2/m, za0h.b[w12, 6]
 // CHECK-INST: mov     z29.b, p2/m, za0h.b[w12, 6]
 // CHECK-ENCODING: [0xdd,0x08,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 08 02 c0 <unknown>
+// CHECK-UNKNOWN: c00208dd <unknown>
 
 mova    z2.b, p5/m, za0h.b[w15, 9]
 // CHECK-INST: mov     z2.b, p5/m, za0h.b[w15, 9]
 // CHECK-ENCODING: [0x22,0x75,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 02 c0 <unknown>
+// CHECK-UNKNOWN: c0027522 <unknown>
 
 mova    z7.b, p2/m, za0h.b[w13, 12]
 // CHECK-INST: mov     z7.b, p2/m, za0h.b[w13, 12]
 // CHECK-ENCODING: [0x87,0x29,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 02 c0 <unknown>
+// CHECK-UNKNOWN: c0022987 <unknown>
 
 // Aliases
 
@@ -93,73 +93,73 @@ mov     z0.b, p0/m, za0h.b[w12, 0]
 // CHECK-INST: mov     z0.b, p0/m, za0h.b[w12, 0]
 // CHECK-ENCODING: [0x00,0x00,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 02 c0 <unknown>
+// CHECK-UNKNOWN: c0020000 <unknown>
 
 mov     z21.b, p5/m, za0h.b[w14, 10]
 // CHECK-INST: mov     z21.b, p5/m, za0h.b[w14, 10]
 // CHECK-ENCODING: [0x55,0x55,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 55 02 c0 <unknown>
+// CHECK-UNKNOWN: c0025555 <unknown>
 
 mov     z23.b, p3/m, za0h.b[w15, 13]
 // CHECK-INST: mov     z23.b, p3/m, za0h.b[w15, 13]
 // CHECK-ENCODING: [0xb7,0x6d,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 6d 02 c0 <unknown>
+// CHECK-UNKNOWN: c0026db7 <unknown>
 
 mov     z31.b, p7/m, za0h.b[w15, 15]
 // CHECK-INST: mov     z31.b, p7/m, za0h.b[w15, 15]
 // CHECK-ENCODING: [0xff,0x7d,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 7d 02 c0 <unknown>
+// CHECK-UNKNOWN: c0027dff <unknown>
 
 mov     z5.b, p3/m, za0h.b[w12, 1]
 // CHECK-INST: mov     z5.b, p3/m, za0h.b[w12, 1]
 // CHECK-ENCODING: [0x25,0x0c,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0c 02 c0 <unknown>
+// CHECK-UNKNOWN: c0020c25 <unknown>
 
 mov     z1.b, p1/m, za0h.b[w12, 1]
 // CHECK-INST: mov     z1.b, p1/m, za0h.b[w12, 1]
 // CHECK-ENCODING: [0x21,0x04,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 02 c0 <unknown>
+// CHECK-UNKNOWN: c0020421 <unknown>
 
 mov     z24.b, p5/m, za0h.b[w14, 3]
 // CHECK-INST: mov     z24.b, p5/m, za0h.b[w14, 3]
 // CHECK-ENCODING: [0x78,0x54,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 54 02 c0 <unknown>
+// CHECK-UNKNOWN: c0025478 <unknown>
 
 mov     z0.b, p6/m, za0h.b[w12, 12]
 // CHECK-INST: mov     z0.b, p6/m, za0h.b[w12, 12]
 // CHECK-ENCODING: [0x80,0x19,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 02 c0 <unknown>
+// CHECK-UNKNOWN: c0021980 <unknown>
 
 mov     z17.b, p2/m, za0h.b[w14, 1]
 // CHECK-INST: mov     z17.b, p2/m, za0h.b[w14, 1]
 // CHECK-ENCODING: [0x31,0x48,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 48 02 c0 <unknown>
+// CHECK-UNKNOWN: c0024831 <unknown>
 
 mov     z29.b, p2/m, za0h.b[w12, 6]
 // CHECK-INST: mov     z29.b, p2/m, za0h.b[w12, 6]
 // CHECK-ENCODING: [0xdd,0x08,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 08 02 c0 <unknown>
+// CHECK-UNKNOWN: c00208dd <unknown>
 
 mov     z2.b, p5/m, za0h.b[w15, 9]
 // CHECK-INST: mov     z2.b, p5/m, za0h.b[w15, 9]
 // CHECK-ENCODING: [0x22,0x75,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 02 c0 <unknown>
+// CHECK-UNKNOWN: c0027522 <unknown>
 
 mov     z7.b, p2/m, za0h.b[w13, 12]
 // CHECK-INST: mov     z7.b, p2/m, za0h.b[w13, 12]
 // CHECK-ENCODING: [0x87,0x29,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 02 c0 <unknown>
+// CHECK-UNKNOWN: c0022987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Extract, tile to vector, vertical, 8-bit
@@ -168,73 +168,73 @@ mova    z0.b, p0/m, za0v.b[w12, 0]
 // CHECK-INST: mov     z0.b, p0/m, za0v.b[w12, 0]
 // CHECK-ENCODING: [0x00,0x80,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 02 c0 <unknown>
+// CHECK-UNKNOWN: c0028000 <unknown>
 
 mova    z21.b, p5/m, za0v.b[w14, 10]
 // CHECK-INST: mov     z21.b, p5/m, za0v.b[w14, 10]
 // CHECK-ENCODING: [0x55,0xd5,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 d5 02 c0 <unknown>
+// CHECK-UNKNOWN: c002d555 <unknown>
 
 mova    z23.b, p3/m, za0v.b[w15, 13]
 // CHECK-INST: mov     z23.b, p3/m, za0v.b[w15, 13]
 // CHECK-ENCODING: [0xb7,0xed,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 ed 02 c0 <unknown>
+// CHECK-UNKNOWN: c002edb7 <unknown>
 
 mova    z31.b, p7/m, za0v.b[w15, 15]
 // CHECK-INST: mov     z31.b, p7/m, za0v.b[w15, 15]
 // CHECK-ENCODING: [0xff,0xfd,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff fd 02 c0 <unknown>
+// CHECK-UNKNOWN: c002fdff <unknown>
 
 mova    z5.b, p3/m, za0v.b[w12, 1]
 // CHECK-INST: mov     z5.b, p3/m, za0v.b[w12, 1]
 // CHECK-ENCODING: [0x25,0x8c,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8c 02 c0 <unknown>
+// CHECK-UNKNOWN: c0028c25 <unknown>
 
 mova    z1.b, p1/m, za0v.b[w12, 1]
 // CHECK-INST: mov     z1.b, p1/m, za0v.b[w12, 1]
 // CHECK-ENCODING: [0x21,0x84,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 02 c0 <unknown>
+// CHECK-UNKNOWN: c0028421 <unknown>
 
 mova    z24.b, p5/m, za0v.b[w14, 3]
 // CHECK-INST: mov     z24.b, p5/m, za0v.b[w14, 3]
 // CHECK-ENCODING: [0x78,0xd4,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 d4 02 c0 <unknown>
+// CHECK-UNKNOWN: c002d478 <unknown>
 
 mova    z0.b, p6/m, za0v.b[w12, 12]
 // CHECK-INST: mov     z0.b, p6/m, za0v.b[w12, 12]
 // CHECK-ENCODING: [0x80,0x99,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 02 c0 <unknown>
+// CHECK-UNKNOWN: c0029980 <unknown>
 
 mova    z17.b, p2/m, za0v.b[w14, 1]
 // CHECK-INST: mov     z17.b, p2/m, za0v.b[w14, 1]
 // CHECK-ENCODING: [0x31,0xc8,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 02 c0 <unknown>
+// CHECK-UNKNOWN: c002c831 <unknown>
 
 mova    z29.b, p2/m, za0v.b[w12, 6]
 // CHECK-INST: mov     z29.b, p2/m, za0v.b[w12, 6]
 // CHECK-ENCODING: [0xdd,0x88,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 88 02 c0 <unknown>
+// CHECK-UNKNOWN: c00288dd <unknown>
 
 mova    z2.b, p5/m, za0v.b[w15, 9]
 // CHECK-INST: mov     z2.b, p5/m, za0v.b[w15, 9]
 // CHECK-ENCODING: [0x22,0xf5,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 02 c0 <unknown>
+// CHECK-UNKNOWN: c002f522 <unknown>
 
 mova    z7.b, p2/m, za0v.b[w13, 12]
 // CHECK-INST: mov     z7.b, p2/m, za0v.b[w13, 12]
 // CHECK-ENCODING: [0x87,0xa9,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 02 c0 <unknown>
+// CHECK-UNKNOWN: c002a987 <unknown>
 
 // Aliases
 
@@ -242,73 +242,73 @@ mov     z0.b, p0/m, za0v.b[w12, 0]
 // CHECK-INST: mov     z0.b, p0/m, za0v.b[w12, 0]
 // CHECK-ENCODING: [0x00,0x80,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 02 c0 <unknown>
+// CHECK-UNKNOWN: c0028000 <unknown>
 
 mov     z21.b, p5/m, za0v.b[w14, 10]
 // CHECK-INST: mov     z21.b, p5/m, za0v.b[w14, 10]
 // CHECK-ENCODING: [0x55,0xd5,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 d5 02 c0 <unknown>
+// CHECK-UNKNOWN: c002d555 <unknown>
 
 mov     z23.b, p3/m, za0v.b[w15, 13]
 // CHECK-INST: mov     z23.b, p3/m, za0v.b[w15, 13]
 // CHECK-ENCODING: [0xb7,0xed,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 ed 02 c0 <unknown>
+// CHECK-UNKNOWN: c002edb7 <unknown>
 
 mov     z31.b, p7/m, za0v.b[w15, 15]
 // CHECK-INST: mov     z31.b, p7/m, za0v.b[w15, 15]
 // CHECK-ENCODING: [0xff,0xfd,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff fd 02 c0 <unknown>
+// CHECK-UNKNOWN: c002fdff <unknown>
 
 mov     z5.b, p3/m, za0v.b[w12, 1]
 // CHECK-INST: mov     z5.b, p3/m, za0v.b[w12, 1]
 // CHECK-ENCODING: [0x25,0x8c,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8c 02 c0 <unknown>
+// CHECK-UNKNOWN: c0028c25 <unknown>
 
 mov     z1.b, p1/m, za0v.b[w12, 1]
 // CHECK-INST: mov     z1.b, p1/m, za0v.b[w12, 1]
 // CHECK-ENCODING: [0x21,0x84,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 02 c0 <unknown>
+// CHECK-UNKNOWN: c0028421 <unknown>
 
 mov     z24.b, p5/m, za0v.b[w14, 3]
 // CHECK-INST: mov     z24.b, p5/m, za0v.b[w14, 3]
 // CHECK-ENCODING: [0x78,0xd4,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 d4 02 c0 <unknown>
+// CHECK-UNKNOWN: c002d478 <unknown>
 
 mov     z0.b, p6/m, za0v.b[w12, 12]
 // CHECK-INST: mov     z0.b, p6/m, za0v.b[w12, 12]
 // CHECK-ENCODING: [0x80,0x99,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 02 c0 <unknown>
+// CHECK-UNKNOWN: c0029980 <unknown>
 
 mov     z17.b, p2/m, za0v.b[w14, 1]
 // CHECK-INST: mov     z17.b, p2/m, za0v.b[w14, 1]
 // CHECK-ENCODING: [0x31,0xc8,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 02 c0 <unknown>
+// CHECK-UNKNOWN: c002c831 <unknown>
 
 mov     z29.b, p2/m, za0v.b[w12, 6]
 // CHECK-INST: mov     z29.b, p2/m, za0v.b[w12, 6]
 // CHECK-ENCODING: [0xdd,0x88,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 88 02 c0 <unknown>
+// CHECK-UNKNOWN: c00288dd <unknown>
 
 mov     z2.b, p5/m, za0v.b[w15, 9]
 // CHECK-INST: mov     z2.b, p5/m, za0v.b[w15, 9]
 // CHECK-ENCODING: [0x22,0xf5,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 02 c0 <unknown>
+// CHECK-UNKNOWN: c002f522 <unknown>
 
 mov     z7.b, p2/m, za0v.b[w13, 12]
 // CHECK-INST: mov     z7.b, p2/m, za0v.b[w13, 12]
 // CHECK-ENCODING: [0x87,0xa9,0x02,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 02 c0 <unknown>
+// CHECK-UNKNOWN: c002a987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Extract, tile to vector, horizontal, 16-bit
@@ -317,73 +317,73 @@ mova    z0.h, p0/m, za0h.h[w12, 0]
 // CHECK-INST: mov     z0.h, p0/m, za0h.h[w12, 0]
 // CHECK-ENCODING: [0x00,0x00,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 42 c0 <unknown>
+// CHECK-UNKNOWN: c0420000 <unknown>
 
 mova    z21.h, p5/m, za1h.h[w14, 2]
 // CHECK-INST: mov     z21.h, p5/m, za1h.h[w14, 2]
 // CHECK-ENCODING: [0x55,0x55,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 55 42 c0 <unknown>
+// CHECK-UNKNOWN: c0425555 <unknown>
 
 mova    z23.h, p3/m, za1h.h[w15, 5]
 // CHECK-INST: mov     z23.h, p3/m, za1h.h[w15, 5]
 // CHECK-ENCODING: [0xb7,0x6d,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 6d 42 c0 <unknown>
+// CHECK-UNKNOWN: c0426db7 <unknown>
 
 mova    z31.h, p7/m, za1h.h[w15, 7]
 // CHECK-INST: mov     z31.h, p7/m, za1h.h[w15, 7]
 // CHECK-ENCODING: [0xff,0x7d,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 7d 42 c0 <unknown>
+// CHECK-UNKNOWN: c0427dff <unknown>
 
 mova    z5.h, p3/m, za0h.h[w12, 1]
 // CHECK-INST: mov     z5.h, p3/m, za0h.h[w12, 1]
 // CHECK-ENCODING: [0x25,0x0c,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0c 42 c0 <unknown>
+// CHECK-UNKNOWN: c0420c25 <unknown>
 
 mova    z1.h, p1/m, za0h.h[w12, 1]
 // CHECK-INST: mov     z1.h, p1/m, za0h.h[w12, 1]
 // CHECK-ENCODING: [0x21,0x04,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 42 c0 <unknown>
+// CHECK-UNKNOWN: c0420421 <unknown>
 
 mova    z24.h, p5/m, za0h.h[w14, 3]
 // CHECK-INST: mov     z24.h, p5/m, za0h.h[w14, 3]
 // CHECK-ENCODING: [0x78,0x54,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 54 42 c0 <unknown>
+// CHECK-UNKNOWN: c0425478 <unknown>
 
 mova    z0.h, p6/m, za1h.h[w12, 4]
 // CHECK-INST: mov     z0.h, p6/m, za1h.h[w12, 4]
 // CHECK-ENCODING: [0x80,0x19,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 42 c0 <unknown>
+// CHECK-UNKNOWN: c0421980 <unknown>
 
 mova    z17.h, p2/m, za0h.h[w14, 1]
 // CHECK-INST: mov     z17.h, p2/m, za0h.h[w14, 1]
 // CHECK-ENCODING: [0x31,0x48,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 48 42 c0 <unknown>
+// CHECK-UNKNOWN: c0424831 <unknown>
 
 mova    z29.h, p2/m, za0h.h[w12, 6]
 // CHECK-INST: mov     z29.h, p2/m, za0h.h[w12, 6]
 // CHECK-ENCODING: [0xdd,0x08,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 08 42 c0 <unknown>
+// CHECK-UNKNOWN: c04208dd <unknown>
 
 mova    z2.h, p5/m, za1h.h[w15, 1]
 // CHECK-INST: mov     z2.h, p5/m, za1h.h[w15, 1]
 // CHECK-ENCODING: [0x22,0x75,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 42 c0 <unknown>
+// CHECK-UNKNOWN: c0427522 <unknown>
 
 mova    z7.h, p2/m, za1h.h[w13, 4]
 // CHECK-INST: mov     z7.h, p2/m, za1h.h[w13, 4]
 // CHECK-ENCODING: [0x87,0x29,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 42 c0 <unknown>
+// CHECK-UNKNOWN: c0422987 <unknown>
 
 // Aliases
 
@@ -391,73 +391,73 @@ mov     z0.h, p0/m, za0h.h[w12, 0]
 // CHECK-INST: mov     z0.h, p0/m, za0h.h[w12, 0]
 // CHECK-ENCODING: [0x00,0x00,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 42 c0 <unknown>
+// CHECK-UNKNOWN: c0420000 <unknown>
 
 mov     z21.h, p5/m, za1h.h[w14, 2]
 // CHECK-INST: mov     z21.h, p5/m, za1h.h[w14, 2]
 // CHECK-ENCODING: [0x55,0x55,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 55 42 c0 <unknown>
+// CHECK-UNKNOWN: c0425555 <unknown>
 
 mov     z23.h, p3/m, za1h.h[w15, 5]
 // CHECK-INST: mov     z23.h, p3/m, za1h.h[w15, 5]
 // CHECK-ENCODING: [0xb7,0x6d,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 6d 42 c0 <unknown>
+// CHECK-UNKNOWN: c0426db7 <unknown>
 
 mov     z31.h, p7/m, za1h.h[w15, 7]
 // CHECK-INST: mov     z31.h, p7/m, za1h.h[w15, 7]
 // CHECK-ENCODING: [0xff,0x7d,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 7d 42 c0 <unknown>
+// CHECK-UNKNOWN: c0427dff <unknown>
 
 mov     z5.h, p3/m, za0h.h[w12, 1]
 // CHECK-INST: mov     z5.h, p3/m, za0h.h[w12, 1]
 // CHECK-ENCODING: [0x25,0x0c,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0c 42 c0 <unknown>
+// CHECK-UNKNOWN: c0420c25 <unknown>
 
 mov     z1.h, p1/m, za0h.h[w12, 1]
 // CHECK-INST: mov     z1.h, p1/m, za0h.h[w12, 1]
 // CHECK-ENCODING: [0x21,0x04,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 42 c0 <unknown>
+// CHECK-UNKNOWN: c0420421 <unknown>
 
 mov     z24.h, p5/m, za0h.h[w14, 3]
 // CHECK-INST: mov     z24.h, p5/m, za0h.h[w14, 3]
 // CHECK-ENCODING: [0x78,0x54,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 54 42 c0 <unknown>
+// CHECK-UNKNOWN: c0425478 <unknown>
 
 mov     z0.h, p6/m, za1h.h[w12, 4]
 // CHECK-INST: mov     z0.h, p6/m, za1h.h[w12, 4]
 // CHECK-ENCODING: [0x80,0x19,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 42 c0 <unknown>
+// CHECK-UNKNOWN: c0421980 <unknown>
 
 mov     z17.h, p2/m, za0h.h[w14, 1]
 // CHECK-INST: mov     z17.h, p2/m, za0h.h[w14, 1]
 // CHECK-ENCODING: [0x31,0x48,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 48 42 c0 <unknown>
+// CHECK-UNKNOWN: c0424831 <unknown>
 
 mov     z29.h, p2/m, za0h.h[w12, 6]
 // CHECK-INST: mov     z29.h, p2/m, za0h.h[w12, 6]
 // CHECK-ENCODING: [0xdd,0x08,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 08 42 c0 <unknown>
+// CHECK-UNKNOWN: c04208dd <unknown>
 
 mov     z2.h, p5/m, za1h.h[w15, 1]
 // CHECK-INST: mov     z2.h, p5/m, za1h.h[w15, 1]
 // CHECK-ENCODING: [0x22,0x75,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 42 c0 <unknown>
+// CHECK-UNKNOWN: c0427522 <unknown>
 
 mov     z7.h, p2/m, za1h.h[w13, 4]
 // CHECK-INST: mov     z7.h, p2/m, za1h.h[w13, 4]
 // CHECK-ENCODING: [0x87,0x29,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 42 c0 <unknown>
+// CHECK-UNKNOWN: c0422987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Extract, tile to vector, vertical, 16-bit
@@ -466,73 +466,73 @@ mova    z0.h, p0/m, za0v.h[w12, 0]
 // CHECK-INST: mov     z0.h, p0/m, za0v.h[w12, 0]
 // CHECK-ENCODING: [0x00,0x80,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 42 c0 <unknown>
+// CHECK-UNKNOWN: c0428000 <unknown>
 
 mova    z21.h, p5/m, za1v.h[w14, 2]
 // CHECK-INST: mov     z21.h, p5/m, za1v.h[w14, 2]
 // CHECK-ENCODING: [0x55,0xd5,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 d5 42 c0 <unknown>
+// CHECK-UNKNOWN: c042d555 <unknown>
 
 mova    z23.h, p3/m, za1v.h[w15, 5]
 // CHECK-INST: mov     z23.h, p3/m, za1v.h[w15, 5]
 // CHECK-ENCODING: [0xb7,0xed,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 ed 42 c0 <unknown>
+// CHECK-UNKNOWN: c042edb7 <unknown>
 
 mova    z31.h, p7/m, za1v.h[w15, 7]
 // CHECK-INST: mov     z31.h, p7/m, za1v.h[w15, 7]
 // CHECK-ENCODING: [0xff,0xfd,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff fd 42 c0 <unknown>
+// CHECK-UNKNOWN: c042fdff <unknown>
 
 mova    z5.h, p3/m, za0v.h[w12, 1]
 // CHECK-INST: mov     z5.h, p3/m, za0v.h[w12, 1]
 // CHECK-ENCODING: [0x25,0x8c,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8c 42 c0 <unknown>
+// CHECK-UNKNOWN: c0428c25 <unknown>
 
 mova    z1.h, p1/m, za0v.h[w12, 1]
 // CHECK-INST: mov     z1.h, p1/m, za0v.h[w12, 1]
 // CHECK-ENCODING: [0x21,0x84,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 42 c0 <unknown>
+// CHECK-UNKNOWN: c0428421 <unknown>
 
 mova    z24.h, p5/m, za0v.h[w14, 3]
 // CHECK-INST: mov     z24.h, p5/m, za0v.h[w14, 3]
 // CHECK-ENCODING: [0x78,0xd4,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 d4 42 c0 <unknown>
+// CHECK-UNKNOWN: c042d478 <unknown>
 
 mova    z0.h, p6/m, za1v.h[w12, 4]
 // CHECK-INST: mov     z0.h, p6/m, za1v.h[w12, 4]
 // CHECK-ENCODING: [0x80,0x99,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 42 c0 <unknown>
+// CHECK-UNKNOWN: c0429980 <unknown>
 
 mova    z17.h, p2/m, za0v.h[w14, 1]
 // CHECK-INST: mov     z17.h, p2/m, za0v.h[w14, 1]
 // CHECK-ENCODING: [0x31,0xc8,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 42 c0 <unknown>
+// CHECK-UNKNOWN: c042c831 <unknown>
 
 mova    z29.h, p2/m, za0v.h[w12, 6]
 // CHECK-INST: mov     z29.h, p2/m, za0v.h[w12, 6]
 // CHECK-ENCODING: [0xdd,0x88,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 88 42 c0 <unknown>
+// CHECK-UNKNOWN: c04288dd <unknown>
 
 mova    z2.h, p5/m, za1v.h[w15, 1]
 // CHECK-INST: mov     z2.h, p5/m, za1v.h[w15, 1]
 // CHECK-ENCODING: [0x22,0xf5,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 42 c0 <unknown>
+// CHECK-UNKNOWN: c042f522 <unknown>
 
 mova    z7.h, p2/m, za1v.h[w13, 4]
 // CHECK-INST: mov     z7.h, p2/m, za1v.h[w13, 4]
 // CHECK-ENCODING: [0x87,0xa9,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 42 c0 <unknown>
+// CHECK-UNKNOWN: c042a987 <unknown>
 
 // Aliases
 
@@ -540,73 +540,73 @@ mov     z0.h, p0/m, za0v.h[w12, 0]
 // CHECK-INST: mov     z0.h, p0/m, za0v.h[w12, 0]
 // CHECK-ENCODING: [0x00,0x80,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 42 c0 <unknown>
+// CHECK-UNKNOWN: c0428000 <unknown>
 
 mov     z21.h, p5/m, za1v.h[w14, 2]
 // CHECK-INST: mov     z21.h, p5/m, za1v.h[w14, 2]
 // CHECK-ENCODING: [0x55,0xd5,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 d5 42 c0 <unknown>
+// CHECK-UNKNOWN: c042d555 <unknown>
 
 mov     z23.h, p3/m, za1v.h[w15, 5]
 // CHECK-INST: mov     z23.h, p3/m, za1v.h[w15, 5]
 // CHECK-ENCODING: [0xb7,0xed,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 ed 42 c0 <unknown>
+// CHECK-UNKNOWN: c042edb7 <unknown>
 
 mov     z31.h, p7/m, za1v.h[w15, 7]
 // CHECK-INST: mov     z31.h, p7/m, za1v.h[w15, 7]
 // CHECK-ENCODING: [0xff,0xfd,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff fd 42 c0 <unknown>
+// CHECK-UNKNOWN: c042fdff <unknown>
 
 mov     z5.h, p3/m, za0v.h[w12, 1]
 // CHECK-INST: mov     z5.h, p3/m, za0v.h[w12, 1]
 // CHECK-ENCODING: [0x25,0x8c,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8c 42 c0 <unknown>
+// CHECK-UNKNOWN: c0428c25 <unknown>
 
 mov     z1.h, p1/m, za0v.h[w12, 1]
 // CHECK-INST: mov     z1.h, p1/m, za0v.h[w12, 1]
 // CHECK-ENCODING: [0x21,0x84,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 42 c0 <unknown>
+// CHECK-UNKNOWN: c0428421 <unknown>
 
 mov     z24.h, p5/m, za0v.h[w14, 3]
 // CHECK-INST: mov     z24.h, p5/m, za0v.h[w14, 3]
 // CHECK-ENCODING: [0x78,0xd4,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 d4 42 c0 <unknown>
+// CHECK-UNKNOWN: c042d478 <unknown>
 
 mov     z0.h, p6/m, za1v.h[w12, 4]
 // CHECK-INST: mov     z0.h, p6/m, za1v.h[w12, 4]
 // CHECK-ENCODING: [0x80,0x99,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 42 c0 <unknown>
+// CHECK-UNKNOWN: c0429980 <unknown>
 
 mov     z17.h, p2/m, za0v.h[w14, 1]
 // CHECK-INST: mov     z17.h, p2/m, za0v.h[w14, 1]
 // CHECK-ENCODING: [0x31,0xc8,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 42 c0 <unknown>
+// CHECK-UNKNOWN: c042c831 <unknown>
 
 mov     z29.h, p2/m, za0v.h[w12, 6]
 // CHECK-INST: mov     z29.h, p2/m, za0v.h[w12, 6]
 // CHECK-ENCODING: [0xdd,0x88,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 88 42 c0 <unknown>
+// CHECK-UNKNOWN: c04288dd <unknown>
 
 mov     z2.h, p5/m, za1v.h[w15, 1]
 // CHECK-INST: mov     z2.h, p5/m, za1v.h[w15, 1]
 // CHECK-ENCODING: [0x22,0xf5,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 42 c0 <unknown>
+// CHECK-UNKNOWN: c042f522 <unknown>
 
 mov     z7.h, p2/m, za1v.h[w13, 4]
 // CHECK-INST: mov     z7.h, p2/m, za1v.h[w13, 4]
 // CHECK-ENCODING: [0x87,0xa9,0x42,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 42 c0 <unknown>
+// CHECK-UNKNOWN: c042a987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Extract, tile to vector, horizontal, 32-bit
@@ -615,73 +615,73 @@ mova    z0.s, p0/m, za0h.s[w12, 0]
 // CHECK-INST: mov     z0.s, p0/m, za0h.s[w12, 0]
 // CHECK-ENCODING: [0x00,0x00,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 82 c0 <unknown>
+// CHECK-UNKNOWN: c0820000 <unknown>
 
 mova    z21.s, p5/m, za2h.s[w14, 2]
 // CHECK-INST: mov     z21.s, p5/m, za2h.s[w14, 2]
 // CHECK-ENCODING: [0x55,0x55,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 55 82 c0 <unknown>
+// CHECK-UNKNOWN: c0825555 <unknown>
 
 mova    z23.s, p3/m, za3h.s[w15, 1]
 // CHECK-INST: mov     z23.s, p3/m, za3h.s[w15, 1]
 // CHECK-ENCODING: [0xb7,0x6d,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 6d 82 c0 <unknown>
+// CHECK-UNKNOWN: c0826db7 <unknown>
 
 mova    z31.s, p7/m, za3h.s[w15, 3]
 // CHECK-INST: mov     z31.s, p7/m, za3h.s[w15, 3]
 // CHECK-ENCODING: [0xff,0x7d,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 7d 82 c0 <unknown>
+// CHECK-UNKNOWN: c0827dff <unknown>
 
 mova    z5.s, p3/m, za0h.s[w12, 1]
 // CHECK-INST: mov     z5.s, p3/m, za0h.s[w12, 1]
 // CHECK-ENCODING: [0x25,0x0c,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0c 82 c0 <unknown>
+// CHECK-UNKNOWN: c0820c25 <unknown>
 
 mova    z1.s, p1/m, za0h.s[w12, 1]
 // CHECK-INST: mov     z1.s, p1/m, za0h.s[w12, 1]
 // CHECK-ENCODING: [0x21,0x04,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 82 c0 <unknown>
+// CHECK-UNKNOWN: c0820421 <unknown>
 
 mova    z24.s, p5/m, za0h.s[w14, 3]
 // CHECK-INST: mov     z24.s, p5/m, za0h.s[w14, 3]
 // CHECK-ENCODING: [0x78,0x54,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 54 82 c0 <unknown>
+// CHECK-UNKNOWN: c0825478 <unknown>
 
 mova    z0.s, p6/m, za3h.s[w12, 0]
 // CHECK-INST: mov     z0.s, p6/m, za3h.s[w12, 0]
 // CHECK-ENCODING: [0x80,0x19,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 82 c0 <unknown>
+// CHECK-UNKNOWN: c0821980 <unknown>
 
 mova    z17.s, p2/m, za0h.s[w14, 1]
 // CHECK-INST: mov     z17.s, p2/m, za0h.s[w14, 1]
 // CHECK-ENCODING: [0x31,0x48,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 48 82 c0 <unknown>
+// CHECK-UNKNOWN: c0824831 <unknown>
 
 mova    z29.s, p2/m, za1h.s[w12, 2]
 // CHECK-INST: mov     z29.s, p2/m, za1h.s[w12, 2]
 // CHECK-ENCODING: [0xdd,0x08,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 08 82 c0 <unknown>
+// CHECK-UNKNOWN: c08208dd <unknown>
 
 mova    z2.s, p5/m, za2h.s[w15, 1]
 // CHECK-INST: mov     z2.s, p5/m, za2h.s[w15, 1]
 // CHECK-ENCODING: [0x22,0x75,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 82 c0 <unknown>
+// CHECK-UNKNOWN: c0827522 <unknown>
 
 mova    z7.s, p2/m, za3h.s[w13, 0]
 // CHECK-INST: mov     z7.s, p2/m, za3h.s[w13, 0]
 // CHECK-ENCODING: [0x87,0x29,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 82 c0 <unknown>
+// CHECK-UNKNOWN: c0822987 <unknown>
 
 // Aliases
 
@@ -689,73 +689,73 @@ mov     z0.s, p0/m, za0h.s[w12, 0]
 // CHECK-INST: mov     z0.s, p0/m, za0h.s[w12, 0]
 // CHECK-ENCODING: [0x00,0x00,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 82 c0 <unknown>
+// CHECK-UNKNOWN: c0820000 <unknown>
 
 mov     z21.s, p5/m, za2h.s[w14, 2]
 // CHECK-INST: mov     z21.s, p5/m, za2h.s[w14, 2]
 // CHECK-ENCODING: [0x55,0x55,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 55 82 c0 <unknown>
+// CHECK-UNKNOWN: c0825555 <unknown>
 
 mov     z23.s, p3/m, za3h.s[w15, 1]
 // CHECK-INST: mov     z23.s, p3/m, za3h.s[w15, 1]
 // CHECK-ENCODING: [0xb7,0x6d,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 6d 82 c0 <unknown>
+// CHECK-UNKNOWN: c0826db7 <unknown>
 
 mov     z31.s, p7/m, za3h.s[w15, 3]
 // CHECK-INST: mov     z31.s, p7/m, za3h.s[w15, 3]
 // CHECK-ENCODING: [0xff,0x7d,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 7d 82 c0 <unknown>
+// CHECK-UNKNOWN: c0827dff <unknown>
 
 mov     z5.s, p3/m, za0h.s[w12, 1]
 // CHECK-INST: mov     z5.s, p3/m, za0h.s[w12, 1]
 // CHECK-ENCODING: [0x25,0x0c,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0c 82 c0 <unknown>
+// CHECK-UNKNOWN: c0820c25 <unknown>
 
 mov     z1.s, p1/m, za0h.s[w12, 1]
 // CHECK-INST: mov     z1.s, p1/m, za0h.s[w12, 1]
 // CHECK-ENCODING: [0x21,0x04,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 82 c0 <unknown>
+// CHECK-UNKNOWN: c0820421 <unknown>
 
 mov     z24.s, p5/m, za0h.s[w14, 3]
 // CHECK-INST: mov     z24.s, p5/m, za0h.s[w14, 3]
 // CHECK-ENCODING: [0x78,0x54,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 54 82 c0 <unknown>
+// CHECK-UNKNOWN: c0825478 <unknown>
 
 mov     z0.s, p6/m, za3h.s[w12, 0]
 // CHECK-INST: mov     z0.s, p6/m, za3h.s[w12, 0]
 // CHECK-ENCODING: [0x80,0x19,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 82 c0 <unknown>
+// CHECK-UNKNOWN: c0821980 <unknown>
 
 mov     z17.s, p2/m, za0h.s[w14, 1]
 // CHECK-INST: mov     z17.s, p2/m, za0h.s[w14, 1]
 // CHECK-ENCODING: [0x31,0x48,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 48 82 c0 <unknown>
+// CHECK-UNKNOWN: c0824831 <unknown>
 
 mov     z29.s, p2/m, za1h.s[w12, 2]
 // CHECK-INST: mov     z29.s, p2/m, za1h.s[w12, 2]
 // CHECK-ENCODING: [0xdd,0x08,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 08 82 c0 <unknown>
+// CHECK-UNKNOWN: c08208dd <unknown>
 
 mov     z2.s, p5/m, za2h.s[w15, 1]
 // CHECK-INST: mov     z2.s, p5/m, za2h.s[w15, 1]
 // CHECK-ENCODING: [0x22,0x75,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 82 c0 <unknown>
+// CHECK-UNKNOWN: c0827522 <unknown>
 
 mov     z7.s, p2/m, za3h.s[w13, 0]
 // CHECK-INST: mov     z7.s, p2/m, za3h.s[w13, 0]
 // CHECK-ENCODING: [0x87,0x29,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 82 c0 <unknown>
+// CHECK-UNKNOWN: c0822987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Extract, tile to vector, vertical, 32-bit
@@ -764,73 +764,73 @@ mova    z0.s, p0/m, za0v.s[w12, 0]
 // CHECK-INST: mov     z0.s, p0/m, za0v.s[w12, 0]
 // CHECK-ENCODING: [0x00,0x80,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 82 c0 <unknown>
+// CHECK-UNKNOWN: c0828000 <unknown>
 
 mova    z21.s, p5/m, za2v.s[w14, 2]
 // CHECK-INST: mov     z21.s, p5/m, za2v.s[w14, 2]
 // CHECK-ENCODING: [0x55,0xd5,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 d5 82 c0 <unknown>
+// CHECK-UNKNOWN: c082d555 <unknown>
 
 mova    z23.s, p3/m, za3v.s[w15, 1]
 // CHECK-INST: mov     z23.s, p3/m, za3v.s[w15, 1]
 // CHECK-ENCODING: [0xb7,0xed,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 ed 82 c0 <unknown>
+// CHECK-UNKNOWN: c082edb7 <unknown>
 
 mova    z31.s, p7/m, za3v.s[w15, 3]
 // CHECK-INST: mov     z31.s, p7/m, za3v.s[w15, 3]
 // CHECK-ENCODING: [0xff,0xfd,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff fd 82 c0 <unknown>
+// CHECK-UNKNOWN: c082fdff <unknown>
 
 mova    z5.s, p3/m, za0v.s[w12, 1]
 // CHECK-INST: mov     z5.s, p3/m, za0v.s[w12, 1]
 // CHECK-ENCODING: [0x25,0x8c,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8c 82 c0 <unknown>
+// CHECK-UNKNOWN: c0828c25 <unknown>
 
 mova    z1.s, p1/m, za0v.s[w12, 1]
 // CHECK-INST: mov     z1.s, p1/m, za0v.s[w12, 1]
 // CHECK-ENCODING: [0x21,0x84,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 82 c0 <unknown>
+// CHECK-UNKNOWN: c0828421 <unknown>
 
 mova    z24.s, p5/m, za0v.s[w14, 3]
 // CHECK-INST: mov     z24.s, p5/m, za0v.s[w14, 3]
 // CHECK-ENCODING: [0x78,0xd4,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 d4 82 c0 <unknown>
+// CHECK-UNKNOWN: c082d478 <unknown>
 
 mova    z0.s, p6/m, za3v.s[w12, 0]
 // CHECK-INST: mov     z0.s, p6/m, za3v.s[w12, 0]
 // CHECK-ENCODING: [0x80,0x99,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 82 c0 <unknown>
+// CHECK-UNKNOWN: c0829980 <unknown>
 
 mova    z17.s, p2/m, za0v.s[w14, 1]
 // CHECK-INST: mov     z17.s, p2/m, za0v.s[w14, 1]
 // CHECK-ENCODING: [0x31,0xc8,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 82 c0 <unknown>
+// CHECK-UNKNOWN: c082c831 <unknown>
 
 mova    z29.s, p2/m, za1v.s[w12, 2]
 // CHECK-INST: mov     z29.s, p2/m, za1v.s[w12, 2]
 // CHECK-ENCODING: [0xdd,0x88,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 88 82 c0 <unknown>
+// CHECK-UNKNOWN: c08288dd <unknown>
 
 mova    z2.s, p5/m, za2v.s[w15, 1]
 // CHECK-INST: mov     z2.s, p5/m, za2v.s[w15, 1]
 // CHECK-ENCODING: [0x22,0xf5,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 82 c0 <unknown>
+// CHECK-UNKNOWN: c082f522 <unknown>
 
 mova    z7.s, p2/m, za3v.s[w13, 0]
 // CHECK-INST: mov     z7.s, p2/m, za3v.s[w13, 0]
 // CHECK-ENCODING: [0x87,0xa9,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 82 c0 <unknown>
+// CHECK-UNKNOWN: c082a987 <unknown>
 
 // Aliases
 
@@ -838,73 +838,73 @@ mov     z0.s, p0/m, za0v.s[w12, 0]
 // CHECK-INST: mov     z0.s, p0/m, za0v.s[w12, 0]
 // CHECK-ENCODING: [0x00,0x80,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 82 c0 <unknown>
+// CHECK-UNKNOWN: c0828000 <unknown>
 
 mov     z21.s, p5/m, za2v.s[w14, 2]
 // CHECK-INST: mov     z21.s, p5/m, za2v.s[w14, 2]
 // CHECK-ENCODING: [0x55,0xd5,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 d5 82 c0 <unknown>
+// CHECK-UNKNOWN: c082d555 <unknown>
 
 mov     z23.s, p3/m, za3v.s[w15, 1]
 // CHECK-INST: mov     z23.s, p3/m, za3v.s[w15, 1]
 // CHECK-ENCODING: [0xb7,0xed,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 ed 82 c0 <unknown>
+// CHECK-UNKNOWN: c082edb7 <unknown>
 
 mov     z31.s, p7/m, za3v.s[w15, 3]
 // CHECK-INST: mov     z31.s, p7/m, za3v.s[w15, 3]
 // CHECK-ENCODING: [0xff,0xfd,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff fd 82 c0 <unknown>
+// CHECK-UNKNOWN: c082fdff <unknown>
 
 mov     z5.s, p3/m, za0v.s[w12, 1]
 // CHECK-INST: mov     z5.s, p3/m, za0v.s[w12, 1]
 // CHECK-ENCODING: [0x25,0x8c,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8c 82 c0 <unknown>
+// CHECK-UNKNOWN: c0828c25 <unknown>
 
 mov     z1.s, p1/m, za0v.s[w12, 1]
 // CHECK-INST: mov     z1.s, p1/m, za0v.s[w12, 1]
 // CHECK-ENCODING: [0x21,0x84,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 82 c0 <unknown>
+// CHECK-UNKNOWN: c0828421 <unknown>
 
 mov     z24.s, p5/m, za0v.s[w14, 3]
 // CHECK-INST: mov     z24.s, p5/m, za0v.s[w14, 3]
 // CHECK-ENCODING: [0x78,0xd4,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 d4 82 c0 <unknown>
+// CHECK-UNKNOWN: c082d478 <unknown>
 
 mov     z0.s, p6/m, za3v.s[w12, 0]
 // CHECK-INST: mov     z0.s, p6/m, za3v.s[w12, 0]
 // CHECK-ENCODING: [0x80,0x99,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 82 c0 <unknown>
+// CHECK-UNKNOWN: c0829980 <unknown>
 
 mov     z17.s, p2/m, za0v.s[w14, 1]
 // CHECK-INST: mov     z17.s, p2/m, za0v.s[w14, 1]
 // CHECK-ENCODING: [0x31,0xc8,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 82 c0 <unknown>
+// CHECK-UNKNOWN: c082c831 <unknown>
 
 mov     z29.s, p2/m, za1v.s[w12, 2]
 // CHECK-INST: mov     z29.s, p2/m, za1v.s[w12, 2]
 // CHECK-ENCODING: [0xdd,0x88,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 88 82 c0 <unknown>
+// CHECK-UNKNOWN: c08288dd <unknown>
 
 mov     z2.s, p5/m, za2v.s[w15, 1]
 // CHECK-INST: mov     z2.s, p5/m, za2v.s[w15, 1]
 // CHECK-ENCODING: [0x22,0xf5,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 82 c0 <unknown>
+// CHECK-UNKNOWN: c082f522 <unknown>
 
 mov     z7.s, p2/m, za3v.s[w13, 0]
 // CHECK-INST: mov     z7.s, p2/m, za3v.s[w13, 0]
 // CHECK-ENCODING: [0x87,0xa9,0x82,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 82 c0 <unknown>
+// CHECK-UNKNOWN: c082a987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Extract, tile to vector, horizontal, 64-bit
@@ -913,73 +913,73 @@ mova    z0.d, p0/m, za0h.d[w12, 0]
 // CHECK-INST: mov     z0.d, p0/m, za0h.d[w12, 0]
 // CHECK-ENCODING: [0x00,0x00,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c20000 <unknown>
 
 mova    z21.d, p5/m, za5h.d[w14, 0]
 // CHECK-INST: mov     z21.d, p5/m, za5h.d[w14, 0]
 // CHECK-ENCODING: [0x55,0x55,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 55 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c25555 <unknown>
 
 mova    z23.d, p3/m, za6h.d[w15, 1]
 // CHECK-INST: mov     z23.d, p3/m, za6h.d[w15, 1]
 // CHECK-ENCODING: [0xb7,0x6d,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 6d c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c26db7 <unknown>
 
 mova    z31.d, p7/m, za7h.d[w15, 1]
 // CHECK-INST: mov     z31.d, p7/m, za7h.d[w15, 1]
 // CHECK-ENCODING: [0xff,0x7d,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 7d c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c27dff <unknown>
 
 mova    z5.d, p3/m, za0h.d[w12, 1]
 // CHECK-INST: mov     z5.d, p3/m, za0h.d[w12, 1]
 // CHECK-ENCODING: [0x25,0x0c,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0c c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c20c25 <unknown>
 
 mova    z1.d, p1/m, za0h.d[w12, 1]
 // CHECK-INST: mov     z1.d, p1/m, za0h.d[w12, 1]
 // CHECK-ENCODING: [0x21,0x04,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c20421 <unknown>
 
 mova    z24.d, p5/m, za1h.d[w14, 1]
 // CHECK-INST: mov     z24.d, p5/m, za1h.d[w14, 1]
 // CHECK-ENCODING: [0x78,0x54,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 54 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c25478 <unknown>
 
 mova    z0.d, p6/m, za6h.d[w12, 0]
 // CHECK-INST: mov     z0.d, p6/m, za6h.d[w12, 0]
 // CHECK-ENCODING: [0x80,0x19,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c21980 <unknown>
 
 mova    z17.d, p2/m, za0h.d[w14, 1]
 // CHECK-INST: mov     z17.d, p2/m, za0h.d[w14, 1]
 // CHECK-ENCODING: [0x31,0x48,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 48 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c24831 <unknown>
 
 mova    z29.d, p2/m, za3h.d[w12, 0]
 // CHECK-INST: mov     z29.d, p2/m, za3h.d[w12, 0]
 // CHECK-ENCODING: [0xdd,0x08,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 08 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c208dd <unknown>
 
 mova    z2.d, p5/m, za4h.d[w15, 1]
 // CHECK-INST: mov     z2.d, p5/m, za4h.d[w15, 1]
 // CHECK-ENCODING: [0x22,0x75,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c27522 <unknown>
 
 mova    z7.d, p2/m, za6h.d[w13, 0]
 // CHECK-INST: mov     z7.d, p2/m, za6h.d[w13, 0]
 // CHECK-ENCODING: [0x87,0x29,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c22987 <unknown>
 
 // Aliases
 
@@ -987,73 +987,73 @@ mov     z0.d, p0/m, za0h.d[w12, 0]
 // CHECK-INST: mov     z0.d, p0/m, za0h.d[w12, 0]
 // CHECK-ENCODING: [0x00,0x00,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c20000 <unknown>
 
 mov     z21.d, p5/m, za5h.d[w14, 0]
 // CHECK-INST: mov     z21.d, p5/m, za5h.d[w14, 0]
 // CHECK-ENCODING: [0x55,0x55,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 55 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c25555 <unknown>
 
 mov     z23.d, p3/m, za6h.d[w15, 1]
 // CHECK-INST: mov     z23.d, p3/m, za6h.d[w15, 1]
 // CHECK-ENCODING: [0xb7,0x6d,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 6d c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c26db7 <unknown>
 
 mov     z31.d, p7/m, za7h.d[w15, 1]
 // CHECK-INST: mov     z31.d, p7/m, za7h.d[w15, 1]
 // CHECK-ENCODING: [0xff,0x7d,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 7d c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c27dff <unknown>
 
 mov     z5.d, p3/m, za0h.d[w12, 1]
 // CHECK-INST: mov     z5.d, p3/m, za0h.d[w12, 1]
 // CHECK-ENCODING: [0x25,0x0c,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0c c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c20c25 <unknown>
 
 mov     z1.d, p1/m, za0h.d[w12, 1]
 // CHECK-INST: mov     z1.d, p1/m, za0h.d[w12, 1]
 // CHECK-ENCODING: [0x21,0x04,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c20421 <unknown>
 
 mov     z24.d, p5/m, za1h.d[w14, 1]
 // CHECK-INST: mov     z24.d, p5/m, za1h.d[w14, 1]
 // CHECK-ENCODING: [0x78,0x54,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 54 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c25478 <unknown>
 
 mov     z0.d, p6/m, za6h.d[w12, 0]
 // CHECK-INST: mov     z0.d, p6/m, za6h.d[w12, 0]
 // CHECK-ENCODING: [0x80,0x19,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c21980 <unknown>
 
 mov     z17.d, p2/m, za0h.d[w14, 1]
 // CHECK-INST: mov     z17.d, p2/m, za0h.d[w14, 1]
 // CHECK-ENCODING: [0x31,0x48,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 48 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c24831 <unknown>
 
 mov     z29.d, p2/m, za3h.d[w12, 0]
 // CHECK-INST: mov     z29.d, p2/m, za3h.d[w12, 0]
 // CHECK-ENCODING: [0xdd,0x08,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 08 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c208dd <unknown>
 
 mov     z2.d, p5/m, za4h.d[w15, 1]
 // CHECK-INST: mov     z2.d, p5/m, za4h.d[w15, 1]
 // CHECK-ENCODING: [0x22,0x75,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c27522 <unknown>
 
 mov     z7.d, p2/m, za6h.d[w13, 0]
 // CHECK-INST: mov     z7.d, p2/m, za6h.d[w13, 0]
 // CHECK-ENCODING: [0x87,0x29,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c22987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Extract, tile to vector, vertical, 64-bit
@@ -1062,73 +1062,73 @@ mova    z0.d, p0/m, za0v.d[w12, 0]
 // CHECK-INST: mov     z0.d, p0/m, za0v.d[w12, 0]
 // CHECK-ENCODING: [0x00,0x80,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c28000 <unknown>
 
 mova    z21.d, p5/m, za5v.d[w14, 0]
 // CHECK-INST: mov     z21.d, p5/m, za5v.d[w14, 0]
 // CHECK-ENCODING: [0x55,0xd5,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 d5 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2d555 <unknown>
 
 mova    z23.d, p3/m, za6v.d[w15, 1]
 // CHECK-INST: mov     z23.d, p3/m, za6v.d[w15, 1]
 // CHECK-ENCODING: [0xb7,0xed,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 ed c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2edb7 <unknown>
 
 mova    z31.d, p7/m, za7v.d[w15, 1]
 // CHECK-INST: mov     z31.d, p7/m, za7v.d[w15, 1]
 // CHECK-ENCODING: [0xff,0xfd,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff fd c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2fdff <unknown>
 
 mova    z5.d, p3/m, za0v.d[w12, 1]
 // CHECK-INST: mov     z5.d, p3/m, za0v.d[w12, 1]
 // CHECK-ENCODING: [0x25,0x8c,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8c c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c28c25 <unknown>
 
 mova    z1.d, p1/m, za0v.d[w12, 1]
 // CHECK-INST: mov     z1.d, p1/m, za0v.d[w12, 1]
 // CHECK-ENCODING: [0x21,0x84,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c28421 <unknown>
 
 mova    z24.d, p5/m, za1v.d[w14, 1]
 // CHECK-INST: mov     z24.d, p5/m, za1v.d[w14, 1]
 // CHECK-ENCODING: [0x78,0xd4,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 d4 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2d478 <unknown>
 
 mova    z0.d, p6/m, za6v.d[w12, 0]
 // CHECK-INST: mov     z0.d, p6/m, za6v.d[w12, 0]
 // CHECK-ENCODING: [0x80,0x99,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c29980 <unknown>
 
 mova    z17.d, p2/m, za0v.d[w14, 1]
 // CHECK-INST: mov     z17.d, p2/m, za0v.d[w14, 1]
 // CHECK-ENCODING: [0x31,0xc8,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2c831 <unknown>
 
 mova    z29.d, p2/m, za3v.d[w12, 0]
 // CHECK-INST: mov     z29.d, p2/m, za3v.d[w12, 0]
 // CHECK-ENCODING: [0xdd,0x88,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 88 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c288dd <unknown>
 
 mova    z2.d, p5/m, za4v.d[w15, 1]
 // CHECK-INST: mov     z2.d, p5/m, za4v.d[w15, 1]
 // CHECK-ENCODING: [0x22,0xf5,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2f522 <unknown>
 
 mova    z7.d, p2/m, za6v.d[w13, 0]
 // CHECK-INST: mov     z7.d, p2/m, za6v.d[w13, 0]
 // CHECK-ENCODING: [0x87,0xa9,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2a987 <unknown>
 
 // Aliases
 
@@ -1136,73 +1136,73 @@ mov     z0.d, p0/m, za0v.d[w12, 0]
 // CHECK-INST: mov     z0.d, p0/m, za0v.d[w12, 0]
 // CHECK-ENCODING: [0x00,0x80,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c28000 <unknown>
 
 mov     z21.d, p5/m, za5v.d[w14, 0]
 // CHECK-INST: mov     z21.d, p5/m, za5v.d[w14, 0]
 // CHECK-ENCODING: [0x55,0xd5,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 d5 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2d555 <unknown>
 
 mov     z23.d, p3/m, za6v.d[w15, 1]
 // CHECK-INST: mov     z23.d, p3/m, za6v.d[w15, 1]
 // CHECK-ENCODING: [0xb7,0xed,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 ed c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2edb7 <unknown>
 
 mov     z31.d, p7/m, za7v.d[w15, 1]
 // CHECK-INST: mov     z31.d, p7/m, za7v.d[w15, 1]
 // CHECK-ENCODING: [0xff,0xfd,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff fd c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2fdff <unknown>
 
 mov     z5.d, p3/m, za0v.d[w12, 1]
 // CHECK-INST: mov     z5.d, p3/m, za0v.d[w12, 1]
 // CHECK-ENCODING: [0x25,0x8c,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8c c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c28c25 <unknown>
 
 mov     z1.d, p1/m, za0v.d[w12, 1]
 // CHECK-INST: mov     z1.d, p1/m, za0v.d[w12, 1]
 // CHECK-ENCODING: [0x21,0x84,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c28421 <unknown>
 
 mov     z24.d, p5/m, za1v.d[w14, 1]
 // CHECK-INST: mov     z24.d, p5/m, za1v.d[w14, 1]
 // CHECK-ENCODING: [0x78,0xd4,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 d4 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2d478 <unknown>
 
 mov     z0.d, p6/m, za6v.d[w12, 0]
 // CHECK-INST: mov     z0.d, p6/m, za6v.d[w12, 0]
 // CHECK-ENCODING: [0x80,0x99,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c29980 <unknown>
 
 mov     z17.d, p2/m, za0v.d[w14, 1]
 // CHECK-INST: mov     z17.d, p2/m, za0v.d[w14, 1]
 // CHECK-ENCODING: [0x31,0xc8,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2c831 <unknown>
 
 mov     z29.d, p2/m, za3v.d[w12, 0]
 // CHECK-INST: mov     z29.d, p2/m, za3v.d[w12, 0]
 // CHECK-ENCODING: [0xdd,0x88,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 88 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c288dd <unknown>
 
 mov     z2.d, p5/m, za4v.d[w15, 1]
 // CHECK-INST: mov     z2.d, p5/m, za4v.d[w15, 1]
 // CHECK-ENCODING: [0x22,0xf5,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2f522 <unknown>
 
 mov     z7.d, p2/m, za6v.d[w13, 0]
 // CHECK-INST: mov     z7.d, p2/m, za6v.d[w13, 0]
 // CHECK-ENCODING: [0x87,0xa9,0xc2,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 c2 c0 <unknown>
+// CHECK-UNKNOWN: c0c2a987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Extract, tile to vector, horizontal, 128-bit
@@ -1211,73 +1211,73 @@ mova    z0.q, p0/m, za0h.q[w12, 0]
 // CHECK-INST: mov     z0.q, p0/m, za0h.q[w12, 0]
 // CHECK-ENCODING: [0x00,0x00,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c30000 <unknown>
 
 mova    z21.q, p5/m, za10h.q[w14, 0]
 // CHECK-INST: mov     z21.q, p5/m, za10h.q[w14, 0]
 // CHECK-ENCODING: [0x55,0x55,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 55 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c35555 <unknown>
 
 mova    z23.q, p3/m, za13h.q[w15, 0]
 // CHECK-INST: mov     z23.q, p3/m, za13h.q[w15, 0]
 // CHECK-ENCODING: [0xb7,0x6d,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 6d c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c36db7 <unknown>
 
 mova    z31.q, p7/m, za15h.q[w15, 0]
 // CHECK-INST: mov     z31.q, p7/m, za15h.q[w15, 0]
 // CHECK-ENCODING: [0xff,0x7d,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 7d c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c37dff <unknown>
 
 mova    z5.q, p3/m, za1h.q[w12, 0]
 // CHECK-INST: mov     z5.q, p3/m, za1h.q[w12, 0]
 // CHECK-ENCODING: [0x25,0x0c,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0c c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c30c25 <unknown>
 
 mova    z1.q, p1/m, za1h.q[w12, 0]
 // CHECK-INST: mov     z1.q, p1/m, za1h.q[w12, 0]
 // CHECK-ENCODING: [0x21,0x04,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c30421 <unknown>
 
 mova    z24.q, p5/m, za3h.q[w14, 0]
 // CHECK-INST: mov     z24.q, p5/m, za3h.q[w14, 0]
 // CHECK-ENCODING: [0x78,0x54,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 54 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c35478 <unknown>
 
 mova    z0.q, p6/m, za12h.q[w12, 0]
 // CHECK-INST: mov     z0.q, p6/m, za12h.q[w12, 0]
 // CHECK-ENCODING: [0x80,0x19,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c31980 <unknown>
 
 mova    z17.q, p2/m, za1h.q[w14, 0]
 // CHECK-INST: mov     z17.q, p2/m, za1h.q[w14, 0]
 // CHECK-ENCODING: [0x31,0x48,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 48 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c34831 <unknown>
 
 mova    z29.q, p2/m, za6h.q[w12, 0]
 // CHECK-INST: mov     z29.q, p2/m, za6h.q[w12, 0]
 // CHECK-ENCODING: [0xdd,0x08,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 08 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c308dd <unknown>
 
 mova    z2.q, p5/m, za9h.q[w15, 0]
 // CHECK-INST: mov     z2.q, p5/m, za9h.q[w15, 0]
 // CHECK-ENCODING: [0x22,0x75,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c37522 <unknown>
 
 mova    z7.q, p2/m, za12h.q[w13, 0]
 // CHECK-INST: mov     z7.q, p2/m, za12h.q[w13, 0]
 // CHECK-ENCODING: [0x87,0x29,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c32987 <unknown>
 
 // Aliases
 
@@ -1285,73 +1285,73 @@ mov     z0.q, p0/m, za0h.q[w12, 0]
 // CHECK-INST: mov     z0.q, p0/m, za0h.q[w12, 0]
 // CHECK-ENCODING: [0x00,0x00,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c30000 <unknown>
 
 mov     z21.q, p5/m, za10h.q[w14, 0]
 // CHECK-INST: mov     z21.q, p5/m, za10h.q[w14, 0]
 // CHECK-ENCODING: [0x55,0x55,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 55 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c35555 <unknown>
 
 mov     z23.q, p3/m, za13h.q[w15, 0]
 // CHECK-INST: mov     z23.q, p3/m, za13h.q[w15, 0]
 // CHECK-ENCODING: [0xb7,0x6d,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 6d c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c36db7 <unknown>
 
 mov     z31.q, p7/m, za15h.q[w15, 0]
 // CHECK-INST: mov     z31.q, p7/m, za15h.q[w15, 0]
 // CHECK-ENCODING: [0xff,0x7d,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 7d c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c37dff <unknown>
 
 mov     z5.q, p3/m, za1h.q[w12, 0]
 // CHECK-INST: mov     z5.q, p3/m, za1h.q[w12, 0]
 // CHECK-ENCODING: [0x25,0x0c,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0c c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c30c25 <unknown>
 
 mov     z1.q, p1/m, za1h.q[w12, 0]
 // CHECK-INST: mov     z1.q, p1/m, za1h.q[w12, 0]
 // CHECK-ENCODING: [0x21,0x04,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c30421 <unknown>
 
 mov     z24.q, p5/m, za3h.q[w14, 0]
 // CHECK-INST: mov     z24.q, p5/m, za3h.q[w14, 0]
 // CHECK-ENCODING: [0x78,0x54,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 54 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c35478 <unknown>
 
 mov     z0.q, p6/m, za12h.q[w12, 0]
 // CHECK-INST: mov     z0.q, p6/m, za12h.q[w12, 0]
 // CHECK-ENCODING: [0x80,0x19,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c31980 <unknown>
 
 mov     z17.q, p2/m, za1h.q[w14, 0]
 // CHECK-INST: mov     z17.q, p2/m, za1h.q[w14, 0]
 // CHECK-ENCODING: [0x31,0x48,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 48 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c34831 <unknown>
 
 mov     z29.q, p2/m, za6h.q[w12, 0]
 // CHECK-INST: mov     z29.q, p2/m, za6h.q[w12, 0]
 // CHECK-ENCODING: [0xdd,0x08,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 08 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c308dd <unknown>
 
 mov     z2.q, p5/m, za9h.q[w15, 0]
 // CHECK-INST: mov     z2.q, p5/m, za9h.q[w15, 0]
 // CHECK-ENCODING: [0x22,0x75,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c37522 <unknown>
 
 mov     z7.q, p2/m, za12h.q[w13, 0]
 // CHECK-INST: mov     z7.q, p2/m, za12h.q[w13, 0]
 // CHECK-ENCODING: [0x87,0x29,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c32987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Extract, tile to vector, vertical, 128-bit
@@ -1360,73 +1360,73 @@ mova    z0.q, p0/m, za0v.q[w12, 0]
 // CHECK-INST: mov     z0.q, p0/m, za0v.q[w12, 0]
 // CHECK-ENCODING: [0x00,0x80,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c38000 <unknown>
 
 mova    z21.q, p5/m, za10v.q[w14, 0]
 // CHECK-INST: mov     z21.q, p5/m, za10v.q[w14, 0]
 // CHECK-ENCODING: [0x55,0xd5,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 d5 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3d555 <unknown>
 
 mova    z23.q, p3/m, za13v.q[w15, 0]
 // CHECK-INST: mov     z23.q, p3/m, za13v.q[w15, 0]
 // CHECK-ENCODING: [0xb7,0xed,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 ed c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3edb7 <unknown>
 
 mova    z31.q, p7/m, za15v.q[w15, 0]
 // CHECK-INST: mov     z31.q, p7/m, za15v.q[w15, 0]
 // CHECK-ENCODING: [0xff,0xfd,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff fd c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3fdff <unknown>
 
 mova    z5.q, p3/m, za1v.q[w12, 0]
 // CHECK-INST: mov     z5.q, p3/m, za1v.q[w12, 0]
 // CHECK-ENCODING: [0x25,0x8c,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8c c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c38c25 <unknown>
 
 mova    z1.q, p1/m, za1v.q[w12, 0]
 // CHECK-INST: mov     z1.q, p1/m, za1v.q[w12, 0]
 // CHECK-ENCODING: [0x21,0x84,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c38421 <unknown>
 
 mova    z24.q, p5/m, za3v.q[w14, 0]
 // CHECK-INST: mov     z24.q, p5/m, za3v.q[w14, 0]
 // CHECK-ENCODING: [0x78,0xd4,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 d4 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3d478 <unknown>
 
 mova    z0.q, p6/m, za12v.q[w12, 0]
 // CHECK-INST: mov     z0.q, p6/m, za12v.q[w12, 0]
 // CHECK-ENCODING: [0x80,0x99,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c39980 <unknown>
 
 mova    z17.q, p2/m, za1v.q[w14, 0]
 // CHECK-INST: mov     z17.q, p2/m, za1v.q[w14, 0]
 // CHECK-ENCODING: [0x31,0xc8,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3c831 <unknown>
 
 mova    z29.q, p2/m, za6v.q[w12, 0]
 // CHECK-INST: mov     z29.q, p2/m, za6v.q[w12, 0]
 // CHECK-ENCODING: [0xdd,0x88,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 88 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c388dd <unknown>
 
 mova    z2.q, p5/m, za9v.q[w15, 0]
 // CHECK-INST: mov     z2.q, p5/m, za9v.q[w15, 0]
 // CHECK-ENCODING: [0x22,0xf5,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3f522 <unknown>
 
 mova    z7.q, p2/m, za12v.q[w13, 0]
 // CHECK-INST: mov     z7.q, p2/m, za12v.q[w13, 0]
 // CHECK-ENCODING: [0x87,0xa9,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3a987 <unknown>
 
 // Aliases
 
@@ -1434,73 +1434,73 @@ mov     z0.q, p0/m, za0v.q[w12, 0]
 // CHECK-INST: mov     z0.q, p0/m, za0v.q[w12, 0]
 // CHECK-ENCODING: [0x00,0x80,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c38000 <unknown>
 
 mov     z21.q, p5/m, za10v.q[w14, 0]
 // CHECK-INST: mov     z21.q, p5/m, za10v.q[w14, 0]
 // CHECK-ENCODING: [0x55,0xd5,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 d5 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3d555 <unknown>
 
 mov     z23.q, p3/m, za13v.q[w15, 0]
 // CHECK-INST: mov     z23.q, p3/m, za13v.q[w15, 0]
 // CHECK-ENCODING: [0xb7,0xed,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 ed c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3edb7 <unknown>
 
 mov     z31.q, p7/m, za15v.q[w15, 0]
 // CHECK-INST: mov     z31.q, p7/m, za15v.q[w15, 0]
 // CHECK-ENCODING: [0xff,0xfd,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff fd c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3fdff <unknown>
 
 mov     z5.q, p3/m, za1v.q[w12, 0]
 // CHECK-INST: mov     z5.q, p3/m, za1v.q[w12, 0]
 // CHECK-ENCODING: [0x25,0x8c,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8c c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c38c25 <unknown>
 
 mov     z1.q, p1/m, za1v.q[w12, 0]
 // CHECK-INST: mov     z1.q, p1/m, za1v.q[w12, 0]
 // CHECK-ENCODING: [0x21,0x84,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c38421 <unknown>
 
 mov     z24.q, p5/m, za3v.q[w14, 0]
 // CHECK-INST: mov     z24.q, p5/m, za3v.q[w14, 0]
 // CHECK-ENCODING: [0x78,0xd4,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 78 d4 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3d478 <unknown>
 
 mov     z0.q, p6/m, za12v.q[w12, 0]
 // CHECK-INST: mov     z0.q, p6/m, za12v.q[w12, 0]
 // CHECK-ENCODING: [0x80,0x99,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c39980 <unknown>
 
 mov     z17.q, p2/m, za1v.q[w14, 0]
 // CHECK-INST: mov     z17.q, p2/m, za1v.q[w14, 0]
 // CHECK-ENCODING: [0x31,0xc8,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3c831 <unknown>
 
 mov     z29.q, p2/m, za6v.q[w12, 0]
 // CHECK-INST: mov     z29.q, p2/m, za6v.q[w12, 0]
 // CHECK-ENCODING: [0xdd,0x88,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 88 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c388dd <unknown>
 
 mov     z2.q, p5/m, za9v.q[w15, 0]
 // CHECK-INST: mov     z2.q, p5/m, za9v.q[w15, 0]
 // CHECK-ENCODING: [0x22,0xf5,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3f522 <unknown>
 
 mov     z7.q, p2/m, za12v.q[w13, 0]
 // CHECK-INST: mov     z7.q, p2/m, za12v.q[w13, 0]
 // CHECK-ENCODING: [0x87,0xa9,0xc3,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 c3 c0 <unknown>
+// CHECK-UNKNOWN: c0c3a987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Insert, vector to tile, horizontal, 8-bit
@@ -1509,73 +1509,73 @@ mova    za0h.b[w12, 0], p0/m, z0.b
 // CHECK-INST: mov     za0h.b[w12, 0], p0/m, z0.b
 // CHECK-ENCODING: [0x00,0x00,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 00 c0 <unknown>
+// CHECK-UNKNOWN: c0000000 <unknown>
 
 mova    za0h.b[w14, 5], p5/m, z10.b
 // CHECK-INST: mov     za0h.b[w14, 5], p5/m, z10.b
 // CHECK-ENCODING: [0x45,0x55,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 00 c0 <unknown>
+// CHECK-UNKNOWN: c0005545 <unknown>
 
 mova    za0h.b[w15, 7], p3/m, z13.b
 // CHECK-INST: mov     za0h.b[w15, 7], p3/m, z13.b
 // CHECK-ENCODING: [0xa7,0x6d,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 00 c0 <unknown>
+// CHECK-UNKNOWN: c0006da7 <unknown>
 
 mova    za0h.b[w15, 15], p7/m, z31.b
 // CHECK-INST: mov     za0h.b[w15, 15], p7/m, z31.b
 // CHECK-ENCODING: [0xef,0x7f,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 00 c0 <unknown>
+// CHECK-UNKNOWN: c0007fef <unknown>
 
 mova    za0h.b[w12, 5], p3/m, z17.b
 // CHECK-INST: mov     za0h.b[w12, 5], p3/m, z17.b
 // CHECK-ENCODING: [0x25,0x0e,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 00 c0 <unknown>
+// CHECK-UNKNOWN: c0000e25 <unknown>
 
 mova    za0h.b[w12, 1], p1/m, z1.b
 // CHECK-INST: mov     za0h.b[w12, 1], p1/m, z1.b
 // CHECK-ENCODING: [0x21,0x04,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 00 c0 <unknown>
+// CHECK-UNKNOWN: c0000421 <unknown>
 
 mova    za0h.b[w14, 8], p5/m, z19.b
 // CHECK-INST: mov     za0h.b[w14, 8], p5/m, z19.b
 // CHECK-ENCODING: [0x68,0x56,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 00 c0 <unknown>
+// CHECK-UNKNOWN: c0005668 <unknown>
 
 mova    za0h.b[w12, 0], p6/m, z12.b
 // CHECK-INST: mov     za0h.b[w12, 0], p6/m, z12.b
 // CHECK-ENCODING: [0x80,0x19,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 00 c0 <unknown>
+// CHECK-UNKNOWN: c0001980 <unknown>
 
 mova    za0h.b[w14, 1], p2/m, z1.b
 // CHECK-INST: mov     za0h.b[w14, 1], p2/m, z1.b
 // CHECK-ENCODING: [0x21,0x48,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 00 c0 <unknown>
+// CHECK-UNKNOWN: c0004821 <unknown>
 
 mova    za0h.b[w12, 13], p2/m, z22.b
 // CHECK-INST: mov     za0h.b[w12, 13], p2/m, z22.b
 // CHECK-ENCODING: [0xcd,0x0a,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 00 c0 <unknown>
+// CHECK-UNKNOWN: c0000acd <unknown>
 
 mova    za0h.b[w15, 2], p5/m, z9.b
 // CHECK-INST: mov     za0h.b[w15, 2], p5/m, z9.b
 // CHECK-ENCODING: [0x22,0x75,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 00 c0 <unknown>
+// CHECK-UNKNOWN: c0007522 <unknown>
 
 mova    za0h.b[w13, 7], p2/m, z12.b
 // CHECK-INST: mov     za0h.b[w13, 7], p2/m, z12.b
 // CHECK-ENCODING: [0x87,0x29,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 00 c0 <unknown>
+// CHECK-UNKNOWN: c0002987 <unknown>
 
 // Aliases
 
@@ -1583,73 +1583,73 @@ mov     za0h.b[w12, 0], p0/m, z0.b
 // CHECK-INST: mov     za0h.b[w12, 0], p0/m, z0.b
 // CHECK-ENCODING: [0x00,0x00,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 00 c0 <unknown>
+// CHECK-UNKNOWN: c0000000 <unknown>
 
 mov     za0h.b[w14, 5], p5/m, z10.b
 // CHECK-INST: mov     za0h.b[w14, 5], p5/m, z10.b
 // CHECK-ENCODING: [0x45,0x55,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 00 c0 <unknown>
+// CHECK-UNKNOWN: c0005545 <unknown>
 
 mov     za0h.b[w15, 7], p3/m, z13.b
 // CHECK-INST: mov     za0h.b[w15, 7], p3/m, z13.b
 // CHECK-ENCODING: [0xa7,0x6d,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 00 c0 <unknown>
+// CHECK-UNKNOWN: c0006da7 <unknown>
 
 mov     za0h.b[w15, 15], p7/m, z31.b
 // CHECK-INST: mov     za0h.b[w15, 15], p7/m, z31.b
 // CHECK-ENCODING: [0xef,0x7f,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 00 c0 <unknown>
+// CHECK-UNKNOWN: c0007fef <unknown>
 
 mov     za0h.b[w12, 5], p3/m, z17.b
 // CHECK-INST: mov     za0h.b[w12, 5], p3/m, z17.b
 // CHECK-ENCODING: [0x25,0x0e,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 00 c0 <unknown>
+// CHECK-UNKNOWN: c0000e25 <unknown>
 
 mov     za0h.b[w12, 1], p1/m, z1.b
 // CHECK-INST: mov     za0h.b[w12, 1], p1/m, z1.b
 // CHECK-ENCODING: [0x21,0x04,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 00 c0 <unknown>
+// CHECK-UNKNOWN: c0000421 <unknown>
 
 mov     za0h.b[w14, 8], p5/m, z19.b
 // CHECK-INST: mov     za0h.b[w14, 8], p5/m, z19.b
 // CHECK-ENCODING: [0x68,0x56,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 00 c0 <unknown>
+// CHECK-UNKNOWN: c0005668 <unknown>
 
 mov     za0h.b[w12, 0], p6/m, z12.b
 // CHECK-INST: mov     za0h.b[w12, 0], p6/m, z12.b
 // CHECK-ENCODING: [0x80,0x19,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 00 c0 <unknown>
+// CHECK-UNKNOWN: c0001980 <unknown>
 
 mov     za0h.b[w14, 1], p2/m, z1.b
 // CHECK-INST: mov     za0h.b[w14, 1], p2/m, z1.b
 // CHECK-ENCODING: [0x21,0x48,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 00 c0 <unknown>
+// CHECK-UNKNOWN: c0004821 <unknown>
 
 mov     za0h.b[w12, 13], p2/m, z22.b
 // CHECK-INST: mov     za0h.b[w12, 13], p2/m, z22.b
 // CHECK-ENCODING: [0xcd,0x0a,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 00 c0 <unknown>
+// CHECK-UNKNOWN: c0000acd <unknown>
 
 mov     za0h.b[w15, 2], p5/m, z9.b
 // CHECK-INST: mov     za0h.b[w15, 2], p5/m, z9.b
 // CHECK-ENCODING: [0x22,0x75,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 00 c0 <unknown>
+// CHECK-UNKNOWN: c0007522 <unknown>
 
 mov     za0h.b[w13, 7], p2/m, z12.b
 // CHECK-INST: mov     za0h.b[w13, 7], p2/m, z12.b
 // CHECK-ENCODING: [0x87,0x29,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 00 c0 <unknown>
+// CHECK-UNKNOWN: c0002987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Insert, vector to tile, vertical, 8-bit
@@ -1658,73 +1658,73 @@ mova    za0v.b[w12, 0], p0/m, z0.b
 // CHECK-INST: mov     za0v.b[w12, 0], p0/m, z0.b
 // CHECK-ENCODING: [0x00,0x80,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 00 c0 <unknown>
+// CHECK-UNKNOWN: c0008000 <unknown>
 
 mova    za0v.b[w14, 5], p5/m, z10.b
 // CHECK-INST: mov     za0v.b[w14, 5], p5/m, z10.b
 // CHECK-ENCODING: [0x45,0xd5,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 00 c0 <unknown>
+// CHECK-UNKNOWN: c000d545 <unknown>
 
 mova    za0v.b[w15, 7], p3/m, z13.b
 // CHECK-INST: mov     za0v.b[w15, 7], p3/m, z13.b
 // CHECK-ENCODING: [0xa7,0xed,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 00 c0 <unknown>
+// CHECK-UNKNOWN: c000eda7 <unknown>
 
 mova    za0v.b[w15, 15], p7/m, z31.b
 // CHECK-INST: mov     za0v.b[w15, 15], p7/m, z31.b
 // CHECK-ENCODING: [0xef,0xff,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 00 c0 <unknown>
+// CHECK-UNKNOWN: c000ffef <unknown>
 
 mova    za0v.b[w12, 5], p3/m, z17.b
 // CHECK-INST: mov     za0v.b[w12, 5], p3/m, z17.b
 // CHECK-ENCODING: [0x25,0x8e,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 00 c0 <unknown>
+// CHECK-UNKNOWN: c0008e25 <unknown>
 
 mova    za0v.b[w12, 1], p1/m, z1.b
 // CHECK-INST: mov     za0v.b[w12, 1], p1/m, z1.b
 // CHECK-ENCODING: [0x21,0x84,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 00 c0 <unknown>
+// CHECK-UNKNOWN: c0008421 <unknown>
 
 mova    za0v.b[w14, 8], p5/m, z19.b
 // CHECK-INST: mov     za0v.b[w14, 8], p5/m, z19.b
 // CHECK-ENCODING: [0x68,0xd6,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 00 c0 <unknown>
+// CHECK-UNKNOWN: c000d668 <unknown>
 
 mova    za0v.b[w12, 0], p6/m, z12.b
 // CHECK-INST: mov     za0v.b[w12, 0], p6/m, z12.b
 // CHECK-ENCODING: [0x80,0x99,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 00 c0 <unknown>
+// CHECK-UNKNOWN: c0009980 <unknown>
 
 mova    za0v.b[w14, 1], p2/m, z1.b
 // CHECK-INST: mov     za0v.b[w14, 1], p2/m, z1.b
 // CHECK-ENCODING: [0x21,0xc8,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 00 c0 <unknown>
+// CHECK-UNKNOWN: c000c821 <unknown>
 
 mova    za0v.b[w12, 13], p2/m, z22.b
 // CHECK-INST: mov     za0v.b[w12, 13], p2/m, z22.b
 // CHECK-ENCODING: [0xcd,0x8a,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 00 c0 <unknown>
+// CHECK-UNKNOWN: c0008acd <unknown>
 
 mova    za0v.b[w15, 2], p5/m, z9.b
 // CHECK-INST: mov     za0v.b[w15, 2], p5/m, z9.b
 // CHECK-ENCODING: [0x22,0xf5,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 00 c0 <unknown>
+// CHECK-UNKNOWN: c000f522 <unknown>
 
 mova    za0v.b[w13, 7], p2/m, z12.b
 // CHECK-INST: mov     za0v.b[w13, 7], p2/m, z12.b
 // CHECK-ENCODING: [0x87,0xa9,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 00 c0 <unknown>
+// CHECK-UNKNOWN: c000a987 <unknown>
 
 // Aliases
 
@@ -1732,73 +1732,73 @@ mov     za0v.b[w12, 0], p0/m, z0.b
 // CHECK-INST: mov     za0v.b[w12, 0], p0/m, z0.b
 // CHECK-ENCODING: [0x00,0x80,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 00 c0 <unknown>
+// CHECK-UNKNOWN: c0008000 <unknown>
 
 mov     za0v.b[w14, 5], p5/m, z10.b
 // CHECK-INST: mov     za0v.b[w14, 5], p5/m, z10.b
 // CHECK-ENCODING: [0x45,0xd5,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 00 c0 <unknown>
+// CHECK-UNKNOWN: c000d545 <unknown>
 
 mov     za0v.b[w15, 7], p3/m, z13.b
 // CHECK-INST: mov     za0v.b[w15, 7], p3/m, z13.b
 // CHECK-ENCODING: [0xa7,0xed,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 00 c0 <unknown>
+// CHECK-UNKNOWN: c000eda7 <unknown>
 
 mov     za0v.b[w15, 15], p7/m, z31.b
 // CHECK-INST: mov     za0v.b[w15, 15], p7/m, z31.b
 // CHECK-ENCODING: [0xef,0xff,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 00 c0 <unknown>
+// CHECK-UNKNOWN: c000ffef <unknown>
 
 mov     za0v.b[w12, 5], p3/m, z17.b
 // CHECK-INST: mov     za0v.b[w12, 5], p3/m, z17.b
 // CHECK-ENCODING: [0x25,0x8e,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 00 c0 <unknown>
+// CHECK-UNKNOWN: c0008e25 <unknown>
 
 mov     za0v.b[w12, 1], p1/m, z1.b
 // CHECK-INST: mov     za0v.b[w12, 1], p1/m, z1.b
 // CHECK-ENCODING: [0x21,0x84,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 00 c0 <unknown>
+// CHECK-UNKNOWN: c0008421 <unknown>
 
 mov     za0v.b[w14, 8], p5/m, z19.b
 // CHECK-INST: mov     za0v.b[w14, 8], p5/m, z19.b
 // CHECK-ENCODING: [0x68,0xd6,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 00 c0 <unknown>
+// CHECK-UNKNOWN: c000d668 <unknown>
 
 mov     za0v.b[w12, 0], p6/m, z12.b
 // CHECK-INST: mov     za0v.b[w12, 0], p6/m, z12.b
 // CHECK-ENCODING: [0x80,0x99,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 00 c0 <unknown>
+// CHECK-UNKNOWN: c0009980 <unknown>
 
 mov     za0v.b[w14, 1], p2/m, z1.b
 // CHECK-INST: mov     za0v.b[w14, 1], p2/m, z1.b
 // CHECK-ENCODING: [0x21,0xc8,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 00 c0 <unknown>
+// CHECK-UNKNOWN: c000c821 <unknown>
 
 mov     za0v.b[w12, 13], p2/m, z22.b
 // CHECK-INST: mov     za0v.b[w12, 13], p2/m, z22.b
 // CHECK-ENCODING: [0xcd,0x8a,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 00 c0 <unknown>
+// CHECK-UNKNOWN: c0008acd <unknown>
 
 mov     za0v.b[w15, 2], p5/m, z9.b
 // CHECK-INST: mov     za0v.b[w15, 2], p5/m, z9.b
 // CHECK-ENCODING: [0x22,0xf5,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 00 c0 <unknown>
+// CHECK-UNKNOWN: c000f522 <unknown>
 
 mov     za0v.b[w13, 7], p2/m, z12.b
 // CHECK-INST: mov     za0v.b[w13, 7], p2/m, z12.b
 // CHECK-ENCODING: [0x87,0xa9,0x00,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 00 c0 <unknown>
+// CHECK-UNKNOWN: c000a987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Insert, vector to tile, horizontal, 16-bit
@@ -1807,73 +1807,73 @@ mova    za0h.h[w12, 0], p0/m, z0.h
 // CHECK-INST: mov     za0h.h[w12, 0], p0/m, z0.h
 // CHECK-ENCODING: [0x00,0x00,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 40 c0 <unknown>
+// CHECK-UNKNOWN: c0400000 <unknown>
 
 mova    za0h.h[w14, 5], p5/m, z10.h
 // CHECK-INST: mov     za0h.h[w14, 5], p5/m, z10.h
 // CHECK-ENCODING: [0x45,0x55,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 40 c0 <unknown>
+// CHECK-UNKNOWN: c0405545 <unknown>
 
 mova    za0h.h[w15, 7], p3/m, z13.h
 // CHECK-INST: mov     za0h.h[w15, 7], p3/m, z13.h
 // CHECK-ENCODING: [0xa7,0x6d,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 40 c0 <unknown>
+// CHECK-UNKNOWN: c0406da7 <unknown>
 
 mova    za1h.h[w15, 7], p7/m, z31.h
 // CHECK-INST: mov     za1h.h[w15, 7], p7/m, z31.h
 // CHECK-ENCODING: [0xef,0x7f,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 40 c0 <unknown>
+// CHECK-UNKNOWN: c0407fef <unknown>
 
 mova    za0h.h[w12, 5], p3/m, z17.h
 // CHECK-INST: mov     za0h.h[w12, 5], p3/m, z17.h
 // CHECK-ENCODING: [0x25,0x0e,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 40 c0 <unknown>
+// CHECK-UNKNOWN: c0400e25 <unknown>
 
 mova    za0h.h[w12, 1], p1/m, z1.h
 // CHECK-INST: mov     za0h.h[w12, 1], p1/m, z1.h
 // CHECK-ENCODING: [0x21,0x04,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 40 c0 <unknown>
+// CHECK-UNKNOWN: c0400421 <unknown>
 
 mova    za1h.h[w14, 0], p5/m, z19.h
 // CHECK-INST: mov     za1h.h[w14, 0], p5/m, z19.h
 // CHECK-ENCODING: [0x68,0x56,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 40 c0 <unknown>
+// CHECK-UNKNOWN: c0405668 <unknown>
 
 mova    za0h.h[w12, 0], p6/m, z12.h
 // CHECK-INST: mov     za0h.h[w12, 0], p6/m, z12.h
 // CHECK-ENCODING: [0x80,0x19,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 40 c0 <unknown>
+// CHECK-UNKNOWN: c0401980 <unknown>
 
 mova    za0h.h[w14, 1], p2/m, z1.h
 // CHECK-INST: mov     za0h.h[w14, 1], p2/m, z1.h
 // CHECK-ENCODING: [0x21,0x48,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 40 c0 <unknown>
+// CHECK-UNKNOWN: c0404821 <unknown>
 
 mova    za1h.h[w12, 5], p2/m, z22.h
 // CHECK-INST: mov     za1h.h[w12, 5], p2/m, z22.h
 // CHECK-ENCODING: [0xcd,0x0a,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 40 c0 <unknown>
+// CHECK-UNKNOWN: c0400acd <unknown>
 
 mova    za0h.h[w15, 2], p5/m, z9.h
 // CHECK-INST: mov     za0h.h[w15, 2], p5/m, z9.h
 // CHECK-ENCODING: [0x22,0x75,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 40 c0 <unknown>
+// CHECK-UNKNOWN: c0407522 <unknown>
 
 mova    za0h.h[w13, 7], p2/m, z12.h
 // CHECK-INST: mov     za0h.h[w13, 7], p2/m, z12.h
 // CHECK-ENCODING: [0x87,0x29,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 40 c0 <unknown>
+// CHECK-UNKNOWN: c0402987 <unknown>
 
 // Aliases
 
@@ -1881,73 +1881,73 @@ mov     za0h.h[w12, 0], p0/m, z0.h
 // CHECK-INST: mov     za0h.h[w12, 0], p0/m, z0.h
 // CHECK-ENCODING: [0x00,0x00,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 40 c0 <unknown>
+// CHECK-UNKNOWN: c0400000 <unknown>
 
 mov     za0h.h[w14, 5], p5/m, z10.h
 // CHECK-INST: mov     za0h.h[w14, 5], p5/m, z10.h
 // CHECK-ENCODING: [0x45,0x55,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 40 c0 <unknown>
+// CHECK-UNKNOWN: c0405545 <unknown>
 
 mov     za0h.h[w15, 7], p3/m, z13.h
 // CHECK-INST: mov     za0h.h[w15, 7], p3/m, z13.h
 // CHECK-ENCODING: [0xa7,0x6d,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 40 c0 <unknown>
+// CHECK-UNKNOWN: c0406da7 <unknown>
 
 mov     za1h.h[w15, 7], p7/m, z31.h
 // CHECK-INST: mov     za1h.h[w15, 7], p7/m, z31.h
 // CHECK-ENCODING: [0xef,0x7f,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 40 c0 <unknown>
+// CHECK-UNKNOWN: c0407fef <unknown>
 
 mov     za0h.h[w12, 5], p3/m, z17.h
 // CHECK-INST: mov     za0h.h[w12, 5], p3/m, z17.h
 // CHECK-ENCODING: [0x25,0x0e,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 40 c0 <unknown>
+// CHECK-UNKNOWN: c0400e25 <unknown>
 
 mov     za0h.h[w12, 1], p1/m, z1.h
 // CHECK-INST: mov     za0h.h[w12, 1], p1/m, z1.h
 // CHECK-ENCODING: [0x21,0x04,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 40 c0 <unknown>
+// CHECK-UNKNOWN: c0400421 <unknown>
 
 mov     za1h.h[w14, 0], p5/m, z19.h
 // CHECK-INST: mov     za1h.h[w14, 0], p5/m, z19.h
 // CHECK-ENCODING: [0x68,0x56,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 40 c0 <unknown>
+// CHECK-UNKNOWN: c0405668 <unknown>
 
 mov     za0h.h[w12, 0], p6/m, z12.h
 // CHECK-INST: mov     za0h.h[w12, 0], p6/m, z12.h
 // CHECK-ENCODING: [0x80,0x19,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 40 c0 <unknown>
+// CHECK-UNKNOWN: c0401980 <unknown>
 
 mov     za0h.h[w14, 1], p2/m, z1.h
 // CHECK-INST: mov     za0h.h[w14, 1], p2/m, z1.h
 // CHECK-ENCODING: [0x21,0x48,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 40 c0 <unknown>
+// CHECK-UNKNOWN: c0404821 <unknown>
 
 mov     za1h.h[w12, 5], p2/m, z22.h
 // CHECK-INST: mov     za1h.h[w12, 5], p2/m, z22.h
 // CHECK-ENCODING: [0xcd,0x0a,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 40 c0 <unknown>
+// CHECK-UNKNOWN: c0400acd <unknown>
 
 mov     za0h.h[w15, 2], p5/m, z9.h
 // CHECK-INST: mov     za0h.h[w15, 2], p5/m, z9.h
 // CHECK-ENCODING: [0x22,0x75,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 40 c0 <unknown>
+// CHECK-UNKNOWN: c0407522 <unknown>
 
 mov     za0h.h[w13, 7], p2/m, z12.h
 // CHECK-INST: mov     za0h.h[w13, 7], p2/m, z12.h
 // CHECK-ENCODING: [0x87,0x29,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 40 c0 <unknown>
+// CHECK-UNKNOWN: c0402987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Insert, vector to tile, vertical, 16-bit
@@ -1956,73 +1956,73 @@ mova    za0v.h[w12, 0], p0/m, z0.h
 // CHECK-INST: mov     za0v.h[w12, 0], p0/m, z0.h
 // CHECK-ENCODING: [0x00,0x80,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 40 c0 <unknown>
+// CHECK-UNKNOWN: c0408000 <unknown>
 
 mova    za0v.h[w14, 5], p5/m, z10.h
 // CHECK-INST: mov     za0v.h[w14, 5], p5/m, z10.h
 // CHECK-ENCODING: [0x45,0xd5,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 40 c0 <unknown>
+// CHECK-UNKNOWN: c040d545 <unknown>
 
 mova    za0v.h[w15, 7], p3/m, z13.h
 // CHECK-INST: mov     za0v.h[w15, 7], p3/m, z13.h
 // CHECK-ENCODING: [0xa7,0xed,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 40 c0 <unknown>
+// CHECK-UNKNOWN: c040eda7 <unknown>
 
 mova    za1v.h[w15, 7], p7/m, z31.h
 // CHECK-INST: mov     za1v.h[w15, 7], p7/m, z31.h
 // CHECK-ENCODING: [0xef,0xff,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 40 c0 <unknown>
+// CHECK-UNKNOWN: c040ffef <unknown>
 
 mova    za0v.h[w12, 5], p3/m, z17.h
 // CHECK-INST: mov     za0v.h[w12, 5], p3/m, z17.h
 // CHECK-ENCODING: [0x25,0x8e,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 40 c0 <unknown>
+// CHECK-UNKNOWN: c0408e25 <unknown>
 
 mova    za0v.h[w12, 1], p1/m, z1.h
 // CHECK-INST: mov     za0v.h[w12, 1], p1/m, z1.h
 // CHECK-ENCODING: [0x21,0x84,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 40 c0 <unknown>
+// CHECK-UNKNOWN: c0408421 <unknown>
 
 mova    za1v.h[w14, 0], p5/m, z19.h
 // CHECK-INST: mov     za1v.h[w14, 0], p5/m, z19.h
 // CHECK-ENCODING: [0x68,0xd6,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 40 c0 <unknown>
+// CHECK-UNKNOWN: c040d668 <unknown>
 
 mova    za0v.h[w12, 0], p6/m, z12.h
 // CHECK-INST: mov     za0v.h[w12, 0], p6/m, z12.h
 // CHECK-ENCODING: [0x80,0x99,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 40 c0 <unknown>
+// CHECK-UNKNOWN: c0409980 <unknown>
 
 mova    za0v.h[w14, 1], p2/m, z1.h
 // CHECK-INST: mov     za0v.h[w14, 1], p2/m, z1.h
 // CHECK-ENCODING: [0x21,0xc8,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 40 c0 <unknown>
+// CHECK-UNKNOWN: c040c821 <unknown>
 
 mova    za1v.h[w12, 5], p2/m, z22.h
 // CHECK-INST: mov     za1v.h[w12, 5], p2/m, z22.h
 // CHECK-ENCODING: [0xcd,0x8a,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 40 c0 <unknown>
+// CHECK-UNKNOWN: c0408acd <unknown>
 
 mova    za0v.h[w15, 2], p5/m, z9.h
 // CHECK-INST: mov     za0v.h[w15, 2], p5/m, z9.h
 // CHECK-ENCODING: [0x22,0xf5,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 40 c0 <unknown>
+// CHECK-UNKNOWN: c040f522 <unknown>
 
 mova    za0v.h[w13, 7], p2/m, z12.h
 // CHECK-INST: mov     za0v.h[w13, 7], p2/m, z12.h
 // CHECK-ENCODING: [0x87,0xa9,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 40 c0 <unknown>
+// CHECK-UNKNOWN: c040a987 <unknown>
 
 // Aliases
 
@@ -2030,73 +2030,73 @@ mov     za0v.h[w12, 0], p0/m, z0.h
 // CHECK-INST: mov     za0v.h[w12, 0], p0/m, z0.h
 // CHECK-ENCODING: [0x00,0x80,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 40 c0 <unknown>
+// CHECK-UNKNOWN: c0408000 <unknown>
 
 mov     za0v.h[w14, 5], p5/m, z10.h
 // CHECK-INST: mov     za0v.h[w14, 5], p5/m, z10.h
 // CHECK-ENCODING: [0x45,0xd5,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 40 c0 <unknown>
+// CHECK-UNKNOWN: c040d545 <unknown>
 
 mov     za0v.h[w15, 7], p3/m, z13.h
 // CHECK-INST: mov     za0v.h[w15, 7], p3/m, z13.h
 // CHECK-ENCODING: [0xa7,0xed,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 40 c0 <unknown>
+// CHECK-UNKNOWN: c040eda7 <unknown>
 
 mov     za1v.h[w15, 7], p7/m, z31.h
 // CHECK-INST: mov     za1v.h[w15, 7], p7/m, z31.h
 // CHECK-ENCODING: [0xef,0xff,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 40 c0 <unknown>
+// CHECK-UNKNOWN: c040ffef <unknown>
 
 mov     za0v.h[w12, 5], p3/m, z17.h
 // CHECK-INST: mov     za0v.h[w12, 5], p3/m, z17.h
 // CHECK-ENCODING: [0x25,0x8e,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 40 c0 <unknown>
+// CHECK-UNKNOWN: c0408e25 <unknown>
 
 mov     za0v.h[w12, 1], p1/m, z1.h
 // CHECK-INST: mov     za0v.h[w12, 1], p1/m, z1.h
 // CHECK-ENCODING: [0x21,0x84,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 40 c0 <unknown>
+// CHECK-UNKNOWN: c0408421 <unknown>
 
 mov     za1v.h[w14, 0], p5/m, z19.h
 // CHECK-INST: mov     za1v.h[w14, 0], p5/m, z19.h
 // CHECK-ENCODING: [0x68,0xd6,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 40 c0 <unknown>
+// CHECK-UNKNOWN: c040d668 <unknown>
 
 mov     za0v.h[w12, 0], p6/m, z12.h
 // CHECK-INST: mov     za0v.h[w12, 0], p6/m, z12.h
 // CHECK-ENCODING: [0x80,0x99,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 40 c0 <unknown>
+// CHECK-UNKNOWN: c0409980 <unknown>
 
 mov     za0v.h[w14, 1], p2/m, z1.h
 // CHECK-INST: mov     za0v.h[w14, 1], p2/m, z1.h
 // CHECK-ENCODING: [0x21,0xc8,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 40 c0 <unknown>
+// CHECK-UNKNOWN: c040c821 <unknown>
 
 mov     za1v.h[w12, 5], p2/m, z22.h
 // CHECK-INST: mov     za1v.h[w12, 5], p2/m, z22.h
 // CHECK-ENCODING: [0xcd,0x8a,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 40 c0 <unknown>
+// CHECK-UNKNOWN: c0408acd <unknown>
 
 mov     za0v.h[w15, 2], p5/m, z9.h
 // CHECK-INST: mov     za0v.h[w15, 2], p5/m, z9.h
 // CHECK-ENCODING: [0x22,0xf5,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 40 c0 <unknown>
+// CHECK-UNKNOWN: c040f522 <unknown>
 
 mov     za0v.h[w13, 7], p2/m, z12.h
 // CHECK-INST: mov     za0v.h[w13, 7], p2/m, z12.h
 // CHECK-ENCODING: [0x87,0xa9,0x40,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 40 c0 <unknown>
+// CHECK-UNKNOWN: c040a987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Insert, vector to tile, horizontal, 32-bit
@@ -2105,73 +2105,73 @@ mova    za0h.s[w12, 0], p0/m, z0.s
 // CHECK-INST: mov     za0h.s[w12, 0], p0/m, z0.s
 // CHECK-ENCODING: [0x00,0x00,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 80 c0 <unknown>
+// CHECK-UNKNOWN: c0800000 <unknown>
 
 mova    za1h.s[w14, 1], p5/m, z10.s
 // CHECK-INST: mov     za1h.s[w14, 1], p5/m, z10.s
 // CHECK-ENCODING: [0x45,0x55,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 80 c0 <unknown>
+// CHECK-UNKNOWN: c0805545 <unknown>
 
 mova    za1h.s[w15, 3], p3/m, z13.s
 // CHECK-INST: mov     za1h.s[w15, 3], p3/m, z13.s
 // CHECK-ENCODING: [0xa7,0x6d,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 80 c0 <unknown>
+// CHECK-UNKNOWN: c0806da7 <unknown>
 
 mova    za3h.s[w15, 3], p7/m, z31.s
 // CHECK-INST: mov     za3h.s[w15, 3], p7/m, z31.s
 // CHECK-ENCODING: [0xef,0x7f,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 80 c0 <unknown>
+// CHECK-UNKNOWN: c0807fef <unknown>
 
 mova    za1h.s[w12, 1], p3/m, z17.s
 // CHECK-INST: mov     za1h.s[w12, 1], p3/m, z17.s
 // CHECK-ENCODING: [0x25,0x0e,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 80 c0 <unknown>
+// CHECK-UNKNOWN: c0800e25 <unknown>
 
 mova    za0h.s[w12, 1], p1/m, z1.s
 // CHECK-INST: mov     za0h.s[w12, 1], p1/m, z1.s
 // CHECK-ENCODING: [0x21,0x04,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 80 c0 <unknown>
+// CHECK-UNKNOWN: c0800421 <unknown>
 
 mova    za2h.s[w14, 0], p5/m, z19.s
 // CHECK-INST: mov     za2h.s[w14, 0], p5/m, z19.s
 // CHECK-ENCODING: [0x68,0x56,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 80 c0 <unknown>
+// CHECK-UNKNOWN: c0805668 <unknown>
 
 mova    za0h.s[w12, 0], p6/m, z12.s
 // CHECK-INST: mov     za0h.s[w12, 0], p6/m, z12.s
 // CHECK-ENCODING: [0x80,0x19,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 80 c0 <unknown>
+// CHECK-UNKNOWN: c0801980 <unknown>
 
 mova    za0h.s[w14, 1], p2/m, z1.s
 // CHECK-INST: mov     za0h.s[w14, 1], p2/m, z1.s
 // CHECK-ENCODING: [0x21,0x48,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 80 c0 <unknown>
+// CHECK-UNKNOWN: c0804821 <unknown>
 
 mova    za3h.s[w12, 1], p2/m, z22.s
 // CHECK-INST: mov     za3h.s[w12, 1], p2/m, z22.s
 // CHECK-ENCODING: [0xcd,0x0a,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 80 c0 <unknown>
+// CHECK-UNKNOWN: c0800acd <unknown>
 
 mova    za0h.s[w15, 2], p5/m, z9.s
 // CHECK-INST: mov     za0h.s[w15, 2], p5/m, z9.s
 // CHECK-ENCODING: [0x22,0x75,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 80 c0 <unknown>
+// CHECK-UNKNOWN: c0807522 <unknown>
 
 mova    za1h.s[w13, 3], p2/m, z12.s
 // CHECK-INST: mov     za1h.s[w13, 3], p2/m, z12.s
 // CHECK-ENCODING: [0x87,0x29,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 80 c0 <unknown>
+// CHECK-UNKNOWN: c0802987 <unknown>
 
 // Aliases
 
@@ -2179,73 +2179,73 @@ mov     za0h.s[w12, 0], p0/m, z0.s
 // CHECK-INST: mov     za0h.s[w12, 0], p0/m, z0.s
 // CHECK-ENCODING: [0x00,0x00,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 80 c0 <unknown>
+// CHECK-UNKNOWN: c0800000 <unknown>
 
 mov     za1h.s[w14, 1], p5/m, z10.s
 // CHECK-INST: mov     za1h.s[w14, 1], p5/m, z10.s
 // CHECK-ENCODING: [0x45,0x55,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 80 c0 <unknown>
+// CHECK-UNKNOWN: c0805545 <unknown>
 
 mov     za1h.s[w15, 3], p3/m, z13.s
 // CHECK-INST: mov     za1h.s[w15, 3], p3/m, z13.s
 // CHECK-ENCODING: [0xa7,0x6d,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 80 c0 <unknown>
+// CHECK-UNKNOWN: c0806da7 <unknown>
 
 mov     za3h.s[w15, 3], p7/m, z31.s
 // CHECK-INST: mov     za3h.s[w15, 3], p7/m, z31.s
 // CHECK-ENCODING: [0xef,0x7f,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 80 c0 <unknown>
+// CHECK-UNKNOWN: c0807fef <unknown>
 
 mov     za1h.s[w12, 1], p3/m, z17.s
 // CHECK-INST: mov     za1h.s[w12, 1], p3/m, z17.s
 // CHECK-ENCODING: [0x25,0x0e,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 80 c0 <unknown>
+// CHECK-UNKNOWN: c0800e25 <unknown>
 
 mov     za0h.s[w12, 1], p1/m, z1.s
 // CHECK-INST: mov     za0h.s[w12, 1], p1/m, z1.s
 // CHECK-ENCODING: [0x21,0x04,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 80 c0 <unknown>
+// CHECK-UNKNOWN: c0800421 <unknown>
 
 mov     za2h.s[w14, 0], p5/m, z19.s
 // CHECK-INST: mov     za2h.s[w14, 0], p5/m, z19.s
 // CHECK-ENCODING: [0x68,0x56,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 80 c0 <unknown>
+// CHECK-UNKNOWN: c0805668 <unknown>
 
 mov     za0h.s[w12, 0], p6/m, z12.s
 // CHECK-INST: mov     za0h.s[w12, 0], p6/m, z12.s
 // CHECK-ENCODING: [0x80,0x19,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 80 c0 <unknown>
+// CHECK-UNKNOWN: c0801980 <unknown>
 
 mov     za0h.s[w14, 1], p2/m, z1.s
 // CHECK-INST: mov     za0h.s[w14, 1], p2/m, z1.s
 // CHECK-ENCODING: [0x21,0x48,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 80 c0 <unknown>
+// CHECK-UNKNOWN: c0804821 <unknown>
 
 mov     za3h.s[w12, 1], p2/m, z22.s
 // CHECK-INST: mov     za3h.s[w12, 1], p2/m, z22.s
 // CHECK-ENCODING: [0xcd,0x0a,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 80 c0 <unknown>
+// CHECK-UNKNOWN: c0800acd <unknown>
 
 mov     za0h.s[w15, 2], p5/m, z9.s
 // CHECK-INST: mov     za0h.s[w15, 2], p5/m, z9.s
 // CHECK-ENCODING: [0x22,0x75,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 80 c0 <unknown>
+// CHECK-UNKNOWN: c0807522 <unknown>
 
 mov     za1h.s[w13, 3], p2/m, z12.s
 // CHECK-INST: mov     za1h.s[w13, 3], p2/m, z12.s
 // CHECK-ENCODING: [0x87,0x29,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 80 c0 <unknown>
+// CHECK-UNKNOWN: c0802987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Insert, vector to tile, vertical, 32-bit
@@ -2254,73 +2254,73 @@ mova    za0v.s[w12, 0], p0/m, z0.s
 // CHECK-INST: mov     za0v.s[w12, 0], p0/m, z0.s
 // CHECK-ENCODING: [0x00,0x80,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 80 c0 <unknown>
+// CHECK-UNKNOWN: c0808000 <unknown>
 
 mova    za1v.s[w14, 1], p5/m, z10.s
 // CHECK-INST: mov     za1v.s[w14, 1], p5/m, z10.s
 // CHECK-ENCODING: [0x45,0xd5,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 80 c0 <unknown>
+// CHECK-UNKNOWN: c080d545 <unknown>
 
 mova    za1v.s[w15, 3], p3/m, z13.s
 // CHECK-INST: mov     za1v.s[w15, 3], p3/m, z13.s
 // CHECK-ENCODING: [0xa7,0xed,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 80 c0 <unknown>
+// CHECK-UNKNOWN: c080eda7 <unknown>
 
 mova    za3v.s[w15, 3], p7/m, z31.s
 // CHECK-INST: mov     za3v.s[w15, 3], p7/m, z31.s
 // CHECK-ENCODING: [0xef,0xff,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 80 c0 <unknown>
+// CHECK-UNKNOWN: c080ffef <unknown>
 
 mova    za1v.s[w12, 1], p3/m, z17.s
 // CHECK-INST: mov     za1v.s[w12, 1], p3/m, z17.s
 // CHECK-ENCODING: [0x25,0x8e,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 80 c0 <unknown>
+// CHECK-UNKNOWN: c0808e25 <unknown>
 
 mova    za0v.s[w12, 1], p1/m, z1.s
 // CHECK-INST: mov     za0v.s[w12, 1], p1/m, z1.s
 // CHECK-ENCODING: [0x21,0x84,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 80 c0 <unknown>
+// CHECK-UNKNOWN: c0808421 <unknown>
 
 mova    za2v.s[w14, 0], p5/m, z19.s
 // CHECK-INST: mov     za2v.s[w14, 0], p5/m, z19.s
 // CHECK-ENCODING: [0x68,0xd6,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 80 c0 <unknown>
+// CHECK-UNKNOWN: c080d668 <unknown>
 
 mova    za0v.s[w12, 0], p6/m, z12.s
 // CHECK-INST: mov     za0v.s[w12, 0], p6/m, z12.s
 // CHECK-ENCODING: [0x80,0x99,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 80 c0 <unknown>
+// CHECK-UNKNOWN: c0809980 <unknown>
 
 mova    za0v.s[w14, 1], p2/m, z1.s
 // CHECK-INST: mov     za0v.s[w14, 1], p2/m, z1.s
 // CHECK-ENCODING: [0x21,0xc8,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 80 c0 <unknown>
+// CHECK-UNKNOWN: c080c821 <unknown>
 
 mova    za3v.s[w12, 1], p2/m, z22.s
 // CHECK-INST: mov     za3v.s[w12, 1], p2/m, z22.s
 // CHECK-ENCODING: [0xcd,0x8a,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 80 c0 <unknown>
+// CHECK-UNKNOWN: c0808acd <unknown>
 
 mova    za0v.s[w15, 2], p5/m, z9.s
 // CHECK-INST: mov     za0v.s[w15, 2], p5/m, z9.s
 // CHECK-ENCODING: [0x22,0xf5,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 80 c0 <unknown>
+// CHECK-UNKNOWN: c080f522 <unknown>
 
 mova    za1v.s[w13, 3], p2/m, z12.s
 // CHECK-INST: mov     za1v.s[w13, 3], p2/m, z12.s
 // CHECK-ENCODING: [0x87,0xa9,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 80 c0 <unknown>
+// CHECK-UNKNOWN: c080a987 <unknown>
 
 // Aliases
 
@@ -2328,73 +2328,73 @@ mov     za0v.s[w12, 0], p0/m, z0.s
 // CHECK-INST: mov     za0v.s[w12, 0], p0/m, z0.s
 // CHECK-ENCODING: [0x00,0x80,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 80 c0 <unknown>
+// CHECK-UNKNOWN: c0808000 <unknown>
 
 mov     za1v.s[w14, 1], p5/m, z10.s
 // CHECK-INST: mov     za1v.s[w14, 1], p5/m, z10.s
 // CHECK-ENCODING: [0x45,0xd5,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 80 c0 <unknown>
+// CHECK-UNKNOWN: c080d545 <unknown>
 
 mov     za1v.s[w15, 3], p3/m, z13.s
 // CHECK-INST: mov     za1v.s[w15, 3], p3/m, z13.s
 // CHECK-ENCODING: [0xa7,0xed,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 80 c0 <unknown>
+// CHECK-UNKNOWN: c080eda7 <unknown>
 
 mov     za3v.s[w15, 3], p7/m, z31.s
 // CHECK-INST: mov     za3v.s[w15, 3], p7/m, z31.s
 // CHECK-ENCODING: [0xef,0xff,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 80 c0 <unknown>
+// CHECK-UNKNOWN: c080ffef <unknown>
 
 mov     za1v.s[w12, 1], p3/m, z17.s
 // CHECK-INST: mov     za1v.s[w12, 1], p3/m, z17.s
 // CHECK-ENCODING: [0x25,0x8e,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 80 c0 <unknown>
+// CHECK-UNKNOWN: c0808e25 <unknown>
 
 mov     za0v.s[w12, 1], p1/m, z1.s
 // CHECK-INST: mov     za0v.s[w12, 1], p1/m, z1.s
 // CHECK-ENCODING: [0x21,0x84,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 80 c0 <unknown>
+// CHECK-UNKNOWN: c0808421 <unknown>
 
 mov     za2v.s[w14, 0], p5/m, z19.s
 // CHECK-INST: mov     za2v.s[w14, 0], p5/m, z19.s
 // CHECK-ENCODING: [0x68,0xd6,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 80 c0 <unknown>
+// CHECK-UNKNOWN: c080d668 <unknown>
 
 mov     za0v.s[w12, 0], p6/m, z12.s
 // CHECK-INST: mov     za0v.s[w12, 0], p6/m, z12.s
 // CHECK-ENCODING: [0x80,0x99,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 80 c0 <unknown>
+// CHECK-UNKNOWN: c0809980 <unknown>
 
 mov     za0v.s[w14, 1], p2/m, z1.s
 // CHECK-INST: mov     za0v.s[w14, 1], p2/m, z1.s
 // CHECK-ENCODING: [0x21,0xc8,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 80 c0 <unknown>
+// CHECK-UNKNOWN: c080c821 <unknown>
 
 mov     za3v.s[w12, 1], p2/m, z22.s
 // CHECK-INST: mov     za3v.s[w12, 1], p2/m, z22.s
 // CHECK-ENCODING: [0xcd,0x8a,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 80 c0 <unknown>
+// CHECK-UNKNOWN: c0808acd <unknown>
 
 mov     za0v.s[w15, 2], p5/m, z9.s
 // CHECK-INST: mov     za0v.s[w15, 2], p5/m, z9.s
 // CHECK-ENCODING: [0x22,0xf5,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 80 c0 <unknown>
+// CHECK-UNKNOWN: c080f522 <unknown>
 
 mov     za1v.s[w13, 3], p2/m, z12.s
 // CHECK-INST: mov     za1v.s[w13, 3], p2/m, z12.s
 // CHECK-ENCODING: [0x87,0xa9,0x80,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 80 c0 <unknown>
+// CHECK-UNKNOWN: c080a987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Insert, vector to tile, horizontal, 64-bit
@@ -2403,73 +2403,73 @@ mova    za0h.d[w12, 0], p0/m, z0.d
 // CHECK-INST: mov     za0h.d[w12, 0], p0/m, z0.d
 // CHECK-ENCODING: [0x00,0x00,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c00000 <unknown>
 
 mova    za2h.d[w14, 1], p5/m, z10.d
 // CHECK-INST: mov     za2h.d[w14, 1], p5/m, z10.d
 // CHECK-ENCODING: [0x45,0x55,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c05545 <unknown>
 
 mova    za3h.d[w15, 1], p3/m, z13.d
 // CHECK-INST: mov     za3h.d[w15, 1], p3/m, z13.d
 // CHECK-ENCODING: [0xa7,0x6d,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c06da7 <unknown>
 
 mova    za7h.d[w15, 1], p7/m, z31.d
 // CHECK-INST: mov     za7h.d[w15, 1], p7/m, z31.d
 // CHECK-ENCODING: [0xef,0x7f,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c07fef <unknown>
 
 mova    za2h.d[w12, 1], p3/m, z17.d
 // CHECK-INST: mov     za2h.d[w12, 1], p3/m, z17.d
 // CHECK-ENCODING: [0x25,0x0e,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c00e25 <unknown>
 
 mova    za0h.d[w12, 1], p1/m, z1.d
 // CHECK-INST: mov     za0h.d[w12, 1], p1/m, z1.d
 // CHECK-ENCODING: [0x21,0x04,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c00421 <unknown>
 
 mova    za4h.d[w14, 0], p5/m, z19.d
 // CHECK-INST: mov     za4h.d[w14, 0], p5/m, z19.d
 // CHECK-ENCODING: [0x68,0x56,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c05668 <unknown>
 
 mova    za0h.d[w12, 0], p6/m, z12.d
 // CHECK-INST: mov     za0h.d[w12, 0], p6/m, z12.d
 // CHECK-ENCODING: [0x80,0x19,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c01980 <unknown>
 
 mova    za0h.d[w14, 1], p2/m, z1.d
 // CHECK-INST: mov     za0h.d[w14, 1], p2/m, z1.d
 // CHECK-ENCODING: [0x21,0x48,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c04821 <unknown>
 
 mova    za6h.d[w12, 1], p2/m, z22.d
 // CHECK-INST: mov     za6h.d[w12, 1], p2/m, z22.d
 // CHECK-ENCODING: [0xcd,0x0a,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c00acd <unknown>
 
 mova    za1h.d[w15, 0], p5/m, z9.d
 // CHECK-INST: mov     za1h.d[w15, 0], p5/m, z9.d
 // CHECK-ENCODING: [0x22,0x75,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c07522 <unknown>
 
 mova    za3h.d[w13, 1], p2/m, z12.d
 // CHECK-INST: mov     za3h.d[w13, 1], p2/m, z12.d
 // CHECK-ENCODING: [0x87,0x29,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c02987 <unknown>
 
 // Aliases
 
@@ -2477,73 +2477,73 @@ mov     za0h.d[w12, 0], p0/m, z0.d
 // CHECK-INST: mov     za0h.d[w12, 0], p0/m, z0.d
 // CHECK-ENCODING: [0x00,0x00,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c00000 <unknown>
 
 mov     za2h.d[w14, 1], p5/m, z10.d
 // CHECK-INST: mov     za2h.d[w14, 1], p5/m, z10.d
 // CHECK-ENCODING: [0x45,0x55,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c05545 <unknown>
 
 mov     za3h.d[w15, 1], p3/m, z13.d
 // CHECK-INST: mov     za3h.d[w15, 1], p3/m, z13.d
 // CHECK-ENCODING: [0xa7,0x6d,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c06da7 <unknown>
 
 mov     za7h.d[w15, 1], p7/m, z31.d
 // CHECK-INST: mov     za7h.d[w15, 1], p7/m, z31.d
 // CHECK-ENCODING: [0xef,0x7f,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c07fef <unknown>
 
 mov     za2h.d[w12, 1], p3/m, z17.d
 // CHECK-INST: mov     za2h.d[w12, 1], p3/m, z17.d
 // CHECK-ENCODING: [0x25,0x0e,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c00e25 <unknown>
 
 mov     za0h.d[w12, 1], p1/m, z1.d
 // CHECK-INST: mov     za0h.d[w12, 1], p1/m, z1.d
 // CHECK-ENCODING: [0x21,0x04,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c00421 <unknown>
 
 mov     za4h.d[w14, 0], p5/m, z19.d
 // CHECK-INST: mov     za4h.d[w14, 0], p5/m, z19.d
 // CHECK-ENCODING: [0x68,0x56,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c05668 <unknown>
 
 mov     za0h.d[w12, 0], p6/m, z12.d
 // CHECK-INST: mov     za0h.d[w12, 0], p6/m, z12.d
 // CHECK-ENCODING: [0x80,0x19,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c01980 <unknown>
 
 mov     za0h.d[w14, 1], p2/m, z1.d
 // CHECK-INST: mov     za0h.d[w14, 1], p2/m, z1.d
 // CHECK-ENCODING: [0x21,0x48,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c04821 <unknown>
 
 mov     za6h.d[w12, 1], p2/m, z22.d
 // CHECK-INST: mov     za6h.d[w12, 1], p2/m, z22.d
 // CHECK-ENCODING: [0xcd,0x0a,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c00acd <unknown>
 
 mov     za1h.d[w15, 0], p5/m, z9.d
 // CHECK-INST: mov     za1h.d[w15, 0], p5/m, z9.d
 // CHECK-ENCODING: [0x22,0x75,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c07522 <unknown>
 
 mov     za3h.d[w13, 1], p2/m, z12.d
 // CHECK-INST: mov     za3h.d[w13, 1], p2/m, z12.d
 // CHECK-ENCODING: [0x87,0x29,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c02987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Insert, vector to tile, vertical, 64-bit
@@ -2552,73 +2552,73 @@ mova    za0v.d[w12, 0], p0/m, z0.d
 // CHECK-INST: mov     za0v.d[w12, 0], p0/m, z0.d
 // CHECK-ENCODING: [0x00,0x80,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c08000 <unknown>
 
 mova    za2v.d[w14, 1], p5/m, z10.d
 // CHECK-INST: mov     za2v.d[w14, 1], p5/m, z10.d
 // CHECK-ENCODING: [0x45,0xd5,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0d545 <unknown>
 
 mova    za3v.d[w15, 1], p3/m, z13.d
 // CHECK-INST: mov     za3v.d[w15, 1], p3/m, z13.d
 // CHECK-ENCODING: [0xa7,0xed,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0eda7 <unknown>
 
 mova    za7v.d[w15, 1], p7/m, z31.d
 // CHECK-INST: mov     za7v.d[w15, 1], p7/m, z31.d
 // CHECK-ENCODING: [0xef,0xff,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0ffef <unknown>
 
 mova    za2v.d[w12, 1], p3/m, z17.d
 // CHECK-INST: mov     za2v.d[w12, 1], p3/m, z17.d
 // CHECK-ENCODING: [0x25,0x8e,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c08e25 <unknown>
 
 mova    za0v.d[w12, 1], p1/m, z1.d
 // CHECK-INST: mov     za0v.d[w12, 1], p1/m, z1.d
 // CHECK-ENCODING: [0x21,0x84,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c08421 <unknown>
 
 mova    za4v.d[w14, 0], p5/m, z19.d
 // CHECK-INST: mov     za4v.d[w14, 0], p5/m, z19.d
 // CHECK-ENCODING: [0x68,0xd6,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0d668 <unknown>
 
 mova    za0v.d[w12, 0], p6/m, z12.d
 // CHECK-INST: mov     za0v.d[w12, 0], p6/m, z12.d
 // CHECK-ENCODING: [0x80,0x99,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c09980 <unknown>
 
 mova    za0v.d[w14, 1], p2/m, z1.d
 // CHECK-INST: mov     za0v.d[w14, 1], p2/m, z1.d
 // CHECK-ENCODING: [0x21,0xc8,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0c821 <unknown>
 
 mova    za6v.d[w12, 1], p2/m, z22.d
 // CHECK-INST: mov     za6v.d[w12, 1], p2/m, z22.d
 // CHECK-ENCODING: [0xcd,0x8a,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c08acd <unknown>
 
 mova    za1v.d[w15, 0], p5/m, z9.d
 // CHECK-INST: mov     za1v.d[w15, 0], p5/m, z9.d
 // CHECK-ENCODING: [0x22,0xf5,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0f522 <unknown>
 
 mova    za3v.d[w13, 1], p2/m, z12.d
 // CHECK-INST: mov     za3v.d[w13, 1], p2/m, z12.d
 // CHECK-ENCODING: [0x87,0xa9,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0a987 <unknown>
 
 // Aliases
 
@@ -2626,73 +2626,73 @@ mov     za0v.d[w12, 0], p0/m, z0.d
 // CHECK-INST: mov     za0v.d[w12, 0], p0/m, z0.d
 // CHECK-ENCODING: [0x00,0x80,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c08000 <unknown>
 
 mov     za2v.d[w14, 1], p5/m, z10.d
 // CHECK-INST: mov     za2v.d[w14, 1], p5/m, z10.d
 // CHECK-ENCODING: [0x45,0xd5,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0d545 <unknown>
 
 mov     za3v.d[w15, 1], p3/m, z13.d
 // CHECK-INST: mov     za3v.d[w15, 1], p3/m, z13.d
 // CHECK-ENCODING: [0xa7,0xed,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0eda7 <unknown>
 
 mov     za7v.d[w15, 1], p7/m, z31.d
 // CHECK-INST: mov     za7v.d[w15, 1], p7/m, z31.d
 // CHECK-ENCODING: [0xef,0xff,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0ffef <unknown>
 
 mov     za2v.d[w12, 1], p3/m, z17.d
 // CHECK-INST: mov     za2v.d[w12, 1], p3/m, z17.d
 // CHECK-ENCODING: [0x25,0x8e,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c08e25 <unknown>
 
 mov     za0v.d[w12, 1], p1/m, z1.d
 // CHECK-INST: mov     za0v.d[w12, 1], p1/m, z1.d
 // CHECK-ENCODING: [0x21,0x84,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c08421 <unknown>
 
 mov     za4v.d[w14, 0], p5/m, z19.d
 // CHECK-INST: mov     za4v.d[w14, 0], p5/m, z19.d
 // CHECK-ENCODING: [0x68,0xd6,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0d668 <unknown>
 
 mov     za0v.d[w12, 0], p6/m, z12.d
 // CHECK-INST: mov     za0v.d[w12, 0], p6/m, z12.d
 // CHECK-ENCODING: [0x80,0x99,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c09980 <unknown>
 
 mov     za0v.d[w14, 1], p2/m, z1.d
 // CHECK-INST: mov     za0v.d[w14, 1], p2/m, z1.d
 // CHECK-ENCODING: [0x21,0xc8,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0c821 <unknown>
 
 mov     za6v.d[w12, 1], p2/m, z22.d
 // CHECK-INST: mov     za6v.d[w12, 1], p2/m, z22.d
 // CHECK-ENCODING: [0xcd,0x8a,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c08acd <unknown>
 
 mov     za1v.d[w15, 0], p5/m, z9.d
 // CHECK-INST: mov     za1v.d[w15, 0], p5/m, z9.d
 // CHECK-ENCODING: [0x22,0xf5,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0f522 <unknown>
 
 mov     za3v.d[w13, 1], p2/m, z12.d
 // CHECK-INST: mov     za3v.d[w13, 1], p2/m, z12.d
 // CHECK-ENCODING: [0x87,0xa9,0xc0,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 c0 c0 <unknown>
+// CHECK-UNKNOWN: c0c0a987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Insert, vector to tile, horizontal, 128-bit
@@ -2701,73 +2701,73 @@ mova    za0h.q[w12, 0], p0/m, z0.q
 // CHECK-INST: mov     za0h.q[w12, 0], p0/m, z0.q
 // CHECK-ENCODING: [0x00,0x00,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c10000 <unknown>
 
 mova    za5h.q[w14, 0], p5/m, z10.q
 // CHECK-INST: mov     za5h.q[w14, 0], p5/m, z10.q
 // CHECK-ENCODING: [0x45,0x55,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c15545 <unknown>
 
 mova    za7h.q[w15, 0], p3/m, z13.q
 // CHECK-INST: mov     za7h.q[w15, 0], p3/m, z13.q
 // CHECK-ENCODING: [0xa7,0x6d,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c16da7 <unknown>
 
 mova    za15h.q[w15, 0], p7/m, z31.q
 // CHECK-INST: mov     za15h.q[w15, 0], p7/m, z31.q
 // CHECK-ENCODING: [0xef,0x7f,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c17fef <unknown>
 
 mova    za5h.q[w12, 0], p3/m, z17.q
 // CHECK-INST: mov     za5h.q[w12, 0], p3/m, z17.q
 // CHECK-ENCODING: [0x25,0x0e,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c10e25 <unknown>
 
 mova    za1h.q[w12, 0], p1/m, z1.q
 // CHECK-INST: mov     za1h.q[w12, 0], p1/m, z1.q
 // CHECK-ENCODING: [0x21,0x04,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c10421 <unknown>
 
 mova    za8h.q[w14, 0], p5/m, z19.q
 // CHECK-INST: mov     za8h.q[w14, 0], p5/m, z19.q
 // CHECK-ENCODING: [0x68,0x56,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c15668 <unknown>
 
 mova    za0h.q[w12, 0], p6/m, z12.q
 // CHECK-INST: mov     za0h.q[w12, 0], p6/m, z12.q
 // CHECK-ENCODING: [0x80,0x19,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c11980 <unknown>
 
 mova    za1h.q[w14, 0], p2/m, z1.q
 // CHECK-INST: mov     za1h.q[w14, 0], p2/m, z1.q
 // CHECK-ENCODING: [0x21,0x48,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c14821 <unknown>
 
 mova    za13h.q[w12, 0], p2/m, z22.q
 // CHECK-INST: mov     za13h.q[w12, 0], p2/m, z22.q
 // CHECK-ENCODING: [0xcd,0x0a,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c10acd <unknown>
 
 mova    za2h.q[w15, 0], p5/m, z9.q
 // CHECK-INST: mov     za2h.q[w15, 0], p5/m, z9.q
 // CHECK-ENCODING: [0x22,0x75,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c17522 <unknown>
 
 mova    za7h.q[w13, 0], p2/m, z12.q
 // CHECK-INST: mov     za7h.q[w13, 0], p2/m, z12.q
 // CHECK-ENCODING: [0x87,0x29,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c12987 <unknown>
 
 // Aliases
 
@@ -2775,73 +2775,73 @@ mov     za0h.q[w12, 0], p0/m, z0.q
 // CHECK-INST: mov     za0h.q[w12, 0], p0/m, z0.q
 // CHECK-ENCODING: [0x00,0x00,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c10000 <unknown>
 
 mov     za5h.q[w14, 0], p5/m, z10.q
 // CHECK-INST: mov     za5h.q[w14, 0], p5/m, z10.q
 // CHECK-ENCODING: [0x45,0x55,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c15545 <unknown>
 
 mov     za7h.q[w15, 0], p3/m, z13.q
 // CHECK-INST: mov     za7h.q[w15, 0], p3/m, z13.q
 // CHECK-ENCODING: [0xa7,0x6d,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c16da7 <unknown>
 
 mov     za15h.q[w15, 0], p7/m, z31.q
 // CHECK-INST: mov     za15h.q[w15, 0], p7/m, z31.q
 // CHECK-ENCODING: [0xef,0x7f,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c17fef <unknown>
 
 mov     za5h.q[w12, 0], p3/m, z17.q
 // CHECK-INST: mov     za5h.q[w12, 0], p3/m, z17.q
 // CHECK-ENCODING: [0x25,0x0e,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c10e25 <unknown>
 
 mov     za1h.q[w12, 0], p1/m, z1.q
 // CHECK-INST: mov     za1h.q[w12, 0], p1/m, z1.q
 // CHECK-ENCODING: [0x21,0x04,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c10421 <unknown>
 
 mov     za8h.q[w14, 0], p5/m, z19.q
 // CHECK-INST: mov     za8h.q[w14, 0], p5/m, z19.q
 // CHECK-ENCODING: [0x68,0x56,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c15668 <unknown>
 
 mov     za0h.q[w12, 0], p6/m, z12.q
 // CHECK-INST: mov     za0h.q[w12, 0], p6/m, z12.q
 // CHECK-ENCODING: [0x80,0x19,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c11980 <unknown>
 
 mov     za1h.q[w14, 0], p2/m, z1.q
 // CHECK-INST: mov     za1h.q[w14, 0], p2/m, z1.q
 // CHECK-ENCODING: [0x21,0x48,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c14821 <unknown>
 
 mov     za13h.q[w12, 0], p2/m, z22.q
 // CHECK-INST: mov     za13h.q[w12, 0], p2/m, z22.q
 // CHECK-ENCODING: [0xcd,0x0a,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c10acd <unknown>
 
 mov     za2h.q[w15, 0], p5/m, z9.q
 // CHECK-INST: mov     za2h.q[w15, 0], p5/m, z9.q
 // CHECK-ENCODING: [0x22,0x75,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c17522 <unknown>
 
 mov     za7h.q[w13, 0], p2/m, z12.q
 // CHECK-INST: mov     za7h.q[w13, 0], p2/m, z12.q
 // CHECK-ENCODING: [0x87,0x29,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c12987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Insert, vector to tile, vertical, 128-bit
@@ -2850,73 +2850,73 @@ mova    za0v.q[w12, 0], p0/m, z0.q
 // CHECK-INST: mov     za0v.q[w12, 0], p0/m, z0.q
 // CHECK-ENCODING: [0x00,0x80,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c18000 <unknown>
 
 mova    za5v.q[w14, 0], p5/m, z10.q
 // CHECK-INST: mov     za5v.q[w14, 0], p5/m, z10.q
 // CHECK-ENCODING: [0x45,0xd5,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1d545 <unknown>
 
 mova    za7v.q[w15, 0], p3/m, z13.q
 // CHECK-INST: mov     za7v.q[w15, 0], p3/m, z13.q
 // CHECK-ENCODING: [0xa7,0xed,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1eda7 <unknown>
 
 mova    za15v.q[w15, 0], p7/m, z31.q
 // CHECK-INST: mov     za15v.q[w15, 0], p7/m, z31.q
 // CHECK-ENCODING: [0xef,0xff,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1ffef <unknown>
 
 mova    za5v.q[w12, 0], p3/m, z17.q
 // CHECK-INST: mov     za5v.q[w12, 0], p3/m, z17.q
 // CHECK-ENCODING: [0x25,0x8e,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c18e25 <unknown>
 
 mova    za1v.q[w12, 0], p1/m, z1.q
 // CHECK-INST: mov     za1v.q[w12, 0], p1/m, z1.q
 // CHECK-ENCODING: [0x21,0x84,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c18421 <unknown>
 
 mova    za8v.q[w14, 0], p5/m, z19.q
 // CHECK-INST: mov     za8v.q[w14, 0], p5/m, z19.q
 // CHECK-ENCODING: [0x68,0xd6,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1d668 <unknown>
 
 mova    za0v.q[w12, 0], p6/m, z12.q
 // CHECK-INST: mov     za0v.q[w12, 0], p6/m, z12.q
 // CHECK-ENCODING: [0x80,0x99,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c19980 <unknown>
 
 mova    za1v.q[w14, 0], p2/m, z1.q
 // CHECK-INST: mov     za1v.q[w14, 0], p2/m, z1.q
 // CHECK-ENCODING: [0x21,0xc8,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1c821 <unknown>
 
 mova    za13v.q[w12, 0], p2/m, z22.q
 // CHECK-INST: mov     za13v.q[w12, 0], p2/m, z22.q
 // CHECK-ENCODING: [0xcd,0x8a,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c18acd <unknown>
 
 mova    za2v.q[w15, 0], p5/m, z9.q
 // CHECK-INST: mov     za2v.q[w15, 0], p5/m, z9.q
 // CHECK-ENCODING: [0x22,0xf5,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1f522 <unknown>
 
 mova    za7v.q[w13, 0], p2/m, z12.q
 // CHECK-INST: mov     za7v.q[w13, 0], p2/m, z12.q
 // CHECK-ENCODING: [0x87,0xa9,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1a987 <unknown>
 
 // Aliases
 
@@ -2924,70 +2924,70 @@ mov     za0v.q[w12, 0], p0/m, z0.q
 // CHECK-INST: mov     za0v.q[w12, 0], p0/m, z0.q
 // CHECK-ENCODING: [0x00,0x80,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c18000 <unknown>
 
 mov     za5v.q[w14, 0], p5/m, z10.q
 // CHECK-INST: mov     za5v.q[w14, 0], p5/m, z10.q
 // CHECK-ENCODING: [0x45,0xd5,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1d545 <unknown>
 
 mov     za7v.q[w15, 0], p3/m, z13.q
 // CHECK-INST: mov     za7v.q[w15, 0], p3/m, z13.q
 // CHECK-ENCODING: [0xa7,0xed,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1eda7 <unknown>
 
 mov     za15v.q[w15, 0], p7/m, z31.q
 // CHECK-INST: mov     za15v.q[w15, 0], p7/m, z31.q
 // CHECK-ENCODING: [0xef,0xff,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1ffef <unknown>
 
 mov     za5v.q[w12, 0], p3/m, z17.q
 // CHECK-INST: mov     za5v.q[w12, 0], p3/m, z17.q
 // CHECK-ENCODING: [0x25,0x8e,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c18e25 <unknown>
 
 mov     za1v.q[w12, 0], p1/m, z1.q
 // CHECK-INST: mov     za1v.q[w12, 0], p1/m, z1.q
 // CHECK-ENCODING: [0x21,0x84,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c18421 <unknown>
 
 mov     za8v.q[w14, 0], p5/m, z19.q
 // CHECK-INST: mov     za8v.q[w14, 0], p5/m, z19.q
 // CHECK-ENCODING: [0x68,0xd6,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1d668 <unknown>
 
 mov     za0v.q[w12, 0], p6/m, z12.q
 // CHECK-INST: mov     za0v.q[w12, 0], p6/m, z12.q
 // CHECK-ENCODING: [0x80,0x99,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c19980 <unknown>
 
 mov     za1v.q[w14, 0], p2/m, z1.q
 // CHECK-INST: mov     za1v.q[w14, 0], p2/m, z1.q
 // CHECK-ENCODING: [0x21,0xc8,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1c821 <unknown>
 
 mov     za13v.q[w12, 0], p2/m, z22.q
 // CHECK-INST: mov     za13v.q[w12, 0], p2/m, z22.q
 // CHECK-ENCODING: [0xcd,0x8a,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c18acd <unknown>
 
 mov     za2v.q[w15, 0], p5/m, z9.q
 // CHECK-INST: mov     za2v.q[w15, 0], p5/m, z9.q
 // CHECK-ENCODING: [0x22,0xf5,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1f522 <unknown>
 
 mov     za7v.q[w13, 0], p2/m, z12.q
 // CHECK-INST: mov     za7v.q[w13, 0], p2/m, z12.q
 // CHECK-ENCODING: [0x87,0xa9,0xc1,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 c1 c0 <unknown>
+// CHECK-UNKNOWN: c0c1a987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/psel.s b/llvm/test/MC/AArch64/SME/psel.s
index ae1c738cc24e5..6db22abf64652 100644
--- a/llvm/test/MC/AArch64/SME/psel.s
+++ b/llvm/test/MC/AArch64/SME/psel.s
@@ -19,25 +19,25 @@ psel    p0, p0, p0.b[w12, 0]
 // CHECK-INST: psel    p0, p0, p0.b[w12, 0]
 // CHECK-ENCODING: [0x00,0x40,0x24,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 40 24 25 <unknown>
+// CHECK-UNKNOWN: 25244000 <unknown>
 
 psel    p5, p5, p10.b[w13, 6]
 // CHECK-INST: psel    p5, p5, p10.b[w13, 6]
 // CHECK-ENCODING: [0x45,0x55,0x75,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 75 25 <unknown>
+// CHECK-UNKNOWN: 25755545 <unknown>
 
 psel    p7, p11, p13.b[w12, 5]
 // CHECK-INST: psel    p7, p11, p13.b[w12, 5]
 // CHECK-ENCODING: [0xa7,0x6d,0x6c,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 6c 25 <unknown>
+// CHECK-UNKNOWN: 256c6da7 <unknown>
 
 psel    p15, p15, p15.b[w15, 15]
 // CHECK-INST: psel    p15, p15, p15.b[w15, 15]
 // CHECK-ENCODING: [0xef,0x7d,0xff,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7d ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff7def <unknown>
 
 // --------------------------------------------------------------------------//
 // 16-bit
@@ -46,25 +46,25 @@ psel    p0, p0, p0.h[w12, 0]
 // CHECK-INST: psel    p0, p0, p0.h[w12, 0]
 // CHECK-ENCODING: [0x00,0x40,0x28,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 40 28 25 <unknown>
+// CHECK-UNKNOWN: 25284000 <unknown>
 
 psel    p5, p5, p10.h[w13, 3]
 // CHECK-INST: psel    p5, p5, p10.h[w13, 3]
 // CHECK-ENCODING: [0x45,0x55,0x79,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 79 25 <unknown>
+// CHECK-UNKNOWN: 25795545 <unknown>
 
 psel    p7, p11, p13.h[w12, 2]
 // CHECK-INST: psel    p7, p11, p13.h[w12, 2]
 // CHECK-ENCODING: [0xa7,0x6d,0x68,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 68 25 <unknown>
+// CHECK-UNKNOWN: 25686da7 <unknown>
 
 psel    p15, p15, p15.h[w15, 7]
 // CHECK-INST: psel    p15, p15, p15.h[w15, 7]
 // CHECK-ENCODING: [0xef,0x7d,0xfb,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7d fb 25 <unknown>
+// CHECK-UNKNOWN: 25fb7def <unknown>
 
 // --------------------------------------------------------------------------//
 // 32-bit
@@ -73,25 +73,25 @@ psel    p0, p0, p0.s[w12, 0]
 // CHECK-INST: psel    p0, p0, p0.s[w12, 0]
 // CHECK-ENCODING: [0x00,0x40,0x30,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 40 30 25 <unknown>
+// CHECK-UNKNOWN: 25304000 <unknown>
 
 psel    p5, p5, p10.s[w13, 1]
 // CHECK-INST: psel    p5, p5, p10.s[w13, 1]
 // CHECK-ENCODING: [0x45,0x55,0x71,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 71 25 <unknown>
+// CHECK-UNKNOWN: 25715545 <unknown>
 
 psel    p7, p11, p13.s[w12, 1]
 // CHECK-INST: psel    p7, p11, p13.s[w12, 1]
 // CHECK-ENCODING: [0xa7,0x6d,0x70,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 70 25 <unknown>
+// CHECK-UNKNOWN: 25706da7 <unknown>
 
 psel    p15, p15, p15.s[w15, 3]
 // CHECK-INST: psel    p15, p15, p15.s[w15, 3]
 // CHECK-ENCODING: [0xef,0x7d,0xf3,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7d f3 25 <unknown>
+// CHECK-UNKNOWN: 25f37def <unknown>
 
 // --------------------------------------------------------------------------//
 // 64-bit
@@ -100,22 +100,22 @@ psel    p0, p0, p0.d[w12, 0]
 // CHECK-INST: psel    p0, p0, p0.d[w12, 0]
 // CHECK-ENCODING: [0x00,0x40,0x60,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 40 60 25 <unknown>
+// CHECK-UNKNOWN: 25604000 <unknown>
 
 psel    p5, p5, p10.d[w13, 0]
 // CHECK-INST: psel    p5, p5, p10.d[w13, 0]
 // CHECK-ENCODING: [0x45,0x55,0x61,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 61 25 <unknown>
+// CHECK-UNKNOWN: 25615545 <unknown>
 
 psel    p7, p11, p13.d[w12, 0]
 // CHECK-INST: psel    p7, p11, p13.d[w12, 0]
 // CHECK-ENCODING: [0xa7,0x6d,0x60,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 60 25 <unknown>
+// CHECK-UNKNOWN: 25606da7 <unknown>
 
 psel    p15, p15, p15.d[w15, 1]
 // CHECK-INST: psel    p15, p15, p15.d[w15, 1]
 // CHECK-ENCODING: [0xef,0x7d,0xe3,0x25]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7d e3 25 <unknown>
+// CHECK-UNKNOWN: 25e37def <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/rdsvl.s b/llvm/test/MC/AArch64/SME/rdsvl.s
index f1c6d3e9ce517..0db0fbd064b8d 100644
--- a/llvm/test/MC/AArch64/SME/rdsvl.s
+++ b/llvm/test/MC/AArch64/SME/rdsvl.s
@@ -11,22 +11,22 @@ rdsvl    x0, #0
 // CHECK-INST: rdsvl    x0, #0
 // CHECK-ENCODING: [0x00,0x58,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 58 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf5800 <unknown>
 
 rdsvl    xzr, #-1
 // CHECK-INST: rdsvl    xzr, #-1
 // CHECK-ENCODING: [0xff,0x5f,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 5f bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf5fff <unknown>
 
 rdsvl    x23, #31
 // CHECK-INST: rdsvl    x23, #31
 // CHECK-ENCODING: [0xf7,0x5b,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: f7 5b bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf5bf7 <unknown>
 
 rdsvl    x21, #-32
 // CHECK-INST: rdsvl    x21, #-32
 // CHECK-ENCODING: [0x15,0x5c,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 15 5c bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf5c15 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/revd.s b/llvm/test/MC/AArch64/SME/revd.s
index fe37073a10407..dc73da1142e84 100644
--- a/llvm/test/MC/AArch64/SME/revd.s
+++ b/llvm/test/MC/AArch64/SME/revd.s
@@ -16,25 +16,25 @@ revd    z0.q, p0/m, z0.q
 // CHECK-INST: revd    z0.q, p0/m, z0.q
 // CHECK-ENCODING: [0x00,0x80,0x2e,0x05]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 2e 05 <unknown>
+// CHECK-UNKNOWN: 052e8000 <unknown>
 
 revd    z21.q, p5/m, z10.q
 // CHECK-INST: revd    z21.q, p5/m, z10.q
 // CHECK-ENCODING: [0x55,0x95,0x2e,0x05]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 95 2e 05 <unknown>
+// CHECK-UNKNOWN: 052e9555 <unknown>
 
 revd    z23.q, p3/m, z13.q
 // CHECK-INST: revd    z23.q, p3/m, z13.q
 // CHECK-ENCODING: [0xb7,0x8d,0x2e,0x05]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 8d 2e 05 <unknown>
+// CHECK-UNKNOWN: 052e8db7 <unknown>
 
 revd    z31.q, p7/m, z31.q
 // CHECK-INST: revd    z31.q, p7/m, z31.q
 // CHECK-ENCODING: [0xff,0x9f,0x2e,0x05]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 9f 2e 05 <unknown>
+// CHECK-UNKNOWN: 052e9fff <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -43,10 +43,10 @@ movprfx z21, z25
 // CHECK-INST: movprfx  z21, z25
 // CHECK-ENCODING: [0x35,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 35 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf35 <unknown>
 
 revd    z21.q, p5/m, z10.q
 // CHECK-INST: revd    z21.q, p5/m, z10.q
 // CHECK-ENCODING: [0x55,0x95,0x2e,0x05]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 95 2e 05 <unknown>
+// CHECK-UNKNOWN: 052e9555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/sclamp.s b/llvm/test/MC/AArch64/SME/sclamp.s
index a40d19a1107a6..fb42fbdbd88bb 100644
--- a/llvm/test/MC/AArch64/SME/sclamp.s
+++ b/llvm/test/MC/AArch64/SME/sclamp.s
@@ -19,25 +19,25 @@ sclamp  z0.b, z0.b, z0.b
 // CHECK-INST: sclamp  z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0xc0,0x00,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 c0 00 44 <unknown>
+// CHECK-UNKNOWN: 4400c000 <unknown>
 
 sclamp  z21.b, z10.b, z21.b
 // CHECK-INST: sclamp  z21.b, z10.b, z21.b
 // CHECK-ENCODING: [0x55,0xc1,0x15,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 c1 15 44 <unknown>
+// CHECK-UNKNOWN: 4415c155 <unknown>
 
 sclamp  z23.b, z13.b, z8.b
 // CHECK-INST: sclamp  z23.b, z13.b, z8.b
 // CHECK-ENCODING: [0xb7,0xc1,0x08,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c1 08 44 <unknown>
+// CHECK-UNKNOWN: 4408c1b7 <unknown>
 
 sclamp  z31.b, z31.b, z31.b
 // CHECK-INST: sclamp  z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0xc3,0x1f,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff c3 1f 44 <unknown>
+// CHECK-UNKNOWN: 441fc3ff <unknown>
 
 // --------------------------------------------------------------------------//
 // 16-bit
@@ -46,25 +46,25 @@ sclamp  z0.h, z0.h, z0.h
 // CHECK-INST: sclamp  z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0xc0,0x40,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 c0 40 44 <unknown>
+// CHECK-UNKNOWN: 4440c000 <unknown>
 
 sclamp  z21.h, z10.h, z21.h
 // CHECK-INST: sclamp  z21.h, z10.h, z21.h
 // CHECK-ENCODING: [0x55,0xc1,0x55,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 c1 55 44 <unknown>
+// CHECK-UNKNOWN: 4455c155 <unknown>
 
 sclamp  z23.h, z13.h, z8.h
 // CHECK-INST: sclamp  z23.h, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0xc1,0x48,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c1 48 44 <unknown>
+// CHECK-UNKNOWN: 4448c1b7 <unknown>
 
 sclamp  z31.h, z31.h, z31.h
 // CHECK-INST: sclamp  z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0xc3,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff c3 5f 44 <unknown>
+// CHECK-UNKNOWN: 445fc3ff <unknown>
 
 // --------------------------------------------------------------------------//
 // 32-bit
@@ -73,25 +73,25 @@ sclamp  z0.s, z0.s, z0.s
 // CHECK-INST: sclamp  z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0xc0,0x80,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 c0 80 44 <unknown>
+// CHECK-UNKNOWN: 4480c000 <unknown>
 
 sclamp  z21.s, z10.s, z21.s
 // CHECK-INST: sclamp  z21.s, z10.s, z21.s
 // CHECK-ENCODING: [0x55,0xc1,0x95,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 c1 95 44 <unknown>
+// CHECK-UNKNOWN: 4495c155 <unknown>
 
 sclamp  z23.s, z13.s, z8.s
 // CHECK-INST: sclamp  z23.s, z13.s, z8.s
 // CHECK-ENCODING: [0xb7,0xc1,0x88,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c1 88 44 <unknown>
+// CHECK-UNKNOWN: 4488c1b7 <unknown>
 
 sclamp  z31.s, z31.s, z31.s
 // CHECK-INST: sclamp  z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0xc3,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff c3 9f 44 <unknown>
+// CHECK-UNKNOWN: 449fc3ff <unknown>
 
 // --------------------------------------------------------------------------//
 // 64-bit
@@ -100,25 +100,25 @@ sclamp  z0.d, z0.d, z0.d
 // CHECK-INST: sclamp  z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0xc0,0xc0,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 c0 c0 44 <unknown>
+// CHECK-UNKNOWN: 44c0c000 <unknown>
 
 sclamp  z21.d, z10.d, z21.d
 // CHECK-INST: sclamp  z21.d, z10.d, z21.d
 // CHECK-ENCODING: [0x55,0xc1,0xd5,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 c1 d5 44 <unknown>
+// CHECK-UNKNOWN: 44d5c155 <unknown>
 
 sclamp  z23.d, z13.d, z8.d
 // CHECK-INST: sclamp  z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0xc1,0xc8,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c1 c8 44 <unknown>
+// CHECK-UNKNOWN: 44c8c1b7 <unknown>
 
 sclamp  z31.d, z31.d, z31.d
 // CHECK-INST: sclamp  z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0xc3,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff c3 df 44 <unknown>
+// CHECK-UNKNOWN: 44dfc3ff <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -127,46 +127,46 @@ movprfx z23, z27
 // CHECK-INST: movprfx  z23, z27
 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 77 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf77 <unknown>
 
 sclamp  z23.b, z13.b, z8.b
 // CHECK-INST: sclamp  z23.b, z13.b, z8.b
 // CHECK-ENCODING: [0xb7,0xc1,0x08,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c1 08 44 <unknown>
+// CHECK-UNKNOWN: 4408c1b7 <unknown>
 
 movprfx z23, z27
 // CHECK-INST: movprfx  z23, z27
 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 77 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf77 <unknown>
 
 sclamp  z23.h, z13.h, z8.h
 // CHECK-INST: sclamp  z23.h, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0xc1,0x48,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c1 48 44 <unknown>
+// CHECK-UNKNOWN: 4448c1b7 <unknown>
 
 movprfx z23, z27
 // CHECK-INST: movprfx  z23, z27
 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 77 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf77 <unknown>
 
 sclamp  z23.s, z13.s, z8.s
 // CHECK-INST: sclamp  z23.s, z13.s, z8.s
 // CHECK-ENCODING: [0xb7,0xc1,0x88,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c1 88 44 <unknown>
+// CHECK-UNKNOWN: 4488c1b7 <unknown>
 
 movprfx z23, z27
 // CHECK-INST: movprfx  z23, z27
 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 77 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf77 <unknown>
 
 sclamp  z23.d, z13.d, z8.d
 // CHECK-INST: sclamp  z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0xc1,0xc8,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c1 c8 44 <unknown>
+// CHECK-UNKNOWN: 44c8c1b7 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/smopa-32.s b/llvm/test/MC/AArch64/SME/smopa-32.s
index 6827b1b8053cf..9617a3a550b52 100644
--- a/llvm/test/MC/AArch64/SME/smopa-32.s
+++ b/llvm/test/MC/AArch64/SME/smopa-32.s
@@ -16,70 +16,70 @@ smopa   za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-INST: smopa   za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x00,0x80,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 80 a0 <unknown>
+// CHECK-UNKNOWN: a0800000 <unknown>
 
 smopa   za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-INST: smopa   za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-ENCODING: [0x41,0x55,0x95,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 41 55 95 a0 <unknown>
+// CHECK-UNKNOWN: a0955541 <unknown>
 
 smopa   za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-INST: smopa   za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-ENCODING: [0xa3,0xed,0x88,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a3 ed 88 a0 <unknown>
+// CHECK-UNKNOWN: a088eda3 <unknown>
 
 smopa   za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-INST: smopa   za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xe3,0xff,0x9f,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: e3 ff 9f a0 <unknown>
+// CHECK-UNKNOWN: a09fffe3 <unknown>
 
 smopa   za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-INST: smopa   za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-ENCODING: [0x21,0x0e,0x90,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 0e 90 a0 <unknown>
+// CHECK-UNKNOWN: a0900e21 <unknown>
 
 smopa   za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-INST: smopa   za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-ENCODING: [0x21,0x84,0x9e,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 9e a0 <unknown>
+// CHECK-UNKNOWN: a09e8421 <unknown>
 
 smopa   za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-INST: smopa   za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-ENCODING: [0x60,0x56,0x94,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 60 56 94 a0 <unknown>
+// CHECK-UNKNOWN: a0945660 <unknown>
 
 smopa   za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-INST: smopa   za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-ENCODING: [0x80,0x19,0x82,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 82 a0 <unknown>
+// CHECK-UNKNOWN: a0821980 <unknown>
 
 smopa   za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-INST: smopa   za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-ENCODING: [0x21,0xc8,0x9a,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 9a a0 <unknown>
+// CHECK-UNKNOWN: a09ac821 <unknown>
 
 smopa   za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-INST: smopa   za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-ENCODING: [0xc1,0x0a,0x9e,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: c1 0a 9e a0 <unknown>
+// CHECK-UNKNOWN: a09e0ac1 <unknown>
 
 smopa   za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-INST: smopa   za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-ENCODING: [0x22,0xf5,0x81,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 81 a0 <unknown>
+// CHECK-UNKNOWN: a081f522 <unknown>
 
 smopa   za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-INST: smopa   za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-ENCODING: [0x83,0xa9,0x8b,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 83 a9 8b a0 <unknown>
+// CHECK-UNKNOWN: a08ba983 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/smopa-64.s b/llvm/test/MC/AArch64/SME/smopa-64.s
index ea32f536668c7..6b06ec1bc0b0a 100644
--- a/llvm/test/MC/AArch64/SME/smopa-64.s
+++ b/llvm/test/MC/AArch64/SME/smopa-64.s
@@ -16,70 +16,70 @@ smopa   za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-INST: smopa   za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x00,0xc0,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 00 00 c0 a0 <unknown>
+// CHECK-UNKNOWN: a0c00000 <unknown>
 
 smopa   za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-INST: smopa   za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-ENCODING: [0x45,0x55,0xd5,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 45 55 d5 a0 <unknown>
+// CHECK-UNKNOWN: a0d55545 <unknown>
 
 smopa   za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-INST: smopa   za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-ENCODING: [0xa7,0xed,0xc8,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: a7 ed c8 a0 <unknown>
+// CHECK-UNKNOWN: a0c8eda7 <unknown>
 
 smopa   za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-INST: smopa   za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xe7,0xff,0xdf,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: e7 ff df a0 <unknown>
+// CHECK-UNKNOWN: a0dfffe7 <unknown>
 
 smopa   za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-INST: smopa   za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-ENCODING: [0x25,0x0e,0xd0,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 25 0e d0 a0 <unknown>
+// CHECK-UNKNOWN: a0d00e25 <unknown>
 
 smopa   za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-INST: smopa   za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-ENCODING: [0x21,0x84,0xde,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 21 84 de a0 <unknown>
+// CHECK-UNKNOWN: a0de8421 <unknown>
 
 smopa   za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-INST: smopa   za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-ENCODING: [0x60,0x56,0xd4,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 60 56 d4 a0 <unknown>
+// CHECK-UNKNOWN: a0d45660 <unknown>
 
 smopa   za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-INST: smopa   za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-ENCODING: [0x80,0x19,0xc2,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 80 19 c2 a0 <unknown>
+// CHECK-UNKNOWN: a0c21980 <unknown>
 
 smopa   za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-INST: smopa   za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-ENCODING: [0x21,0xc8,0xda,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 21 c8 da a0 <unknown>
+// CHECK-UNKNOWN: a0dac821 <unknown>
 
 smopa   za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-INST: smopa   za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-ENCODING: [0xc5,0x0a,0xde,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: c5 0a de a0 <unknown>
+// CHECK-UNKNOWN: a0de0ac5 <unknown>
 
 smopa   za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-INST: smopa   za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-ENCODING: [0x22,0xf5,0xc1,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 22 f5 c1 a0 <unknown>
+// CHECK-UNKNOWN: a0c1f522 <unknown>
 
 smopa   za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-INST: smopa   za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-ENCODING: [0x87,0xa9,0xcb,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 87 a9 cb a0 <unknown>
+// CHECK-UNKNOWN: a0cba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/smops-32.s b/llvm/test/MC/AArch64/SME/smops-32.s
index b35909d5dd1a2..ebb3c1b4b45ed 100644
--- a/llvm/test/MC/AArch64/SME/smops-32.s
+++ b/llvm/test/MC/AArch64/SME/smops-32.s
@@ -16,70 +16,70 @@ smops   za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-INST: smops   za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x10,0x00,0x80,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 10 00 80 a0 <unknown>
+// CHECK-UNKNOWN: a0800010 <unknown>
 
 smops   za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-INST: smops   za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-ENCODING: [0x51,0x55,0x95,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 51 55 95 a0 <unknown>
+// CHECK-UNKNOWN: a0955551 <unknown>
 
 smops   za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-INST: smops   za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-ENCODING: [0xb3,0xed,0x88,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b3 ed 88 a0 <unknown>
+// CHECK-UNKNOWN: a088edb3 <unknown>
 
 smops   za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-INST: smops   za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xf3,0xff,0x9f,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: f3 ff 9f a0 <unknown>
+// CHECK-UNKNOWN: a09ffff3 <unknown>
 
 smops   za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-INST: smops   za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-ENCODING: [0x31,0x0e,0x90,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 0e 90 a0 <unknown>
+// CHECK-UNKNOWN: a0900e31 <unknown>
 
 smops   za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-INST: smops   za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-ENCODING: [0x31,0x84,0x9e,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 84 9e a0 <unknown>
+// CHECK-UNKNOWN: a09e8431 <unknown>
 
 smops   za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-INST: smops   za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-ENCODING: [0x70,0x56,0x94,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 70 56 94 a0 <unknown>
+// CHECK-UNKNOWN: a0945670 <unknown>
 
 smops   za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-INST: smops   za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-ENCODING: [0x90,0x19,0x82,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 90 19 82 a0 <unknown>
+// CHECK-UNKNOWN: a0821990 <unknown>
 
 smops   za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-INST: smops   za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-ENCODING: [0x31,0xc8,0x9a,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 9a a0 <unknown>
+// CHECK-UNKNOWN: a09ac831 <unknown>
 
 smops   za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-INST: smops   za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-ENCODING: [0xd1,0x0a,0x9e,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: d1 0a 9e a0 <unknown>
+// CHECK-UNKNOWN: a09e0ad1 <unknown>
 
 smops   za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-INST: smops   za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-ENCODING: [0x32,0xf5,0x81,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 32 f5 81 a0 <unknown>
+// CHECK-UNKNOWN: a081f532 <unknown>
 
 smops   za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-INST: smops   za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-ENCODING: [0x93,0xa9,0x8b,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 93 a9 8b a0 <unknown>
+// CHECK-UNKNOWN: a08ba993 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/smops-64.s b/llvm/test/MC/AArch64/SME/smops-64.s
index a028d9a489c79..5865204f00c81 100644
--- a/llvm/test/MC/AArch64/SME/smops-64.s
+++ b/llvm/test/MC/AArch64/SME/smops-64.s
@@ -16,70 +16,70 @@ smops   za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-INST: smops   za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x10,0x00,0xc0,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 10 00 c0 a0 <unknown>
+// CHECK-UNKNOWN: a0c00010 <unknown>
 
 smops   za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-INST: smops   za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-ENCODING: [0x55,0x55,0xd5,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 55 55 d5 a0 <unknown>
+// CHECK-UNKNOWN: a0d55555 <unknown>
 
 smops   za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-INST: smops   za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0xed,0xc8,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: b7 ed c8 a0 <unknown>
+// CHECK-UNKNOWN: a0c8edb7 <unknown>
 
 smops   za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-INST: smops   za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xf7,0xff,0xdf,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: f7 ff df a0 <unknown>
+// CHECK-UNKNOWN: a0dffff7 <unknown>
 
 smops   za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-INST: smops   za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-ENCODING: [0x35,0x0e,0xd0,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 35 0e d0 a0 <unknown>
+// CHECK-UNKNOWN: a0d00e35 <unknown>
 
 smops   za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-INST: smops   za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-ENCODING: [0x31,0x84,0xde,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 31 84 de a0 <unknown>
+// CHECK-UNKNOWN: a0de8431 <unknown>
 
 smops   za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-INST: smops   za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-ENCODING: [0x70,0x56,0xd4,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 70 56 d4 a0 <unknown>
+// CHECK-UNKNOWN: a0d45670 <unknown>
 
 smops   za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-INST: smops   za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-ENCODING: [0x90,0x19,0xc2,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 90 19 c2 a0 <unknown>
+// CHECK-UNKNOWN: a0c21990 <unknown>
 
 smops   za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-INST: smops   za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-ENCODING: [0x31,0xc8,0xda,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 31 c8 da a0 <unknown>
+// CHECK-UNKNOWN: a0dac831 <unknown>
 
 smops   za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-INST: smops   za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-ENCODING: [0xd5,0x0a,0xde,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: d5 0a de a0 <unknown>
+// CHECK-UNKNOWN: a0de0ad5 <unknown>
 
 smops   za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-INST: smops   za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-ENCODING: [0x32,0xf5,0xc1,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 32 f5 c1 a0 <unknown>
+// CHECK-UNKNOWN: a0c1f532 <unknown>
 
 smops   za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-INST: smops   za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-ENCODING: [0x97,0xa9,0xcb,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 97 a9 cb a0 <unknown>
+// CHECK-UNKNOWN: a0cba997 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/smstart.s b/llvm/test/MC/AArch64/SME/smstart.s
index 8976653a8f2a5..1628a279bb353 100644
--- a/llvm/test/MC/AArch64/SME/smstart.s
+++ b/llvm/test/MC/AArch64/SME/smstart.s
@@ -11,28 +11,28 @@ smstart
 // CHECK-INST: smstart
 // CHECK-ENCODING: [0x7f,0x47,0x03,0xd5]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 7f 47 03 d5   msr   S0_3_C4_C7_3, xzr
+// CHECK-UNKNOWN: d503477f   msr   S0_3_C4_C7_3, xzr
 
 smstart sm
 // CHECK-INST: smstart sm
 // CHECK-ENCODING: [0x7f,0x43,0x03,0xd5]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 7f 43 03 d5   msr   S0_3_C4_C3_3, xzr
+// CHECK-UNKNOWN: d503437f   msr   S0_3_C4_C3_3, xzr
 
 smstart za
 // CHECK-INST: smstart za
 // CHECK-ENCODING: [0x7f,0x45,0x03,0xd5]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 7f 45 03 d5   msr   S0_3_C4_C5_3, xzr
+// CHECK-UNKNOWN: d503457f   msr   S0_3_C4_C5_3, xzr
 
 smstart SM
 // CHECK-INST: smstart sm
 // CHECK-ENCODING: [0x7f,0x43,0x03,0xd5]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 7f 43 03 d5   msr   S0_3_C4_C3_3, xzr
+// CHECK-UNKNOWN: d503437f   msr   S0_3_C4_C3_3, xzr
 
 smstart ZA
 // CHECK-INST: smstart za
 // CHECK-ENCODING: [0x7f,0x45,0x03,0xd5]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 7f 45 03 d5   msr   S0_3_C4_C5_3, xzr
+// CHECK-UNKNOWN: d503457f   msr   S0_3_C4_C5_3, xzr

diff  --git a/llvm/test/MC/AArch64/SME/smstop.s b/llvm/test/MC/AArch64/SME/smstop.s
index 10d37625feebb..b7c21d939e9a9 100644
--- a/llvm/test/MC/AArch64/SME/smstop.s
+++ b/llvm/test/MC/AArch64/SME/smstop.s
@@ -11,28 +11,28 @@ smstop
 // CHECK-INST: smstop
 // CHECK-ENCODING: [0x7f,0x46,0x03,0xd5]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 7f 46 03 d5   msr   S0_3_C4_C6_3, xzr
+// CHECK-UNKNOWN: d503467f   msr   S0_3_C4_C6_3, xzr
 
 smstop sm
 // CHECK-INST: smstop sm
 // CHECK-ENCODING: [0x7f,0x42,0x03,0xd5]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 7f 42 03 d5   msr   S0_3_C4_C2_3, xzr
+// CHECK-UNKNOWN: d503427f   msr   S0_3_C4_C2_3, xzr
 
 smstop za
 // CHECK-INST: smstop za
 // CHECK-ENCODING: [0x7f,0x44,0x03,0xd5]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 7f 44 03 d5   msr   S0_3_C4_C4_3, xzr
+// CHECK-UNKNOWN: d503447f   msr   S0_3_C4_C4_3, xzr
 
 smstop SM
 // CHECK-INST: smstop sm
 // CHECK-ENCODING: [0x7f,0x42,0x03,0xd5]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 7f 42 03 d5   msr   S0_3_C4_C2_3, xzr
+// CHECK-UNKNOWN: d503427f   msr   S0_3_C4_C2_3, xzr
 
 smstop ZA
 // CHECK-INST: smstop za
 // CHECK-ENCODING: [0x7f,0x44,0x03,0xd5]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 7f 44 03 d5   msr   S0_3_C4_C4_3, xzr
+// CHECK-UNKNOWN: d503447f   msr   S0_3_C4_C4_3, xzr

diff  --git a/llvm/test/MC/AArch64/SME/st1b.s b/llvm/test/MC/AArch64/SME/st1b.s
index ad1bb20771cc7..8b048b2195b87 100644
--- a/llvm/test/MC/AArch64/SME/st1b.s
+++ b/llvm/test/MC/AArch64/SME/st1b.s
@@ -19,145 +19,145 @@ st1b    {za0h.b[w12, 0]}, p0, [x0, x0]
 // CHECK-INST: st1b    {za0h.b[w12, 0]}, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x00,0x20,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 20 e0 <unknown>
+// CHECK-UNKNOWN: e0200000 <unknown>
 
 st1b    {za0h.b[w14, 5]}, p5, [x10, x21]
 // CHECK-INST: st1b    {za0h.b[w14, 5]}, p5, [x10, x21]
 // CHECK-ENCODING: [0x45,0x55,0x35,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 35 e0 <unknown>
+// CHECK-UNKNOWN: e0355545 <unknown>
 
 st1b    {za0h.b[w15, 7]}, p3, [x13, x8]
 // CHECK-INST: st1b    {za0h.b[w15, 7]}, p3, [x13, x8]
 // CHECK-ENCODING: [0xa7,0x6d,0x28,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 28 e0 <unknown>
+// CHECK-UNKNOWN: e0286da7 <unknown>
 
 st1b    {za0h.b[w15, 15]}, p7, [sp]
 // CHECK-INST: st1b    {za0h.b[w15, 15]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0x3f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 3f e0 <unknown>
+// CHECK-UNKNOWN: e03f7fef <unknown>
 
 st1b    {za0h.b[w12, 5]}, p3, [x17, x16]
 // CHECK-INST: st1b    {za0h.b[w12, 5]}, p3, [x17, x16]
 // CHECK-ENCODING: [0x25,0x0e,0x30,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 30 e0 <unknown>
+// CHECK-UNKNOWN: e0300e25 <unknown>
 
 st1b    {za0h.b[w12, 1]}, p1, [x1, x30]
 // CHECK-INST: st1b    {za0h.b[w12, 1]}, p1, [x1, x30]
 // CHECK-ENCODING: [0x21,0x04,0x3e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 3e e0 <unknown>
+// CHECK-UNKNOWN: e03e0421 <unknown>
 
 st1b    {za0h.b[w14, 8]}, p5, [x19, x20]
 // CHECK-INST: st1b    {za0h.b[w14, 8]}, p5, [x19, x20]
 // CHECK-ENCODING: [0x68,0x56,0x34,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 34 e0 <unknown>
+// CHECK-UNKNOWN: e0345668 <unknown>
 
 st1b    {za0h.b[w12, 0]}, p6, [x12, x2]
 // CHECK-INST: st1b    {za0h.b[w12, 0]}, p6, [x12, x2]
 // CHECK-ENCODING: [0x80,0x19,0x22,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 22 e0 <unknown>
+// CHECK-UNKNOWN: e0221980 <unknown>
 
 st1b    {za0h.b[w14, 1]}, p2, [x1, x26]
 // CHECK-INST: st1b    {za0h.b[w14, 1]}, p2, [x1, x26]
 // CHECK-ENCODING: [0x21,0x48,0x3a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 3a e0 <unknown>
+// CHECK-UNKNOWN: e03a4821 <unknown>
 
 st1b    {za0h.b[w12, 13]}, p2, [x22, x30]
 // CHECK-INST: st1b    {za0h.b[w12, 13]}, p2, [x22, x30]
 // CHECK-ENCODING: [0xcd,0x0a,0x3e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 3e e0 <unknown>
+// CHECK-UNKNOWN: e03e0acd <unknown>
 
 st1b    {za0h.b[w15, 2]}, p5, [x9, x1]
 // CHECK-INST: st1b    {za0h.b[w15, 2]}, p5, [x9, x1]
 // CHECK-ENCODING: [0x22,0x75,0x21,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 21 e0 <unknown>
+// CHECK-UNKNOWN: e0217522 <unknown>
 
 st1b    {za0h.b[w13, 7]}, p2, [x12, x11]
 // CHECK-INST: st1b    {za0h.b[w13, 7]}, p2, [x12, x11]
 // CHECK-ENCODING: [0x87,0x29,0x2b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 2b e0 <unknown>
+// CHECK-UNKNOWN: e02b2987 <unknown>
 
 st1b    za0h.b[w12, 0], p0, [x0, x0]
 // CHECK-INST: st1b    {za0h.b[w12, 0]}, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x00,0x20,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 20 e0 <unknown>
+// CHECK-UNKNOWN: e0200000 <unknown>
 
 st1b    za0h.b[w14, 5], p5, [x10, x21]
 // CHECK-INST: st1b    {za0h.b[w14, 5]}, p5, [x10, x21]
 // CHECK-ENCODING: [0x45,0x55,0x35,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 35 e0 <unknown>
+// CHECK-UNKNOWN: e0355545 <unknown>
 
 st1b    za0h.b[w15, 7], p3, [x13, x8]
 // CHECK-INST: st1b    {za0h.b[w15, 7]}, p3, [x13, x8]
 // CHECK-ENCODING: [0xa7,0x6d,0x28,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 28 e0 <unknown>
+// CHECK-UNKNOWN: e0286da7 <unknown>
 
 st1b    za0h.b[w15, 15], p7, [sp]
 // CHECK-INST: st1b    {za0h.b[w15, 15]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0x3f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 3f e0 <unknown>
+// CHECK-UNKNOWN: e03f7fef <unknown>
 
 st1b    za0h.b[w12, 5], p3, [x17, x16]
 // CHECK-INST: st1b    {za0h.b[w12, 5]}, p3, [x17, x16]
 // CHECK-ENCODING: [0x25,0x0e,0x30,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 30 e0 <unknown>
+// CHECK-UNKNOWN: e0300e25 <unknown>
 
 st1b    za0h.b[w12, 1], p1, [x1, x30]
 // CHECK-INST: st1b    {za0h.b[w12, 1]}, p1, [x1, x30]
 // CHECK-ENCODING: [0x21,0x04,0x3e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 3e e0 <unknown>
+// CHECK-UNKNOWN: e03e0421 <unknown>
 
 st1b    za0h.b[w14, 8], p5, [x19, x20]
 // CHECK-INST: st1b    {za0h.b[w14, 8]}, p5, [x19, x20]
 // CHECK-ENCODING: [0x68,0x56,0x34,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 34 e0 <unknown>
+// CHECK-UNKNOWN: e0345668 <unknown>
 
 st1b    za0h.b[w12, 0], p6, [x12, x2]
 // CHECK-INST: st1b    {za0h.b[w12, 0]}, p6, [x12, x2]
 // CHECK-ENCODING: [0x80,0x19,0x22,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 22 e0 <unknown>
+// CHECK-UNKNOWN: e0221980 <unknown>
 
 st1b    za0h.b[w14, 1], p2, [x1, x26]
 // CHECK-INST: st1b    {za0h.b[w14, 1]}, p2, [x1, x26]
 // CHECK-ENCODING: [0x21,0x48,0x3a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 3a e0 <unknown>
+// CHECK-UNKNOWN: e03a4821 <unknown>
 
 st1b    za0h.b[w12, 13], p2, [x22, x30]
 // CHECK-INST: st1b    {za0h.b[w12, 13]}, p2, [x22, x30]
 // CHECK-ENCODING: [0xcd,0x0a,0x3e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 3e e0 <unknown>
+// CHECK-UNKNOWN: e03e0acd <unknown>
 
 st1b    za0h.b[w15, 2], p5, [x9, x1]
 // CHECK-INST: st1b    {za0h.b[w15, 2]}, p5, [x9, x1]
 // CHECK-ENCODING: [0x22,0x75,0x21,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 21 e0 <unknown>
+// CHECK-UNKNOWN: e0217522 <unknown>
 
 st1b    za0h.b[w13, 7], p2, [x12, x11]
 // CHECK-INST: st1b    {za0h.b[w13, 7]}, p2, [x12, x11]
 // CHECK-ENCODING: [0x87,0x29,0x2b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 2b e0 <unknown>
+// CHECK-UNKNOWN: e02b2987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Vertical
@@ -166,142 +166,142 @@ st1b    {za0v.b[w12, 0]}, p0, [x0, x0]
 // CHECK-INST: st1b    {za0v.b[w12, 0]}, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x80,0x20,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 20 e0 <unknown>
+// CHECK-UNKNOWN: e0208000 <unknown>
 
 st1b    {za0v.b[w14, 5]}, p5, [x10, x21]
 // CHECK-INST: st1b    {za0v.b[w14, 5]}, p5, [x10, x21]
 // CHECK-ENCODING: [0x45,0xd5,0x35,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 35 e0 <unknown>
+// CHECK-UNKNOWN: e035d545 <unknown>
 
 st1b    {za0v.b[w15, 7]}, p3, [x13, x8]
 // CHECK-INST: st1b    {za0v.b[w15, 7]}, p3, [x13, x8]
 // CHECK-ENCODING: [0xa7,0xed,0x28,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 28 e0 <unknown>
+// CHECK-UNKNOWN: e028eda7 <unknown>
 
 st1b    {za0v.b[w15, 15]}, p7, [sp]
 // CHECK-INST: st1b    {za0v.b[w15, 15]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0xff,0x3f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 3f e0 <unknown>
+// CHECK-UNKNOWN: e03fffef <unknown>
 
 st1b    {za0v.b[w12, 5]}, p3, [x17, x16]
 // CHECK-INST: st1b    {za0v.b[w12, 5]}, p3, [x17, x16]
 // CHECK-ENCODING: [0x25,0x8e,0x30,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 30 e0 <unknown>
+// CHECK-UNKNOWN: e0308e25 <unknown>
 
 st1b    {za0v.b[w12, 1]}, p1, [x1, x30]
 // CHECK-INST: st1b    {za0v.b[w12, 1]}, p1, [x1, x30]
 // CHECK-ENCODING: [0x21,0x84,0x3e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 3e e0 <unknown>
+// CHECK-UNKNOWN: e03e8421 <unknown>
 
 st1b    {za0v.b[w14, 8]}, p5, [x19, x20]
 // CHECK-INST: st1b    {za0v.b[w14, 8]}, p5, [x19, x20]
 // CHECK-ENCODING: [0x68,0xd6,0x34,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 34 e0 <unknown>
+// CHECK-UNKNOWN: e034d668 <unknown>
 
 st1b    {za0v.b[w12, 0]}, p6, [x12, x2]
 // CHECK-INST: st1b    {za0v.b[w12, 0]}, p6, [x12, x2]
 // CHECK-ENCODING: [0x80,0x99,0x22,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 22 e0 <unknown>
+// CHECK-UNKNOWN: e0229980 <unknown>
 
 st1b    {za0v.b[w14, 1]}, p2, [x1, x26]
 // CHECK-INST: st1b    {za0v.b[w14, 1]}, p2, [x1, x26]
 // CHECK-ENCODING: [0x21,0xc8,0x3a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 3a e0 <unknown>
+// CHECK-UNKNOWN: e03ac821 <unknown>
 
 st1b    {za0v.b[w12, 13]}, p2, [x22, x30]
 // CHECK-INST: st1b    {za0v.b[w12, 13]}, p2, [x22, x30]
 // CHECK-ENCODING: [0xcd,0x8a,0x3e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 3e e0 <unknown>
+// CHECK-UNKNOWN: e03e8acd <unknown>
 
 st1b    {za0v.b[w15, 2]}, p5, [x9, x1]
 // CHECK-INST: st1b    {za0v.b[w15, 2]}, p5, [x9, x1]
 // CHECK-ENCODING: [0x22,0xf5,0x21,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 21 e0 <unknown>
+// CHECK-UNKNOWN: e021f522 <unknown>
 
 st1b    {za0v.b[w13, 7]}, p2, [x12, x11]
 // CHECK-INST: st1b    {za0v.b[w13, 7]}, p2, [x12, x11]
 // CHECK-ENCODING: [0x87,0xa9,0x2b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 2b e0 <unknown>
+// CHECK-UNKNOWN: e02ba987 <unknown>
 
 st1b    za0v.b[w12, 0], p0, [x0, x0]
 // CHECK-INST: st1b    {za0v.b[w12, 0]}, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x80,0x20,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 20 e0 <unknown>
+// CHECK-UNKNOWN: e0208000 <unknown>
 
 st1b    za0v.b[w14, 5], p5, [x10, x21]
 // CHECK-INST: st1b    {za0v.b[w14, 5]}, p5, [x10, x21]
 // CHECK-ENCODING: [0x45,0xd5,0x35,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 35 e0 <unknown>
+// CHECK-UNKNOWN: e035d545 <unknown>
 
 st1b    za0v.b[w15, 7], p3, [x13, x8]
 // CHECK-INST: st1b    {za0v.b[w15, 7]}, p3, [x13, x8]
 // CHECK-ENCODING: [0xa7,0xed,0x28,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 28 e0 <unknown>
+// CHECK-UNKNOWN: e028eda7 <unknown>
 
 st1b    za0v.b[w15, 15], p7, [sp]
 // CHECK-INST: st1b    {za0v.b[w15, 15]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0xff,0x3f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 3f e0 <unknown>
+// CHECK-UNKNOWN: e03fffef <unknown>
 
 st1b    za0v.b[w12, 5], p3, [x17, x16]
 // CHECK-INST: st1b    {za0v.b[w12, 5]}, p3, [x17, x16]
 // CHECK-ENCODING: [0x25,0x8e,0x30,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 30 e0 <unknown>
+// CHECK-UNKNOWN: e0308e25 <unknown>
 
 st1b    za0v.b[w12, 1], p1, [x1, x30]
 // CHECK-INST: st1b    {za0v.b[w12, 1]}, p1, [x1, x30]
 // CHECK-ENCODING: [0x21,0x84,0x3e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 3e e0 <unknown>
+// CHECK-UNKNOWN: e03e8421 <unknown>
 
 st1b    za0v.b[w14, 8], p5, [x19, x20]
 // CHECK-INST: st1b    {za0v.b[w14, 8]}, p5, [x19, x20]
 // CHECK-ENCODING: [0x68,0xd6,0x34,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 34 e0 <unknown>
+// CHECK-UNKNOWN: e034d668 <unknown>
 
 st1b    za0v.b[w12, 0], p6, [x12, x2]
 // CHECK-INST: st1b    {za0v.b[w12, 0]}, p6, [x12, x2]
 // CHECK-ENCODING: [0x80,0x99,0x22,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 22 e0 <unknown>
+// CHECK-UNKNOWN: e0229980 <unknown>
 
 st1b    za0v.b[w14, 1], p2, [x1, x26]
 // CHECK-INST: st1b    {za0v.b[w14, 1]}, p2, [x1, x26]
 // CHECK-ENCODING: [0x21,0xc8,0x3a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 3a e0 <unknown>
+// CHECK-UNKNOWN: e03ac821 <unknown>
 
 st1b    za0v.b[w12, 13], p2, [x22, x30]
 // CHECK-INST: st1b    {za0v.b[w12, 13]}, p2, [x22, x30]
 // CHECK-ENCODING: [0xcd,0x8a,0x3e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 3e e0 <unknown>
+// CHECK-UNKNOWN: e03e8acd <unknown>
 
 st1b    za0v.b[w15, 2], p5, [x9, x1]
 // CHECK-INST: st1b    {za0v.b[w15, 2]}, p5, [x9, x1]
 // CHECK-ENCODING: [0x22,0xf5,0x21,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 21 e0 <unknown>
+// CHECK-UNKNOWN: e021f522 <unknown>
 
 st1b    za0v.b[w13, 7], p2, [x12, x11]
 // CHECK-INST: st1b    {za0v.b[w13, 7]}, p2, [x12, x11]
 // CHECK-ENCODING: [0x87,0xa9,0x2b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 2b e0 <unknown>
+// CHECK-UNKNOWN: e02ba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/st1d.s b/llvm/test/MC/AArch64/SME/st1d.s
index ab35cc2c0ff85..104b619528bb3 100644
--- a/llvm/test/MC/AArch64/SME/st1d.s
+++ b/llvm/test/MC/AArch64/SME/st1d.s
@@ -19,145 +19,145 @@ st1d    {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3]
 // CHECK-INST: st1d    {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x00,0xe0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 e0 e0 <unknown>
+// CHECK-UNKNOWN: e0e00000 <unknown>
 
 st1d    {za2h.d[w14, 1]}, p5, [x10, x21, lsl #3]
 // CHECK-INST: st1d    {za2h.d[w14, 1]}, p5, [x10, x21, lsl #3]
 // CHECK-ENCODING: [0x45,0x55,0xf5,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 f5 e0 <unknown>
+// CHECK-UNKNOWN: e0f55545 <unknown>
 
 st1d    {za3h.d[w15, 1]}, p3, [x13, x8, lsl #3]
 // CHECK-INST: st1d    {za3h.d[w15, 1]}, p3, [x13, x8, lsl #3]
 // CHECK-ENCODING: [0xa7,0x6d,0xe8,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d e8 e0 <unknown>
+// CHECK-UNKNOWN: e0e86da7 <unknown>
 
 st1d    {za7h.d[w15, 1]}, p7, [sp]
 // CHECK-INST: st1d    {za7h.d[w15, 1]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0xff,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f ff e0 <unknown>
+// CHECK-UNKNOWN: e0ff7fef <unknown>
 
 st1d    {za2h.d[w12, 1]}, p3, [x17, x16, lsl #3]
 // CHECK-INST: st1d    {za2h.d[w12, 1]}, p3, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0x0e,0xf0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e f0 e0 <unknown>
+// CHECK-UNKNOWN: e0f00e25 <unknown>
 
 st1d    {za0h.d[w12, 1]}, p1, [x1, x30, lsl #3]
 // CHECK-INST: st1d    {za0h.d[w12, 1]}, p1, [x1, x30, lsl #3]
 // CHECK-ENCODING: [0x21,0x04,0xfe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 fe e0 <unknown>
+// CHECK-UNKNOWN: e0fe0421 <unknown>
 
 st1d    {za4h.d[w14, 0]}, p5, [x19, x20, lsl #3]
 // CHECK-INST: st1d    {za4h.d[w14, 0]}, p5, [x19, x20, lsl #3]
 // CHECK-ENCODING: [0x68,0x56,0xf4,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 f4 e0 <unknown>
+// CHECK-UNKNOWN: e0f45668 <unknown>
 
 st1d    {za0h.d[w12, 0]}, p6, [x12, x2, lsl #3]
 // CHECK-INST: st1d    {za0h.d[w12, 0]}, p6, [x12, x2, lsl #3]
 // CHECK-ENCODING: [0x80,0x19,0xe2,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 e2 e0 <unknown>
+// CHECK-UNKNOWN: e0e21980 <unknown>
 
 st1d    {za0h.d[w14, 1]}, p2, [x1, x26, lsl #3]
 // CHECK-INST: st1d    {za0h.d[w14, 1]}, p2, [x1, x26, lsl #3]
 // CHECK-ENCODING: [0x21,0x48,0xfa,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 fa e0 <unknown>
+// CHECK-UNKNOWN: e0fa4821 <unknown>
 
 st1d    {za6h.d[w12, 1]}, p2, [x22, x30, lsl #3]
 // CHECK-INST: st1d    {za6h.d[w12, 1]}, p2, [x22, x30, lsl #3]
 // CHECK-ENCODING: [0xcd,0x0a,0xfe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a fe e0 <unknown>
+// CHECK-UNKNOWN: e0fe0acd <unknown>
 
 st1d    {za1h.d[w15, 0]}, p5, [x9, x1, lsl #3]
 // CHECK-INST: st1d    {za1h.d[w15, 0]}, p5, [x9, x1, lsl #3]
 // CHECK-ENCODING: [0x22,0x75,0xe1,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 e1 e0 <unknown>
+// CHECK-UNKNOWN: e0e17522 <unknown>
 
 st1d    {za3h.d[w13, 1]}, p2, [x12, x11, lsl #3]
 // CHECK-INST: st1d    {za3h.d[w13, 1]}, p2, [x12, x11, lsl #3]
 // CHECK-ENCODING: [0x87,0x29,0xeb,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 eb e0 <unknown>
+// CHECK-UNKNOWN: e0eb2987 <unknown>
 
 st1d    za0h.d[w12, 0], p0, [x0, x0, lsl #3]
 // CHECK-INST: st1d    {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x00,0xe0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 e0 e0 <unknown>
+// CHECK-UNKNOWN: e0e00000 <unknown>
 
 st1d    za2h.d[w14, 1], p5, [x10, x21, lsl #3]
 // CHECK-INST: st1d    {za2h.d[w14, 1]}, p5, [x10, x21, lsl #3]
 // CHECK-ENCODING: [0x45,0x55,0xf5,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 f5 e0 <unknown>
+// CHECK-UNKNOWN: e0f55545 <unknown>
 
 st1d    za3h.d[w15, 1], p3, [x13, x8, lsl #3]
 // CHECK-INST: st1d    {za3h.d[w15, 1]}, p3, [x13, x8, lsl #3]
 // CHECK-ENCODING: [0xa7,0x6d,0xe8,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d e8 e0 <unknown>
+// CHECK-UNKNOWN: e0e86da7 <unknown>
 
 st1d    za7h.d[w15, 1], p7, [sp]
 // CHECK-INST: st1d    {za7h.d[w15, 1]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0xff,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f ff e0 <unknown>
+// CHECK-UNKNOWN: e0ff7fef <unknown>
 
 st1d    za2h.d[w12, 1], p3, [x17, x16, lsl #3]
 // CHECK-INST: st1d    {za2h.d[w12, 1]}, p3, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0x0e,0xf0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e f0 e0 <unknown>
+// CHECK-UNKNOWN: e0f00e25 <unknown>
 
 st1d    za0h.d[w12, 1], p1, [x1, x30, lsl #3]
 // CHECK-INST: st1d    {za0h.d[w12, 1]}, p1, [x1, x30, lsl #3]
 // CHECK-ENCODING: [0x21,0x04,0xfe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 fe e0 <unknown>
+// CHECK-UNKNOWN: e0fe0421 <unknown>
 
 st1d    za4h.d[w14, 0], p5, [x19, x20, lsl #3]
 // CHECK-INST: st1d    {za4h.d[w14, 0]}, p5, [x19, x20, lsl #3]
 // CHECK-ENCODING: [0x68,0x56,0xf4,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 f4 e0 <unknown>
+// CHECK-UNKNOWN: e0f45668 <unknown>
 
 st1d    za0h.d[w12, 0], p6, [x12, x2, lsl #3]
 // CHECK-INST: st1d    {za0h.d[w12, 0]}, p6, [x12, x2, lsl #3]
 // CHECK-ENCODING: [0x80,0x19,0xe2,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 e2 e0 <unknown>
+// CHECK-UNKNOWN: e0e21980 <unknown>
 
 st1d    za0h.d[w14, 1], p2, [x1, x26, lsl #3]
 // CHECK-INST: st1d    {za0h.d[w14, 1]}, p2, [x1, x26, lsl #3]
 // CHECK-ENCODING: [0x21,0x48,0xfa,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 fa e0 <unknown>
+// CHECK-UNKNOWN: e0fa4821 <unknown>
 
 st1d    za6h.d[w12, 1], p2, [x22, x30, lsl #3]
 // CHECK-INST: st1d    {za6h.d[w12, 1]}, p2, [x22, x30, lsl #3]
 // CHECK-ENCODING: [0xcd,0x0a,0xfe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a fe e0 <unknown>
+// CHECK-UNKNOWN: e0fe0acd <unknown>
 
 st1d    za1h.d[w15, 0], p5, [x9, x1, lsl #3]
 // CHECK-INST: st1d    {za1h.d[w15, 0]}, p5, [x9, x1, lsl #3]
 // CHECK-ENCODING: [0x22,0x75,0xe1,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 e1 e0 <unknown>
+// CHECK-UNKNOWN: e0e17522 <unknown>
 
 st1d    za3h.d[w13, 1], p2, [x12, x11, lsl #3]
 // CHECK-INST: st1d    {za3h.d[w13, 1]}, p2, [x12, x11, lsl #3]
 // CHECK-ENCODING: [0x87,0x29,0xeb,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 eb e0 <unknown>
+// CHECK-UNKNOWN: e0eb2987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Vertical
@@ -166,142 +166,142 @@ st1d    {za0v.d[w12, 0]}, p0, [x0, x0, lsl #3]
 // CHECK-INST: st1d    {za0v.d[w12, 0]}, p0, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x80,0xe0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 e0 e0 <unknown>
+// CHECK-UNKNOWN: e0e08000 <unknown>
 
 st1d    {za2v.d[w14, 1]}, p5, [x10, x21, lsl #3]
 // CHECK-INST: st1d    {za2v.d[w14, 1]}, p5, [x10, x21, lsl #3]
 // CHECK-ENCODING: [0x45,0xd5,0xf5,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 f5 e0 <unknown>
+// CHECK-UNKNOWN: e0f5d545 <unknown>
 
 st1d    {za3v.d[w15, 1]}, p3, [x13, x8, lsl #3]
 // CHECK-INST: st1d    {za3v.d[w15, 1]}, p3, [x13, x8, lsl #3]
 // CHECK-ENCODING: [0xa7,0xed,0xe8,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed e8 e0 <unknown>
+// CHECK-UNKNOWN: e0e8eda7 <unknown>
 
 st1d    {za7v.d[w15, 1]}, p7, [sp]
 // CHECK-INST: st1d    {za7v.d[w15, 1]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0xff,0xff,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff ff e0 <unknown>
+// CHECK-UNKNOWN: e0ffffef <unknown>
 
 st1d    {za2v.d[w12, 1]}, p3, [x17, x16, lsl #3]
 // CHECK-INST: st1d    {za2v.d[w12, 1]}, p3, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0x8e,0xf0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e f0 e0 <unknown>
+// CHECK-UNKNOWN: e0f08e25 <unknown>
 
 st1d    {za0v.d[w12, 1]}, p1, [x1, x30, lsl #3]
 // CHECK-INST: st1d    {za0v.d[w12, 1]}, p1, [x1, x30, lsl #3]
 // CHECK-ENCODING: [0x21,0x84,0xfe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 fe e0 <unknown>
+// CHECK-UNKNOWN: e0fe8421 <unknown>
 
 st1d    {za4v.d[w14, 0]}, p5, [x19, x20, lsl #3]
 // CHECK-INST: st1d    {za4v.d[w14, 0]}, p5, [x19, x20, lsl #3]
 // CHECK-ENCODING: [0x68,0xd6,0xf4,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 f4 e0 <unknown>
+// CHECK-UNKNOWN: e0f4d668 <unknown>
 
 st1d    {za0v.d[w12, 0]}, p6, [x12, x2, lsl #3]
 // CHECK-INST: st1d    {za0v.d[w12, 0]}, p6, [x12, x2, lsl #3]
 // CHECK-ENCODING: [0x80,0x99,0xe2,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 e2 e0 <unknown>
+// CHECK-UNKNOWN: e0e29980 <unknown>
 
 st1d    {za0v.d[w14, 1]}, p2, [x1, x26, lsl #3]
 // CHECK-INST: st1d    {za0v.d[w14, 1]}, p2, [x1, x26, lsl #3]
 // CHECK-ENCODING: [0x21,0xc8,0xfa,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 fa e0 <unknown>
+// CHECK-UNKNOWN: e0fac821 <unknown>
 
 st1d    {za6v.d[w12, 1]}, p2, [x22, x30, lsl #3]
 // CHECK-INST: st1d    {za6v.d[w12, 1]}, p2, [x22, x30, lsl #3]
 // CHECK-ENCODING: [0xcd,0x8a,0xfe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a fe e0 <unknown>
+// CHECK-UNKNOWN: e0fe8acd <unknown>
 
 st1d    {za1v.d[w15, 0]}, p5, [x9, x1, lsl #3]
 // CHECK-INST: st1d    {za1v.d[w15, 0]}, p5, [x9, x1, lsl #3]
 // CHECK-ENCODING: [0x22,0xf5,0xe1,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 e1 e0 <unknown>
+// CHECK-UNKNOWN: e0e1f522 <unknown>
 
 st1d    {za3v.d[w13, 1]}, p2, [x12, x11, lsl #3]
 // CHECK-INST: st1d    {za3v.d[w13, 1]}, p2, [x12, x11, lsl #3]
 // CHECK-ENCODING: [0x87,0xa9,0xeb,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 eb e0 <unknown>
+// CHECK-UNKNOWN: e0eba987 <unknown>
 
 st1d    za0v.d[w12, 0], p0, [x0, x0, lsl #3]
 // CHECK-INST: st1d    {za0v.d[w12, 0]}, p0, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x80,0xe0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 e0 e0 <unknown>
+// CHECK-UNKNOWN: e0e08000 <unknown>
 
 st1d    za2v.d[w14, 1], p5, [x10, x21, lsl #3]
 // CHECK-INST: st1d    {za2v.d[w14, 1]}, p5, [x10, x21, lsl #3]
 // CHECK-ENCODING: [0x45,0xd5,0xf5,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 f5 e0 <unknown>
+// CHECK-UNKNOWN: e0f5d545 <unknown>
 
 st1d    za3v.d[w15, 1], p3, [x13, x8, lsl #3]
 // CHECK-INST: st1d    {za3v.d[w15, 1]}, p3, [x13, x8, lsl #3]
 // CHECK-ENCODING: [0xa7,0xed,0xe8,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed e8 e0 <unknown>
+// CHECK-UNKNOWN: e0e8eda7 <unknown>
 
 st1d    za7v.d[w15, 1], p7, [sp]
 // CHECK-INST: st1d    {za7v.d[w15, 1]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0xff,0xff,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff ff e0 <unknown>
+// CHECK-UNKNOWN: e0ffffef <unknown>
 
 st1d    za2v.d[w12, 1], p3, [x17, x16, lsl #3]
 // CHECK-INST: st1d    {za2v.d[w12, 1]}, p3, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0x8e,0xf0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e f0 e0 <unknown>
+// CHECK-UNKNOWN: e0f08e25 <unknown>
 
 st1d    za0v.d[w12, 1], p1, [x1, x30, lsl #3]
 // CHECK-INST: st1d    {za0v.d[w12, 1]}, p1, [x1, x30, lsl #3]
 // CHECK-ENCODING: [0x21,0x84,0xfe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 fe e0 <unknown>
+// CHECK-UNKNOWN: e0fe8421 <unknown>
 
 st1d    za4v.d[w14, 0], p5, [x19, x20, lsl #3]
 // CHECK-INST: st1d    {za4v.d[w14, 0]}, p5, [x19, x20, lsl #3]
 // CHECK-ENCODING: [0x68,0xd6,0xf4,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 f4 e0 <unknown>
+// CHECK-UNKNOWN: e0f4d668 <unknown>
 
 st1d    za0v.d[w12, 0], p6, [x12, x2, lsl #3]
 // CHECK-INST: st1d    {za0v.d[w12, 0]}, p6, [x12, x2, lsl #3]
 // CHECK-ENCODING: [0x80,0x99,0xe2,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 e2 e0 <unknown>
+// CHECK-UNKNOWN: e0e29980 <unknown>
 
 st1d    za0v.d[w14, 1], p2, [x1, x26, lsl #3]
 // CHECK-INST: st1d    {za0v.d[w14, 1]}, p2, [x1, x26, lsl #3]
 // CHECK-ENCODING: [0x21,0xc8,0xfa,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 fa e0 <unknown>
+// CHECK-UNKNOWN: e0fac821 <unknown>
 
 st1d    za6v.d[w12, 1], p2, [x22, x30, lsl #3]
 // CHECK-INST: st1d    {za6v.d[w12, 1]}, p2, [x22, x30, lsl #3]
 // CHECK-ENCODING: [0xcd,0x8a,0xfe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a fe e0 <unknown>
+// CHECK-UNKNOWN: e0fe8acd <unknown>
 
 st1d    za1v.d[w15, 0], p5, [x9, x1, lsl #3]
 // CHECK-INST: st1d    {za1v.d[w15, 0]}, p5, [x9, x1, lsl #3]
 // CHECK-ENCODING: [0x22,0xf5,0xe1,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 e1 e0 <unknown>
+// CHECK-UNKNOWN: e0e1f522 <unknown>
 
 st1d    za3v.d[w13, 1], p2, [x12, x11, lsl #3]
 // CHECK-INST: st1d    {za3v.d[w13, 1]}, p2, [x12, x11, lsl #3]
 // CHECK-ENCODING: [0x87,0xa9,0xeb,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 eb e0 <unknown>
+// CHECK-UNKNOWN: e0eba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/st1h.s b/llvm/test/MC/AArch64/SME/st1h.s
index d3cbbd867e67c..4586ba024c764 100644
--- a/llvm/test/MC/AArch64/SME/st1h.s
+++ b/llvm/test/MC/AArch64/SME/st1h.s
@@ -19,145 +19,145 @@ st1h    {za0h.h[w12, 0]}, p0, [x0, x0, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w12, 0]}, p0, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x00,0x60,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 60 e0 <unknown>
+// CHECK-UNKNOWN: e0600000 <unknown>
 
 st1h    {za0h.h[w14, 5]}, p5, [x10, x21, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w14, 5]}, p5, [x10, x21, lsl #1]
 // CHECK-ENCODING: [0x45,0x55,0x75,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 75 e0 <unknown>
+// CHECK-UNKNOWN: e0755545 <unknown>
 
 st1h    {za0h.h[w15, 7]}, p3, [x13, x8, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w15, 7]}, p3, [x13, x8, lsl #1]
 // CHECK-ENCODING: [0xa7,0x6d,0x68,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 68 e0 <unknown>
+// CHECK-UNKNOWN: e0686da7 <unknown>
 
 st1h    {za1h.h[w15, 7]}, p7, [sp]
 // CHECK-INST: st1h    {za1h.h[w15, 7]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0x7f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 7f e0 <unknown>
+// CHECK-UNKNOWN: e07f7fef <unknown>
 
 st1h    {za0h.h[w12, 5]}, p3, [x17, x16, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w12, 5]}, p3, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x0e,0x70,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 70 e0 <unknown>
+// CHECK-UNKNOWN: e0700e25 <unknown>
 
 st1h    {za0h.h[w12, 1]}, p1, [x1, x30, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w12, 1]}, p1, [x1, x30, lsl #1]
 // CHECK-ENCODING: [0x21,0x04,0x7e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 7e e0 <unknown>
+// CHECK-UNKNOWN: e07e0421 <unknown>
 
 st1h    {za1h.h[w14, 0]}, p5, [x19, x20, lsl #1]
 // CHECK-INST: st1h    {za1h.h[w14, 0]}, p5, [x19, x20, lsl #1]
 // CHECK-ENCODING: [0x68,0x56,0x74,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 74 e0 <unknown>
+// CHECK-UNKNOWN: e0745668 <unknown>
 
 st1h    {za0h.h[w12, 0]}, p6, [x12, x2, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w12, 0]}, p6, [x12, x2, lsl #1]
 // CHECK-ENCODING: [0x80,0x19,0x62,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 62 e0 <unknown>
+// CHECK-UNKNOWN: e0621980 <unknown>
 
 st1h    {za0h.h[w14, 1]}, p2, [x1, x26, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w14, 1]}, p2, [x1, x26, lsl #1]
 // CHECK-ENCODING: [0x21,0x48,0x7a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 7a e0 <unknown>
+// CHECK-UNKNOWN: e07a4821 <unknown>
 
 st1h    {za1h.h[w12, 5]}, p2, [x22, x30, lsl #1]
 // CHECK-INST: st1h    {za1h.h[w12, 5]}, p2, [x22, x30, lsl #1]
 // CHECK-ENCODING: [0xcd,0x0a,0x7e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 7e e0 <unknown>
+// CHECK-UNKNOWN: e07e0acd <unknown>
 
 st1h    {za0h.h[w15, 2]}, p5, [x9, x1, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w15, 2]}, p5, [x9, x1, lsl #1]
 // CHECK-ENCODING: [0x22,0x75,0x61,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 61 e0 <unknown>
+// CHECK-UNKNOWN: e0617522 <unknown>
 
 st1h    {za0h.h[w13, 7]}, p2, [x12, x11, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w13, 7]}, p2, [x12, x11, lsl #1]
 // CHECK-ENCODING: [0x87,0x29,0x6b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 6b e0 <unknown>
+// CHECK-UNKNOWN: e06b2987 <unknown>
 
 st1h    za0h.h[w12, 0], p0, [x0, x0, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w12, 0]}, p0, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x00,0x60,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 60 e0 <unknown>
+// CHECK-UNKNOWN: e0600000 <unknown>
 
 st1h    za0h.h[w14, 5], p5, [x10, x21, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w14, 5]}, p5, [x10, x21, lsl #1]
 // CHECK-ENCODING: [0x45,0x55,0x75,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 75 e0 <unknown>
+// CHECK-UNKNOWN: e0755545 <unknown>
 
 st1h    za0h.h[w15, 7], p3, [x13, x8, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w15, 7]}, p3, [x13, x8, lsl #1]
 // CHECK-ENCODING: [0xa7,0x6d,0x68,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d 68 e0 <unknown>
+// CHECK-UNKNOWN: e0686da7 <unknown>
 
 st1h    za1h.h[w15, 7], p7, [sp]
 // CHECK-INST: st1h    {za1h.h[w15, 7]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0x7f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f 7f e0 <unknown>
+// CHECK-UNKNOWN: e07f7fef <unknown>
 
 st1h    za0h.h[w12, 5], p3, [x17, x16, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w12, 5]}, p3, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x0e,0x70,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e 70 e0 <unknown>
+// CHECK-UNKNOWN: e0700e25 <unknown>
 
 st1h    za0h.h[w12, 1], p1, [x1, x30, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w12, 1]}, p1, [x1, x30, lsl #1]
 // CHECK-ENCODING: [0x21,0x04,0x7e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 7e e0 <unknown>
+// CHECK-UNKNOWN: e07e0421 <unknown>
 
 st1h    za1h.h[w14, 0], p5, [x19, x20, lsl #1]
 // CHECK-INST: st1h    {za1h.h[w14, 0]}, p5, [x19, x20, lsl #1]
 // CHECK-ENCODING: [0x68,0x56,0x74,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 74 e0 <unknown>
+// CHECK-UNKNOWN: e0745668 <unknown>
 
 st1h    za0h.h[w12, 0], p6, [x12, x2, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w12, 0]}, p6, [x12, x2, lsl #1]
 // CHECK-ENCODING: [0x80,0x19,0x62,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 62 e0 <unknown>
+// CHECK-UNKNOWN: e0621980 <unknown>
 
 st1h    za0h.h[w14, 1], p2, [x1, x26, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w14, 1]}, p2, [x1, x26, lsl #1]
 // CHECK-ENCODING: [0x21,0x48,0x7a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 7a e0 <unknown>
+// CHECK-UNKNOWN: e07a4821 <unknown>
 
 st1h    za1h.h[w12, 5], p2, [x22, x30, lsl #1]
 // CHECK-INST: st1h    {za1h.h[w12, 5]}, p2, [x22, x30, lsl #1]
 // CHECK-ENCODING: [0xcd,0x0a,0x7e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a 7e e0 <unknown>
+// CHECK-UNKNOWN: e07e0acd <unknown>
 
 st1h    za0h.h[w15, 2], p5, [x9, x1, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w15, 2]}, p5, [x9, x1, lsl #1]
 // CHECK-ENCODING: [0x22,0x75,0x61,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 61 e0 <unknown>
+// CHECK-UNKNOWN: e0617522 <unknown>
 
 st1h    za0h.h[w13, 7], p2, [x12, x11, lsl #1]
 // CHECK-INST: st1h    {za0h.h[w13, 7]}, p2, [x12, x11, lsl #1]
 // CHECK-ENCODING: [0x87,0x29,0x6b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 6b e0 <unknown>
+// CHECK-UNKNOWN: e06b2987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Vertical
@@ -166,142 +166,142 @@ st1h    {za0v.h[w12, 0]}, p0, [x0, x0, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w12, 0]}, p0, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x80,0x60,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 60 e0 <unknown>
+// CHECK-UNKNOWN: e0608000 <unknown>
 
 st1h    {za0v.h[w14, 5]}, p5, [x10, x21, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w14, 5]}, p5, [x10, x21, lsl #1]
 // CHECK-ENCODING: [0x45,0xd5,0x75,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 75 e0 <unknown>
+// CHECK-UNKNOWN: e075d545 <unknown>
 
 st1h    {za0v.h[w15, 7]}, p3, [x13, x8, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w15, 7]}, p3, [x13, x8, lsl #1]
 // CHECK-ENCODING: [0xa7,0xed,0x68,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 68 e0 <unknown>
+// CHECK-UNKNOWN: e068eda7 <unknown>
 
 st1h    {za1v.h[w15, 7]}, p7, [sp]
 // CHECK-INST: st1h    {za1v.h[w15, 7]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0xff,0x7f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 7f e0 <unknown>
+// CHECK-UNKNOWN: e07fffef <unknown>
 
 st1h    {za0v.h[w12, 5]}, p3, [x17, x16, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w12, 5]}, p3, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x8e,0x70,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 70 e0 <unknown>
+// CHECK-UNKNOWN: e0708e25 <unknown>
 
 st1h    {za0v.h[w12, 1]}, p1, [x1, x30, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w12, 1]}, p1, [x1, x30, lsl #1]
 // CHECK-ENCODING: [0x21,0x84,0x7e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 7e e0 <unknown>
+// CHECK-UNKNOWN: e07e8421 <unknown>
 
 st1h    {za1v.h[w14, 0]}, p5, [x19, x20, lsl #1]
 // CHECK-INST: st1h    {za1v.h[w14, 0]}, p5, [x19, x20, lsl #1]
 // CHECK-ENCODING: [0x68,0xd6,0x74,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 74 e0 <unknown>
+// CHECK-UNKNOWN: e074d668 <unknown>
 
 st1h    {za0v.h[w12, 0]}, p6, [x12, x2, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w12, 0]}, p6, [x12, x2, lsl #1]
 // CHECK-ENCODING: [0x80,0x99,0x62,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 62 e0 <unknown>
+// CHECK-UNKNOWN: e0629980 <unknown>
 
 st1h    {za0v.h[w14, 1]}, p2, [x1, x26, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w14, 1]}, p2, [x1, x26, lsl #1]
 // CHECK-ENCODING: [0x21,0xc8,0x7a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 7a e0 <unknown>
+// CHECK-UNKNOWN: e07ac821 <unknown>
 
 st1h    {za1v.h[w12, 5]}, p2, [x22, x30, lsl #1]
 // CHECK-INST: st1h    {za1v.h[w12, 5]}, p2, [x22, x30, lsl #1]
 // CHECK-ENCODING: [0xcd,0x8a,0x7e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 7e e0 <unknown>
+// CHECK-UNKNOWN: e07e8acd <unknown>
 
 st1h    {za0v.h[w15, 2]}, p5, [x9, x1, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w15, 2]}, p5, [x9, x1, lsl #1]
 // CHECK-ENCODING: [0x22,0xf5,0x61,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 61 e0 <unknown>
+// CHECK-UNKNOWN: e061f522 <unknown>
 
 st1h    {za0v.h[w13, 7]}, p2, [x12, x11, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w13, 7]}, p2, [x12, x11, lsl #1]
 // CHECK-ENCODING: [0x87,0xa9,0x6b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 6b e0 <unknown>
+// CHECK-UNKNOWN: e06ba987 <unknown>
 
 st1h    za0v.h[w12, 0], p0, [x0, x0, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w12, 0]}, p0, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x80,0x60,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 60 e0 <unknown>
+// CHECK-UNKNOWN: e0608000 <unknown>
 
 st1h    za0v.h[w14, 5], p5, [x10, x21, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w14, 5]}, p5, [x10, x21, lsl #1]
 // CHECK-ENCODING: [0x45,0xd5,0x75,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 75 e0 <unknown>
+// CHECK-UNKNOWN: e075d545 <unknown>
 
 st1h    za0v.h[w15, 7], p3, [x13, x8, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w15, 7]}, p3, [x13, x8, lsl #1]
 // CHECK-ENCODING: [0xa7,0xed,0x68,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed 68 e0 <unknown>
+// CHECK-UNKNOWN: e068eda7 <unknown>
 
 st1h    za1v.h[w15, 7], p7, [sp]
 // CHECK-INST: st1h    {za1v.h[w15, 7]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0xff,0x7f,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff 7f e0 <unknown>
+// CHECK-UNKNOWN: e07fffef <unknown>
 
 st1h    za0v.h[w12, 5], p3, [x17, x16, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w12, 5]}, p3, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x8e,0x70,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e 70 e0 <unknown>
+// CHECK-UNKNOWN: e0708e25 <unknown>
 
 st1h    za0v.h[w12, 1], p1, [x1, x30, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w12, 1]}, p1, [x1, x30, lsl #1]
 // CHECK-ENCODING: [0x21,0x84,0x7e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 7e e0 <unknown>
+// CHECK-UNKNOWN: e07e8421 <unknown>
 
 st1h    za1v.h[w14, 0], p5, [x19, x20, lsl #1]
 // CHECK-INST: st1h    {za1v.h[w14, 0]}, p5, [x19, x20, lsl #1]
 // CHECK-ENCODING: [0x68,0xd6,0x74,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 74 e0 <unknown>
+// CHECK-UNKNOWN: e074d668 <unknown>
 
 st1h    za0v.h[w12, 0], p6, [x12, x2, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w12, 0]}, p6, [x12, x2, lsl #1]
 // CHECK-ENCODING: [0x80,0x99,0x62,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 62 e0 <unknown>
+// CHECK-UNKNOWN: e0629980 <unknown>
 
 st1h    za0v.h[w14, 1], p2, [x1, x26, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w14, 1]}, p2, [x1, x26, lsl #1]
 // CHECK-ENCODING: [0x21,0xc8,0x7a,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 7a e0 <unknown>
+// CHECK-UNKNOWN: e07ac821 <unknown>
 
 st1h    za1v.h[w12, 5], p2, [x22, x30, lsl #1]
 // CHECK-INST: st1h    {za1v.h[w12, 5]}, p2, [x22, x30, lsl #1]
 // CHECK-ENCODING: [0xcd,0x8a,0x7e,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a 7e e0 <unknown>
+// CHECK-UNKNOWN: e07e8acd <unknown>
 
 st1h    za0v.h[w15, 2], p5, [x9, x1, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w15, 2]}, p5, [x9, x1, lsl #1]
 // CHECK-ENCODING: [0x22,0xf5,0x61,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 61 e0 <unknown>
+// CHECK-UNKNOWN: e061f522 <unknown>
 
 st1h    za0v.h[w13, 7], p2, [x12, x11, lsl #1]
 // CHECK-INST: st1h    {za0v.h[w13, 7]}, p2, [x12, x11, lsl #1]
 // CHECK-ENCODING: [0x87,0xa9,0x6b,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 6b e0 <unknown>
+// CHECK-UNKNOWN: e06ba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/st1q.s b/llvm/test/MC/AArch64/SME/st1q.s
index 1df89f1324802..90e648f749dc7 100644
--- a/llvm/test/MC/AArch64/SME/st1q.s
+++ b/llvm/test/MC/AArch64/SME/st1q.s
@@ -19,145 +19,145 @@ st1q    {za0h.q[w12, 0]}, p0, [x0, x0, lsl #4]
 // CHECK-INST: st1q    {za0h.q[w12, 0]}, p0, [x0, x0, lsl #4]
 // CHECK-ENCODING: [0x00,0x00,0xe0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 e0 e1 <unknown>
+// CHECK-UNKNOWN: e1e00000 <unknown>
 
 st1q    {za5h.q[w14, 0]}, p5, [x10, x21, lsl #4]
 // CHECK-INST: st1q    {za5h.q[w14, 0]}, p5, [x10, x21, lsl #4]
 // CHECK-ENCODING: [0x45,0x55,0xf5,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 f5 e1 <unknown>
+// CHECK-UNKNOWN: e1f55545 <unknown>
 
 st1q    {za7h.q[w15, 0]}, p3, [x13, x8, lsl #4]
 // CHECK-INST: st1q    {za7h.q[w15, 0]}, p3, [x13, x8, lsl #4]
 // CHECK-ENCODING: [0xa7,0x6d,0xe8,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d e8 e1 <unknown>
+// CHECK-UNKNOWN: e1e86da7 <unknown>
 
 st1q    {za15h.q[w15, 0]}, p7, [sp]
 // CHECK-INST: st1q    {za15h.q[w15, 0]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0xff,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f ff e1 <unknown>
+// CHECK-UNKNOWN: e1ff7fef <unknown>
 
 st1q    {za5h.q[w12, 0]}, p3, [x17, x16, lsl #4]
 // CHECK-INST: st1q    {za5h.q[w12, 0]}, p3, [x17, x16, lsl #4]
 // CHECK-ENCODING: [0x25,0x0e,0xf0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e f0 e1 <unknown>
+// CHECK-UNKNOWN: e1f00e25 <unknown>
 
 st1q    {za1h.q[w12, 0]}, p1, [x1, x30, lsl #4]
 // CHECK-INST: st1q    {za1h.q[w12, 0]}, p1, [x1, x30, lsl #4]
 // CHECK-ENCODING: [0x21,0x04,0xfe,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 fe e1 <unknown>
+// CHECK-UNKNOWN: e1fe0421 <unknown>
 
 st1q    {za8h.q[w14, 0]}, p5, [x19, x20, lsl #4]
 // CHECK-INST: st1q    {za8h.q[w14, 0]}, p5, [x19, x20, lsl #4]
 // CHECK-ENCODING: [0x68,0x56,0xf4,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 f4 e1 <unknown>
+// CHECK-UNKNOWN: e1f45668 <unknown>
 
 st1q    {za0h.q[w12, 0]}, p6, [x12, x2, lsl #4]
 // CHECK-INST: st1q    {za0h.q[w12, 0]}, p6, [x12, x2, lsl #4]
 // CHECK-ENCODING: [0x80,0x19,0xe2,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 e2 e1 <unknown>
+// CHECK-UNKNOWN: e1e21980 <unknown>
 
 st1q    {za1h.q[w14, 0]}, p2, [x1, x26, lsl #4]
 // CHECK-INST: st1q    {za1h.q[w14, 0]}, p2, [x1, x26, lsl #4]
 // CHECK-ENCODING: [0x21,0x48,0xfa,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 fa e1 <unknown>
+// CHECK-UNKNOWN: e1fa4821 <unknown>
 
 st1q    {za13h.q[w12, 0]}, p2, [x22, x30, lsl #4]
 // CHECK-INST: st1q    {za13h.q[w12, 0]}, p2, [x22, x30, lsl #4]
 // CHECK-ENCODING: [0xcd,0x0a,0xfe,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a fe e1 <unknown>
+// CHECK-UNKNOWN: e1fe0acd <unknown>
 
 st1q    {za2h.q[w15, 0]}, p5, [x9, x1, lsl #4]
 // CHECK-INST: st1q    {za2h.q[w15, 0]}, p5, [x9, x1, lsl #4]
 // CHECK-ENCODING: [0x22,0x75,0xe1,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 e1 e1 <unknown>
+// CHECK-UNKNOWN: e1e17522 <unknown>
 
 st1q    {za7h.q[w13, 0]}, p2, [x12, x11, lsl #4]
 // CHECK-INST: st1q    {za7h.q[w13, 0]}, p2, [x12, x11, lsl #4]
 // CHECK-ENCODING: [0x87,0x29,0xeb,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 eb e1 <unknown>
+// CHECK-UNKNOWN: e1eb2987 <unknown>
 
 st1q    za0h.q[w12, 0], p0, [x0, x0, lsl #4]
 // CHECK-INST: st1q    {za0h.q[w12, 0]}, p0, [x0, x0, lsl #4]
 // CHECK-ENCODING: [0x00,0x00,0xe0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 e0 e1 <unknown>
+// CHECK-UNKNOWN: e1e00000 <unknown>
 
 st1q    za5h.q[w14, 0], p5, [x10, x21, lsl #4]
 // CHECK-INST: st1q    {za5h.q[w14, 0]}, p5, [x10, x21, lsl #4]
 // CHECK-ENCODING: [0x45,0x55,0xf5,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 f5 e1 <unknown>
+// CHECK-UNKNOWN: e1f55545 <unknown>
 
 st1q    za7h.q[w15, 0], p3, [x13, x8, lsl #4]
 // CHECK-INST: st1q    {za7h.q[w15, 0]}, p3, [x13, x8, lsl #4]
 // CHECK-ENCODING: [0xa7,0x6d,0xe8,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d e8 e1 <unknown>
+// CHECK-UNKNOWN: e1e86da7 <unknown>
 
 st1q    za15h.q[w15, 0], p7, [sp]
 // CHECK-INST: st1q    {za15h.q[w15, 0]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0xff,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f ff e1 <unknown>
+// CHECK-UNKNOWN: e1ff7fef <unknown>
 
 st1q    za5h.q[w12, 0], p3, [x17, x16, lsl #4]
 // CHECK-INST: st1q    {za5h.q[w12, 0]}, p3, [x17, x16, lsl #4]
 // CHECK-ENCODING: [0x25,0x0e,0xf0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e f0 e1 <unknown>
+// CHECK-UNKNOWN: e1f00e25 <unknown>
 
 st1q    za1h.q[w12, 0], p1, [x1, x30, lsl #4]
 // CHECK-INST: st1q    {za1h.q[w12, 0]}, p1, [x1, x30, lsl #4]
 // CHECK-ENCODING: [0x21,0x04,0xfe,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 fe e1 <unknown>
+// CHECK-UNKNOWN: e1fe0421 <unknown>
 
 st1q    za8h.q[w14, 0], p5, [x19, x20, lsl #4]
 // CHECK-INST: st1q    {za8h.q[w14, 0]}, p5, [x19, x20, lsl #4]
 // CHECK-ENCODING: [0x68,0x56,0xf4,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 f4 e1 <unknown>
+// CHECK-UNKNOWN: e1f45668 <unknown>
 
 st1q    za0h.q[w12, 0], p6, [x12, x2, lsl #4]
 // CHECK-INST: st1q    {za0h.q[w12, 0]}, p6, [x12, x2, lsl #4]
 // CHECK-ENCODING: [0x80,0x19,0xe2,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 e2 e1 <unknown>
+// CHECK-UNKNOWN: e1e21980 <unknown>
 
 st1q    za1h.q[w14, 0], p2, [x1, x26, lsl #4]
 // CHECK-INST: st1q    {za1h.q[w14, 0]}, p2, [x1, x26, lsl #4]
 // CHECK-ENCODING: [0x21,0x48,0xfa,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 fa e1 <unknown>
+// CHECK-UNKNOWN: e1fa4821 <unknown>
 
 st1q    za13h.q[w12, 0], p2, [x22, x30, lsl #4]
 // CHECK-INST: st1q    {za13h.q[w12, 0]}, p2, [x22, x30, lsl #4]
 // CHECK-ENCODING: [0xcd,0x0a,0xfe,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a fe e1 <unknown>
+// CHECK-UNKNOWN: e1fe0acd <unknown>
 
 st1q    za2h.q[w15, 0], p5, [x9, x1, lsl #4]
 // CHECK-INST: st1q    {za2h.q[w15, 0]}, p5, [x9, x1, lsl #4]
 // CHECK-ENCODING: [0x22,0x75,0xe1,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 e1 e1 <unknown>
+// CHECK-UNKNOWN: e1e17522 <unknown>
 
 st1q    za7h.q[w13, 0], p2, [x12, x11, lsl #4]
 // CHECK-INST: st1q    {za7h.q[w13, 0]}, p2, [x12, x11, lsl #4]
 // CHECK-ENCODING: [0x87,0x29,0xeb,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 eb e1 <unknown>
+// CHECK-UNKNOWN: e1eb2987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Vertical
@@ -166,142 +166,142 @@ st1q    {za0v.q[w12, 0]}, p0, [x0, x0, lsl #4]
 // CHECK-INST: st1q    {za0v.q[w12, 0]}, p0, [x0, x0, lsl #4]
 // CHECK-ENCODING: [0x00,0x80,0xe0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 e0 e1 <unknown>
+// CHECK-UNKNOWN: e1e08000 <unknown>
 
 st1q    {za5v.q[w14, 0]}, p5, [x10, x21, lsl #4]
 // CHECK-INST: st1q    {za5v.q[w14, 0]}, p5, [x10, x21, lsl #4]
 // CHECK-ENCODING: [0x45,0xd5,0xf5,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 f5 e1 <unknown>
+// CHECK-UNKNOWN: e1f5d545 <unknown>
 
 st1q    {za7v.q[w15, 0]}, p3, [x13, x8, lsl #4]
 // CHECK-INST: st1q    {za7v.q[w15, 0]}, p3, [x13, x8, lsl #4]
 // CHECK-ENCODING: [0xa7,0xed,0xe8,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed e8 e1 <unknown>
+// CHECK-UNKNOWN: e1e8eda7 <unknown>
 
 st1q    {za15v.q[w15, 0]}, p7, [sp]
 // CHECK-INST: st1q    {za15v.q[w15, 0]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0xff,0xff,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff ff e1 <unknown>
+// CHECK-UNKNOWN: e1ffffef <unknown>
 
 st1q    {za5v.q[w12, 0]}, p3, [x17, x16, lsl #4]
 // CHECK-INST: st1q    {za5v.q[w12, 0]}, p3, [x17, x16, lsl #4]
 // CHECK-ENCODING: [0x25,0x8e,0xf0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e f0 e1 <unknown>
+// CHECK-UNKNOWN: e1f08e25 <unknown>
 
 st1q    {za1v.q[w12, 0]}, p1, [x1, x30, lsl #4]
 // CHECK-INST: st1q    {za1v.q[w12, 0]}, p1, [x1, x30, lsl #4]
 // CHECK-ENCODING: [0x21,0x84,0xfe,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 fe e1 <unknown>
+// CHECK-UNKNOWN: e1fe8421 <unknown>
 
 st1q    {za8v.q[w14, 0]}, p5, [x19, x20, lsl #4]
 // CHECK-INST: st1q    {za8v.q[w14, 0]}, p5, [x19, x20, lsl #4]
 // CHECK-ENCODING: [0x68,0xd6,0xf4,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 f4 e1 <unknown>
+// CHECK-UNKNOWN: e1f4d668 <unknown>
 
 st1q    {za0v.q[w12, 0]}, p6, [x12, x2, lsl #4]
 // CHECK-INST: st1q    {za0v.q[w12, 0]}, p6, [x12, x2, lsl #4]
 // CHECK-ENCODING: [0x80,0x99,0xe2,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 e2 e1 <unknown>
+// CHECK-UNKNOWN: e1e29980 <unknown>
 
 st1q    {za1v.q[w14, 0]}, p2, [x1, x26, lsl #4]
 // CHECK-INST: st1q    {za1v.q[w14, 0]}, p2, [x1, x26, lsl #4]
 // CHECK-ENCODING: [0x21,0xc8,0xfa,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 fa e1 <unknown>
+// CHECK-UNKNOWN: e1fac821 <unknown>
 
 st1q    {za13v.q[w12, 0]}, p2, [x22, x30, lsl #4]
 // CHECK-INST: st1q    {za13v.q[w12, 0]}, p2, [x22, x30, lsl #4]
 // CHECK-ENCODING: [0xcd,0x8a,0xfe,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a fe e1 <unknown>
+// CHECK-UNKNOWN: e1fe8acd <unknown>
 
 st1q    {za2v.q[w15, 0]}, p5, [x9, x1, lsl #4]
 // CHECK-INST: st1q    {za2v.q[w15, 0]}, p5, [x9, x1, lsl #4]
 // CHECK-ENCODING: [0x22,0xf5,0xe1,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 e1 e1 <unknown>
+// CHECK-UNKNOWN: e1e1f522 <unknown>
 
 st1q    {za7v.q[w13, 0]}, p2, [x12, x11, lsl #4]
 // CHECK-INST: st1q    {za7v.q[w13, 0]}, p2, [x12, x11, lsl #4]
 // CHECK-ENCODING: [0x87,0xa9,0xeb,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 eb e1 <unknown>
+// CHECK-UNKNOWN: e1eba987 <unknown>
 
 st1q    za0v.q[w12, 0], p0, [x0, x0, lsl #4]
 // CHECK-INST: st1q    {za0v.q[w12, 0]}, p0, [x0, x0, lsl #4]
 // CHECK-ENCODING: [0x00,0x80,0xe0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 e0 e1 <unknown>
+// CHECK-UNKNOWN: e1e08000 <unknown>
 
 st1q    za5v.q[w14, 0], p5, [x10, x21, lsl #4]
 // CHECK-INST: st1q    {za5v.q[w14, 0]}, p5, [x10, x21, lsl #4]
 // CHECK-ENCODING: [0x45,0xd5,0xf5,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 f5 e1 <unknown>
+// CHECK-UNKNOWN: e1f5d545 <unknown>
 
 st1q    za7v.q[w15, 0], p3, [x13, x8, lsl #4]
 // CHECK-INST: st1q    {za7v.q[w15, 0]}, p3, [x13, x8, lsl #4]
 // CHECK-ENCODING: [0xa7,0xed,0xe8,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed e8 e1 <unknown>
+// CHECK-UNKNOWN: e1e8eda7 <unknown>
 
 st1q    za15v.q[w15, 0], p7, [sp]
 // CHECK-INST: st1q    {za15v.q[w15, 0]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0xff,0xff,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff ff e1 <unknown>
+// CHECK-UNKNOWN: e1ffffef <unknown>
 
 st1q    za5v.q[w12, 0], p3, [x17, x16, lsl #4]
 // CHECK-INST: st1q    {za5v.q[w12, 0]}, p3, [x17, x16, lsl #4]
 // CHECK-ENCODING: [0x25,0x8e,0xf0,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e f0 e1 <unknown>
+// CHECK-UNKNOWN: e1f08e25 <unknown>
 
 st1q    za1v.q[w12, 0], p1, [x1, x30, lsl #4]
 // CHECK-INST: st1q    {za1v.q[w12, 0]}, p1, [x1, x30, lsl #4]
 // CHECK-ENCODING: [0x21,0x84,0xfe,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 fe e1 <unknown>
+// CHECK-UNKNOWN: e1fe8421 <unknown>
 
 st1q    za8v.q[w14, 0], p5, [x19, x20, lsl #4]
 // CHECK-INST: st1q    {za8v.q[w14, 0]}, p5, [x19, x20, lsl #4]
 // CHECK-ENCODING: [0x68,0xd6,0xf4,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 f4 e1 <unknown>
+// CHECK-UNKNOWN: e1f4d668 <unknown>
 
 st1q    za0v.q[w12, 0], p6, [x12, x2, lsl #4]
 // CHECK-INST: st1q    {za0v.q[w12, 0]}, p6, [x12, x2, lsl #4]
 // CHECK-ENCODING: [0x80,0x99,0xe2,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 e2 e1 <unknown>
+// CHECK-UNKNOWN: e1e29980 <unknown>
 
 st1q    za1v.q[w14, 0], p2, [x1, x26, lsl #4]
 // CHECK-INST: st1q    {za1v.q[w14, 0]}, p2, [x1, x26, lsl #4]
 // CHECK-ENCODING: [0x21,0xc8,0xfa,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 fa e1 <unknown>
+// CHECK-UNKNOWN: e1fac821 <unknown>
 
 st1q    za13v.q[w12, 0], p2, [x22, x30, lsl #4]
 // CHECK-INST: st1q    {za13v.q[w12, 0]}, p2, [x22, x30, lsl #4]
 // CHECK-ENCODING: [0xcd,0x8a,0xfe,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a fe e1 <unknown>
+// CHECK-UNKNOWN: e1fe8acd <unknown>
 
 st1q    za2v.q[w15, 0], p5, [x9, x1, lsl #4]
 // CHECK-INST: st1q    {za2v.q[w15, 0]}, p5, [x9, x1, lsl #4]
 // CHECK-ENCODING: [0x22,0xf5,0xe1,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 e1 e1 <unknown>
+// CHECK-UNKNOWN: e1e1f522 <unknown>
 
 st1q    za7v.q[w13, 0], p2, [x12, x11, lsl #4]
 // CHECK-INST: st1q    {za7v.q[w13, 0]}, p2, [x12, x11, lsl #4]
 // CHECK-ENCODING: [0x87,0xa9,0xeb,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 eb e1 <unknown>
+// CHECK-UNKNOWN: e1eba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/st1w.s b/llvm/test/MC/AArch64/SME/st1w.s
index 88ce4679689d5..40a9c83baadb2 100644
--- a/llvm/test/MC/AArch64/SME/st1w.s
+++ b/llvm/test/MC/AArch64/SME/st1w.s
@@ -19,145 +19,145 @@ st1w    {za0h.s[w12, 0]}, p0, [x0, x0, lsl #2]
 // CHECK-INST: st1w    {za0h.s[w12, 0]}, p0, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x00,0xa0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 a0 e0 <unknown>
+// CHECK-UNKNOWN: e0a00000 <unknown>
 
 st1w    {za1h.s[w14, 1]}, p5, [x10, x21, lsl #2]
 // CHECK-INST: st1w    {za1h.s[w14, 1]}, p5, [x10, x21, lsl #2]
 // CHECK-ENCODING: [0x45,0x55,0xb5,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 b5 e0 <unknown>
+// CHECK-UNKNOWN: e0b55545 <unknown>
 
 st1w    {za1h.s[w15, 3]}, p3, [x13, x8, lsl #2]
 // CHECK-INST: st1w    {za1h.s[w15, 3]}, p3, [x13, x8, lsl #2]
 // CHECK-ENCODING: [0xa7,0x6d,0xa8,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d a8 e0 <unknown>
+// CHECK-UNKNOWN: e0a86da7 <unknown>
 
 st1w    {za3h.s[w15, 3]}, p7, [sp]
 // CHECK-INST: st1w    {za3h.s[w15, 3]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0xbf,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f bf e0 <unknown>
+// CHECK-UNKNOWN: e0bf7fef <unknown>
 
 st1w    {za1h.s[w12, 1]}, p3, [x17, x16, lsl #2]
 // CHECK-INST: st1w    {za1h.s[w12, 1]}, p3, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0x0e,0xb0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e b0 e0 <unknown>
+// CHECK-UNKNOWN: e0b00e25 <unknown>
 
 st1w    {za0h.s[w12, 1]}, p1, [x1, x30, lsl #2]
 // CHECK-INST: st1w    {za0h.s[w12, 1]}, p1, [x1, x30, lsl #2]
 // CHECK-ENCODING: [0x21,0x04,0xbe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 be e0 <unknown>
+// CHECK-UNKNOWN: e0be0421 <unknown>
 
 st1w    {za2h.s[w14, 0]}, p5, [x19, x20, lsl #2]
 // CHECK-INST: st1w    {za2h.s[w14, 0]}, p5, [x19, x20, lsl #2]
 // CHECK-ENCODING: [0x68,0x56,0xb4,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 b4 e0 <unknown>
+// CHECK-UNKNOWN: e0b45668 <unknown>
 
 st1w    {za0h.s[w12, 0]}, p6, [x12, x2, lsl #2]
 // CHECK-INST: st1w    {za0h.s[w12, 0]}, p6, [x12, x2, lsl #2]
 // CHECK-ENCODING: [0x80,0x19,0xa2,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 a2 e0 <unknown>
+// CHECK-UNKNOWN: e0a21980 <unknown>
 
 st1w    {za0h.s[w14, 1]}, p2, [x1, x26, lsl #2]
 // CHECK-INST: st1w    {za0h.s[w14, 1]}, p2, [x1, x26, lsl #2]
 // CHECK-ENCODING: [0x21,0x48,0xba,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 ba e0 <unknown>
+// CHECK-UNKNOWN: e0ba4821 <unknown>
 
 st1w    {za3h.s[w12, 1]}, p2, [x22, x30, lsl #2]
 // CHECK-INST: st1w    {za3h.s[w12, 1]}, p2, [x22, x30, lsl #2]
 // CHECK-ENCODING: [0xcd,0x0a,0xbe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a be e0 <unknown>
+// CHECK-UNKNOWN: e0be0acd <unknown>
 
 st1w    {za0h.s[w15, 2]}, p5, [x9, x1, lsl #2]
 // CHECK-INST: st1w    {za0h.s[w15, 2]}, p5, [x9, x1, lsl #2]
 // CHECK-ENCODING: [0x22,0x75,0xa1,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 a1 e0 <unknown>
+// CHECK-UNKNOWN: e0a17522 <unknown>
 
 st1w    {za1h.s[w13, 3]}, p2, [x12, x11, lsl #2]
 // CHECK-INST: st1w    {za1h.s[w13, 3]}, p2, [x12, x11, lsl #2]
 // CHECK-ENCODING: [0x87,0x29,0xab,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 ab e0 <unknown>
+// CHECK-UNKNOWN: e0ab2987 <unknown>
 
 st1w    za0h.s[w12, 0], p0, [x0, x0, lsl #2]
 // CHECK-INST: st1w    {za0h.s[w12, 0]}, p0, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x00,0xa0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 a0 e0 <unknown>
+// CHECK-UNKNOWN: e0a00000 <unknown>
 
 st1w    za1h.s[w14, 1], p5, [x10, x21, lsl #2]
 // CHECK-INST: st1w    {za1h.s[w14, 1]}, p5, [x10, x21, lsl #2]
 // CHECK-ENCODING: [0x45,0x55,0xb5,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 55 b5 e0 <unknown>
+// CHECK-UNKNOWN: e0b55545 <unknown>
 
 st1w    za1h.s[w15, 3], p3, [x13, x8, lsl #2]
 // CHECK-INST: st1w    {za1h.s[w15, 3]}, p3, [x13, x8, lsl #2]
 // CHECK-ENCODING: [0xa7,0x6d,0xa8,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 6d a8 e0 <unknown>
+// CHECK-UNKNOWN: e0a86da7 <unknown>
 
 st1w    za3h.s[w15, 3], p7, [sp]
 // CHECK-INST: st1w    {za3h.s[w15, 3]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0x7f,0xbf,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 7f bf e0 <unknown>
+// CHECK-UNKNOWN: e0bf7fef <unknown>
 
 st1w    za1h.s[w12, 1], p3, [x17, x16, lsl #2]
 // CHECK-INST: st1w    {za1h.s[w12, 1]}, p3, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0x0e,0xb0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 0e b0 e0 <unknown>
+// CHECK-UNKNOWN: e0b00e25 <unknown>
 
 st1w    za0h.s[w12, 1], p1, [x1, x30, lsl #2]
 // CHECK-INST: st1w    {za0h.s[w12, 1]}, p1, [x1, x30, lsl #2]
 // CHECK-ENCODING: [0x21,0x04,0xbe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 04 be e0 <unknown>
+// CHECK-UNKNOWN: e0be0421 <unknown>
 
 st1w    za2h.s[w14, 0], p5, [x19, x20, lsl #2]
 // CHECK-INST: st1w    {za2h.s[w14, 0]}, p5, [x19, x20, lsl #2]
 // CHECK-ENCODING: [0x68,0x56,0xb4,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 56 b4 e0 <unknown>
+// CHECK-UNKNOWN: e0b45668 <unknown>
 
 st1w    za0h.s[w12, 0], p6, [x12, x2, lsl #2]
 // CHECK-INST: st1w    {za0h.s[w12, 0]}, p6, [x12, x2, lsl #2]
 // CHECK-ENCODING: [0x80,0x19,0xa2,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 a2 e0 <unknown>
+// CHECK-UNKNOWN: e0a21980 <unknown>
 
 st1w    za0h.s[w14, 1], p2, [x1, x26, lsl #2]
 // CHECK-INST: st1w    {za0h.s[w14, 1]}, p2, [x1, x26, lsl #2]
 // CHECK-ENCODING: [0x21,0x48,0xba,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 48 ba e0 <unknown>
+// CHECK-UNKNOWN: e0ba4821 <unknown>
 
 st1w    za3h.s[w12, 1], p2, [x22, x30, lsl #2]
 // CHECK-INST: st1w    {za3h.s[w12, 1]}, p2, [x22, x30, lsl #2]
 // CHECK-ENCODING: [0xcd,0x0a,0xbe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 0a be e0 <unknown>
+// CHECK-UNKNOWN: e0be0acd <unknown>
 
 st1w    za0h.s[w15, 2], p5, [x9, x1, lsl #2]
 // CHECK-INST: st1w    {za0h.s[w15, 2]}, p5, [x9, x1, lsl #2]
 // CHECK-ENCODING: [0x22,0x75,0xa1,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 75 a1 e0 <unknown>
+// CHECK-UNKNOWN: e0a17522 <unknown>
 
 st1w    za1h.s[w13, 3], p2, [x12, x11, lsl #2]
 // CHECK-INST: st1w    {za1h.s[w13, 3]}, p2, [x12, x11, lsl #2]
 // CHECK-ENCODING: [0x87,0x29,0xab,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 29 ab e0 <unknown>
+// CHECK-UNKNOWN: e0ab2987 <unknown>
 
 // --------------------------------------------------------------------------//
 // Vertical
@@ -166,142 +166,142 @@ st1w    {za0v.s[w12, 0]}, p0, [x0, x0, lsl #2]
 // CHECK-INST: st1w    {za0v.s[w12, 0]}, p0, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x80,0xa0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 a0 e0 <unknown>
+// CHECK-UNKNOWN: e0a08000 <unknown>
 
 st1w    {za1v.s[w14, 1]}, p5, [x10, x21, lsl #2]
 // CHECK-INST: st1w    {za1v.s[w14, 1]}, p5, [x10, x21, lsl #2]
 // CHECK-ENCODING: [0x45,0xd5,0xb5,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 b5 e0 <unknown>
+// CHECK-UNKNOWN: e0b5d545 <unknown>
 
 st1w    {za1v.s[w15, 3]}, p3, [x13, x8, lsl #2]
 // CHECK-INST: st1w    {za1v.s[w15, 3]}, p3, [x13, x8, lsl #2]
 // CHECK-ENCODING: [0xa7,0xed,0xa8,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed a8 e0 <unknown>
+// CHECK-UNKNOWN: e0a8eda7 <unknown>
 
 st1w    {za3v.s[w15, 3]}, p7, [sp]
 // CHECK-INST: st1w    {za3v.s[w15, 3]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0xff,0xbf,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff bf e0 <unknown>
+// CHECK-UNKNOWN: e0bfffef <unknown>
 
 st1w    {za1v.s[w12, 1]}, p3, [x17, x16, lsl #2]
 // CHECK-INST: st1w    {za1v.s[w12, 1]}, p3, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0x8e,0xb0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e b0 e0 <unknown>
+// CHECK-UNKNOWN: e0b08e25 <unknown>
 
 st1w    {za0v.s[w12, 1]}, p1, [x1, x30, lsl #2]
 // CHECK-INST: st1w    {za0v.s[w12, 1]}, p1, [x1, x30, lsl #2]
 // CHECK-ENCODING: [0x21,0x84,0xbe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 be e0 <unknown>
+// CHECK-UNKNOWN: e0be8421 <unknown>
 
 st1w    {za2v.s[w14, 0]}, p5, [x19, x20, lsl #2]
 // CHECK-INST: st1w    {za2v.s[w14, 0]}, p5, [x19, x20, lsl #2]
 // CHECK-ENCODING: [0x68,0xd6,0xb4,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 b4 e0 <unknown>
+// CHECK-UNKNOWN: e0b4d668 <unknown>
 
 st1w    {za0v.s[w12, 0]}, p6, [x12, x2, lsl #2]
 // CHECK-INST: st1w    {za0v.s[w12, 0]}, p6, [x12, x2, lsl #2]
 // CHECK-ENCODING: [0x80,0x99,0xa2,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 a2 e0 <unknown>
+// CHECK-UNKNOWN: e0a29980 <unknown>
 
 st1w    {za0v.s[w14, 1]}, p2, [x1, x26, lsl #2]
 // CHECK-INST: st1w    {za0v.s[w14, 1]}, p2, [x1, x26, lsl #2]
 // CHECK-ENCODING: [0x21,0xc8,0xba,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 ba e0 <unknown>
+// CHECK-UNKNOWN: e0bac821 <unknown>
 
 st1w    {za3v.s[w12, 1]}, p2, [x22, x30, lsl #2]
 // CHECK-INST: st1w    {za3v.s[w12, 1]}, p2, [x22, x30, lsl #2]
 // CHECK-ENCODING: [0xcd,0x8a,0xbe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a be e0 <unknown>
+// CHECK-UNKNOWN: e0be8acd <unknown>
 
 st1w    {za0v.s[w15, 2]}, p5, [x9, x1, lsl #2]
 // CHECK-INST: st1w    {za0v.s[w15, 2]}, p5, [x9, x1, lsl #2]
 // CHECK-ENCODING: [0x22,0xf5,0xa1,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 a1 e0 <unknown>
+// CHECK-UNKNOWN: e0a1f522 <unknown>
 
 st1w    {za1v.s[w13, 3]}, p2, [x12, x11, lsl #2]
 // CHECK-INST: st1w    {za1v.s[w13, 3]}, p2, [x12, x11, lsl #2]
 // CHECK-ENCODING: [0x87,0xa9,0xab,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 ab e0 <unknown>
+// CHECK-UNKNOWN: e0aba987 <unknown>
 
 st1w    za0v.s[w12, 0], p0, [x0, x0, lsl #2]
 // CHECK-INST: st1w    {za0v.s[w12, 0]}, p0, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x80,0xa0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 80 a0 e0 <unknown>
+// CHECK-UNKNOWN: e0a08000 <unknown>
 
 st1w    za1v.s[w14, 1], p5, [x10, x21, lsl #2]
 // CHECK-INST: st1w    {za1v.s[w14, 1]}, p5, [x10, x21, lsl #2]
 // CHECK-ENCODING: [0x45,0xd5,0xb5,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 d5 b5 e0 <unknown>
+// CHECK-UNKNOWN: e0b5d545 <unknown>
 
 st1w    za1v.s[w15, 3], p3, [x13, x8, lsl #2]
 // CHECK-INST: st1w    {za1v.s[w15, 3]}, p3, [x13, x8, lsl #2]
 // CHECK-ENCODING: [0xa7,0xed,0xa8,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 ed a8 e0 <unknown>
+// CHECK-UNKNOWN: e0a8eda7 <unknown>
 
 st1w    za3v.s[w15, 3], p7, [sp]
 // CHECK-INST: st1w    {za3v.s[w15, 3]}, p7, [sp]
 // CHECK-ENCODING: [0xef,0xff,0xbf,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef ff bf e0 <unknown>
+// CHECK-UNKNOWN: e0bfffef <unknown>
 
 st1w    za1v.s[w12, 1], p3, [x17, x16, lsl #2]
 // CHECK-INST: st1w    {za1v.s[w12, 1]}, p3, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0x8e,0xb0,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 8e b0 e0 <unknown>
+// CHECK-UNKNOWN: e0b08e25 <unknown>
 
 st1w    za0v.s[w12, 1], p1, [x1, x30, lsl #2]
 // CHECK-INST: st1w    {za0v.s[w12, 1]}, p1, [x1, x30, lsl #2]
 // CHECK-ENCODING: [0x21,0x84,0xbe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 be e0 <unknown>
+// CHECK-UNKNOWN: e0be8421 <unknown>
 
 st1w    za2v.s[w14, 0], p5, [x19, x20, lsl #2]
 // CHECK-INST: st1w    {za2v.s[w14, 0]}, p5, [x19, x20, lsl #2]
 // CHECK-ENCODING: [0x68,0xd6,0xb4,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 d6 b4 e0 <unknown>
+// CHECK-UNKNOWN: e0b4d668 <unknown>
 
 st1w    za0v.s[w12, 0], p6, [x12, x2, lsl #2]
 // CHECK-INST: st1w    {za0v.s[w12, 0]}, p6, [x12, x2, lsl #2]
 // CHECK-ENCODING: [0x80,0x99,0xa2,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 99 a2 e0 <unknown>
+// CHECK-UNKNOWN: e0a29980 <unknown>
 
 st1w    za0v.s[w14, 1], p2, [x1, x26, lsl #2]
 // CHECK-INST: st1w    {za0v.s[w14, 1]}, p2, [x1, x26, lsl #2]
 // CHECK-ENCODING: [0x21,0xc8,0xba,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 ba e0 <unknown>
+// CHECK-UNKNOWN: e0bac821 <unknown>
 
 st1w    za3v.s[w12, 1], p2, [x22, x30, lsl #2]
 // CHECK-INST: st1w    {za3v.s[w12, 1]}, p2, [x22, x30, lsl #2]
 // CHECK-ENCODING: [0xcd,0x8a,0xbe,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 8a be e0 <unknown>
+// CHECK-UNKNOWN: e0be8acd <unknown>
 
 st1w    za0v.s[w15, 2], p5, [x9, x1, lsl #2]
 // CHECK-INST: st1w    {za0v.s[w15, 2]}, p5, [x9, x1, lsl #2]
 // CHECK-ENCODING: [0x22,0xf5,0xa1,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 a1 e0 <unknown>
+// CHECK-UNKNOWN: e0a1f522 <unknown>
 
 st1w    za1v.s[w13, 3], p2, [x12, x11, lsl #2]
 // CHECK-INST: st1w    {za1v.s[w13, 3]}, p2, [x12, x11, lsl #2]
 // CHECK-ENCODING: [0x87,0xa9,0xab,0xe0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 a9 ab e0 <unknown>
+// CHECK-UNKNOWN: e0aba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/str.s b/llvm/test/MC/AArch64/SME/str.s
index b407c1199bbed..0d5b42ec64475 100644
--- a/llvm/test/MC/AArch64/SME/str.s
+++ b/llvm/test/MC/AArch64/SME/str.s
@@ -16,70 +16,70 @@ str     za[w12, 0], [x0]
 // CHECK-INST: str     za[w12, 0], [x0]
 // CHECK-ENCODING: [0x00,0x00,0x20,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 20 e1 <unknown>
+// CHECK-UNKNOWN: e1200000 <unknown>
 
 str     za[w14, 5], [x10, #5, mul vl]
 // CHECK-INST: str     za[w14, 5], [x10, #5, mul vl]
 // CHECK-ENCODING: [0x45,0x41,0x20,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 45 41 20 e1 <unknown>
+// CHECK-UNKNOWN: e1204145 <unknown>
 
 str     za[w15, 7], [x13, #7, mul vl]
 // CHECK-INST: str     za[w15, 7], [x13, #7, mul vl]
 // CHECK-ENCODING: [0xa7,0x61,0x20,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a7 61 20 e1 <unknown>
+// CHECK-UNKNOWN: e12061a7 <unknown>
 
 str     za[w15, 15], [sp, #15, mul vl]
 // CHECK-INST: str     za[w15, 15], [sp, #15, mul vl]
 // CHECK-ENCODING: [0xef,0x63,0x20,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ef 63 20 e1 <unknown>
+// CHECK-UNKNOWN: e12063ef <unknown>
 
 str     za[w12, 5], [x17, #5, mul vl]
 // CHECK-INST: str     za[w12, 5], [x17, #5, mul vl]
 // CHECK-ENCODING: [0x25,0x02,0x20,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 25 02 20 e1 <unknown>
+// CHECK-UNKNOWN: e1200225 <unknown>
 
 str     za[w12, 1], [x1, #1, mul vl]
 // CHECK-INST: str     za[w12, 1], [x1, #1, mul vl]
 // CHECK-ENCODING: [0x21,0x00,0x20,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 00 20 e1 <unknown>
+// CHECK-UNKNOWN: e1200021 <unknown>
 
 str     za[w14, 8], [x19, #8, mul vl]
 // CHECK-INST: str     za[w14, 8], [x19, #8, mul vl]
 // CHECK-ENCODING: [0x68,0x42,0x20,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 68 42 20 e1 <unknown>
+// CHECK-UNKNOWN: e1204268 <unknown>
 
 str     za[w12, 0], [x12]
 // CHECK-INST: str     za[w12, 0], [x12]
 // CHECK-ENCODING: [0x80,0x01,0x20,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 01 20 e1 <unknown>
+// CHECK-UNKNOWN: e1200180 <unknown>
 
 str     za[w14, 1], [x1, #1, mul vl]
 // CHECK-INST: str     za[w14, 1], [x1, #1, mul vl]
 // CHECK-ENCODING: [0x21,0x40,0x20,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 40 20 e1 <unknown>
+// CHECK-UNKNOWN: e1204021 <unknown>
 
 str     za[w12, 13], [x22, #13, mul vl]
 // CHECK-INST: str     za[w12, 13], [x22, #13, mul vl]
 // CHECK-ENCODING: [0xcd,0x02,0x20,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cd 02 20 e1 <unknown>
+// CHECK-UNKNOWN: e12002cd <unknown>
 
 str     za[w15, 2], [x9, #2, mul vl]
 // CHECK-INST: str     za[w15, 2], [x9, #2, mul vl]
 // CHECK-ENCODING: [0x22,0x61,0x20,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 61 20 e1 <unknown>
+// CHECK-UNKNOWN: e1206122 <unknown>
 
 str     za[w13, 7], [x12, #7, mul vl]
 // CHECK-INST: str     za[w13, 7], [x12, #7, mul vl]
 // CHECK-ENCODING: [0x87,0x21,0x20,0xe1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 87 21 20 e1 <unknown>
+// CHECK-UNKNOWN: e1202187 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/sumopa-32.s b/llvm/test/MC/AArch64/SME/sumopa-32.s
index 611268a68becc..d5604b4346234 100644
--- a/llvm/test/MC/AArch64/SME/sumopa-32.s
+++ b/llvm/test/MC/AArch64/SME/sumopa-32.s
@@ -16,70 +16,70 @@ sumopa  za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-INST: sumopa  za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x00,0xa0,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 a0 a0 <unknown>
+// CHECK-UNKNOWN: a0a00000 <unknown>
 
 sumopa  za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-INST: sumopa  za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-ENCODING: [0x41,0x55,0xb5,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 41 55 b5 a0 <unknown>
+// CHECK-UNKNOWN: a0b55541 <unknown>
 
 sumopa  za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-INST: sumopa  za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-ENCODING: [0xa3,0xed,0xa8,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a3 ed a8 a0 <unknown>
+// CHECK-UNKNOWN: a0a8eda3 <unknown>
 
 sumopa  za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-INST: sumopa  za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xe3,0xff,0xbf,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: e3 ff bf a0 <unknown>
+// CHECK-UNKNOWN: a0bfffe3 <unknown>
 
 sumopa  za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-INST: sumopa  za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-ENCODING: [0x21,0x0e,0xb0,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 0e b0 a0 <unknown>
+// CHECK-UNKNOWN: a0b00e21 <unknown>
 
 sumopa  za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-INST: sumopa  za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-ENCODING: [0x21,0x84,0xbe,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 be a0 <unknown>
+// CHECK-UNKNOWN: a0be8421 <unknown>
 
 sumopa  za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-INST: sumopa  za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-ENCODING: [0x60,0x56,0xb4,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 60 56 b4 a0 <unknown>
+// CHECK-UNKNOWN: a0b45660 <unknown>
 
 sumopa  za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-INST: sumopa  za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-ENCODING: [0x80,0x19,0xa2,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 a2 a0 <unknown>
+// CHECK-UNKNOWN: a0a21980 <unknown>
 
 sumopa  za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-INST: sumopa  za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-ENCODING: [0x21,0xc8,0xba,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 ba a0 <unknown>
+// CHECK-UNKNOWN: a0bac821 <unknown>
 
 sumopa  za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-INST: sumopa  za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-ENCODING: [0xc1,0x0a,0xbe,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: c1 0a be a0 <unknown>
+// CHECK-UNKNOWN: a0be0ac1 <unknown>
 
 sumopa  za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-INST: sumopa  za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-ENCODING: [0x22,0xf5,0xa1,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 a1 a0 <unknown>
+// CHECK-UNKNOWN: a0a1f522 <unknown>
 
 sumopa  za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-INST: sumopa  za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-ENCODING: [0x83,0xa9,0xab,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 83 a9 ab a0 <unknown>
+// CHECK-UNKNOWN: a0aba983 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/sumopa-64.s b/llvm/test/MC/AArch64/SME/sumopa-64.s
index be1615bffd091..87a1f4b19f26a 100644
--- a/llvm/test/MC/AArch64/SME/sumopa-64.s
+++ b/llvm/test/MC/AArch64/SME/sumopa-64.s
@@ -16,70 +16,70 @@ sumopa  za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-INST: sumopa  za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x00,0xe0,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 00 00 e0 a0 <unknown>
+// CHECK-UNKNOWN: a0e00000 <unknown>
 
 sumopa  za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-INST: sumopa  za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-ENCODING: [0x45,0x55,0xf5,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 45 55 f5 a0 <unknown>
+// CHECK-UNKNOWN: a0f55545 <unknown>
 
 sumopa  za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-INST: sumopa  za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-ENCODING: [0xa7,0xed,0xe8,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: a7 ed e8 a0 <unknown>
+// CHECK-UNKNOWN: a0e8eda7 <unknown>
 
 sumopa  za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-INST: sumopa  za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xe7,0xff,0xff,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: e7 ff ff a0 <unknown>
+// CHECK-UNKNOWN: a0ffffe7 <unknown>
 
 sumopa  za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-INST: sumopa  za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-ENCODING: [0x25,0x0e,0xf0,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 25 0e f0 a0 <unknown>
+// CHECK-UNKNOWN: a0f00e25 <unknown>
 
 sumopa  za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-INST: sumopa  za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-ENCODING: [0x21,0x84,0xfe,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 21 84 fe a0 <unknown>
+// CHECK-UNKNOWN: a0fe8421 <unknown>
 
 sumopa  za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-INST: sumopa  za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-ENCODING: [0x60,0x56,0xf4,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 60 56 f4 a0 <unknown>
+// CHECK-UNKNOWN: a0f45660 <unknown>
 
 sumopa  za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-INST: sumopa  za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-ENCODING: [0x80,0x19,0xe2,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 80 19 e2 a0 <unknown>
+// CHECK-UNKNOWN: a0e21980 <unknown>
 
 sumopa  za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-INST: sumopa  za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-ENCODING: [0x21,0xc8,0xfa,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 21 c8 fa a0 <unknown>
+// CHECK-UNKNOWN: a0fac821 <unknown>
 
 sumopa  za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-INST: sumopa  za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-ENCODING: [0xc5,0x0a,0xfe,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: c5 0a fe a0 <unknown>
+// CHECK-UNKNOWN: a0fe0ac5 <unknown>
 
 sumopa  za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-INST: sumopa  za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-ENCODING: [0x22,0xf5,0xe1,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 22 f5 e1 a0 <unknown>
+// CHECK-UNKNOWN: a0e1f522 <unknown>
 
 sumopa  za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-INST: sumopa  za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-ENCODING: [0x87,0xa9,0xeb,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 87 a9 eb a0 <unknown>
+// CHECK-UNKNOWN: a0eba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/sumops-32.s b/llvm/test/MC/AArch64/SME/sumops-32.s
index 81ce097cb108e..6a5a0dfec1106 100644
--- a/llvm/test/MC/AArch64/SME/sumops-32.s
+++ b/llvm/test/MC/AArch64/SME/sumops-32.s
@@ -16,70 +16,70 @@ sumops  za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-INST: sumops  za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x10,0x00,0xa0,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 10 00 a0 a0 <unknown>
+// CHECK-UNKNOWN: a0a00010 <unknown>
 
 sumops  za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-INST: sumops  za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-ENCODING: [0x51,0x55,0xb5,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 51 55 b5 a0 <unknown>
+// CHECK-UNKNOWN: a0b55551 <unknown>
 
 sumops  za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-INST: sumops  za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-ENCODING: [0xb3,0xed,0xa8,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b3 ed a8 a0 <unknown>
+// CHECK-UNKNOWN: a0a8edb3 <unknown>
 
 sumops  za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-INST: sumops  za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xf3,0xff,0xbf,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: f3 ff bf a0 <unknown>
+// CHECK-UNKNOWN: a0bffff3 <unknown>
 
 sumops  za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-INST: sumops  za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-ENCODING: [0x31,0x0e,0xb0,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 0e b0 a0 <unknown>
+// CHECK-UNKNOWN: a0b00e31 <unknown>
 
 sumops  za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-INST: sumops  za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-ENCODING: [0x31,0x84,0xbe,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 84 be a0 <unknown>
+// CHECK-UNKNOWN: a0be8431 <unknown>
 
 sumops  za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-INST: sumops  za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-ENCODING: [0x70,0x56,0xb4,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 70 56 b4 a0 <unknown>
+// CHECK-UNKNOWN: a0b45670 <unknown>
 
 sumops  za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-INST: sumops  za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-ENCODING: [0x90,0x19,0xa2,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 90 19 a2 a0 <unknown>
+// CHECK-UNKNOWN: a0a21990 <unknown>
 
 sumops  za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-INST: sumops  za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-ENCODING: [0x31,0xc8,0xba,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 ba a0 <unknown>
+// CHECK-UNKNOWN: a0bac831 <unknown>
 
 sumops  za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-INST: sumops  za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-ENCODING: [0xd1,0x0a,0xbe,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: d1 0a be a0 <unknown>
+// CHECK-UNKNOWN: a0be0ad1 <unknown>
 
 sumops  za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-INST: sumops  za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-ENCODING: [0x32,0xf5,0xa1,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 32 f5 a1 a0 <unknown>
+// CHECK-UNKNOWN: a0a1f532 <unknown>
 
 sumops  za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-INST: sumops  za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-ENCODING: [0x93,0xa9,0xab,0xa0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 93 a9 ab a0 <unknown>
+// CHECK-UNKNOWN: a0aba993 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/sumops-64.s b/llvm/test/MC/AArch64/SME/sumops-64.s
index ca636d497fc1f..d805572d132da 100644
--- a/llvm/test/MC/AArch64/SME/sumops-64.s
+++ b/llvm/test/MC/AArch64/SME/sumops-64.s
@@ -16,70 +16,70 @@ sumops  za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-INST: sumops  za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x10,0x00,0xe0,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 10 00 e0 a0 <unknown>
+// CHECK-UNKNOWN: a0e00010 <unknown>
 
 sumops  za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-INST: sumops  za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-ENCODING: [0x55,0x55,0xf5,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 55 55 f5 a0 <unknown>
+// CHECK-UNKNOWN: a0f55555 <unknown>
 
 sumops  za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-INST: sumops  za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0xed,0xe8,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: b7 ed e8 a0 <unknown>
+// CHECK-UNKNOWN: a0e8edb7 <unknown>
 
 sumops  za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-INST: sumops  za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xf7,0xff,0xff,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: f7 ff ff a0 <unknown>
+// CHECK-UNKNOWN: a0fffff7 <unknown>
 
 sumops  za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-INST: sumops  za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-ENCODING: [0x35,0x0e,0xf0,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 35 0e f0 a0 <unknown>
+// CHECK-UNKNOWN: a0f00e35 <unknown>
 
 sumops  za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-INST: sumops  za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-ENCODING: [0x31,0x84,0xfe,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 31 84 fe a0 <unknown>
+// CHECK-UNKNOWN: a0fe8431 <unknown>
 
 sumops  za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-INST: sumops  za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-ENCODING: [0x70,0x56,0xf4,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 70 56 f4 a0 <unknown>
+// CHECK-UNKNOWN: a0f45670 <unknown>
 
 sumops  za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-INST: sumops  za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-ENCODING: [0x90,0x19,0xe2,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 90 19 e2 a0 <unknown>
+// CHECK-UNKNOWN: a0e21990 <unknown>
 
 sumops  za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-INST: sumops  za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-ENCODING: [0x31,0xc8,0xfa,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 31 c8 fa a0 <unknown>
+// CHECK-UNKNOWN: a0fac831 <unknown>
 
 sumops  za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-INST: sumops  za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-ENCODING: [0xd5,0x0a,0xfe,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: d5 0a fe a0 <unknown>
+// CHECK-UNKNOWN: a0fe0ad5 <unknown>
 
 sumops  za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-INST: sumops  za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-ENCODING: [0x32,0xf5,0xe1,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 32 f5 e1 a0 <unknown>
+// CHECK-UNKNOWN: a0e1f532 <unknown>
 
 sumops  za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-INST: sumops  za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-ENCODING: [0x97,0xa9,0xeb,0xa0]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 97 a9 eb a0 <unknown>
+// CHECK-UNKNOWN: a0eba997 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/system-regs-mpam.s b/llvm/test/MC/AArch64/SME/system-regs-mpam.s
index d3eb90c15106c..7d343514b9f13 100644
--- a/llvm/test/MC/AArch64/SME/system-regs-mpam.s
+++ b/llvm/test/MC/AArch64/SME/system-regs-mpam.s
@@ -22,7 +22,7 @@ mrs x3, MPAMSM_EL1
 // CHECK-INST: mrs x3, MPAMSM_EL1
 // CHECK-ENCODING: [0x63,0xa5,0x38,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: 63 a5 38 d5   mrs   x3, S3_0_C10_C5_3
+// CHECK-UNKNOWN: d538a563   mrs   x3, S3_0_C10_C5_3
 
 // --------------------------------------------------------------------------//
 // write
@@ -31,4 +31,4 @@ msr MPAMSM_EL1, x3
 // CHECK-INST: msr MPAMSM_EL1, x3
 // CHECK-ENCODING: [0x63,0xa5,0x18,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: 63 a5 18 d5   msr   S3_0_C10_C5_3, x3
+// CHECK-UNKNOWN: d518a563   msr   S3_0_C10_C5_3, x3

diff  --git a/llvm/test/MC/AArch64/SME/system-regs.s b/llvm/test/MC/AArch64/SME/system-regs.s
index 39942b8d3ebc9..48033d026c44b 100644
--- a/llvm/test/MC/AArch64/SME/system-regs.s
+++ b/llvm/test/MC/AArch64/SME/system-regs.s
@@ -14,61 +14,61 @@ mrs x3, ID_AA64SMFR0_EL1
 // CHECK-INST: mrs x3, ID_AA64SMFR0_EL1
 // CHECK-ENCODING: [0xa3,0x04,0x38,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: a3 04 38 d5   mrs   x3, S3_0_C0_C4_5
+// CHECK-UNKNOWN: d53804a3   mrs   x3, S3_0_C0_C4_5
 
 mrs x3, SMCR_EL1
 // CHECK-INST: mrs x3, SMCR_EL1
 // CHECK-ENCODING: [0xc3,0x12,0x38,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: c3 12 38 d5   mrs   x3, S3_0_C1_C2_6
+// CHECK-UNKNOWN: d53812c3   mrs   x3, S3_0_C1_C2_6
 
 mrs x3, SMCR_EL2
 // CHECK-INST: mrs x3, SMCR_EL2
 // CHECK-ENCODING: [0xc3,0x12,0x3c,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: c3 12 3c d5   mrs   x3, S3_4_C1_C2_6
+// CHECK-UNKNOWN: d53c12c3   mrs   x3, S3_4_C1_C2_6
 
 mrs x3, SMCR_EL3
 // CHECK-INST: mrs x3, SMCR_EL3
 // CHECK-ENCODING: [0xc3,0x12,0x3e,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: c3 12 3e d5   mrs   x3, S3_6_C1_C2_6
+// CHECK-UNKNOWN: d53e12c3   mrs   x3, S3_6_C1_C2_6
 
 mrs x3, SMCR_EL12
 // CHECK-INST: mrs x3, SMCR_EL12
 // CHECK-ENCODING: [0xc3,0x12,0x3d,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: c3 12 3d d5   mrs   x3, S3_5_C1_C2_6
+// CHECK-UNKNOWN: d53d12c3   mrs   x3, S3_5_C1_C2_6
 
 mrs x3, SVCR
 // CHECK-INST: mrs x3, SVCR
 // CHECK-ENCODING: [0x43,0x42,0x3b,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: 43 42 3b d5   mrs   x3, S3_3_C4_C2_2
+// CHECK-UNKNOWN: d53b4243   mrs   x3, S3_3_C4_C2_2
 
 mrs x3, SMPRI_EL1
 // CHECK-INST: mrs x3, SMPRI_EL1
 // CHECK-ENCODING: [0x83,0x12,0x38,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: 83 12 38 d5   mrs   x3, S3_0_C1_C2_4
+// CHECK-UNKNOWN: d5381283   mrs   x3, S3_0_C1_C2_4
 
 mrs x3, SMPRIMAP_EL2
 // CHECK-INST: mrs x3, SMPRIMAP_EL2
 // CHECK-ENCODING: [0xa3,0x12,0x3c,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: a3 12 3c d5   mrs   x3, S3_4_C1_C2_5
+// CHECK-UNKNOWN: d53c12a3   mrs   x3, S3_4_C1_C2_5
 
 mrs x3, SMIDR_EL1
 // CHECK-INST: mrs x3, SMIDR_EL1
 // CHECK-ENCODING: [0xc3,0x00,0x39,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: c3 00 39 d5   mrs   x3, S3_1_C0_C0_6
+// CHECK-UNKNOWN: d53900c3   mrs   x3, S3_1_C0_C0_6
 
 mrs x3, TPIDR2_EL0
 // CHECK-INST: mrs x3, TPIDR2_EL0
 // CHECK-ENCODING: [0xa3,0xd0,0x3b,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: a3 d0 3b d5   mrs   x3, S3_3_C13_C0_5
+// CHECK-UNKNOWN: d53bd0a3   mrs   x3, S3_3_C13_C0_5
 
 // --------------------------------------------------------------------------//
 // write
@@ -77,82 +77,82 @@ msr SMCR_EL1, x3
 // CHECK-INST: msr SMCR_EL1, x3
 // CHECK-ENCODING: [0xc3,0x12,0x18,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: c3 12 18 d5   msr   S3_0_C1_C2_6, x3
+// CHECK-UNKNOWN: d51812c3   msr   S3_0_C1_C2_6, x3
 
 msr SMCR_EL2, x3
 // CHECK-INST: msr SMCR_EL2, x3
 // CHECK-ENCODING: [0xc3,0x12,0x1c,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: c3 12 1c d5   msr   S3_4_C1_C2_6, x3
+// CHECK-UNKNOWN: d51c12c3   msr   S3_4_C1_C2_6, x3
 
 msr SMCR_EL3, x3
 // CHECK-INST: msr SMCR_EL3, x3
 // CHECK-ENCODING: [0xc3,0x12,0x1e,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: c3 12 1e d5   msr   S3_6_C1_C2_6, x3
+// CHECK-UNKNOWN: d51e12c3   msr   S3_6_C1_C2_6, x3
 
 msr SMCR_EL12, x3
 // CHECK-INST: msr SMCR_EL12, x3
 // CHECK-ENCODING: [0xc3,0x12,0x1d,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: c3 12 1d d5   msr   S3_5_C1_C2_6, x3
+// CHECK-UNKNOWN: d51d12c3   msr   S3_5_C1_C2_6, x3
 
 msr SVCR, x3
 // CHECK-INST: msr SVCR, x3
 // CHECK-ENCODING: [0x43,0x42,0x1b,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: 43 42 1b d5   msr   S3_3_C4_C2_2, x3
+// CHECK-UNKNOWN: d51b4243   msr   S3_3_C4_C2_2, x3
 
 msr SMPRI_EL1, x3
 // CHECK-INST: msr SMPRI_EL1, x3
 // CHECK-ENCODING: [0x83,0x12,0x18,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: 83 12 18 d5   msr   S3_0_C1_C2_4, x3
+// CHECK-UNKNOWN: d5181283   msr   S3_0_C1_C2_4, x3
 
 msr SMPRIMAP_EL2, x3
 // CHECK-INST: msr SMPRIMAP_EL2, x3
 // CHECK-ENCODING: [0xa3,0x12,0x1c,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: a3 12 1c d5   msr   S3_4_C1_C2_5, x3
+// CHECK-UNKNOWN: d51c12a3   msr   S3_4_C1_C2_5, x3
 
 msr SVCRSM, #0
 // CHECK-INST: smstop sm
 // CHECK-ENCODING: [0x7f,0x42,0x03,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: 7f 42 03 d5   msr   S0_3_C4_C2_3, xzr
+// CHECK-UNKNOWN: d503427f   msr   S0_3_C4_C2_3, xzr
 
 msr SVCRSM, #1
 // CHECK-INST: smstart
 // CHECK-ENCODING: [0x7f,0x43,0x03,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: 7f 43 03 d5   msr   S0_3_C4_C3_3, xzr
+// CHECK-UNKNOWN: d503437f   msr   S0_3_C4_C3_3, xzr
 
 msr SVCRZA, #0
 // CHECK-INST: smstop za
 // CHECK-ENCODING: [0x7f,0x44,0x03,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: 7f 44 03 d5   msr   S0_3_C4_C4_3, xzr
+// CHECK-UNKNOWN: d503447f   msr   S0_3_C4_C4_3, xzr
 
 msr SVCRZA, #1
 // CHECK-INST: smstart za
 // CHECK-ENCODING: [0x7f,0x45,0x03,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: 7f 45 03 d5   msr   S0_3_C4_C5_3, xzr
+// CHECK-UNKNOWN: d503457f   msr   S0_3_C4_C5_3, xzr
 
 msr SVCRSMZA, #0
 // CHECK-INST: smstop
 // CHECK-ENCODING: [0x7f,0x46,0x03,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: 7f 46 03 d5   msr   S0_3_C4_C6_3, xzr
+// CHECK-UNKNOWN: d503467f   msr   S0_3_C4_C6_3, xzr
 
 msr SVCRSMZA, #1
 // CHECK-INST: smstart
 // CHECK-ENCODING: [0x7f,0x47,0x03,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: 7f 47 03 d5   msr   S0_3_C4_C7_3, xzr
+// CHECK-UNKNOWN: d503477f   msr   S0_3_C4_C7_3, xzr
 
 msr TPIDR2_EL0, x3
 // CHECK-INST: msr TPIDR2_EL0, x3
 // CHECK-ENCODING: [0xa3,0xd0,0x1b,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: a3 d0 1b d5   msr   S3_3_C13_C0_5, x3
+// CHECK-UNKNOWN: d51bd0a3   msr   S3_3_C13_C0_5, x3

diff  --git a/llvm/test/MC/AArch64/SME/uclamp.s b/llvm/test/MC/AArch64/SME/uclamp.s
index e9c21a24cfa6b..5b10d7d26b5b9 100644
--- a/llvm/test/MC/AArch64/SME/uclamp.s
+++ b/llvm/test/MC/AArch64/SME/uclamp.s
@@ -19,25 +19,25 @@ uclamp  z0.b, z0.b, z0.b
 // CHECK-INST: uclamp  z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0xc4,0x00,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 c4 00 44 <unknown>
+// CHECK-UNKNOWN: 4400c400 <unknown>
 
 uclamp  z21.b, z10.b, z21.b
 // CHECK-INST: uclamp  z21.b, z10.b, z21.b
 // CHECK-ENCODING: [0x55,0xc5,0x15,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 c5 15 44 <unknown>
+// CHECK-UNKNOWN: 4415c555 <unknown>
 
 uclamp  z23.b, z13.b, z8.b
 // CHECK-INST: uclamp  z23.b, z13.b, z8.b
 // CHECK-ENCODING: [0xb7,0xc5,0x08,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c5 08 44 <unknown>
+// CHECK-UNKNOWN: 4408c5b7 <unknown>
 
 uclamp  z31.b, z31.b, z31.b
 // CHECK-INST: uclamp  z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0xc7,0x1f,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff c7 1f 44 <unknown>
+// CHECK-UNKNOWN: 441fc7ff <unknown>
 
 // --------------------------------------------------------------------------//
 // 16-bit
@@ -46,25 +46,25 @@ uclamp  z0.h, z0.h, z0.h
 // CHECK-INST: uclamp  z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0xc4,0x40,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 c4 40 44 <unknown>
+// CHECK-UNKNOWN: 4440c400 <unknown>
 
 uclamp  z21.h, z10.h, z21.h
 // CHECK-INST: uclamp  z21.h, z10.h, z21.h
 // CHECK-ENCODING: [0x55,0xc5,0x55,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 c5 55 44 <unknown>
+// CHECK-UNKNOWN: 4455c555 <unknown>
 
 uclamp  z23.h, z13.h, z8.h
 // CHECK-INST: uclamp  z23.h, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0xc5,0x48,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c5 48 44 <unknown>
+// CHECK-UNKNOWN: 4448c5b7 <unknown>
 
 uclamp  z31.h, z31.h, z31.h
 // CHECK-INST: uclamp  z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0xc7,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff c7 5f 44 <unknown>
+// CHECK-UNKNOWN: 445fc7ff <unknown>
 
 // --------------------------------------------------------------------------//
 // 32-bit
@@ -73,25 +73,25 @@ uclamp  z0.s, z0.s, z0.s
 // CHECK-INST: uclamp  z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0xc4,0x80,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 c4 80 44 <unknown>
+// CHECK-UNKNOWN: 4480c400 <unknown>
 
 uclamp  z21.s, z10.s, z21.s
 // CHECK-INST: uclamp  z21.s, z10.s, z21.s
 // CHECK-ENCODING: [0x55,0xc5,0x95,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 c5 95 44 <unknown>
+// CHECK-UNKNOWN: 4495c555 <unknown>
 
 uclamp  z23.s, z13.s, z8.s
 // CHECK-INST: uclamp  z23.s, z13.s, z8.s
 // CHECK-ENCODING: [0xb7,0xc5,0x88,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c5 88 44 <unknown>
+// CHECK-UNKNOWN: 4488c5b7 <unknown>
 
 uclamp  z31.s, z31.s, z31.s
 // CHECK-INST: uclamp  z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0xc7,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff c7 9f 44 <unknown>
+// CHECK-UNKNOWN: 449fc7ff <unknown>
 
 // --------------------------------------------------------------------------//
 // 64-bit
@@ -100,25 +100,25 @@ uclamp  z0.d, z0.d, z0.d
 // CHECK-INST: uclamp  z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0xc4,0xc0,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 c4 c0 44 <unknown>
+// CHECK-UNKNOWN: 44c0c400 <unknown>
 
 uclamp  z21.d, z10.d, z21.d
 // CHECK-INST: uclamp  z21.d, z10.d, z21.d
 // CHECK-ENCODING: [0x55,0xc5,0xd5,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 c5 d5 44 <unknown>
+// CHECK-UNKNOWN: 44d5c555 <unknown>
 
 uclamp  z23.d, z13.d, z8.d
 // CHECK-INST: uclamp  z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0xc5,0xc8,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c5 c8 44 <unknown>
+// CHECK-UNKNOWN: 44c8c5b7 <unknown>
 
 uclamp  z31.d, z31.d, z31.d
 // CHECK-INST: uclamp  z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0xc7,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff c7 df 44 <unknown>
+// CHECK-UNKNOWN: 44dfc7ff <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -127,46 +127,46 @@ movprfx z23, z27
 // CHECK-INST: movprfx  z23, z27
 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 77 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf77 <unknown>
 
 uclamp  z23.b, z13.b, z8.b
 // CHECK-INST: uclamp  z23.b, z13.b, z8.b
 // CHECK-ENCODING: [0xb7,0xc5,0x08,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c5 08 44 <unknown>
+// CHECK-UNKNOWN: 4408c5b7 <unknown>
 
 movprfx z23, z27
 // CHECK-INST: movprfx  z23, z27
 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 77 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf77 <unknown>
 
 uclamp  z23.h, z13.h, z8.h
 // CHECK-INST: uclamp  z23.h, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0xc5,0x48,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c5 48 44 <unknown>
+// CHECK-UNKNOWN: 4448c5b7 <unknown>
 
 movprfx z23, z27
 // CHECK-INST: movprfx  z23, z27
 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 77 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf77 <unknown>
 
 uclamp  z23.s, z13.s, z8.s
 // CHECK-INST: uclamp  z23.s, z13.s, z8.s
 // CHECK-ENCODING: [0xb7,0xc5,0x88,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c5 88 44 <unknown>
+// CHECK-UNKNOWN: 4488c5b7 <unknown>
 
 movprfx z23, z27
 // CHECK-INST: movprfx  z23, z27
 // CHECK-ENCODING: [0x77,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 77 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf77 <unknown>
 
 uclamp  z23.d, z13.d, z8.d
 // CHECK-INST: uclamp  z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0xc5,0xc8,0x44]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 c5 c8 44 <unknown>
+// CHECK-UNKNOWN: 44c8c5b7 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/umopa-32.s b/llvm/test/MC/AArch64/SME/umopa-32.s
index c740cdbf5b717..b505ffe3c98a7 100644
--- a/llvm/test/MC/AArch64/SME/umopa-32.s
+++ b/llvm/test/MC/AArch64/SME/umopa-32.s
@@ -16,70 +16,70 @@ umopa   za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-INST: umopa   za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x00,0xa0,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 a0 a1 <unknown>
+// CHECK-UNKNOWN: a1a00000 <unknown>
 
 umopa   za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-INST: umopa   za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-ENCODING: [0x41,0x55,0xb5,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 41 55 b5 a1 <unknown>
+// CHECK-UNKNOWN: a1b55541 <unknown>
 
 umopa   za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-INST: umopa   za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-ENCODING: [0xa3,0xed,0xa8,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a3 ed a8 a1 <unknown>
+// CHECK-UNKNOWN: a1a8eda3 <unknown>
 
 umopa   za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-INST: umopa   za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xe3,0xff,0xbf,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: e3 ff bf a1 <unknown>
+// CHECK-UNKNOWN: a1bfffe3 <unknown>
 
 umopa   za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-INST: umopa   za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-ENCODING: [0x21,0x0e,0xb0,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 0e b0 a1 <unknown>
+// CHECK-UNKNOWN: a1b00e21 <unknown>
 
 umopa   za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-INST: umopa   za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-ENCODING: [0x21,0x84,0xbe,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 be a1 <unknown>
+// CHECK-UNKNOWN: a1be8421 <unknown>
 
 umopa   za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-INST: umopa   za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-ENCODING: [0x60,0x56,0xb4,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 60 56 b4 a1 <unknown>
+// CHECK-UNKNOWN: a1b45660 <unknown>
 
 umopa   za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-INST: umopa   za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-ENCODING: [0x80,0x19,0xa2,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 a2 a1 <unknown>
+// CHECK-UNKNOWN: a1a21980 <unknown>
 
 umopa   za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-INST: umopa   za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-ENCODING: [0x21,0xc8,0xba,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 ba a1 <unknown>
+// CHECK-UNKNOWN: a1bac821 <unknown>
 
 umopa   za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-INST: umopa   za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-ENCODING: [0xc1,0x0a,0xbe,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: c1 0a be a1 <unknown>
+// CHECK-UNKNOWN: a1be0ac1 <unknown>
 
 umopa   za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-INST: umopa   za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-ENCODING: [0x22,0xf5,0xa1,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 a1 a1 <unknown>
+// CHECK-UNKNOWN: a1a1f522 <unknown>
 
 umopa   za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-INST: umopa   za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-ENCODING: [0x83,0xa9,0xab,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 83 a9 ab a1 <unknown>
+// CHECK-UNKNOWN: a1aba983 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/umopa-64.s b/llvm/test/MC/AArch64/SME/umopa-64.s
index c6bd222ec6263..872f7fe183d84 100644
--- a/llvm/test/MC/AArch64/SME/umopa-64.s
+++ b/llvm/test/MC/AArch64/SME/umopa-64.s
@@ -16,70 +16,70 @@ umopa   za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-INST: umopa   za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x00,0xe0,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 00 00 e0 a1 <unknown>
+// CHECK-UNKNOWN: a1e00000 <unknown>
 
 umopa   za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-INST: umopa   za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-ENCODING: [0x45,0x55,0xf5,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 45 55 f5 a1 <unknown>
+// CHECK-UNKNOWN: a1f55545 <unknown>
 
 umopa   za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-INST: umopa   za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-ENCODING: [0xa7,0xed,0xe8,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: a7 ed e8 a1 <unknown>
+// CHECK-UNKNOWN: a1e8eda7 <unknown>
 
 umopa   za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-INST: umopa   za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xe7,0xff,0xff,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: e7 ff ff a1 <unknown>
+// CHECK-UNKNOWN: a1ffffe7 <unknown>
 
 umopa   za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-INST: umopa   za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-ENCODING: [0x25,0x0e,0xf0,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 25 0e f0 a1 <unknown>
+// CHECK-UNKNOWN: a1f00e25 <unknown>
 
 umopa   za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-INST: umopa   za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-ENCODING: [0x21,0x84,0xfe,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 21 84 fe a1 <unknown>
+// CHECK-UNKNOWN: a1fe8421 <unknown>
 
 umopa   za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-INST: umopa   za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-ENCODING: [0x60,0x56,0xf4,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 60 56 f4 a1 <unknown>
+// CHECK-UNKNOWN: a1f45660 <unknown>
 
 umopa   za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-INST: umopa   za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-ENCODING: [0x80,0x19,0xe2,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 80 19 e2 a1 <unknown>
+// CHECK-UNKNOWN: a1e21980 <unknown>
 
 umopa   za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-INST: umopa   za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-ENCODING: [0x21,0xc8,0xfa,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 21 c8 fa a1 <unknown>
+// CHECK-UNKNOWN: a1fac821 <unknown>
 
 umopa   za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-INST: umopa   za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-ENCODING: [0xc5,0x0a,0xfe,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: c5 0a fe a1 <unknown>
+// CHECK-UNKNOWN: a1fe0ac5 <unknown>
 
 umopa   za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-INST: umopa   za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-ENCODING: [0x22,0xf5,0xe1,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 22 f5 e1 a1 <unknown>
+// CHECK-UNKNOWN: a1e1f522 <unknown>
 
 umopa   za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-INST: umopa   za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-ENCODING: [0x87,0xa9,0xeb,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 87 a9 eb a1 <unknown>
+// CHECK-UNKNOWN: a1eba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/umops-32.s b/llvm/test/MC/AArch64/SME/umops-32.s
index 75f2c8febe75a..77e49620a19da 100644
--- a/llvm/test/MC/AArch64/SME/umops-32.s
+++ b/llvm/test/MC/AArch64/SME/umops-32.s
@@ -16,70 +16,70 @@ umops   za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-INST: umops   za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x10,0x00,0xa0,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 10 00 a0 a1 <unknown>
+// CHECK-UNKNOWN: a1a00010 <unknown>
 
 umops   za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-INST: umops   za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-ENCODING: [0x51,0x55,0xb5,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 51 55 b5 a1 <unknown>
+// CHECK-UNKNOWN: a1b55551 <unknown>
 
 umops   za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-INST: umops   za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-ENCODING: [0xb3,0xed,0xa8,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b3 ed a8 a1 <unknown>
+// CHECK-UNKNOWN: a1a8edb3 <unknown>
 
 umops   za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-INST: umops   za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xf3,0xff,0xbf,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: f3 ff bf a1 <unknown>
+// CHECK-UNKNOWN: a1bffff3 <unknown>
 
 umops   za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-INST: umops   za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-ENCODING: [0x31,0x0e,0xb0,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 0e b0 a1 <unknown>
+// CHECK-UNKNOWN: a1b00e31 <unknown>
 
 umops   za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-INST: umops   za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-ENCODING: [0x31,0x84,0xbe,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 84 be a1 <unknown>
+// CHECK-UNKNOWN: a1be8431 <unknown>
 
 umops   za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-INST: umops   za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-ENCODING: [0x70,0x56,0xb4,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 70 56 b4 a1 <unknown>
+// CHECK-UNKNOWN: a1b45670 <unknown>
 
 umops   za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-INST: umops   za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-ENCODING: [0x90,0x19,0xa2,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 90 19 a2 a1 <unknown>
+// CHECK-UNKNOWN: a1a21990 <unknown>
 
 umops   za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-INST: umops   za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-ENCODING: [0x31,0xc8,0xba,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 ba a1 <unknown>
+// CHECK-UNKNOWN: a1bac831 <unknown>
 
 umops   za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-INST: umops   za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-ENCODING: [0xd1,0x0a,0xbe,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: d1 0a be a1 <unknown>
+// CHECK-UNKNOWN: a1be0ad1 <unknown>
 
 umops   za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-INST: umops   za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-ENCODING: [0x32,0xf5,0xa1,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 32 f5 a1 a1 <unknown>
+// CHECK-UNKNOWN: a1a1f532 <unknown>
 
 umops   za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-INST: umops   za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-ENCODING: [0x93,0xa9,0xab,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 93 a9 ab a1 <unknown>
+// CHECK-UNKNOWN: a1aba993 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/umops-64.s b/llvm/test/MC/AArch64/SME/umops-64.s
index f81f22e0411ea..6554abb4be469 100644
--- a/llvm/test/MC/AArch64/SME/umops-64.s
+++ b/llvm/test/MC/AArch64/SME/umops-64.s
@@ -16,70 +16,70 @@ umops   za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-INST: umops   za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x10,0x00,0xe0,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 10 00 e0 a1 <unknown>
+// CHECK-UNKNOWN: a1e00010 <unknown>
 
 umops   za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-INST: umops   za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-ENCODING: [0x55,0x55,0xf5,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 55 55 f5 a1 <unknown>
+// CHECK-UNKNOWN: a1f55555 <unknown>
 
 umops   za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-INST: umops   za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0xed,0xe8,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: b7 ed e8 a1 <unknown>
+// CHECK-UNKNOWN: a1e8edb7 <unknown>
 
 umops   za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-INST: umops   za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xf7,0xff,0xff,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: f7 ff ff a1 <unknown>
+// CHECK-UNKNOWN: a1fffff7 <unknown>
 
 umops   za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-INST: umops   za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-ENCODING: [0x35,0x0e,0xf0,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 35 0e f0 a1 <unknown>
+// CHECK-UNKNOWN: a1f00e35 <unknown>
 
 umops   za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-INST: umops   za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-ENCODING: [0x31,0x84,0xfe,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 31 84 fe a1 <unknown>
+// CHECK-UNKNOWN: a1fe8431 <unknown>
 
 umops   za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-INST: umops   za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-ENCODING: [0x70,0x56,0xf4,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 70 56 f4 a1 <unknown>
+// CHECK-UNKNOWN: a1f45670 <unknown>
 
 umops   za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-INST: umops   za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-ENCODING: [0x90,0x19,0xe2,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 90 19 e2 a1 <unknown>
+// CHECK-UNKNOWN: a1e21990 <unknown>
 
 umops   za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-INST: umops   za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-ENCODING: [0x31,0xc8,0xfa,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 31 c8 fa a1 <unknown>
+// CHECK-UNKNOWN: a1fac831 <unknown>
 
 umops   za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-INST: umops   za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-ENCODING: [0xd5,0x0a,0xfe,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: d5 0a fe a1 <unknown>
+// CHECK-UNKNOWN: a1fe0ad5 <unknown>
 
 umops   za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-INST: umops   za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-ENCODING: [0x32,0xf5,0xe1,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 32 f5 e1 a1 <unknown>
+// CHECK-UNKNOWN: a1e1f532 <unknown>
 
 umops   za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-INST: umops   za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-ENCODING: [0x97,0xa9,0xeb,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 97 a9 eb a1 <unknown>
+// CHECK-UNKNOWN: a1eba997 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/usmopa-32.s b/llvm/test/MC/AArch64/SME/usmopa-32.s
index 1ddc06cff2d94..594f9ab7c9bdb 100644
--- a/llvm/test/MC/AArch64/SME/usmopa-32.s
+++ b/llvm/test/MC/AArch64/SME/usmopa-32.s
@@ -16,70 +16,70 @@ usmopa  za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-INST: usmopa  za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x00,0x80,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 80 a1 <unknown>
+// CHECK-UNKNOWN: a1800000 <unknown>
 
 usmopa  za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-INST: usmopa  za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-ENCODING: [0x41,0x55,0x95,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 41 55 95 a1 <unknown>
+// CHECK-UNKNOWN: a1955541 <unknown>
 
 usmopa  za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-INST: usmopa  za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-ENCODING: [0xa3,0xed,0x88,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: a3 ed 88 a1 <unknown>
+// CHECK-UNKNOWN: a188eda3 <unknown>
 
 usmopa  za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-INST: usmopa  za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xe3,0xff,0x9f,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: e3 ff 9f a1 <unknown>
+// CHECK-UNKNOWN: a19fffe3 <unknown>
 
 usmopa  za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-INST: usmopa  za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-ENCODING: [0x21,0x0e,0x90,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 0e 90 a1 <unknown>
+// CHECK-UNKNOWN: a1900e21 <unknown>
 
 usmopa  za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-INST: usmopa  za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-ENCODING: [0x21,0x84,0x9e,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 84 9e a1 <unknown>
+// CHECK-UNKNOWN: a19e8421 <unknown>
 
 usmopa  za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-INST: usmopa  za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-ENCODING: [0x60,0x56,0x94,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 60 56 94 a1 <unknown>
+// CHECK-UNKNOWN: a1945660 <unknown>
 
 usmopa  za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-INST: usmopa  za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-ENCODING: [0x80,0x19,0x82,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 80 19 82 a1 <unknown>
+// CHECK-UNKNOWN: a1821980 <unknown>
 
 usmopa  za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-INST: usmopa  za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-ENCODING: [0x21,0xc8,0x9a,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 21 c8 9a a1 <unknown>
+// CHECK-UNKNOWN: a19ac821 <unknown>
 
 usmopa  za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-INST: usmopa  za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-ENCODING: [0xc1,0x0a,0x9e,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: c1 0a 9e a1 <unknown>
+// CHECK-UNKNOWN: a19e0ac1 <unknown>
 
 usmopa  za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-INST: usmopa  za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-ENCODING: [0x22,0xf5,0x81,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 f5 81 a1 <unknown>
+// CHECK-UNKNOWN: a181f522 <unknown>
 
 usmopa  za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-INST: usmopa  za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-ENCODING: [0x83,0xa9,0x8b,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 83 a9 8b a1 <unknown>
+// CHECK-UNKNOWN: a18ba983 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/usmopa-64.s b/llvm/test/MC/AArch64/SME/usmopa-64.s
index e1b4b8e5f9939..7da286c92c789 100644
--- a/llvm/test/MC/AArch64/SME/usmopa-64.s
+++ b/llvm/test/MC/AArch64/SME/usmopa-64.s
@@ -16,70 +16,70 @@ usmopa  za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-INST: usmopa  za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x00,0xc0,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 00 00 c0 a1 <unknown>
+// CHECK-UNKNOWN: a1c00000 <unknown>
 
 usmopa  za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-INST: usmopa  za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-ENCODING: [0x45,0x55,0xd5,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 45 55 d5 a1 <unknown>
+// CHECK-UNKNOWN: a1d55545 <unknown>
 
 usmopa  za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-INST: usmopa  za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-ENCODING: [0xa7,0xed,0xc8,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: a7 ed c8 a1 <unknown>
+// CHECK-UNKNOWN: a1c8eda7 <unknown>
 
 usmopa  za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-INST: usmopa  za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xe7,0xff,0xdf,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: e7 ff df a1 <unknown>
+// CHECK-UNKNOWN: a1dfffe7 <unknown>
 
 usmopa  za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-INST: usmopa  za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-ENCODING: [0x25,0x0e,0xd0,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 25 0e d0 a1 <unknown>
+// CHECK-UNKNOWN: a1d00e25 <unknown>
 
 usmopa  za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-INST: usmopa  za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-ENCODING: [0x21,0x84,0xde,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 21 84 de a1 <unknown>
+// CHECK-UNKNOWN: a1de8421 <unknown>
 
 usmopa  za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-INST: usmopa  za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-ENCODING: [0x60,0x56,0xd4,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 60 56 d4 a1 <unknown>
+// CHECK-UNKNOWN: a1d45660 <unknown>
 
 usmopa  za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-INST: usmopa  za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-ENCODING: [0x80,0x19,0xc2,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 80 19 c2 a1 <unknown>
+// CHECK-UNKNOWN: a1c21980 <unknown>
 
 usmopa  za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-INST: usmopa  za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-ENCODING: [0x21,0xc8,0xda,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 21 c8 da a1 <unknown>
+// CHECK-UNKNOWN: a1dac821 <unknown>
 
 usmopa  za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-INST: usmopa  za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-ENCODING: [0xc5,0x0a,0xde,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: c5 0a de a1 <unknown>
+// CHECK-UNKNOWN: a1de0ac5 <unknown>
 
 usmopa  za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-INST: usmopa  za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-ENCODING: [0x22,0xf5,0xc1,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 22 f5 c1 a1 <unknown>
+// CHECK-UNKNOWN: a1c1f522 <unknown>
 
 usmopa  za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-INST: usmopa  za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-ENCODING: [0x87,0xa9,0xcb,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 87 a9 cb a1 <unknown>
+// CHECK-UNKNOWN: a1cba987 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/usmops-32.s b/llvm/test/MC/AArch64/SME/usmops-32.s
index aff37daa7da66..c86586b92f3d6 100644
--- a/llvm/test/MC/AArch64/SME/usmops-32.s
+++ b/llvm/test/MC/AArch64/SME/usmops-32.s
@@ -16,70 +16,70 @@ usmops  za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-INST: usmops  za0.s, p0/m, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x10,0x00,0x80,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 10 00 80 a1 <unknown>
+// CHECK-UNKNOWN: a1800010 <unknown>
 
 usmops  za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-INST: usmops  za1.s, p5/m, p2/m, z10.b, z21.b
 // CHECK-ENCODING: [0x51,0x55,0x95,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 51 55 95 a1 <unknown>
+// CHECK-UNKNOWN: a1955551 <unknown>
 
 usmops  za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-INST: usmops  za3.s, p3/m, p7/m, z13.b, z8.b
 // CHECK-ENCODING: [0xb3,0xed,0x88,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b3 ed 88 a1 <unknown>
+// CHECK-UNKNOWN: a188edb3 <unknown>
 
 usmops  za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-INST: usmops  za3.s, p7/m, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xf3,0xff,0x9f,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: f3 ff 9f a1 <unknown>
+// CHECK-UNKNOWN: a19ffff3 <unknown>
 
 usmops  za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-INST: usmops  za1.s, p3/m, p0/m, z17.b, z16.b
 // CHECK-ENCODING: [0x31,0x0e,0x90,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 0e 90 a1 <unknown>
+// CHECK-UNKNOWN: a1900e31 <unknown>
 
 usmops  za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-INST: usmops  za1.s, p1/m, p4/m, z1.b, z30.b
 // CHECK-ENCODING: [0x31,0x84,0x9e,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 84 9e a1 <unknown>
+// CHECK-UNKNOWN: a19e8431 <unknown>
 
 usmops  za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-INST: usmops  za0.s, p5/m, p2/m, z19.b, z20.b
 // CHECK-ENCODING: [0x70,0x56,0x94,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 70 56 94 a1 <unknown>
+// CHECK-UNKNOWN: a1945670 <unknown>
 
 usmops  za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-INST: usmops  za0.s, p6/m, p0/m, z12.b, z2.b
 // CHECK-ENCODING: [0x90,0x19,0x82,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 90 19 82 a1 <unknown>
+// CHECK-UNKNOWN: a1821990 <unknown>
 
 usmops  za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-INST: usmops  za1.s, p2/m, p6/m, z1.b, z26.b
 // CHECK-ENCODING: [0x31,0xc8,0x9a,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 31 c8 9a a1 <unknown>
+// CHECK-UNKNOWN: a19ac831 <unknown>
 
 usmops  za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-INST: usmops  za1.s, p2/m, p0/m, z22.b, z30.b
 // CHECK-ENCODING: [0xd1,0x0a,0x9e,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: d1 0a 9e a1 <unknown>
+// CHECK-UNKNOWN: a19e0ad1 <unknown>
 
 usmops  za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-INST: usmops  za2.s, p5/m, p7/m, z9.b, z1.b
 // CHECK-ENCODING: [0x32,0xf5,0x81,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 32 f5 81 a1 <unknown>
+// CHECK-UNKNOWN: a181f532 <unknown>
 
 usmops  za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-INST: usmops  za3.s, p2/m, p5/m, z12.b, z11.b
 // CHECK-ENCODING: [0x93,0xa9,0x8b,0xa1]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 93 a9 8b a1 <unknown>
+// CHECK-UNKNOWN: a18ba993 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/usmops-64.s b/llvm/test/MC/AArch64/SME/usmops-64.s
index 8100984a06196..a72596a882f07 100644
--- a/llvm/test/MC/AArch64/SME/usmops-64.s
+++ b/llvm/test/MC/AArch64/SME/usmops-64.s
@@ -16,70 +16,70 @@ usmops  za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-INST: usmops  za0.d, p0/m, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x10,0x00,0xc0,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 10 00 c0 a1 <unknown>
+// CHECK-UNKNOWN: a1c00010 <unknown>
 
 usmops  za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-INST: usmops  za5.d, p5/m, p2/m, z10.h, z21.h
 // CHECK-ENCODING: [0x55,0x55,0xd5,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 55 55 d5 a1 <unknown>
+// CHECK-UNKNOWN: a1d55555 <unknown>
 
 usmops  za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-INST: usmops  za7.d, p3/m, p7/m, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0xed,0xc8,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: b7 ed c8 a1 <unknown>
+// CHECK-UNKNOWN: a1c8edb7 <unknown>
 
 usmops  za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-INST: usmops  za7.d, p7/m, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xf7,0xff,0xdf,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: f7 ff df a1 <unknown>
+// CHECK-UNKNOWN: a1dffff7 <unknown>
 
 usmops  za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-INST: usmops  za5.d, p3/m, p0/m, z17.h, z16.h
 // CHECK-ENCODING: [0x35,0x0e,0xd0,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 35 0e d0 a1 <unknown>
+// CHECK-UNKNOWN: a1d00e35 <unknown>
 
 usmops  za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-INST: usmops  za1.d, p1/m, p4/m, z1.h, z30.h
 // CHECK-ENCODING: [0x31,0x84,0xde,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 31 84 de a1 <unknown>
+// CHECK-UNKNOWN: a1de8431 <unknown>
 
 usmops  za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-INST: usmops  za0.d, p5/m, p2/m, z19.h, z20.h
 // CHECK-ENCODING: [0x70,0x56,0xd4,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 70 56 d4 a1 <unknown>
+// CHECK-UNKNOWN: a1d45670 <unknown>
 
 usmops  za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-INST: usmops  za0.d, p6/m, p0/m, z12.h, z2.h
 // CHECK-ENCODING: [0x90,0x19,0xc2,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 90 19 c2 a1 <unknown>
+// CHECK-UNKNOWN: a1c21990 <unknown>
 
 usmops  za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-INST: usmops  za1.d, p2/m, p6/m, z1.h, z26.h
 // CHECK-ENCODING: [0x31,0xc8,0xda,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 31 c8 da a1 <unknown>
+// CHECK-UNKNOWN: a1dac831 <unknown>
 
 usmops  za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-INST: usmops  za5.d, p2/m, p0/m, z22.h, z30.h
 // CHECK-ENCODING: [0xd5,0x0a,0xde,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: d5 0a de a1 <unknown>
+// CHECK-UNKNOWN: a1de0ad5 <unknown>
 
 usmops  za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-INST: usmops  za2.d, p5/m, p7/m, z9.h, z1.h
 // CHECK-ENCODING: [0x32,0xf5,0xc1,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 32 f5 c1 a1 <unknown>
+// CHECK-UNKNOWN: a1c1f532 <unknown>
 
 usmops  za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-INST: usmops  za7.d, p2/m, p5/m, z12.h, z11.h
 // CHECK-ENCODING: [0x97,0xa9,0xcb,0xa1]
 // CHECK-ERROR: instruction requires: sme-i64
-// CHECK-UNKNOWN: 97 a9 cb a1 <unknown>
+// CHECK-UNKNOWN: a1cba997 <unknown>

diff  --git a/llvm/test/MC/AArch64/SME/zero.s b/llvm/test/MC/AArch64/SME/zero.s
index 5a00d4b533ec1..9a433020eaf84 100644
--- a/llvm/test/MC/AArch64/SME/zero.s
+++ b/llvm/test/MC/AArch64/SME/zero.s
@@ -16,25 +16,25 @@ zero    {}
 // CHECK-INST: zero    {}
 // CHECK-ENCODING: [0x00,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 00 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080000 <unknown>
 
 zero    {za0.d, za2.d, za4.d, za6.d}
 // CHECK-INST: zero {za0.h}
 // CHECK-ENCODING: [0x55,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080055 <unknown>
 
 zero    {za0.d, za1.d, za2.d, za4.d, za5.d, za7.d}
 // CHECK-INST: zero    {za0.d, za1.d, za2.d, za4.d, za5.d, za7.d}
 // CHECK-ENCODING: [0xb7,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: b7 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800b7 <unknown>
 
 zero    {za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d}
 // CHECK-INST: zero {za}
 // CHECK-ENCODING: [0xff,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800ff <unknown>
 
 // --------------------------------------------------------------------------//
 // Aliases
@@ -43,208 +43,208 @@ zero {za}
 // CHECK-INST: zero {za}
 // CHECK-ENCODING: [0xff,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800ff <unknown>
 
 zero {za0.b}
 // CHECK-INST: zero {za}
 // CHECK-ENCODING: [0xff,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800ff <unknown>
 
 zero {za0.h}
 // CHECK-INST: zero {za0.h}
 // CHECK-ENCODING: [0x55,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080055 <unknown>
 
 zero {za1.h}
 // CHECK-INST: zero {za1.h}
 // CHECK-ENCODING: [0xaa,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: aa 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800aa <unknown>
 
 zero {za0.h,za1.h}
 // CHECK-INST: zero {za}
 // CHECK-ENCODING: [0xff,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800ff <unknown>
 
 zero {za0.s}
 // CHECK-INST: zero {za0.s}
 // CHECK-ENCODING: [0x11,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 11 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080011 <unknown>
 
 zero {za1.s}
 // CHECK-INST: zero {za1.s}
 // CHECK-ENCODING: [0x22,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080022 <unknown>
 
 zero {za2.s}
 // CHECK-INST: zero {za2.s}
 // CHECK-ENCODING: [0x44,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 44 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080044 <unknown>
 
 zero {za3.s}
 // CHECK-INST: zero {za3.s}
 // CHECK-ENCODING: [0x88,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 88 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080088 <unknown>
 
 zero {za0.s,za1.s}
 // CHECK-INST: zero {za0.s,za1.s}
 // CHECK-ENCODING: [0x33,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 33 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080033 <unknown>
 
 zero {za0.s,za2.s}
 // CHECK-INST: zero {za0.h}
 // CHECK-ENCODING: [0x55,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080055 <unknown>
 
 zero {za0.s,za3.s}
 // CHECK-INST: zero {za0.s,za3.s}
 // CHECK-ENCODING: [0x99,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 99 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080099 <unknown>
 
 zero {za1.s,za2.s}
 // CHECK-INST: zero {za1.s,za2.s}
 // CHECK-ENCODING: [0x66,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 66 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080066 <unknown>
 
 zero {za1.s,za3.s}
 // CHECK-INST: zero {za1.h}
 // CHECK-ENCODING: [0xaa,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: aa 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800aa <unknown>
 
 zero {za2.s,za3.s}
 // CHECK-INST: zero {za2.s,za3.s}
 // CHECK-ENCODING: [0xcc,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cc 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800cc <unknown>
 
 zero {za0.s,za1.s,za2.s}
 // CHECK-INST: zero {za0.s,za1.s,za2.s}
 // CHECK-ENCODING: [0x77,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 77 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080077 <unknown>
 
 zero {za0.s,za1.s,za3.s}
 // CHECK-INST: zero {za0.s,za1.s,za3.s}
 // CHECK-ENCODING: [0xbb,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: bb 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800bb <unknown>
 
 zero {za0.s,za2.s,za3.s}
 // CHECK-INST: zero {za0.s,za2.s,za3.s}
 // CHECK-ENCODING: [0xdd,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800dd <unknown>
 
 zero {za1.s,za2.s,za3.s}
 // CHECK-INST: zero {za1.s,za2.s,za3.s}
 // CHECK-ENCODING: [0xee,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ee 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800ee <unknown>
 
 zero {za0.s,za1.s,za2.s,za3.s}
 // CHECK-INST: zero {za}
 // CHECK-ENCODING: [0xff,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800ff <unknown>
 
 zero {za0.d,za1.d,za2.d,za3.d,za4.d,za5.d,za6.d,za7.d}
 // CHECK-INST: zero {za}
 // CHECK-ENCODING: [0xff,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ff 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800ff <unknown>
 
 zero {za0.d,za2.d,za4.d,za6.d}
 // CHECK-INST: zero {za0.h}
 // CHECK-ENCODING: [0x55,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 55 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080055 <unknown>
 
 zero {za1.d,za3.d,za5.d,za7.d}
 // CHECK-INST: zero {za1.h}
 // CHECK-ENCODING: [0xaa,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: aa 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800aa <unknown>
 
 zero {za0.d,za4.d}
 // CHECK-INST: zero {za0.s}
 // CHECK-ENCODING: [0x11,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 11 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080011 <unknown>
 
 zero {za1.d,za5.d}
 // CHECK-INST: zero {za1.s}
 // CHECK-ENCODING: [0x22,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 22 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080022 <unknown>
 
 zero {za2.d,za6.d}
 // CHECK-INST: zero {za2.s}
 // CHECK-ENCODING: [0x44,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 44 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080044 <unknown>
 
 zero {za3.d,za7.d}
 // CHECK-INST: zero {za3.s}
 // CHECK-ENCODING: [0x88,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 88 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080088 <unknown>
 
 zero {za0.d,za1.d,za4.d,za5.d}
 // CHECK-INST: zero {za0.s,za1.s}
 // CHECK-ENCODING: [0x33,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 33 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080033 <unknown>
 
 zero {za0.d,za3.d,za4.d,za7.d}
 // CHECK-INST: zero {za0.s,za3.s}
 // CHECK-ENCODING: [0x99,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 99 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080099 <unknown>
 
 zero {za1.d,za2.d,za5.d,za6.d}
 // CHECK-INST: zero {za1.s,za2.s}
 // CHECK-ENCODING: [0x66,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 66 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080066 <unknown>
 
 zero {za2.d,za3.d,za6.d,za7.d}
 // CHECK-INST: zero {za2.s,za3.s}
 // CHECK-ENCODING: [0xcc,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: cc 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800cc <unknown>
 
 zero {za0.d,za1.d,za2.d,za4.d,za5.d,za6.d}
 // CHECK-INST: zero {za0.s,za1.s,za2.s}
 // CHECK-ENCODING: [0x77,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: 77 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c0080077 <unknown>
 
 zero {za0.d,za1.d,za3.d,za4.d,za5.d,za7.d}
 // CHECK-INST: zero {za0.s,za1.s,za3.s}
 // CHECK-ENCODING: [0xbb,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: bb 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800bb <unknown>
 
 zero {za0.d,za2.d,za3.d,za4.d,za6.d,za7.d}
 // CHECK-INST: zero {za0.s,za2.s,za3.s}
 // CHECK-ENCODING: [0xdd,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: dd 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800dd <unknown>
 
 zero {za1.d,za2.d,za3.d,za5.d,za6.d,za7.d}
 // CHECK-INST: zero {za1.s,za2.s,za3.s}
 // CHECK-ENCODING: [0xee,0x00,0x08,0xc0]
 // CHECK-ERROR: instruction requires: sme
-// CHECK-UNKNOWN: ee 00 08 c0 <unknown>
+// CHECK-UNKNOWN: c00800ee <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/abs.s b/llvm/test/MC/AArch64/SVE/abs.s
index 1e6ae376535ab..87350dc8a1b55 100644
--- a/llvm/test/MC/AArch64/SVE/abs.s
+++ b/llvm/test/MC/AArch64/SVE/abs.s
@@ -13,49 +13,49 @@ abs     z0.b, p0/m, z0.b
 // CHECK-INST: abs     z0.b, p0/m, z0.b
 // CHECK-ENCODING: [0x00,0xa0,0x16,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 16 04 <unknown>
+// CHECK-UNKNOWN: 0416a000 <unknown>
 
 abs     z0.h, p0/m, z0.h
 // CHECK-INST: abs     z0.h, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x56,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 56 04 <unknown>
+// CHECK-UNKNOWN: 0456a000 <unknown>
 
 abs     z0.s, p0/m, z0.s
 // CHECK-INST: abs     z0.s, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x96,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 96 04 <unknown>
+// CHECK-UNKNOWN: 0496a000 <unknown>
 
 abs     z0.d, p0/m, z0.d
 // CHECK-INST: abs     z0.d, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd6,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d6 04 <unknown>
+// CHECK-UNKNOWN: 04d6a000 <unknown>
 
 abs     z31.b, p7/m, z31.b
 // CHECK-INST: abs     z31.b, p7/m, z31.b
 // CHECK-ENCODING: [0xff,0xbf,0x16,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 16 04 <unknown>
+// CHECK-UNKNOWN: 0416bfff <unknown>
 
 abs     z31.h, p7/m, z31.h
 // CHECK-INST: abs     z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x56,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 56 04 <unknown>
+// CHECK-UNKNOWN: 0456bfff <unknown>
 
 abs     z31.s, p7/m, z31.s
 // CHECK-INST: abs     z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x96,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 96 04 <unknown>
+// CHECK-UNKNOWN: 0496bfff <unknown>
 
 abs     z31.d, p7/m, z31.d
 // CHECK-INST: abs     z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xd6,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf d6 04 <unknown>
+// CHECK-UNKNOWN: 04d6bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -65,22 +65,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 abs     z4.d, p7/m, z31.d
 // CHECK-INST: abs	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd6,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d6 04 <unknown>
+// CHECK-UNKNOWN: 04d6bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 abs     z4.d, p7/m, z31.d
 // CHECK-INST: abs	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd6,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d6 04 <unknown>
+// CHECK-UNKNOWN: 04d6bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/add.s b/llvm/test/MC/AArch64/SVE/add.s
index 39594d063bb41..07134b7e514e0 100644
--- a/llvm/test/MC/AArch64/SVE/add.s
+++ b/llvm/test/MC/AArch64/SVE/add.s
@@ -13,277 +13,277 @@ add     z31.s, z31.s, z31.s
 // CHECK-INST: add     z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x03,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 03 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf03ff <unknown>
 
 add     z23.d, z13.d, z8.d
 // CHECK-INST: add     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x01,0xe8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 01 e8 04 <unknown>
+// CHECK-UNKNOWN: 04e801b7 <unknown>
 
 add     z23.b, p3/m, z23.b, z13.b
 // CHECK-INST: add     z23.b, p3/m, z23.b, z13.b
 // CHECK-ENCODING: [0xb7,0x0d,0x00,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 0d 00 04 <unknown>
+// CHECK-UNKNOWN: 04000db7 <unknown>
 
 add     z0.s, z0.s, z0.s
 // CHECK-INST: add     z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x00,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a00000 <unknown>
 
 add     z31.d, z31.d, z31.d
 // CHECK-INST: add     z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x03,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 03 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff03ff <unknown>
 
 add     z21.b, z10.b, z21.b
 // CHECK-INST: add     z21.b, z10.b, z21.b
 // CHECK-ENCODING: [0x55,0x01,0x35,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 01 35 04 <unknown>
+// CHECK-UNKNOWN: 04350155 <unknown>
 
 add     z31.b, z31.b, z31.b
 // CHECK-INST: add     z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x03,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 03 3f 04 <unknown>
+// CHECK-UNKNOWN: 043f03ff <unknown>
 
 add     z0.h, p0/m, z0.h, z0.h
 // CHECK-INST: add     z0.h, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x00,0x40,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 40 04 <unknown>
+// CHECK-UNKNOWN: 04400000 <unknown>
 
 add     z0.h, z0.h, z0.h
 // CHECK-INST: add     z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x00,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 60 04 <unknown>
+// CHECK-UNKNOWN: 04600000 <unknown>
 
 add     z0.b, p0/m, z0.b, z0.b
 // CHECK-INST: add     z0.b, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x00,0x00,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 00 04 <unknown>
+// CHECK-UNKNOWN: 04000000 <unknown>
 
 add     z0.s, p0/m, z0.s, z0.s
 // CHECK-INST: add     z0.s, p0/m, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x00,0x80,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 80 04 <unknown>
+// CHECK-UNKNOWN: 04800000 <unknown>
 
 add     z23.b, z13.b, z8.b
 // CHECK-INST: add     z23.b, z13.b, z8.b
 // CHECK-ENCODING: [0xb7,0x01,0x28,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 01 28 04 <unknown>
+// CHECK-UNKNOWN: 042801b7 <unknown>
 
 add     z0.d, z0.d, z0.d
 // CHECK-INST: add     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x00,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e00000 <unknown>
 
 add     z0.d, p0/m, z0.d, z0.d
 // CHECK-INST: add     z0.d, p0/m, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x00,0xc0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 c0 04 <unknown>
+// CHECK-UNKNOWN: 04c00000 <unknown>
 
 add     z31.h, z31.h, z31.h
 // CHECK-INST: add     z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x03,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 03 7f 04 <unknown>
+// CHECK-UNKNOWN: 047f03ff <unknown>
 
 add     z0.b, z0.b, z0.b
 // CHECK-INST: add     z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x00,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 20 04 <unknown>
+// CHECK-UNKNOWN: 04200000 <unknown>
 
 add     z21.d, z10.d, z21.d
 // CHECK-INST: add     z21.d, z10.d, z21.d
 // CHECK-ENCODING: [0x55,0x01,0xf5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 01 f5 04 <unknown>
+// CHECK-UNKNOWN: 04f50155 <unknown>
 
 add     z23.h, p3/m, z23.h, z13.h
 // CHECK-INST: add     z23.h, p3/m, z23.h, z13.h
 // CHECK-ENCODING: [0xb7,0x0d,0x40,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 0d 40 04 <unknown>
+// CHECK-UNKNOWN: 04400db7 <unknown>
 
 add     z23.s, p3/m, z23.s, z13.s
 // CHECK-INST: add     z23.s, p3/m, z23.s, z13.s
 // CHECK-ENCODING: [0xb7,0x0d,0x80,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 0d 80 04 <unknown>
+// CHECK-UNKNOWN: 04800db7 <unknown>
 
 add     z31.s, p7/m, z31.s, z31.s
 // CHECK-INST: add     z31.s, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1f,0x80,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 80 04 <unknown>
+// CHECK-UNKNOWN: 04801fff <unknown>
 
 add     z21.h, z10.h, z21.h
 // CHECK-INST: add     z21.h, z10.h, z21.h
 // CHECK-ENCODING: [0x55,0x01,0x75,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 01 75 04 <unknown>
+// CHECK-UNKNOWN: 04750155 <unknown>
 
 add     z23.d, p3/m, z23.d, z13.d
 // CHECK-INST: add     z23.d, p3/m, z23.d, z13.d
 // CHECK-ENCODING: [0xb7,0x0d,0xc0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 0d c0 04 <unknown>
+// CHECK-UNKNOWN: 04c00db7 <unknown>
 
 add     z21.d, p5/m, z21.d, z10.d
 // CHECK-INST: add     z21.d, p5/m, z21.d, z10.d
 // CHECK-ENCODING: [0x55,0x15,0xc0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 15 c0 04 <unknown>
+// CHECK-UNKNOWN: 04c01555 <unknown>
 
 add     z21.b, p5/m, z21.b, z10.b
 // CHECK-INST: add     z21.b, p5/m, z21.b, z10.b
 // CHECK-ENCODING: [0x55,0x15,0x00,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 15 00 04 <unknown>
+// CHECK-UNKNOWN: 04001555 <unknown>
 
 add     z21.s, z10.s, z21.s
 // CHECK-INST: add     z21.s, z10.s, z21.s
 // CHECK-ENCODING: [0x55,0x01,0xb5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 01 b5 04 <unknown>
+// CHECK-UNKNOWN: 04b50155 <unknown>
 
 add     z21.h, p5/m, z21.h, z10.h
 // CHECK-INST: add     z21.h, p5/m, z21.h, z10.h
 // CHECK-ENCODING: [0x55,0x15,0x40,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 15 40 04 <unknown>
+// CHECK-UNKNOWN: 04401555 <unknown>
 
 add     z31.h, p7/m, z31.h, z31.h
 // CHECK-INST: add     z31.h, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x1f,0x40,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 40 04 <unknown>
+// CHECK-UNKNOWN: 04401fff <unknown>
 
 add     z23.h, z13.h, z8.h
 // CHECK-INST: add     z23.h, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0x01,0x68,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 01 68 04 <unknown>
+// CHECK-UNKNOWN: 046801b7 <unknown>
 
 add     z31.d, p7/m, z31.d, z31.d
 // CHECK-INST: add     z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xc0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f c0 04 <unknown>
+// CHECK-UNKNOWN: 04c01fff <unknown>
 
 add     z21.s, p5/m, z21.s, z10.s
 // CHECK-INST: add     z21.s, p5/m, z21.s, z10.s
 // CHECK-ENCODING: [0x55,0x15,0x80,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 15 80 04 <unknown>
+// CHECK-UNKNOWN: 04801555 <unknown>
 
 add     z31.b, p7/m, z31.b, z31.b
 // CHECK-INST: add     z31.b, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x1f,0x00,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 00 04 <unknown>
+// CHECK-UNKNOWN: 04001fff <unknown>
 
 add     z23.s, z13.s, z8.s
 // CHECK-INST: add     z23.s, z13.s, z8.s
 // CHECK-ENCODING: [0xb7,0x01,0xa8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 01 a8 04 <unknown>
+// CHECK-UNKNOWN: 04a801b7 <unknown>
 
 add     z0.b, z0.b, #0
 // CHECK-INST: add     z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 20 25 <unknown>
+// CHECK-UNKNOWN: 2520c000 <unknown>
 
 add     z31.b, z31.b, #255
 // CHECK-INST: add     z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 20 25 <unknown>
+// CHECK-UNKNOWN: 2520dfff <unknown>
 
 add     z0.h, z0.h, #0
 // CHECK-INST: add     z0.h, z0.h, #0
 // CHECK-ENCODING: [0x00,0xc0,0x60,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 60 25 <unknown>
+// CHECK-UNKNOWN: 2560c000 <unknown>
 
 add     z0.h, z0.h, #0, lsl #8
 // CHECK-INST: add     z0.h, z0.h, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0x60,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 60 25 <unknown>
+// CHECK-UNKNOWN: 2560e000 <unknown>
 
 add     z31.h, z31.h, #255, lsl #8
 // CHECK-INST: add     z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x60,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 60 25 <unknown>
+// CHECK-UNKNOWN: 2560ffff <unknown>
 
 add     z31.h, z31.h, #65280
 // CHECK-INST: add     z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x60,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 60 25 <unknown>
+// CHECK-UNKNOWN: 2560ffff <unknown>
 
 add     z0.s, z0.s, #0
 // CHECK-INST: add     z0.s, z0.s, #0
 // CHECK-ENCODING: [0x00,0xc0,0xa0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 a0 25 <unknown>
+// CHECK-UNKNOWN: 25a0c000 <unknown>
 
 add     z0.s, z0.s, #0, lsl #8
 // CHECK-INST: add     z0.s, z0.s, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xa0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 a0 25 <unknown>
+// CHECK-UNKNOWN: 25a0e000 <unknown>
 
 add     z31.s, z31.s, #255, lsl #8
 // CHECK-INST: add     z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a0 25 <unknown>
+// CHECK-UNKNOWN: 25a0ffff <unknown>
 
 add     z31.s, z31.s, #65280
 // CHECK-INST: add     z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a0 25 <unknown>
+// CHECK-UNKNOWN: 25a0ffff <unknown>
 
 add     z0.d, z0.d, #0
 // CHECK-INST: add     z0.d, z0.d, #0
 // CHECK-ENCODING: [0x00,0xc0,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 e0 25 <unknown>
+// CHECK-UNKNOWN: 25e0c000 <unknown>
 
 add     z0.d, z0.d, #0, lsl #8
 // CHECK-INST: add     z0.d, z0.d, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e0 25 <unknown>
+// CHECK-UNKNOWN: 25e0e000 <unknown>
 
 add     z31.d, z31.d, #255, lsl #8
 // CHECK-INST: add     z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e0 25 <unknown>
+// CHECK-UNKNOWN: 25e0ffff <unknown>
 
 add     z31.d, z31.d, #65280
 // CHECK-INST: add     z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e0 25 <unknown>
+// CHECK-UNKNOWN: 25e0ffff <unknown>
 
 
 
@@ -294,34 +294,34 @@ movprfx z4.b, p7/z, z6.b
 // CHECK-INST: movprfx	z4.b, p7/z, z6.b
 // CHECK-ENCODING: [0xc4,0x3c,0x10,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c 10 04 <unknown>
+// CHECK-UNKNOWN: 04103cc4 <unknown>
 
 add     z4.b, p7/m, z4.b, z31.b
 // CHECK-INST: add	z4.b, p7/m, z4.b, z31.b
 // CHECK-ENCODING: [0xe4,0x1f,0x00,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f 00 04 <unknown>
+// CHECK-UNKNOWN: 04001fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 add     z4.b, p7/m, z4.b, z31.b
 // CHECK-INST: add	z4.b, p7/m, z4.b, z31.b
 // CHECK-ENCODING: [0xe4,0x1f,0x00,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f 00 04 <unknown>
+// CHECK-UNKNOWN: 04001fe4 <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 add     z31.d, z31.d, #65280
 // CHECK-INST: add	z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e0 25 <unknown>
+// CHECK-UNKNOWN: 25e0ffff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/addpl.s b/llvm/test/MC/AArch64/SVE/addpl.s
index 3ec731bb6d361..ec30d6c353629 100644
--- a/llvm/test/MC/AArch64/SVE/addpl.s
+++ b/llvm/test/MC/AArch64/SVE/addpl.s
@@ -13,22 +13,22 @@ addpl   x21, x21, #0
 // CHECK-INST: addpl   x21, x21, #0
 // CHECK-ENCODING: [0x15,0x50,0x75,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 50 75 04 <unknown>
+// CHECK-UNKNOWN: 04755015 <unknown>
 
 addpl   x23, x8, #-1
 // CHECK-INST: addpl   x23, x8, #-1
 // CHECK-ENCODING: [0xf7,0x57,0x68,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f7 57 68 04 <unknown>
+// CHECK-UNKNOWN: 046857f7 <unknown>
 
 addpl   sp, sp, #31
 // CHECK-INST: addpl   sp, sp, #31
 // CHECK-ENCODING: [0xff,0x53,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 53 7f 04 <unknown>
+// CHECK-UNKNOWN: 047f53ff <unknown>
 
 addpl   x0, x0, #-32
 // CHECK-INST: addpl   x0, x0, #-32
 // CHECK-ENCODING: [0x00,0x54,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 54 60 04 <unknown>
+// CHECK-UNKNOWN: 04605400 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/addvl.s b/llvm/test/MC/AArch64/SVE/addvl.s
index 793664ca2ebe5..45c970c37f1da 100644
--- a/llvm/test/MC/AArch64/SVE/addvl.s
+++ b/llvm/test/MC/AArch64/SVE/addvl.s
@@ -13,22 +13,22 @@ addvl   x21, x21, #0
 // CHECK-INST: addvl   x21, x21, #0
 // CHECK-ENCODING: [0x15,0x50,0x35,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 50 35 04 <unknown>
+// CHECK-UNKNOWN: 04355015 <unknown>
 
 addvl   x23, x8, #-1
 // CHECK-INST: addvl   x23, x8, #-1
 // CHECK-ENCODING: [0xf7,0x57,0x28,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f7 57 28 04 <unknown>
+// CHECK-UNKNOWN: 042857f7 <unknown>
 
 addvl   sp, sp, #31
 // CHECK-INST: addvl   sp, sp, #31
 // CHECK-ENCODING: [0xff,0x53,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 53 3f 04 <unknown>
+// CHECK-UNKNOWN: 043f53ff <unknown>
 
 addvl   x0, x0, #-32
 // CHECK-INST: addvl   x0, x0, #-32
 // CHECK-ENCODING: [0x00,0x54,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 54 20 04 <unknown>
+// CHECK-UNKNOWN: 04205400 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/adr.s b/llvm/test/MC/AArch64/SVE/adr.s
index 1dd2ab55ac13d..3751a662841f9 100644
--- a/llvm/test/MC/AArch64/SVE/adr.s
+++ b/llvm/test/MC/AArch64/SVE/adr.s
@@ -11,118 +11,118 @@ adr     z0.s, [z0.s, z0.s]
 // CHECK-INST: adr z0.s, [z0.s, z0.s]
 // CHECK-ENCODING: [0x00,0xa0,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0a000 <unknown>
 
 adr     z0.s, [z0.s, z0.s, lsl #0]
 // CHECK-INST: adr z0.s, [z0.s, z0.s]
 // CHECK-ENCODING: [0x00,0xa0,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0a000 <unknown>
 
 adr     z0.s, [z0.s, z0.s, lsl #1]
 // CHECK-INST: adr z0.s, [z0.s, z0.s, lsl #1]
 // CHECK-ENCODING: [0x00,0xa4,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a4 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0a400 <unknown>
 
 adr     z0.s, [z0.s, z0.s, lsl #2]
 // CHECK-INST: adr z0.s, [z0.s, z0.s, lsl #2]
 // CHECK-ENCODING: [0x00,0xa8,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a8 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0a800 <unknown>
 
 adr     z0.s, [z0.s, z0.s, lsl #3]
 // CHECK-INST: adr z0.s, [z0.s, z0.s, lsl #3]
 // CHECK-ENCODING: [0x00,0xac,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 ac a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0ac00 <unknown>
 
 adr     z0.d, [z0.d, z0.d]
 // CHECK-INST: adr z0.d, [z0.d, z0.d]
 // CHECK-ENCODING: [0x00,0xa0,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0a000 <unknown>
 
 adr     z0.d, [z0.d, z0.d, lsl #0]
 // CHECK-INST: adr z0.d, [z0.d, z0.d]
 // CHECK-ENCODING: [0x00,0xa0,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0a000 <unknown>
 
 adr     z0.d, [z0.d, z0.d, lsl #1]
 // CHECK-INST: adr z0.d, [z0.d, z0.d, lsl #1]
 // CHECK-ENCODING: [0x00,0xa4,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a4 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0a400 <unknown>
 
 adr     z0.d, [z0.d, z0.d, lsl #2]
 // CHECK-INST: adr z0.d, [z0.d, z0.d, lsl #2]
 // CHECK-ENCODING: [0x00,0xa8,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a8 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0a800 <unknown>
 
 adr     z0.d, [z0.d, z0.d, lsl #3]
 // CHECK-INST: adr z0.d, [z0.d, z0.d, lsl #3]
 // CHECK-ENCODING: [0x00,0xac,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 ac e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0ac00 <unknown>
 
 adr     z0.d, [z0.d, z0.d, uxtw]
 // CHECK-INST: adr z0.d, [z0.d, z0.d, uxtw]
 // CHECK-ENCODING: [0x00,0xa0,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 60 04 <unknown>
+// CHECK-UNKNOWN: 0460a000 <unknown>
 
 adr     z0.d, [z0.d, z0.d, uxtw #0]
 // CHECK-INST: adr z0.d, [z0.d, z0.d, uxtw]
 // CHECK-ENCODING: [0x00,0xa0,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 60 04 <unknown>
+// CHECK-UNKNOWN: 0460a000 <unknown>
 
 adr     z0.d, [z0.d, z0.d, uxtw #1]
 // CHECK-INST: adr z0.d, [z0.d, z0.d, uxtw #1]
 // CHECK-ENCODING: [0x00,0xa4,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a4 60 04 <unknown>
+// CHECK-UNKNOWN: 0460a400 <unknown>
 
 adr     z0.d, [z0.d, z0.d, uxtw #2]
 // CHECK-INST: adr z0.d, [z0.d, z0.d, uxtw #2]
 // CHECK-ENCODING: [0x00,0xa8,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a8 60 04 <unknown>
+// CHECK-UNKNOWN: 0460a800 <unknown>
 
 adr     z0.d, [z0.d, z0.d, uxtw #3]
 // CHECK-INST: adr z0.d, [z0.d, z0.d, uxtw #3]
 // CHECK-ENCODING: [0x00,0xac,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 ac 60 04 <unknown>
+// CHECK-UNKNOWN: 0460ac00 <unknown>
 
 adr     z0.d, [z0.d, z0.d, sxtw]
 // CHECK-INST: adr z0.d, [z0.d, z0.d, sxtw]
 // CHECK-ENCODING: [0x00,0xa0,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 20 04 <unknown>
+// CHECK-UNKNOWN: 0420a000 <unknown>
 
 adr     z0.d, [z0.d, z0.d, sxtw #0]
 // CHECK-INST: adr z0.d, [z0.d, z0.d, sxtw]
 // CHECK-ENCODING: [0x00,0xa0,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 20 04 <unknown>
+// CHECK-UNKNOWN: 0420a000 <unknown>
 
 adr     z0.d, [z0.d, z0.d, sxtw #1]
 // CHECK-INST: adr z0.d, [z0.d, z0.d, sxtw #1]
 // CHECK-ENCODING: [0x00,0xa4,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a4 20 04 <unknown>
+// CHECK-UNKNOWN: 0420a400 <unknown>
 
 adr     z0.d, [z0.d, z0.d, sxtw #2]
 // CHECK-INST: adr z0.d, [z0.d, z0.d, sxtw #2]
 // CHECK-ENCODING: [0x00,0xa8,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a8 20 04 <unknown>
+// CHECK-UNKNOWN: 0420a800 <unknown>
 
 adr     z0.d, [z0.d, z0.d, sxtw #3]
 // CHECK-INST: adr z0.d, [z0.d, z0.d, sxtw #3]
 // CHECK-ENCODING: [0x00,0xac,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 ac 20 04 <unknown>
+// CHECK-UNKNOWN: 0420ac00 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/and.s b/llvm/test/MC/AArch64/SVE/and.s
index 3c48541c63220..cc9ca6e86177a 100644
--- a/llvm/test/MC/AArch64/SVE/and.s
+++ b/llvm/test/MC/AArch64/SVE/and.s
@@ -13,103 +13,103 @@ and     z5.b, z5.b, #0xf9
 // CHECK-INST: and     z5.b, z5.b, #0xf9
 // CHECK-ENCODING: [0xa5,0x2e,0x80,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a5 2e 80 05 <unknown>
+// CHECK-UNKNOWN: 05802ea5 <unknown>
 
 and     z23.h, z23.h, #0xfff9
 // CHECK-INST: and     z23.h, z23.h, #0xfff9
 // CHECK-ENCODING: [0xb7,0x6d,0x80,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 6d 80 05 <unknown>
+// CHECK-UNKNOWN: 05806db7 <unknown>
 
 and     z0.s, z0.s, #0xfffffff9
 // CHECK-INST: and     z0.s, z0.s, #0xfffffff9
 // CHECK-ENCODING: [0xa0,0xeb,0x80,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 eb 80 05 <unknown>
+// CHECK-UNKNOWN: 0580eba0 <unknown>
 
 and     z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-INST: and     z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-ENCODING: [0xa0,0xef,0x83,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ef 83 05 <unknown>
+// CHECK-UNKNOWN: 0583efa0 <unknown>
 
 and     z5.b, z5.b, #0x6
 // CHECK-INST: and     z5.b, z5.b, #0x6
 // CHECK-ENCODING: [0x25,0x3e,0x80,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 3e 80 05 <unknown>
+// CHECK-UNKNOWN: 05803e25 <unknown>
 
 and     z23.h, z23.h, #0x6
 // CHECK-INST: and     z23.h, z23.h, #0x6
 // CHECK-ENCODING: [0x37,0x7c,0x80,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 37 7c 80 05 <unknown>
+// CHECK-UNKNOWN: 05807c37 <unknown>
 
 and     z0.s, z0.s, #0x6
 // CHECK-INST: and     z0.s, z0.s, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x80,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 80 05 <unknown>
+// CHECK-UNKNOWN: 0580f820 <unknown>
 
 and     z0.d, z0.d, #0x6
 // CHECK-INST: and     z0.d, z0.d, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x83,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 83 05 <unknown>
+// CHECK-UNKNOWN: 0583f820 <unknown>
 
 and     z0.d, z0.d, z0.d
 // CHECK-INST: and     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+// CHECK-UNKNOWN: 04203000 <unknown>
 
 and     z23.d, z13.d, z8.d
 // CHECK-INST: and     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x31,0x28,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 31 28 04 <unknown>
+// CHECK-UNKNOWN: 042831b7 <unknown>
 
 and     z31.b, p7/m, z31.b, z31.b
 // CHECK-INST: and     z31.b, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x1f,0x1a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 1a 04 <unknown>
+// CHECK-UNKNOWN: 041a1fff <unknown>
 
 and     z31.h, p7/m, z31.h, z31.h
 // CHECK-INST: and     z31.h, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x1f,0x5a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 5a 04 <unknown>
+// CHECK-UNKNOWN: 045a1fff <unknown>
 
 and     z31.s, p7/m, z31.s, z31.s
 // CHECK-INST: and     z31.s, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1f,0x9a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 9a 04 <unknown>
+// CHECK-UNKNOWN: 049a1fff <unknown>
 
 and     z31.d, p7/m, z31.d, z31.d
 // CHECK-INST: and     z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xda,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f da 04 <unknown>
+// CHECK-UNKNOWN: 04da1fff <unknown>
 
 and     p0.b, p0/z, p0.b, p1.b
 // CHECK-INST: and     p0.b, p0/z, p0.b, p1.b
 // CHECK-ENCODING: [0x00,0x40,0x01,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 01 25 <unknown>
+// CHECK-UNKNOWN: 25014000 <unknown>
 
 and     p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: mov     p0.b, p0/z, p0.b
 // CHECK-ENCODING: [0x00,0x40,0x00,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 00 25 <unknown>
+// CHECK-UNKNOWN: 25004000 <unknown>
 
 and     p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: mov     p15.b, p15/z, p15.b
 // CHECK-ENCODING: [0xef,0x7d,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7d 0f 25 <unknown>
+// CHECK-UNKNOWN: 250f7def <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -119,19 +119,19 @@ and     z0.s, z0.s, z0.s
 // CHECK-INST: and     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+// CHECK-UNKNOWN: 04203000 <unknown>
 
 and     z0.h, z0.h, z0.h
 // CHECK-INST: and     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+// CHECK-UNKNOWN: 04203000 <unknown>
 
 and     z0.b, z0.b, z0.b
 // CHECK-INST: and     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+// CHECK-UNKNOWN: 04203000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -141,34 +141,34 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 and     z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: and	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xda,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f da 04 <unknown>
+// CHECK-UNKNOWN: 04da1fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 and     z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: and	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xda,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f da 04 <unknown>
+// CHECK-UNKNOWN: 04da1fe4 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 and     z0.d, z0.d, #0x6
 // CHECK-INST: and	z0.d, z0.d, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x83,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 83 05 <unknown>
+// CHECK-UNKNOWN: 0583f820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ands.s b/llvm/test/MC/AArch64/SVE/ands.s
index 42a76ce60888a..07eec3ad47801 100644
--- a/llvm/test/MC/AArch64/SVE/ands.s
+++ b/llvm/test/MC/AArch64/SVE/ands.s
@@ -13,17 +13,17 @@ ands    p0.b, p0/z, p0.b, p1.b
 // CHECK-INST: ands    p0.b, p0/z, p0.b, p1.b
 // CHECK-ENCODING: [0x00,0x40,0x41,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 41 25 <unknown>
+// CHECK-UNKNOWN: 25414000 <unknown>
 
 ands    p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: movs    p0.b, p0/z, p0.b
 // CHECK-ENCODING: [0x00,0x40,0x40,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 40 25 <unknown>
+// CHECK-UNKNOWN: 25404000 <unknown>
 
 ands    p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: movs    p15.b, p15/z, p15.b
 // CHECK-ENCODING: [0xef,0x7d,0x4f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7d 4f 25 <unknown>
+// CHECK-UNKNOWN: 254f7def <unknown>
 

diff  --git a/llvm/test/MC/AArch64/SVE/andv.s b/llvm/test/MC/AArch64/SVE/andv.s
index 19c71d12faceb..f734e984bad8f 100644
--- a/llvm/test/MC/AArch64/SVE/andv.s
+++ b/llvm/test/MC/AArch64/SVE/andv.s
@@ -13,22 +13,22 @@ andv b0, p7, z31.b
 // CHECK-INST: andv	b0, p7, z31.b
 // CHECK-ENCODING: [0xe0,0x3f,0x1a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 1a 04 <unknown>
+// CHECK-UNKNOWN: 041a3fe0 <unknown>
 
 andv h0, p7, z31.h
 // CHECK-INST: andv	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x5a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 5a 04 <unknown>
+// CHECK-UNKNOWN: 045a3fe0 <unknown>
 
 andv s0, p7, z31.s
 // CHECK-INST: andv	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x9a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 9a 04 <unknown>
+// CHECK-UNKNOWN: 049a3fe0 <unknown>
 
 andv d0, p7, z31.d
 // CHECK-INST: andv	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xda,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f da 04 <unknown>
+// CHECK-UNKNOWN: 04da3fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/asr.s b/llvm/test/MC/AArch64/SVE/asr.s
index 4cfa450c06eb3..c6ce254bf2ef2 100644
--- a/llvm/test/MC/AArch64/SVE/asr.s
+++ b/llvm/test/MC/AArch64/SVE/asr.s
@@ -13,157 +13,157 @@ asr     z0.b, z0.b, #1
 // CHECK-INST: asr	z0.b, z0.b, #1
 // CHECK-ENCODING: [0x00,0x90,0x2f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 90 2f 04 <unknown>
+// CHECK-UNKNOWN: 042f9000 <unknown>
 
 asr     z31.b, z31.b, #8
 // CHECK-INST: asr	z31.b, z31.b, #8
 // CHECK-ENCODING: [0xff,0x93,0x28,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 93 28 04 <unknown>
+// CHECK-UNKNOWN: 042893ff <unknown>
 
 asr     z0.h, z0.h, #1
 // CHECK-INST: asr	z0.h, z0.h, #1
 // CHECK-ENCODING: [0x00,0x90,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 90 3f 04 <unknown>
+// CHECK-UNKNOWN: 043f9000 <unknown>
 
 asr     z31.h, z31.h, #16
 // CHECK-INST: asr	z31.h, z31.h, #16
 // CHECK-ENCODING: [0xff,0x93,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 93 30 04 <unknown>
+// CHECK-UNKNOWN: 043093ff <unknown>
 
 asr     z0.s, z0.s, #1
 // CHECK-INST: asr	z0.s, z0.s, #1
 // CHECK-ENCODING: [0x00,0x90,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 90 7f 04 <unknown>
+// CHECK-UNKNOWN: 047f9000 <unknown>
 
 asr     z31.s, z31.s, #32
 // CHECK-INST: asr	z31.s, z31.s, #32
 // CHECK-ENCODING: [0xff,0x93,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 93 60 04 <unknown>
+// CHECK-UNKNOWN: 046093ff <unknown>
 
 asr     z0.d, z0.d, #1
 // CHECK-INST: asr	z0.d, z0.d, #1
 // CHECK-ENCODING: [0x00,0x90,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 90 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff9000 <unknown>
 
 asr     z31.d, z31.d, #64
 // CHECK-INST: asr	z31.d, z31.d, #64
 // CHECK-ENCODING: [0xff,0x93,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 93 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a093ff <unknown>
 
 asr     z0.b, p0/m, z0.b, #1
 // CHECK-INST: asr	z0.b, p0/m, z0.b, #1
 // CHECK-ENCODING: [0xe0,0x81,0x00,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 81 00 04 <unknown>
+// CHECK-UNKNOWN: 040081e0 <unknown>
 
 asr     z31.b, p0/m, z31.b, #8
 // CHECK-INST: asr	z31.b, p0/m, z31.b, #8
 // CHECK-ENCODING: [0x1f,0x81,0x00,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 81 00 04 <unknown>
+// CHECK-UNKNOWN: 0400811f <unknown>
 
 asr     z0.h, p0/m, z0.h, #1
 // CHECK-INST: asr	z0.h, p0/m, z0.h, #1
 // CHECK-ENCODING: [0xe0,0x83,0x00,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 83 00 04 <unknown>
+// CHECK-UNKNOWN: 040083e0 <unknown>
 
 asr     z31.h, p0/m, z31.h, #16
 // CHECK-INST: asr	z31.h, p0/m, z31.h, #16
 // CHECK-ENCODING: [0x1f,0x82,0x00,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 82 00 04 <unknown>
+// CHECK-UNKNOWN: 0400821f <unknown>
 
 asr     z0.s, p0/m, z0.s, #1
 // CHECK-INST: asr	z0.s, p0/m, z0.s, #1
 // CHECK-ENCODING: [0xe0,0x83,0x40,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 83 40 04 <unknown>
+// CHECK-UNKNOWN: 044083e0 <unknown>
 
 asr     z31.s, p0/m, z31.s, #32
 // CHECK-INST: asr	z31.s, p0/m, z31.s, #32
 // CHECK-ENCODING: [0x1f,0x80,0x40,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 80 40 04 <unknown>
+// CHECK-UNKNOWN: 0440801f <unknown>
 
 asr     z0.d, p0/m, z0.d, #1
 // CHECK-INST: asr	z0.d, p0/m, z0.d, #1
 // CHECK-ENCODING: [0xe0,0x83,0xc0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 83 c0 04 <unknown>
+// CHECK-UNKNOWN: 04c083e0 <unknown>
 
 asr     z31.d, p0/m, z31.d, #64
 // CHECK-INST: asr	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x80,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 80 80 04 <unknown>
+// CHECK-UNKNOWN: 0480801f <unknown>
 
 asr     z0.b, p0/m, z0.b, z0.b
 // CHECK-INST: asr	z0.b, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x80,0x10,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 10 04 <unknown>
+// CHECK-UNKNOWN: 04108000 <unknown>
 
 asr     z0.h, p0/m, z0.h, z0.h
 // CHECK-INST: asr	z0.h, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x80,0x50,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 50 04 <unknown>
+// CHECK-UNKNOWN: 04508000 <unknown>
 
 asr     z0.s, p0/m, z0.s, z0.s
 // CHECK-INST: asr	z0.s, p0/m, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x80,0x90,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 90 04 <unknown>
+// CHECK-UNKNOWN: 04908000 <unknown>
 
 asr     z0.d, p0/m, z0.d, z0.d
 // CHECK-INST: asr	z0.d, p0/m, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x80,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d08000 <unknown>
 
 asr     z0.b, p0/m, z0.b, z1.d
 // CHECK-INST: asr	z0.b, p0/m, z0.b, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x18,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 18 04 <unknown>
+// CHECK-UNKNOWN: 04188020 <unknown>
 
 asr     z0.h, p0/m, z0.h, z1.d
 // CHECK-INST: asr	z0.h, p0/m, z0.h, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x58,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 58 04 <unknown>
+// CHECK-UNKNOWN: 04588020 <unknown>
 
 asr     z0.s, p0/m, z0.s, z1.d
 // CHECK-INST: asr	z0.s, p0/m, z0.s, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x98,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 98 04 <unknown>
+// CHECK-UNKNOWN: 04988020 <unknown>
 
 asr     z0.b, z1.b, z2.d
 // CHECK-INST: asr	z0.b, z1.b, z2.d
 // CHECK-ENCODING: [0x20,0x80,0x22,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 22 04 <unknown>
+// CHECK-UNKNOWN: 04228020 <unknown>
 
 asr     z0.h, z1.h, z2.d
 // CHECK-INST: asr	z0.h, z1.h, z2.d
 // CHECK-ENCODING: [0x20,0x80,0x62,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 62 04 <unknown>
+// CHECK-UNKNOWN: 04628020 <unknown>
 
 asr     z0.s, z1.s, z2.d
 // CHECK-INST: asr	z0.s, z1.s, z2.d
 // CHECK-ENCODING: [0x20,0x80,0xa2,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 a2 04 <unknown>
+// CHECK-UNKNOWN: 04a28020 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -173,46 +173,46 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx	z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 asr     z31.d, p0/m, z31.d, #64
 // CHECK-INST: asr	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x80,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 80 80 04 <unknown>
+// CHECK-UNKNOWN: 0480801f <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 asr     z31.d, p0/m, z31.d, #64
 // CHECK-INST: asr	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x80,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 80 80 04 <unknown>
+// CHECK-UNKNOWN: 0480801f <unknown>
 
 movprfx z0.s, p0/z, z7.s
 // CHECK-INST: movprfx	z0.s, p0/z, z7.s
 // CHECK-ENCODING: [0xe0,0x20,0x90,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 20 90 04 <unknown>
+// CHECK-UNKNOWN: 049020e0 <unknown>
 
 asr     z0.s, p0/m, z0.s, z1.d
 // CHECK-INST: asr	z0.s, p0/m, z0.s, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x98,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 98 04 <unknown>
+// CHECK-UNKNOWN: 04988020 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 asr     z0.s, p0/m, z0.s, z1.d
 // CHECK-INST: asr	z0.s, p0/m, z0.s, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x98,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 98 04 <unknown>
+// CHECK-UNKNOWN: 04988020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/asrd.s b/llvm/test/MC/AArch64/SVE/asrd.s
index 1f06cf48b7642..de08dd1a619c6 100644
--- a/llvm/test/MC/AArch64/SVE/asrd.s
+++ b/llvm/test/MC/AArch64/SVE/asrd.s
@@ -13,49 +13,49 @@ asrd    z0.b, p0/m, z0.b, #1
 // CHECK-INST: asrd	z0.b, p0/m, z0.b, #1
 // CHECK-ENCODING: [0xe0,0x81,0x04,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 81 04 04 <unknown>
+// CHECK-UNKNOWN: 040481e0 <unknown>
 
 asrd    z31.b, p0/m, z31.b, #8
 // CHECK-INST: asrd	z31.b, p0/m, z31.b, #8
 // CHECK-ENCODING: [0x1f,0x81,0x04,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 81 04 04 <unknown>
+// CHECK-UNKNOWN: 0404811f <unknown>
 
 asrd    z0.h, p0/m, z0.h, #1
 // CHECK-INST: asrd	z0.h, p0/m, z0.h, #1
 // CHECK-ENCODING: [0xe0,0x83,0x04,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 83 04 04 <unknown>
+// CHECK-UNKNOWN: 040483e0 <unknown>
 
 asrd    z31.h, p0/m, z31.h, #16
 // CHECK-INST: asrd	z31.h, p0/m, z31.h, #16
 // CHECK-ENCODING: [0x1f,0x82,0x04,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 82 04 04 <unknown>
+// CHECK-UNKNOWN: 0404821f <unknown>
 
 asrd    z0.s, p0/m, z0.s, #1
 // CHECK-INST: asrd	z0.s, p0/m, z0.s, #1
 // CHECK-ENCODING: [0xe0,0x83,0x44,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 83 44 04 <unknown>
+// CHECK-UNKNOWN: 044483e0 <unknown>
 
 asrd    z31.s, p0/m, z31.s, #32
 // CHECK-INST: asrd	z31.s, p0/m, z31.s, #32
 // CHECK-ENCODING: [0x1f,0x80,0x44,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 80 44 04 <unknown>
+// CHECK-UNKNOWN: 0444801f <unknown>
 
 asrd    z0.d, p0/m, z0.d, #1
 // CHECK-INST: asrd	z0.d, p0/m, z0.d, #1
 // CHECK-ENCODING: [0xe0,0x83,0xc4,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 83 c4 04 <unknown>
+// CHECK-UNKNOWN: 04c483e0 <unknown>
 
 asrd    z31.d, p0/m, z31.d, #64
 // CHECK-INST: asrd	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x84,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 80 84 04 <unknown>
+// CHECK-UNKNOWN: 0484801f <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -65,22 +65,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx	z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 asrd    z31.d, p0/m, z31.d, #64
 // CHECK-INST: asrd	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x84,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 80 84 04 <unknown>
+// CHECK-UNKNOWN: 0484801f <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 asrd    z31.d, p0/m, z31.d, #64
 // CHECK-INST: asrd	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x84,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 80 84 04 <unknown>
+// CHECK-UNKNOWN: 0484801f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/asrr.s b/llvm/test/MC/AArch64/SVE/asrr.s
index 64031cf3c041e..9b90bfd1e9c27 100644
--- a/llvm/test/MC/AArch64/SVE/asrr.s
+++ b/llvm/test/MC/AArch64/SVE/asrr.s
@@ -13,25 +13,25 @@ asrr    z0.b, p0/m, z0.b, z0.b
 // CHECK-INST: asrr	z0.b, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x80,0x14,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 14 04 <unknown>
+// CHECK-UNKNOWN: 04148000 <unknown>
 
 asrr    z0.h, p0/m, z0.h, z0.h
 // CHECK-INST: asrr	z0.h, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x80,0x54,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 54 04 <unknown>
+// CHECK-UNKNOWN: 04548000 <unknown>
 
 asrr    z0.s, p0/m, z0.s, z0.s
 // CHECK-INST: asrr	z0.s, p0/m, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x80,0x94,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 94 04 <unknown>
+// CHECK-UNKNOWN: 04948000 <unknown>
 
 asrr    z0.d, p0/m, z0.d, z0.d
 // CHECK-INST: asrr	z0.d, p0/m, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x80,0xd4,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 d4 04 <unknown>
+// CHECK-UNKNOWN: 04d48000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z5.d, p0/z, z7.d
 // CHECK-INST: movprfx	z5.d, p0/z, z7.d
 // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020e5 <unknown>
 
 asrr    z5.d, p0/m, z5.d, z0.d
 // CHECK-INST: asrr	z5.d, p0/m, z5.d, z0.d
 // CHECK-ENCODING: [0x05,0x80,0xd4,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 80 d4 04 <unknown>
+// CHECK-UNKNOWN: 04d48005 <unknown>
 
 movprfx z5, z7
 // CHECK-INST: movprfx	z5, z7
 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce5 <unknown>
 
 asrr    z5.d, p0/m, z5.d, z0.d
 // CHECK-INST: asrr	z5.d, p0/m, z5.d, z0.d
 // CHECK-ENCODING: [0x05,0x80,0xd4,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 80 d4 04 <unknown>
+// CHECK-UNKNOWN: 04d48005 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/bic.s b/llvm/test/MC/AArch64/SVE/bic.s
index be824ebfdcdeb..a4121b57ed413 100644
--- a/llvm/test/MC/AArch64/SVE/bic.s
+++ b/llvm/test/MC/AArch64/SVE/bic.s
@@ -13,97 +13,97 @@ bic     z5.b, z5.b, #0xf9
 // CHECK-INST: and     z5.b, z5.b, #0x6
 // CHECK-ENCODING: [0x25,0x3e,0x80,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 3e 80 05 <unknown>
+// CHECK-UNKNOWN: 05803e25 <unknown>
 
 bic     z23.h, z23.h, #0xfff9
 // CHECK-INST: and     z23.h, z23.h, #0x6
 // CHECK-ENCODING: [0x37,0x7c,0x80,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 37 7c 80 05 <unknown>
+// CHECK-UNKNOWN: 05807c37 <unknown>
 
 bic     z0.s, z0.s, #0xfffffff9
 // CHECK-INST: and     z0.s, z0.s, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x80,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 80 05 <unknown>
+// CHECK-UNKNOWN: 0580f820 <unknown>
 
 bic     z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-INST: and     z0.d, z0.d, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x83,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 83 05 <unknown>
+// CHECK-UNKNOWN: 0583f820 <unknown>
 
 bic     z5.b, z5.b, #0x6
 // CHECK-INST: and     z5.b, z5.b, #0xf9
 // CHECK-ENCODING: [0xa5,0x2e,0x80,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a5 2e 80 05 <unknown>
+// CHECK-UNKNOWN: 05802ea5 <unknown>
 
 bic     z23.h, z23.h, #0x6
 // CHECK-INST: and     z23.h, z23.h, #0xfff9
 // CHECK-ENCODING: [0xb7,0x6d,0x80,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 6d 80 05 <unknown>
+// CHECK-UNKNOWN: 05806db7 <unknown>
 
 bic     z0.s, z0.s, #0x6
 // CHECK-INST: and     z0.s, z0.s, #0xfffffff9
 // CHECK-ENCODING: [0xa0,0xeb,0x80,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 eb 80 05 <unknown>
+// CHECK-UNKNOWN: 0580eba0 <unknown>
 
 bic     z0.d, z0.d, #0x6
 // CHECK-INST: and     z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-ENCODING: [0xa0,0xef,0x83,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ef 83 05 <unknown>
+// CHECK-UNKNOWN: 0583efa0 <unknown>
 
 bic     z0.d, z0.d, z0.d
 // CHECK-INST: bic     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e03000 <unknown>
 
 bic     z23.d, z13.d, z8.d
 // CHECK-INST: bic     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x31,0xe8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 31 e8 04 <unknown>
+// CHECK-UNKNOWN: 04e831b7 <unknown>
 
 bic     z31.b, p7/m, z31.b, z31.b
 // CHECK-INST: bic     z31.b, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x1f,0x1b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 1b 04 <unknown>
+// CHECK-UNKNOWN: 041b1fff <unknown>
 
 bic     z31.h, p7/m, z31.h, z31.h
 // CHECK-INST: bic     z31.h, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x1f,0x5b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 5b 04 <unknown>
+// CHECK-UNKNOWN: 045b1fff <unknown>
 
 bic     z31.s, p7/m, z31.s, z31.s
 // CHECK-INST: bic     z31.s, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1f,0x9b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 9b 04 <unknown>
+// CHECK-UNKNOWN: 049b1fff <unknown>
 
 bic     z31.d, p7/m, z31.d, z31.d
 // CHECK-INST: bic     z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xdb,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f db 04 <unknown>
+// CHECK-UNKNOWN: 04db1fff <unknown>
 
 bic     p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: bic     p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xff,0x7d,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 7d 0f 25 <unknown>
+// CHECK-UNKNOWN: 250f7dff <unknown>
 
 bic     p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: bic     p0.b, p0/z, p0.b, p0.b
 // CHECK-ENCODING: [0x10,0x40,0x00,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 40 00 25 <unknown>
+// CHECK-UNKNOWN: 25004010 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -113,19 +113,19 @@ bic     z0.s, z0.s, z0.s
 // CHECK-INST: bic     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e03000 <unknown>
 
 bic     z0.h, z0.h, z0.h
 // CHECK-INST: bic     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e03000 <unknown>
 
 bic     z0.b, z0.b, z0.b
 // CHECK-INST: bic     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e03000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -135,34 +135,34 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 bic     z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: bic	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xdb,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f db 04 <unknown>
+// CHECK-UNKNOWN: 04db1fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 bic     z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: bic	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xdb,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f db 04 <unknown>
+// CHECK-UNKNOWN: 04db1fe4 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 bic     z0.d, z0.d, #0x6
 // CHECK-INST: and	z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-ENCODING: [0xa0,0xef,0x83,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ef 83 05 <unknown>
+// CHECK-UNKNOWN: 0583efa0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/bics.s b/llvm/test/MC/AArch64/SVE/bics.s
index 1790967bcfc99..0a36276dc0658 100644
--- a/llvm/test/MC/AArch64/SVE/bics.s
+++ b/llvm/test/MC/AArch64/SVE/bics.s
@@ -13,10 +13,10 @@ bics    p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: bics    p0.b, p0/z, p0.b, p0.b
 // CHECK-ENCODING: [0x10,0x40,0x40,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 40 40 25 <unknown>
+// CHECK-UNKNOWN: 25404010 <unknown>
 
 bics    p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: bics    p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xff,0x7d,0x4f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 7d 4f 25 <unknown>
+// CHECK-UNKNOWN: 254f7dff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/brka.s b/llvm/test/MC/AArch64/SVE/brka.s
index 0d99a5f222954..01bb43b22edd0 100644
--- a/llvm/test/MC/AArch64/SVE/brka.s
+++ b/llvm/test/MC/AArch64/SVE/brka.s
@@ -13,10 +13,10 @@ brka  p0.b, p15/m, p15.b
 // CHECK-INST: brka	p0.b, p15/m, p15.b
 // CHECK-ENCODING: [0xf0,0x7d,0x10,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f0 7d 10 25 <unknown>
+// CHECK-UNKNOWN: 25107df0 <unknown>
 
 brka  p0.b, p15/z, p15.b
 // CHECK-INST: brka	p0.b, p15/z, p15.b
 // CHECK-ENCODING: [0xe0,0x7d,0x10,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 7d 10 25 <unknown>
+// CHECK-UNKNOWN: 25107de0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/brkas.s b/llvm/test/MC/AArch64/SVE/brkas.s
index f3eef2f231e00..badfd325d5225 100644
--- a/llvm/test/MC/AArch64/SVE/brkas.s
+++ b/llvm/test/MC/AArch64/SVE/brkas.s
@@ -13,4 +13,4 @@ brkas  p0.b, p15/z, p15.b
 // CHECK-INST: brkas	p0.b, p15/z, p15.b
 // CHECK-ENCODING: [0xe0,0x7d,0x50,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 7d 50 25 <unknown>
+// CHECK-UNKNOWN: 25507de0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/brkb.s b/llvm/test/MC/AArch64/SVE/brkb.s
index ced3be4448237..ec15253956045 100644
--- a/llvm/test/MC/AArch64/SVE/brkb.s
+++ b/llvm/test/MC/AArch64/SVE/brkb.s
@@ -13,10 +13,10 @@ brkb  p0.b, p15/m, p15.b
 // CHECK-INST: brkb	p0.b, p15/m, p15.b
 // CHECK-ENCODING: [0xf0,0x7d,0x90,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f0 7d 90 25 <unknown>
+// CHECK-UNKNOWN: 25907df0 <unknown>
 
 brkb  p0.b, p15/z, p15.b
 // CHECK-INST: brkb	p0.b, p15/z, p15.b
 // CHECK-ENCODING: [0xe0,0x7d,0x90,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 7d 90 25 <unknown>
+// CHECK-UNKNOWN: 25907de0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/brkbs.s b/llvm/test/MC/AArch64/SVE/brkbs.s
index 59ae88fb76d64..db34251ab29bc 100644
--- a/llvm/test/MC/AArch64/SVE/brkbs.s
+++ b/llvm/test/MC/AArch64/SVE/brkbs.s
@@ -13,4 +13,4 @@ brkbs  p0.b, p15/z, p15.b
 // CHECK-INST: brkbs	p0.b, p15/z, p15.b
 // CHECK-ENCODING: [0xe0,0x7d,0xd0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 7d d0 25 <unknown>
+// CHECK-UNKNOWN: 25d07de0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/brkn.s b/llvm/test/MC/AArch64/SVE/brkn.s
index 51fea7868442d..2fe93b833e483 100644
--- a/llvm/test/MC/AArch64/SVE/brkn.s
+++ b/llvm/test/MC/AArch64/SVE/brkn.s
@@ -13,10 +13,10 @@ brkn  p0.b, p15/z, p1.b, p0.b
 // CHECK-INST: brkn	p0.b, p15/z, p1.b, p0.b
 // CHECK-ENCODING: [0x20,0x7c,0x18,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 7c 18 25 <unknown>
+// CHECK-UNKNOWN: 25187c20 <unknown>
 
 brkn  p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: brkn	p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x7d,0x18,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7d 18 25 <unknown>
+// CHECK-UNKNOWN: 25187def <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/brkns.s b/llvm/test/MC/AArch64/SVE/brkns.s
index 2a256b1ecadc4..9420c32ab5037 100644
--- a/llvm/test/MC/AArch64/SVE/brkns.s
+++ b/llvm/test/MC/AArch64/SVE/brkns.s
@@ -13,10 +13,10 @@ brkns  p0.b, p15/z, p1.b, p0.b
 // CHECK-INST: brkns	p0.b, p15/z, p1.b, p0.b
 // CHECK-ENCODING: [0x20,0x7c,0x58,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 7c 58 25 <unknown>
+// CHECK-UNKNOWN: 25587c20 <unknown>
 
 brkns  p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: brkns	p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x7d,0x58,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7d 58 25 <unknown>
+// CHECK-UNKNOWN: 25587def <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/brkpa.s b/llvm/test/MC/AArch64/SVE/brkpa.s
index e210b21323492..557fdd381c52a 100644
--- a/llvm/test/MC/AArch64/SVE/brkpa.s
+++ b/llvm/test/MC/AArch64/SVE/brkpa.s
@@ -13,10 +13,10 @@ brkpa  p0.b,  p15/z, p1.b,  p2.b
 // CHECK-INST: brkpa	p0.b, p15/z, p1.b, p2.b
 // CHECK-ENCODING: [0x20,0xfc,0x02,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fc 02 25 <unknown>
+// CHECK-UNKNOWN: 2502fc20 <unknown>
 
 brkpa  p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: brkpa	p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0xfd,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef fd 0f 25 <unknown>
+// CHECK-UNKNOWN: 250ffdef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/brkpas.s b/llvm/test/MC/AArch64/SVE/brkpas.s
index 70583b1673c50..c6d7a06948eb0 100644
--- a/llvm/test/MC/AArch64/SVE/brkpas.s
+++ b/llvm/test/MC/AArch64/SVE/brkpas.s
@@ -13,10 +13,10 @@ brkpas  p0.b,  p15/z, p1.b,  p2.b
 // CHECK-INST: brkpas	p0.b, p15/z, p1.b, p2.b
 // CHECK-ENCODING: [0x20,0xfc,0x42,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fc 42 25 <unknown>
+// CHECK-UNKNOWN: 2542fc20 <unknown>
 
 brkpas  p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: brkpas	p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0xfd,0x4f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef fd 4f 25 <unknown>
+// CHECK-UNKNOWN: 254ffdef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/brkpb.s b/llvm/test/MC/AArch64/SVE/brkpb.s
index 490e74718f039..a8d933bf7d0df 100644
--- a/llvm/test/MC/AArch64/SVE/brkpb.s
+++ b/llvm/test/MC/AArch64/SVE/brkpb.s
@@ -13,10 +13,10 @@ brkpb  p0.b,  p15/z, p1.b,  p2.b
 // CHECK-INST: brkpb	p0.b, p15/z, p1.b, p2.b
 // CHECK-ENCODING: [0x30,0xfc,0x02,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 fc 02 25 <unknown>
+// CHECK-UNKNOWN: 2502fc30 <unknown>
 
 brkpb  p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: brkpb	p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xff,0xfd,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff fd 0f 25 <unknown>
+// CHECK-UNKNOWN: 250ffdff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/brkpbs.s b/llvm/test/MC/AArch64/SVE/brkpbs.s
index f2608721f373e..32383712a0435 100644
--- a/llvm/test/MC/AArch64/SVE/brkpbs.s
+++ b/llvm/test/MC/AArch64/SVE/brkpbs.s
@@ -13,10 +13,10 @@ brkpbs  p0.b,  p15/z, p1.b,  p2.b
 // CHECK-INST: brkpbs	p0.b, p15/z, p1.b, p2.b
 // CHECK-ENCODING: [0x30,0xfc,0x42,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 fc 42 25 <unknown>
+// CHECK-UNKNOWN: 2542fc30 <unknown>
 
 brkpbs  p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: brkpbs	p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xff,0xfd,0x4f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff fd 4f 25 <unknown>
+// CHECK-UNKNOWN: 254ffdff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/clasta.s b/llvm/test/MC/AArch64/SVE/clasta.s
index 5e3ef463c03b6..ccf516ae05549 100644
--- a/llvm/test/MC/AArch64/SVE/clasta.s
+++ b/llvm/test/MC/AArch64/SVE/clasta.s
@@ -13,73 +13,73 @@ clasta   w0, p7, w0, z31.b
 // CHECK-INST: clasta	w0, p7, w0, z31.b
 // CHECK-ENCODING: [0xe0,0xbf,0x30,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf 30 05 <unknown>
+// CHECK-UNKNOWN: 0530bfe0 <unknown>
 
 clasta   w0, p7, w0, z31.h
 // CHECK-INST: clasta	w0, p7, w0, z31.h
 // CHECK-ENCODING: [0xe0,0xbf,0x70,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf 70 05 <unknown>
+// CHECK-UNKNOWN: 0570bfe0 <unknown>
 
 clasta   w0, p7, w0, z31.s
 // CHECK-INST: clasta	w0, p7, w0, z31.s
 // CHECK-ENCODING: [0xe0,0xbf,0xb0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf b0 05 <unknown>
+// CHECK-UNKNOWN: 05b0bfe0 <unknown>
 
 clasta   x0, p7, x0, z31.d
 // CHECK-INST: clasta	x0, p7, x0, z31.d
 // CHECK-ENCODING: [0xe0,0xbf,0xf0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf f0 05 <unknown>
+// CHECK-UNKNOWN: 05f0bfe0 <unknown>
 
 clasta   b0, p7, b0, z31.b
 // CHECK-INST: clasta	b0, p7, b0, z31.b
 // CHECK-ENCODING: [0xe0,0x9f,0x2a,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 2a 05 <unknown>
+// CHECK-UNKNOWN: 052a9fe0 <unknown>
 
 clasta   h0, p7, h0, z31.h
 // CHECK-INST: clasta	h0, p7, h0, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x6a,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 6a 05 <unknown>
+// CHECK-UNKNOWN: 056a9fe0 <unknown>
 
 clasta   s0, p7, s0, z31.s
 // CHECK-INST: clasta	s0, p7, s0, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0xaa,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f aa 05 <unknown>
+// CHECK-UNKNOWN: 05aa9fe0 <unknown>
 
 clasta   d0, p7, d0, z31.d
 // CHECK-INST: clasta	d0, p7, d0, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xea,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f ea 05 <unknown>
+// CHECK-UNKNOWN: 05ea9fe0 <unknown>
 
 clasta   z0.b, p7, z0.b, z31.b
 // CHECK-INST: clasta	z0.b, p7, z0.b, z31.b
 // CHECK-ENCODING: [0xe0,0x9f,0x28,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 28 05 <unknown>
+// CHECK-UNKNOWN: 05289fe0 <unknown>
 
 clasta   z0.h, p7, z0.h, z31.h
 // CHECK-INST: clasta	z0.h, p7, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x68,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 68 05 <unknown>
+// CHECK-UNKNOWN: 05689fe0 <unknown>
 
 clasta   z0.s, p7, z0.s, z31.s
 // CHECK-INST: clasta	z0.s, p7, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0xa8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f a8 05 <unknown>
+// CHECK-UNKNOWN: 05a89fe0 <unknown>
 
 clasta   z0.d, p7, z0.d, z31.d
 // CHECK-INST: clasta	z0.d, p7, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e8 05 <unknown>
+// CHECK-UNKNOWN: 05e89fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -89,10 +89,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 clasta   z0.d, p7, z0.d, z31.d
 // CHECK-INST: clasta	z0.d, p7, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e8 05 <unknown>
+// CHECK-UNKNOWN: 05e89fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/clastb.s b/llvm/test/MC/AArch64/SVE/clastb.s
index f9c5e0cf33e3e..e9dd34b0d4b22 100644
--- a/llvm/test/MC/AArch64/SVE/clastb.s
+++ b/llvm/test/MC/AArch64/SVE/clastb.s
@@ -13,73 +13,73 @@ clastb   w0, p7, w0, z31.b
 // CHECK-INST: clastb	w0, p7, w0, z31.b
 // CHECK-ENCODING: [0xe0,0xbf,0x31,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf 31 05 <unknown>
+// CHECK-UNKNOWN: 0531bfe0 <unknown>
 
 clastb   w0, p7, w0, z31.h
 // CHECK-INST: clastb	w0, p7, w0, z31.h
 // CHECK-ENCODING: [0xe0,0xbf,0x71,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf 71 05 <unknown>
+// CHECK-UNKNOWN: 0571bfe0 <unknown>
 
 clastb   w0, p7, w0, z31.s
 // CHECK-INST: clastb	w0, p7, w0, z31.s
 // CHECK-ENCODING: [0xe0,0xbf,0xb1,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf b1 05 <unknown>
+// CHECK-UNKNOWN: 05b1bfe0 <unknown>
 
 clastb   x0, p7, x0, z31.d
 // CHECK-INST: clastb	x0, p7, x0, z31.d
 // CHECK-ENCODING: [0xe0,0xbf,0xf1,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf f1 05 <unknown>
+// CHECK-UNKNOWN: 05f1bfe0 <unknown>
 
 clastb   b0, p7, b0, z31.b
 // CHECK-INST: clastb	b0, p7, b0, z31.b
 // CHECK-ENCODING: [0xe0,0x9f,0x2b,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 2b 05 <unknown>
+// CHECK-UNKNOWN: 052b9fe0 <unknown>
 
 clastb   h0, p7, h0, z31.h
 // CHECK-INST: clastb	h0, p7, h0, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x6b,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 6b 05 <unknown>
+// CHECK-UNKNOWN: 056b9fe0 <unknown>
 
 clastb   s0, p7, s0, z31.s
 // CHECK-INST: clastb	s0, p7, s0, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0xab,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f ab 05 <unknown>
+// CHECK-UNKNOWN: 05ab9fe0 <unknown>
 
 clastb   d0, p7, d0, z31.d
 // CHECK-INST: clastb	d0, p7, d0, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xeb,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f eb 05 <unknown>
+// CHECK-UNKNOWN: 05eb9fe0 <unknown>
 
 clastb   z0.b, p7, z0.b, z31.b
 // CHECK-INST: clastb	z0.b, p7, z0.b, z31.b
 // CHECK-ENCODING: [0xe0,0x9f,0x29,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 29 05 <unknown>
+// CHECK-UNKNOWN: 05299fe0 <unknown>
 
 clastb   z0.h, p7, z0.h, z31.h
 // CHECK-INST: clastb	z0.h, p7, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x69,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 69 05 <unknown>
+// CHECK-UNKNOWN: 05699fe0 <unknown>
 
 clastb   z0.s, p7, z0.s, z31.s
 // CHECK-INST: clastb	z0.s, p7, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0xa9,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f a9 05 <unknown>
+// CHECK-UNKNOWN: 05a99fe0 <unknown>
 
 clastb   z0.d, p7, z0.d, z31.d
 // CHECK-INST: clastb	z0.d, p7, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e9 05 <unknown>
+// CHECK-UNKNOWN: 05e99fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -89,10 +89,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 clastb   z0.d, p7, z0.d, z31.d
 // CHECK-INST: clastb	z0.d, p7, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe9,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e9 05 <unknown>
+// CHECK-UNKNOWN: 05e99fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cls.s b/llvm/test/MC/AArch64/SVE/cls.s
index e5f49f94bfaaf..e71d319f2f6af 100644
--- a/llvm/test/MC/AArch64/SVE/cls.s
+++ b/llvm/test/MC/AArch64/SVE/cls.s
@@ -13,25 +13,25 @@ cls     z31.b, p7/m, z31.b
 // CHECK-INST: cls	z31.b, p7/m, z31.b
 // CHECK-ENCODING: [0xff,0xbf,0x18,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 18 04 <unknown>
+// CHECK-UNKNOWN: 0418bfff <unknown>
 
 cls     z31.h, p7/m, z31.h
 // CHECK-INST: cls	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x58,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 58 04 <unknown>
+// CHECK-UNKNOWN: 0458bfff <unknown>
 
 cls     z31.s, p7/m, z31.s
 // CHECK-INST: cls	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x98,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 98 04 <unknown>
+// CHECK-UNKNOWN: 0498bfff <unknown>
 
 cls     z31.d, p7/m, z31.d
 // CHECK-INST: cls	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xd8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf d8 04 <unknown>
+// CHECK-UNKNOWN: 04d8bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 cls     z4.d, p7/m, z31.d
 // CHECK-INST: cls	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d8 04 <unknown>
+// CHECK-UNKNOWN: 04d8bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 cls     z4.d, p7/m, z31.d
 // CHECK-INST: cls	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d8 04 <unknown>
+// CHECK-UNKNOWN: 04d8bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/clz.s b/llvm/test/MC/AArch64/SVE/clz.s
index ba2e79af4ce0d..b3d156819663a 100644
--- a/llvm/test/MC/AArch64/SVE/clz.s
+++ b/llvm/test/MC/AArch64/SVE/clz.s
@@ -13,25 +13,25 @@ clz     z31.b, p7/m, z31.b
 // CHECK-INST: clz	z31.b, p7/m, z31.b
 // CHECK-ENCODING: [0xff,0xbf,0x19,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 19 04 <unknown>
+// CHECK-UNKNOWN: 0419bfff <unknown>
 
 clz     z31.h, p7/m, z31.h
 // CHECK-INST: clz	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x59,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 59 04 <unknown>
+// CHECK-UNKNOWN: 0459bfff <unknown>
 
 clz     z31.s, p7/m, z31.s
 // CHECK-INST: clz	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x99,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 99 04 <unknown>
+// CHECK-UNKNOWN: 0499bfff <unknown>
 
 clz     z31.d, p7/m, z31.d
 // CHECK-INST: clz	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xd9,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf d9 04 <unknown>
+// CHECK-UNKNOWN: 04d9bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 clz     z4.d, p7/m, z31.d
 // CHECK-INST: clz	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd9,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d9 04 <unknown>
+// CHECK-UNKNOWN: 04d9bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 clz     z4.d, p7/m, z31.d
 // CHECK-INST: clz	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd9,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d9 04 <unknown>
+// CHECK-UNKNOWN: 04d9bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cmpeq.s b/llvm/test/MC/AArch64/SVE/cmpeq.s
index c070d893c1700..7269c64096857 100644
--- a/llvm/test/MC/AArch64/SVE/cmpeq.s
+++ b/llvm/test/MC/AArch64/SVE/cmpeq.s
@@ -14,88 +14,88 @@ cmpeq   p0.b, p0/z, z0.b, z0.b
 // CHECK-INST: cmpeq p0.b, p0/z, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0xa0,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 00 24 <unknown>
+// CHECK-UNKNOWN: 2400a000 <unknown>
 
 cmpeq   p0.h, p0/z, z0.h, z0.h
 // CHECK-INST: cmpeq p0.h, p0/z, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 40 24 <unknown>
+// CHECK-UNKNOWN: 2440a000 <unknown>
 
 cmpeq   p0.s, p0/z, z0.s, z0.s
 // CHECK-INST: cmpeq p0.s, p0/z, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 80 24 <unknown>
+// CHECK-UNKNOWN: 2480a000 <unknown>
 
 cmpeq   p0.d, p0/z, z0.d, z0.d
 // CHECK-INST: cmpeq p0.d, p0/z, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xc0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 c0 24 <unknown>
+// CHECK-UNKNOWN: 24c0a000 <unknown>
 
 cmpeq   p0.b, p0/z, z0.b, z0.d
 // CHECK-INST: cmpeq p0.b, p0/z, z0.b, z0.d
 // CHECK-ENCODING: [0x00,0x20,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 00 24 <unknown>
+// CHECK-UNKNOWN: 24002000 <unknown>
 
 cmpeq   p0.h, p0/z, z0.h, z0.d
 // CHECK-INST: cmpeq p0.h, p0/z, z0.h, z0.d
 // CHECK-ENCODING: [0x00,0x20,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 40 24 <unknown>
+// CHECK-UNKNOWN: 24402000 <unknown>
 
 cmpeq   p0.s, p0/z, z0.s, z0.d
 // CHECK-INST: cmpeq p0.s, p0/z, z0.s, z0.d
 // CHECK-ENCODING: [0x00,0x20,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 80 24 <unknown>
+// CHECK-UNKNOWN: 24802000 <unknown>
 
 cmpeq   p0.b, p0/z, z0.b, #-16
 // CHECK-INST: cmpeq p0.b, p0/z, z0.b, #-16
 // CHECK-ENCODING: [0x00,0x80,0x10,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 10 25 <unknown>
+// CHECK-UNKNOWN: 25108000 <unknown>
 
 cmpeq   p0.h, p0/z, z0.h, #-16
 // CHECK-INST: cmpeq p0.h, p0/z, z0.h, #-16
 // CHECK-ENCODING: [0x00,0x80,0x50,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 50 25 <unknown>
+// CHECK-UNKNOWN: 25508000 <unknown>
 
 cmpeq   p0.s, p0/z, z0.s, #-16
 // CHECK-INST: cmpeq p0.s, p0/z, z0.s, #-16
 // CHECK-ENCODING: [0x00,0x80,0x90,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 90 25 <unknown>
+// CHECK-UNKNOWN: 25908000 <unknown>
 
 cmpeq   p0.d, p0/z, z0.d, #-16
 // CHECK-INST: cmpeq p0.d, p0/z, z0.d, #-16
 // CHECK-ENCODING: [0x00,0x80,0xd0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 d0 25 <unknown>
+// CHECK-UNKNOWN: 25d08000 <unknown>
 
 cmpeq   p0.b, p0/z, z0.b, #15
 // CHECK-INST: cmpeq p0.b, p0/z, z0.b, #15
 // CHECK-ENCODING: [0x00,0x80,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 0f 25 <unknown>
+// CHECK-UNKNOWN: 250f8000 <unknown>
 
 cmpeq   p0.h, p0/z, z0.h, #15
 // CHECK-INST: cmpeq p0.h, p0/z, z0.h, #15
 // CHECK-ENCODING: [0x00,0x80,0x4f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 4f 25 <unknown>
+// CHECK-UNKNOWN: 254f8000 <unknown>
 
 cmpeq   p0.s, p0/z, z0.s, #15
 // CHECK-INST: cmpeq p0.s, p0/z, z0.s, #15
 // CHECK-ENCODING: [0x00,0x80,0x8f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 8f 25 <unknown>
+// CHECK-UNKNOWN: 258f8000 <unknown>
 
 cmpeq   p0.d, p0/z, z0.d, #15
 // CHECK-INST: cmpeq p0.d, p0/z, z0.d, #15
 // CHECK-ENCODING: [0x00,0x80,0xcf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 cf 25 <unknown>
+// CHECK-UNKNOWN: 25cf8000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cmpge.s b/llvm/test/MC/AArch64/SVE/cmpge.s
index 3bbf150b9f1e1..e11262003af7a 100644
--- a/llvm/test/MC/AArch64/SVE/cmpge.s
+++ b/llvm/test/MC/AArch64/SVE/cmpge.s
@@ -13,88 +13,88 @@ cmpge   p0.b, p0/z, z0.b, z0.b
 // CHECK-INST: cmpge   p0.b, p0/z, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x80,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 00 24 <unknown>
+// CHECK-UNKNOWN: 24008000 <unknown>
 
 cmpge   p0.h, p0/z, z0.h, z0.h
 // CHECK-INST: cmpge   p0.h, p0/z, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x80,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 40 24 <unknown>
+// CHECK-UNKNOWN: 24408000 <unknown>
 
 cmpge   p0.s, p0/z, z0.s, z0.s
 // CHECK-INST: cmpge   p0.s, p0/z, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x80,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 80 24 <unknown>
+// CHECK-UNKNOWN: 24808000 <unknown>
 
 cmpge   p0.d, p0/z, z0.d, z0.d
 // CHECK-INST: cmpge   p0.d, p0/z, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x80,0xc0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 c0 24 <unknown>
+// CHECK-UNKNOWN: 24c08000 <unknown>
 
 cmpge   p0.b, p0/z, z0.b, z0.d
 // CHECK-INST: cmpge   p0.b, p0/z, z0.b, z0.d
 // CHECK-ENCODING: [0x00,0x40,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 00 24 <unknown>
+// CHECK-UNKNOWN: 24004000 <unknown>
 
 cmpge   p0.h, p0/z, z0.h, z0.d
 // CHECK-INST: cmpge   p0.h, p0/z, z0.h, z0.d
 // CHECK-ENCODING: [0x00,0x40,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 40 24 <unknown>
+// CHECK-UNKNOWN: 24404000 <unknown>
 
 cmpge   p0.s, p0/z, z0.s, z0.d
 // CHECK-INST: cmpge   p0.s, p0/z, z0.s, z0.d
 // CHECK-ENCODING: [0x00,0x40,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 80 24 <unknown>
+// CHECK-UNKNOWN: 24804000 <unknown>
 
 cmpge   p0.b, p0/z, z0.b, #-16
 // CHECK-INST: cmpge p0.b, p0/z, z0.b, #-16
 // CHECK-ENCODING: [0x00,0x00,0x10,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 10 25 <unknown>
+// CHECK-UNKNOWN: 25100000 <unknown>
 
 cmpge   p0.h, p0/z, z0.h, #-16
 // CHECK-INST: cmpge p0.h, p0/z, z0.h, #-16
 // CHECK-ENCODING: [0x00,0x00,0x50,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 50 25 <unknown>
+// CHECK-UNKNOWN: 25500000 <unknown>
 
 cmpge   p0.s, p0/z, z0.s, #-16
 // CHECK-INST: cmpge p0.s, p0/z, z0.s, #-16
 // CHECK-ENCODING: [0x00,0x00,0x90,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 90 25 <unknown>
+// CHECK-UNKNOWN: 25900000 <unknown>
 
 cmpge   p0.d, p0/z, z0.d, #-16
 // CHECK-INST: cmpge p0.d, p0/z, z0.d, #-16
 // CHECK-ENCODING: [0x00,0x00,0xd0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 d0 25 <unknown>
+// CHECK-UNKNOWN: 25d00000 <unknown>
 
 cmpge   p0.b, p0/z, z0.b, #15
 // CHECK-INST: cmpge p0.b, p0/z, z0.b, #15
 // CHECK-ENCODING: [0x00,0x00,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 0f 25 <unknown>
+// CHECK-UNKNOWN: 250f0000 <unknown>
 
 cmpge   p0.h, p0/z, z0.h, #15
 // CHECK-INST: cmpge p0.h, p0/z, z0.h, #15
 // CHECK-ENCODING: [0x00,0x00,0x4f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 4f 25 <unknown>
+// CHECK-UNKNOWN: 254f0000 <unknown>
 
 cmpge   p0.s, p0/z, z0.s, #15
 // CHECK-INST: cmpge p0.s, p0/z, z0.s, #15
 // CHECK-ENCODING: [0x00,0x00,0x8f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 8f 25 <unknown>
+// CHECK-UNKNOWN: 258f0000 <unknown>
 
 cmpge   p0.d, p0/z, z0.d, #15
 // CHECK-INST: cmpge p0.d, p0/z, z0.d, #15
 // CHECK-ENCODING: [0x00,0x00,0xcf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 cf 25 <unknown>
+// CHECK-UNKNOWN: 25cf0000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cmpgt.s b/llvm/test/MC/AArch64/SVE/cmpgt.s
index 0fc1c65e1e67a..856d29acd00a9 100644
--- a/llvm/test/MC/AArch64/SVE/cmpgt.s
+++ b/llvm/test/MC/AArch64/SVE/cmpgt.s
@@ -14,88 +14,88 @@ cmpgt   p0.b, p0/z, z0.b, z0.b
 // CHECK-INST: cmpgt p0.b, p0/z, z0.b, z0.b
 // CHECK-ENCODING: [0x10,0x80,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 80 00 24 <unknown>
+// CHECK-UNKNOWN: 24008010 <unknown>
 
 cmpgt   p0.h, p0/z, z0.h, z0.h
 // CHECK-INST: cmpgt p0.h, p0/z, z0.h, z0.h
 // CHECK-ENCODING: [0x10,0x80,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 80 40 24 <unknown>
+// CHECK-UNKNOWN: 24408010 <unknown>
 
 cmpgt   p0.s, p0/z, z0.s, z0.s
 // CHECK-INST: cmpgt p0.s, p0/z, z0.s, z0.s
 // CHECK-ENCODING: [0x10,0x80,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 80 80 24 <unknown>
+// CHECK-UNKNOWN: 24808010 <unknown>
 
 cmpgt   p0.d, p0/z, z0.d, z0.d
 // CHECK-INST: cmpgt p0.d, p0/z, z0.d, z0.d
 // CHECK-ENCODING: [0x10,0x80,0xc0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 80 c0 24 <unknown>
+// CHECK-UNKNOWN: 24c08010 <unknown>
 
 cmpgt   p0.b, p0/z, z0.b, z0.d
 // CHECK-INST: cmpgt p0.b, p0/z, z0.b, z0.d
 // CHECK-ENCODING: [0x10,0x40,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 40 00 24 <unknown>
+// CHECK-UNKNOWN: 24004010 <unknown>
 
 cmpgt   p0.h, p0/z, z0.h, z0.d
 // CHECK-INST: cmpgt p0.h, p0/z, z0.h, z0.d
 // CHECK-ENCODING: [0x10,0x40,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 40 40 24 <unknown>
+// CHECK-UNKNOWN: 24404010 <unknown>
 
 cmpgt   p0.s, p0/z, z0.s, z0.d
 // CHECK-INST: cmpgt p0.s, p0/z, z0.s, z0.d
 // CHECK-ENCODING: [0x10,0x40,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 40 80 24 <unknown>
+// CHECK-UNKNOWN: 24804010 <unknown>
 
 cmpgt   p0.b, p0/z, z0.b, #-16
 // CHECK-INST: cmpgt p0.b, p0/z, z0.b, #-16
 // CHECK-ENCODING: [0x10,0x00,0x10,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 10 25 <unknown>
+// CHECK-UNKNOWN: 25100010 <unknown>
 
 cmpgt   p0.h, p0/z, z0.h, #-16
 // CHECK-INST: cmpgt p0.h, p0/z, z0.h, #-16
 // CHECK-ENCODING: [0x10,0x00,0x50,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 50 25 <unknown>
+// CHECK-UNKNOWN: 25500010 <unknown>
 
 cmpgt   p0.s, p0/z, z0.s, #-16
 // CHECK-INST: cmpgt p0.s, p0/z, z0.s, #-16
 // CHECK-ENCODING: [0x10,0x00,0x90,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 90 25 <unknown>
+// CHECK-UNKNOWN: 25900010 <unknown>
 
 cmpgt   p0.d, p0/z, z0.d, #-16
 // CHECK-INST: cmpgt p0.d, p0/z, z0.d, #-16
 // CHECK-ENCODING: [0x10,0x00,0xd0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 d0 25 <unknown>
+// CHECK-UNKNOWN: 25d00010 <unknown>
 
 cmpgt   p0.b, p0/z, z0.b, #15
 // CHECK-INST: cmpgt p0.b, p0/z, z0.b, #15
 // CHECK-ENCODING: [0x10,0x00,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 0f 25 <unknown>
+// CHECK-UNKNOWN: 250f0010 <unknown>
 
 cmpgt   p0.h, p0/z, z0.h, #15
 // CHECK-INST: cmpgt p0.h, p0/z, z0.h, #15
 // CHECK-ENCODING: [0x10,0x00,0x4f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 4f 25 <unknown>
+// CHECK-UNKNOWN: 254f0010 <unknown>
 
 cmpgt   p0.s, p0/z, z0.s, #15
 // CHECK-INST: cmpgt p0.s, p0/z, z0.s, #15
 // CHECK-ENCODING: [0x10,0x00,0x8f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 8f 25 <unknown>
+// CHECK-UNKNOWN: 258f0010 <unknown>
 
 cmpgt   p0.d, p0/z, z0.d, #15
 // CHECK-INST: cmpgt p0.d, p0/z, z0.d, #15
 // CHECK-ENCODING: [0x10,0x00,0xcf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 cf 25 <unknown>
+// CHECK-UNKNOWN: 25cf0010 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cmphi.s b/llvm/test/MC/AArch64/SVE/cmphi.s
index af23cebc3c158..2121f30b5c86c 100644
--- a/llvm/test/MC/AArch64/SVE/cmphi.s
+++ b/llvm/test/MC/AArch64/SVE/cmphi.s
@@ -14,88 +14,88 @@ cmphi   p0.b, p0/z, z0.b, z0.b
 // CHECK-INST: cmphi p0.b, p0/z, z0.b, z0.b
 // CHECK-ENCODING: [0x10,0x00,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 00 24 <unknown>
+// CHECK-UNKNOWN: 24000010 <unknown>
 
 cmphi   p0.h, p0/z, z0.h, z0.h
 // CHECK-INST: cmphi p0.h, p0/z, z0.h, z0.h
 // CHECK-ENCODING: [0x10,0x00,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 40 24 <unknown>
+// CHECK-UNKNOWN: 24400010 <unknown>
 
 cmphi   p0.s, p0/z, z0.s, z0.s
 // CHECK-INST: cmphi p0.s, p0/z, z0.s, z0.s
 // CHECK-ENCODING: [0x10,0x00,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 80 24 <unknown>
+// CHECK-UNKNOWN: 24800010 <unknown>
 
 cmphi   p0.d, p0/z, z0.d, z0.d
 // CHECK-INST: cmphi p0.d, p0/z, z0.d, z0.d
 // CHECK-ENCODING: [0x10,0x00,0xc0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 c0 24 <unknown>
+// CHECK-UNKNOWN: 24c00010 <unknown>
 
 cmphi   p0.b, p0/z, z0.b, z0.d
 // CHECK-INST: cmphi p0.b, p0/z, z0.b, z0.d
 // CHECK-ENCODING: [0x10,0xc0,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 c0 00 24 <unknown>
+// CHECK-UNKNOWN: 2400c010 <unknown>
 
 cmphi   p0.h, p0/z, z0.h, z0.d
 // CHECK-INST: cmphi p0.h, p0/z, z0.h, z0.d
 // CHECK-ENCODING: [0x10,0xc0,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 c0 40 24 <unknown>
+// CHECK-UNKNOWN: 2440c010 <unknown>
 
 cmphi   p0.s, p0/z, z0.s, z0.d
 // CHECK-INST: cmphi p0.s, p0/z, z0.s, z0.d
 // CHECK-ENCODING: [0x10,0xc0,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 c0 80 24 <unknown>
+// CHECK-UNKNOWN: 2480c010 <unknown>
 
 cmphi   p0.b, p0/z, z0.b, #0
 // CHECK-INST: cmphi p0.b, p0/z, z0.b, #0
 // CHECK-ENCODING: [0x10,0x00,0x20,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 20 24 <unknown>
+// CHECK-UNKNOWN: 24200010 <unknown>
 
 cmphi   p0.h, p0/z, z0.h, #0
 // CHECK-INST: cmphi p0.h, p0/z, z0.h, #0
 // CHECK-ENCODING: [0x10,0x00,0x60,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 60 24 <unknown>
+// CHECK-UNKNOWN: 24600010 <unknown>
 
 cmphi   p0.s, p0/z, z0.s, #0
 // CHECK-INST: cmphi p0.s, p0/z, z0.s, #0
 // CHECK-ENCODING: [0x10,0x00,0xa0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 a0 24 <unknown>
+// CHECK-UNKNOWN: 24a00010 <unknown>
 
 cmphi   p0.d, p0/z, z0.d, #0
 // CHECK-INST: cmphi p0.d, p0/z, z0.d, #0
 // CHECK-ENCODING: [0x10,0x00,0xe0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 00 e0 24 <unknown>
+// CHECK-UNKNOWN: 24e00010 <unknown>
 
 cmphi   p0.b, p0/z, z0.b, #127
 // CHECK-INST: cmphi p0.b, p0/z, z0.b, #127
 // CHECK-ENCODING: [0x10,0xc0,0x3f,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 c0 3f 24 <unknown>
+// CHECK-UNKNOWN: 243fc010 <unknown>
 
 cmphi   p0.h, p0/z, z0.h, #127
 // CHECK-INST: cmphi p0.h, p0/z, z0.h, #127
 // CHECK-ENCODING: [0x10,0xc0,0x7f,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 c0 7f 24 <unknown>
+// CHECK-UNKNOWN: 247fc010 <unknown>
 
 cmphi   p0.s, p0/z, z0.s, #127
 // CHECK-INST: cmphi p0.s, p0/z, z0.s, #127
 // CHECK-ENCODING: [0x10,0xc0,0xbf,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 c0 bf 24 <unknown>
+// CHECK-UNKNOWN: 24bfc010 <unknown>
 
 cmphi   p0.d, p0/z, z0.d, #127
 // CHECK-INST: cmphi p0.d, p0/z, z0.d, #127
 // CHECK-ENCODING: [0x10,0xc0,0xff,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 c0 ff 24 <unknown>
+// CHECK-UNKNOWN: 24ffc010 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cmphs.s b/llvm/test/MC/AArch64/SVE/cmphs.s
index 382b2d792e9e1..39a1b4e0f6ac2 100644
--- a/llvm/test/MC/AArch64/SVE/cmphs.s
+++ b/llvm/test/MC/AArch64/SVE/cmphs.s
@@ -14,88 +14,88 @@ cmphs   p0.b, p0/z, z0.b, z0.b
 // CHECK-INST: cmphs p0.b, p0/z, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x00,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 00 24 <unknown>
+// CHECK-UNKNOWN: 24000000 <unknown>
 
 cmphs   p0.h, p0/z, z0.h, z0.h
 // CHECK-INST: cmphs p0.h, p0/z, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x00,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 40 24 <unknown>
+// CHECK-UNKNOWN: 24400000 <unknown>
 
 cmphs   p0.s, p0/z, z0.s, z0.s
 // CHECK-INST: cmphs p0.s, p0/z, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x00,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 80 24 <unknown>
+// CHECK-UNKNOWN: 24800000 <unknown>
 
 cmphs   p0.d, p0/z, z0.d, z0.d
 // CHECK-INST: cmphs p0.d, p0/z, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x00,0xc0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 c0 24 <unknown>
+// CHECK-UNKNOWN: 24c00000 <unknown>
 
 cmphs   p0.b, p0/z, z0.b, z0.d
 // CHECK-INST: cmphs p0.b, p0/z, z0.b, z0.d
 // CHECK-ENCODING: [0x00,0xc0,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 00 24 <unknown>
+// CHECK-UNKNOWN: 2400c000 <unknown>
 
 cmphs   p0.h, p0/z, z0.h, z0.d
 // CHECK-INST: cmphs p0.h, p0/z, z0.h, z0.d
 // CHECK-ENCODING: [0x00,0xc0,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 40 24 <unknown>
+// CHECK-UNKNOWN: 2440c000 <unknown>
 
 cmphs   p0.s, p0/z, z0.s, z0.d
 // CHECK-INST: cmphs p0.s, p0/z, z0.s, z0.d
 // CHECK-ENCODING: [0x00,0xc0,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 80 24 <unknown>
+// CHECK-UNKNOWN: 2480c000 <unknown>
 
 cmphs   p0.b, p0/z, z0.b, #0
 // CHECK-INST: cmphs p0.b, p0/z, z0.b, #0
 // CHECK-ENCODING: [0x00,0x00,0x20,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 20 24 <unknown>
+// CHECK-UNKNOWN: 24200000 <unknown>
 
 cmphs   p0.h, p0/z, z0.h, #0
 // CHECK-INST: cmphs p0.h, p0/z, z0.h, #0
 // CHECK-ENCODING: [0x00,0x00,0x60,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 60 24 <unknown>
+// CHECK-UNKNOWN: 24600000 <unknown>
 
 cmphs   p0.s, p0/z, z0.s, #0
 // CHECK-INST: cmphs p0.s, p0/z, z0.s, #0
 // CHECK-ENCODING: [0x00,0x00,0xa0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 a0 24 <unknown>
+// CHECK-UNKNOWN: 24a00000 <unknown>
 
 cmphs   p0.d, p0/z, z0.d, #0
 // CHECK-INST: cmphs p0.d, p0/z, z0.d, #0
 // CHECK-ENCODING: [0x00,0x00,0xe0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 e0 24 <unknown>
+// CHECK-UNKNOWN: 24e00000 <unknown>
 
 cmphs   p0.b, p0/z, z0.b, #127
 // CHECK-INST: cmphs p0.b, p0/z, z0.b, #127
 // CHECK-ENCODING: [0x00,0xc0,0x3f,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 3f 24 <unknown>
+// CHECK-UNKNOWN: 243fc000 <unknown>
 
 cmphs   p0.h, p0/z, z0.h, #127
 // CHECK-INST: cmphs p0.h, p0/z, z0.h, #127
 // CHECK-ENCODING: [0x00,0xc0,0x7f,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 7f 24 <unknown>
+// CHECK-UNKNOWN: 247fc000 <unknown>
 
 cmphs   p0.s, p0/z, z0.s, #127
 // CHECK-INST: cmphs p0.s, p0/z, z0.s, #127
 // CHECK-ENCODING: [0x00,0xc0,0xbf,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 bf 24 <unknown>
+// CHECK-UNKNOWN: 24bfc000 <unknown>
 
 cmphs   p0.d, p0/z, z0.d, #127
 // CHECK-INST: cmphs p0.d, p0/z, z0.d, #127
 // CHECK-ENCODING: [0x00,0xc0,0xff,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 ff 24 <unknown>
+// CHECK-UNKNOWN: 24ffc000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cmple.s b/llvm/test/MC/AArch64/SVE/cmple.s
index ad29a028c36af..7c68d183f688f 100644
--- a/llvm/test/MC/AArch64/SVE/cmple.s
+++ b/llvm/test/MC/AArch64/SVE/cmple.s
@@ -13,88 +13,88 @@ cmple   p0.b, p0/z, z0.b, z1.b
 // CHECK-INST: cmpge	p0.b, p0/z, z1.b, z0.b
 // CHECK-ENCODING: [0x20,0x80,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 00 24 <unknown>
+// CHECK-UNKNOWN: 24008020 <unknown>
 
 cmple   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: cmpge	p0.h, p0/z, z1.h, z0.h
 // CHECK-ENCODING: [0x20,0x80,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 40 24 <unknown>
+// CHECK-UNKNOWN: 24408020 <unknown>
 
 cmple   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: cmpge	p0.s, p0/z, z1.s, z0.s
 // CHECK-ENCODING: [0x20,0x80,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 80 24 <unknown>
+// CHECK-UNKNOWN: 24808020 <unknown>
 
 cmple   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: cmpge	p0.d, p0/z, z1.d, z0.d
 // CHECK-ENCODING: [0x20,0x80,0xc0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 c0 24 <unknown>
+// CHECK-UNKNOWN: 24c08020 <unknown>
 
 cmple   p0.b, p0/z, z0.b, z0.d
 // CHECK-INST: cmple p0.b, p0/z, z0.b, z0.d
 // CHECK-ENCODING: [0x10,0x60,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 60 00 24 <unknown>
+// CHECK-UNKNOWN: 24006010 <unknown>
 
 cmple   p0.h, p0/z, z0.h, z0.d
 // CHECK-INST: cmple p0.h, p0/z, z0.h, z0.d
 // CHECK-ENCODING: [0x10,0x60,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 60 40 24 <unknown>
+// CHECK-UNKNOWN: 24406010 <unknown>
 
 cmple   p0.s, p0/z, z0.s, z0.d
 // CHECK-INST: cmple p0.s, p0/z, z0.s, z0.d
 // CHECK-ENCODING: [0x10,0x60,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 60 80 24 <unknown>
+// CHECK-UNKNOWN: 24806010 <unknown>
 
 cmple   p0.b, p0/z, z0.b, #-16
 // CHECK-INST: cmple p0.b, p0/z, z0.b, #-16
 // CHECK-ENCODING: [0x10,0x20,0x10,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 10 25 <unknown>
+// CHECK-UNKNOWN: 25102010 <unknown>
 
 cmple   p0.h, p0/z, z0.h, #-16
 // CHECK-INST: cmple p0.h, p0/z, z0.h, #-16
 // CHECK-ENCODING: [0x10,0x20,0x50,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 50 25 <unknown>
+// CHECK-UNKNOWN: 25502010 <unknown>
 
 cmple   p0.s, p0/z, z0.s, #-16
 // CHECK-INST: cmple p0.s, p0/z, z0.s, #-16
 // CHECK-ENCODING: [0x10,0x20,0x90,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 90 25 <unknown>
+// CHECK-UNKNOWN: 25902010 <unknown>
 
 cmple   p0.d, p0/z, z0.d, #-16
 // CHECK-INST: cmple p0.d, p0/z, z0.d, #-16
 // CHECK-ENCODING: [0x10,0x20,0xd0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 d0 25 <unknown>
+// CHECK-UNKNOWN: 25d02010 <unknown>
 
 cmple   p0.b, p0/z, z0.b, #15
 // CHECK-INST: cmple p0.b, p0/z, z0.b, #15
 // CHECK-ENCODING: [0x10,0x20,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 0f 25 <unknown>
+// CHECK-UNKNOWN: 250f2010 <unknown>
 
 cmple   p0.h, p0/z, z0.h, #15
 // CHECK-INST: cmple p0.h, p0/z, z0.h, #15
 // CHECK-ENCODING: [0x10,0x20,0x4f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 4f 25 <unknown>
+// CHECK-UNKNOWN: 254f2010 <unknown>
 
 cmple   p0.s, p0/z, z0.s, #15
 // CHECK-INST: cmple p0.s, p0/z, z0.s, #15
 // CHECK-ENCODING: [0x10,0x20,0x8f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 8f 25 <unknown>
+// CHECK-UNKNOWN: 258f2010 <unknown>
 
 cmple   p0.d, p0/z, z0.d, #15
 // CHECK-INST: cmple p0.d, p0/z, z0.d, #15
 // CHECK-ENCODING: [0x10,0x20,0xcf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 cf 25 <unknown>
+// CHECK-UNKNOWN: 25cf2010 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cmplo.s b/llvm/test/MC/AArch64/SVE/cmplo.s
index 6aedc089b4a7a..4fe9329f15e2c 100644
--- a/llvm/test/MC/AArch64/SVE/cmplo.s
+++ b/llvm/test/MC/AArch64/SVE/cmplo.s
@@ -13,88 +13,88 @@ cmplo   p0.b, p0/z, z0.b, z1.b
 // CHECK-INST: cmphi	p0.b, p0/z, z1.b, z0.b
 // CHECK-ENCODING: [0x30,0x00,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 00 00 24 <unknown>
+// CHECK-UNKNOWN: 24000030 <unknown>
 
 cmplo   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: cmphi	p0.h, p0/z, z1.h, z0.h
 // CHECK-ENCODING: [0x30,0x00,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 00 40 24 <unknown>
+// CHECK-UNKNOWN: 24400030 <unknown>
 
 cmplo   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: cmphi	p0.s, p0/z, z1.s, z0.s
 // CHECK-ENCODING: [0x30,0x00,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 00 80 24 <unknown>
+// CHECK-UNKNOWN: 24800030 <unknown>
 
 cmplo   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: cmphi	p0.d, p0/z, z1.d, z0.d
 // CHECK-ENCODING: [0x30,0x00,0xc0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 00 c0 24 <unknown>
+// CHECK-UNKNOWN: 24c00030 <unknown>
 
 cmplo   p0.b, p0/z, z0.b, z0.d
 // CHECK-INST: cmplo p0.b, p0/z, z0.b, z0.d
 // CHECK-ENCODING: [0x00,0xe0,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 00 24 <unknown>
+// CHECK-UNKNOWN: 2400e000 <unknown>
 
 cmplo   p0.h, p0/z, z0.h, z0.d
 // CHECK-INST: cmplo p0.h, p0/z, z0.h, z0.d
 // CHECK-ENCODING: [0x00,0xe0,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 40 24 <unknown>
+// CHECK-UNKNOWN: 2440e000 <unknown>
 
 cmplo   p0.s, p0/z, z0.s, z0.d
 // CHECK-INST: cmplo p0.s, p0/z, z0.s, z0.d
 // CHECK-ENCODING: [0x00,0xe0,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 80 24 <unknown>
+// CHECK-UNKNOWN: 2480e000 <unknown>
 
 cmplo   p0.b, p0/z, z0.b, #0
 // CHECK-INST: cmplo p0.b, p0/z, z0.b, #0
 // CHECK-ENCODING: [0x00,0x20,0x20,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 20 24 <unknown>
+// CHECK-UNKNOWN: 24202000 <unknown>
 
 cmplo   p0.h, p0/z, z0.h, #0
 // CHECK-INST: cmplo p0.h, p0/z, z0.h, #0
 // CHECK-ENCODING: [0x00,0x20,0x60,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 60 24 <unknown>
+// CHECK-UNKNOWN: 24602000 <unknown>
 
 cmplo   p0.s, p0/z, z0.s, #0
 // CHECK-INST: cmplo p0.s, p0/z, z0.s, #0
 // CHECK-ENCODING: [0x00,0x20,0xa0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 a0 24 <unknown>
+// CHECK-UNKNOWN: 24a02000 <unknown>
 
 cmplo   p0.d, p0/z, z0.d, #0
 // CHECK-INST: cmplo p0.d, p0/z, z0.d, #0
 // CHECK-ENCODING: [0x00,0x20,0xe0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 e0 24 <unknown>
+// CHECK-UNKNOWN: 24e02000 <unknown>
 
 cmplo   p0.b, p0/z, z0.b, #127
 // CHECK-INST: cmplo p0.b, p0/z, z0.b, #127
 // CHECK-ENCODING: [0x00,0xe0,0x3f,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 3f 24 <unknown>
+// CHECK-UNKNOWN: 243fe000 <unknown>
 
 cmplo   p0.h, p0/z, z0.h, #127
 // CHECK-INST: cmplo p0.h, p0/z, z0.h, #127
 // CHECK-ENCODING: [0x00,0xe0,0x7f,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 7f 24 <unknown>
+// CHECK-UNKNOWN: 247fe000 <unknown>
 
 cmplo   p0.s, p0/z, z0.s, #127
 // CHECK-INST: cmplo p0.s, p0/z, z0.s, #127
 // CHECK-ENCODING: [0x00,0xe0,0xbf,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 bf 24 <unknown>
+// CHECK-UNKNOWN: 24bfe000 <unknown>
 
 cmplo   p0.d, p0/z, z0.d, #127
 // CHECK-INST: cmplo p0.d, p0/z, z0.d, #127
 // CHECK-ENCODING: [0x00,0xe0,0xff,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 ff 24 <unknown>
+// CHECK-UNKNOWN: 24ffe000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cmpls.s b/llvm/test/MC/AArch64/SVE/cmpls.s
index a33196245e43c..a8e130a8ef3de 100644
--- a/llvm/test/MC/AArch64/SVE/cmpls.s
+++ b/llvm/test/MC/AArch64/SVE/cmpls.s
@@ -13,88 +13,88 @@ cmpls   p0.b, p0/z, z0.b, z1.b
 // CHECK-INST: cmphs	p0.b, p0/z, z1.b, z0.b
 // CHECK-ENCODING: [0x20,0x00,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 00 24 <unknown>
+// CHECK-UNKNOWN: 24000020 <unknown>
 
 cmpls   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: cmphs	p0.h, p0/z, z1.h, z0.h
 // CHECK-ENCODING: [0x20,0x00,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 40 24 <unknown>
+// CHECK-UNKNOWN: 24400020 <unknown>
 
 cmpls   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: cmphs	p0.s, p0/z, z1.s, z0.s
 // CHECK-ENCODING: [0x20,0x00,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 80 24 <unknown>
+// CHECK-UNKNOWN: 24800020 <unknown>
 
 cmpls   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: cmphs	p0.d, p0/z, z1.d, z0.d
 // CHECK-ENCODING: [0x20,0x00,0xc0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 c0 24 <unknown>
+// CHECK-UNKNOWN: 24c00020 <unknown>
 
 cmpls   p0.b, p0/z, z0.b, z0.d
 // CHECK-INST: cmpls p0.b, p0/z, z0.b, z0.d
 // CHECK-ENCODING: [0x10,0xe0,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 e0 00 24 <unknown>
+// CHECK-UNKNOWN: 2400e010 <unknown>
 
 cmpls   p0.h, p0/z, z0.h, z0.d
 // CHECK-INST: cmpls p0.h, p0/z, z0.h, z0.d
 // CHECK-ENCODING: [0x10,0xe0,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 e0 40 24 <unknown>
+// CHECK-UNKNOWN: 2440e010 <unknown>
 
 cmpls   p0.s, p0/z, z0.s, z0.d
 // CHECK-INST: cmpls p0.s, p0/z, z0.s, z0.d
 // CHECK-ENCODING: [0x10,0xe0,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 e0 80 24 <unknown>
+// CHECK-UNKNOWN: 2480e010 <unknown>
 
 cmpls   p0.b, p0/z, z0.b, #0
 // CHECK-INST: cmpls p0.b, p0/z, z0.b, #0
 // CHECK-ENCODING: [0x10,0x20,0x20,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 20 24 <unknown>
+// CHECK-UNKNOWN: 24202010 <unknown>
 
 cmpls   p0.h, p0/z, z0.h, #0
 // CHECK-INST: cmpls p0.h, p0/z, z0.h, #0
 // CHECK-ENCODING: [0x10,0x20,0x60,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 60 24 <unknown>
+// CHECK-UNKNOWN: 24602010 <unknown>
 
 cmpls   p0.s, p0/z, z0.s, #0
 // CHECK-INST: cmpls p0.s, p0/z, z0.s, #0
 // CHECK-ENCODING: [0x10,0x20,0xa0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 a0 24 <unknown>
+// CHECK-UNKNOWN: 24a02010 <unknown>
 
 cmpls   p0.d, p0/z, z0.d, #0
 // CHECK-INST: cmpls p0.d, p0/z, z0.d, #0
 // CHECK-ENCODING: [0x10,0x20,0xe0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 e0 24 <unknown>
+// CHECK-UNKNOWN: 24e02010 <unknown>
 
 cmpls   p0.b, p0/z, z0.b, #127
 // CHECK-INST: cmpls p0.b, p0/z, z0.b, #127
 // CHECK-ENCODING: [0x10,0xe0,0x3f,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 e0 3f 24 <unknown>
+// CHECK-UNKNOWN: 243fe010 <unknown>
 
 cmpls   p0.h, p0/z, z0.h, #127
 // CHECK-INST: cmpls p0.h, p0/z, z0.h, #127
 // CHECK-ENCODING: [0x10,0xe0,0x7f,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 e0 7f 24 <unknown>
+// CHECK-UNKNOWN: 247fe010 <unknown>
 
 cmpls   p0.s, p0/z, z0.s, #127
 // CHECK-INST: cmpls p0.s, p0/z, z0.s, #127
 // CHECK-ENCODING: [0x10,0xe0,0xbf,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 e0 bf 24 <unknown>
+// CHECK-UNKNOWN: 24bfe010 <unknown>
 
 cmpls   p0.d, p0/z, z0.d, #127
 // CHECK-INST: cmpls p0.d, p0/z, z0.d, #127
 // CHECK-ENCODING: [0x10,0xe0,0xff,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 e0 ff 24 <unknown>
+// CHECK-UNKNOWN: 24ffe010 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cmplt.s b/llvm/test/MC/AArch64/SVE/cmplt.s
index 149f9a0e52877..0139fe8ed448a 100644
--- a/llvm/test/MC/AArch64/SVE/cmplt.s
+++ b/llvm/test/MC/AArch64/SVE/cmplt.s
@@ -13,88 +13,88 @@ cmplt   p0.b, p0/z, z0.b, z1.b
 // CHECK-INST: cmpgt	p0.b, p0/z, z1.b, z0.b
 // CHECK-ENCODING: [0x30,0x80,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 80 00 24 <unknown>
+// CHECK-UNKNOWN: 24008030 <unknown>
 
 cmplt   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: cmpgt	p0.h, p0/z, z1.h, z0.h
 // CHECK-ENCODING: [0x30,0x80,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 80 40 24 <unknown>
+// CHECK-UNKNOWN: 24408030 <unknown>
 
 cmplt   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: cmpgt	p0.s, p0/z, z1.s, z0.s
 // CHECK-ENCODING: [0x30,0x80,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 80 80 24 <unknown>
+// CHECK-UNKNOWN: 24808030 <unknown>
 
 cmplt   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: cmpgt	p0.d, p0/z, z1.d, z0.d
 // CHECK-ENCODING: [0x30,0x80,0xc0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 80 c0 24 <unknown>
+// CHECK-UNKNOWN: 24c08030 <unknown>
 
 cmplt   p0.b, p0/z, z0.b, z0.d
 // CHECK-INST: cmplt p0.b, p0/z, z0.b, z0.d
 // CHECK-ENCODING: [0x00,0x60,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 00 24 <unknown>
+// CHECK-UNKNOWN: 24006000 <unknown>
 
 cmplt   p0.h, p0/z, z0.h, z0.d
 // CHECK-INST: cmplt p0.h, p0/z, z0.h, z0.d
 // CHECK-ENCODING: [0x00,0x60,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 40 24 <unknown>
+// CHECK-UNKNOWN: 24406000 <unknown>
 
 cmplt   p0.s, p0/z, z0.s, z0.d
 // CHECK-INST: cmplt p0.s, p0/z, z0.s, z0.d
 // CHECK-ENCODING: [0x00,0x60,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 80 24 <unknown>
+// CHECK-UNKNOWN: 24806000 <unknown>
 
 cmplt   p0.b, p0/z, z0.b, #-16
 // CHECK-INST: cmplt p0.b, p0/z, z0.b, #-16
 // CHECK-ENCODING: [0x00,0x20,0x10,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 10 25 <unknown>
+// CHECK-UNKNOWN: 25102000 <unknown>
 
 cmplt   p0.h, p0/z, z0.h, #-16
 // CHECK-INST: cmplt p0.h, p0/z, z0.h, #-16
 // CHECK-ENCODING: [0x00,0x20,0x50,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 50 25 <unknown>
+// CHECK-UNKNOWN: 25502000 <unknown>
 
 cmplt   p0.s, p0/z, z0.s, #-16
 // CHECK-INST: cmplt p0.s, p0/z, z0.s, #-16
 // CHECK-ENCODING: [0x00,0x20,0x90,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 90 25 <unknown>
+// CHECK-UNKNOWN: 25902000 <unknown>
 
 cmplt   p0.d, p0/z, z0.d, #-16
 // CHECK-INST: cmplt p0.d, p0/z, z0.d, #-16
 // CHECK-ENCODING: [0x00,0x20,0xd0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 d0 25 <unknown>
+// CHECK-UNKNOWN: 25d02000 <unknown>
 
 cmplt   p0.b, p0/z, z0.b, #15
 // CHECK-INST: cmplt p0.b, p0/z, z0.b, #15
 // CHECK-ENCODING: [0x00,0x20,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 0f 25 <unknown>
+// CHECK-UNKNOWN: 250f2000 <unknown>
 
 cmplt   p0.h, p0/z, z0.h, #15
 // CHECK-INST: cmplt p0.h, p0/z, z0.h, #15
 // CHECK-ENCODING: [0x00,0x20,0x4f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 4f 25 <unknown>
+// CHECK-UNKNOWN: 254f2000 <unknown>
 
 cmplt   p0.s, p0/z, z0.s, #15
 // CHECK-INST: cmplt p0.s, p0/z, z0.s, #15
 // CHECK-ENCODING: [0x00,0x20,0x8f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 8f 25 <unknown>
+// CHECK-UNKNOWN: 258f2000 <unknown>
 
 cmplt   p0.d, p0/z, z0.d, #15
 // CHECK-INST: cmplt p0.d, p0/z, z0.d, #15
 // CHECK-ENCODING: [0x00,0x20,0xcf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 cf 25 <unknown>
+// CHECK-UNKNOWN: 25cf2000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cmpne.s b/llvm/test/MC/AArch64/SVE/cmpne.s
index 13928dc666d50..5ec8d83544916 100644
--- a/llvm/test/MC/AArch64/SVE/cmpne.s
+++ b/llvm/test/MC/AArch64/SVE/cmpne.s
@@ -14,88 +14,88 @@ cmpne   p0.b, p0/z, z0.b, z0.b
 // CHECK-INST: cmpne p0.b, p0/z, z0.b, z0.b
 // CHECK-ENCODING: [0x10,0xa0,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 a0 00 24 <unknown>
+// CHECK-UNKNOWN: 2400a010 <unknown>
 
 cmpne   p0.h, p0/z, z0.h, z0.h
 // CHECK-INST: cmpne p0.h, p0/z, z0.h, z0.h
 // CHECK-ENCODING: [0x10,0xa0,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 a0 40 24 <unknown>
+// CHECK-UNKNOWN: 2440a010 <unknown>
 
 cmpne   p0.s, p0/z, z0.s, z0.s
 // CHECK-INST: cmpne p0.s, p0/z, z0.s, z0.s
 // CHECK-ENCODING: [0x10,0xa0,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 a0 80 24 <unknown>
+// CHECK-UNKNOWN: 2480a010 <unknown>
 
 cmpne   p0.d, p0/z, z0.d, z0.d
 // CHECK-INST: cmpne p0.d, p0/z, z0.d, z0.d
 // CHECK-ENCODING: [0x10,0xa0,0xc0,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 a0 c0 24 <unknown>
+// CHECK-UNKNOWN: 24c0a010 <unknown>
 
 cmpne   p0.b, p0/z, z0.b, z0.d
 // CHECK-INST: cmpne p0.b, p0/z, z0.b, z0.d
 // CHECK-ENCODING: [0x10,0x20,0x00,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 00 24 <unknown>
+// CHECK-UNKNOWN: 24002010 <unknown>
 
 cmpne   p0.h, p0/z, z0.h, z0.d
 // CHECK-INST: cmpne p0.h, p0/z, z0.h, z0.d
 // CHECK-ENCODING: [0x10,0x20,0x40,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 40 24 <unknown>
+// CHECK-UNKNOWN: 24402010 <unknown>
 
 cmpne   p0.s, p0/z, z0.s, z0.d
 // CHECK-INST: cmpne p0.s, p0/z, z0.s, z0.d
 // CHECK-ENCODING: [0x10,0x20,0x80,0x24]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 80 24 <unknown>
+// CHECK-UNKNOWN: 24802010 <unknown>
 
 cmpne   p0.b, p0/z, z0.b, #-16
 // CHECK-INST: cmpne p0.b, p0/z, z0.b, #-16
 // CHECK-ENCODING: [0x10,0x80,0x10,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 80 10 25 <unknown>
+// CHECK-UNKNOWN: 25108010 <unknown>
 
 cmpne   p0.h, p0/z, z0.h, #-16
 // CHECK-INST: cmpne p0.h, p0/z, z0.h, #-16
 // CHECK-ENCODING: [0x10,0x80,0x50,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 80 50 25 <unknown>
+// CHECK-UNKNOWN: 25508010 <unknown>
 
 cmpne   p0.s, p0/z, z0.s, #-16
 // CHECK-INST: cmpne p0.s, p0/z, z0.s, #-16
 // CHECK-ENCODING: [0x10,0x80,0x90,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 80 90 25 <unknown>
+// CHECK-UNKNOWN: 25908010 <unknown>
 
 cmpne   p0.d, p0/z, z0.d, #-16
 // CHECK-INST: cmpne p0.d, p0/z, z0.d, #-16
 // CHECK-ENCODING: [0x10,0x80,0xd0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 80 d0 25 <unknown>
+// CHECK-UNKNOWN: 25d08010 <unknown>
 
 cmpne   p0.b, p0/z, z0.b, #15
 // CHECK-INST: cmpne p0.b, p0/z, z0.b, #15
 // CHECK-ENCODING: [0x10,0x80,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 80 0f 25 <unknown>
+// CHECK-UNKNOWN: 250f8010 <unknown>
 
 cmpne   p0.h, p0/z, z0.h, #15
 // CHECK-INST: cmpne p0.h, p0/z, z0.h, #15
 // CHECK-ENCODING: [0x10,0x80,0x4f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 80 4f 25 <unknown>
+// CHECK-UNKNOWN: 254f8010 <unknown>
 
 cmpne   p0.s, p0/z, z0.s, #15
 // CHECK-INST: cmpne p0.s, p0/z, z0.s, #15
 // CHECK-ENCODING: [0x10,0x80,0x8f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 80 8f 25 <unknown>
+// CHECK-UNKNOWN: 258f8010 <unknown>
 
 cmpne   p0.d, p0/z, z0.d, #15
 // CHECK-INST: cmpne p0.d, p0/z, z0.d, #15
 // CHECK-ENCODING: [0x10,0x80,0xcf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 80 cf 25 <unknown>
+// CHECK-UNKNOWN: 25cf8010 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cnot.s b/llvm/test/MC/AArch64/SVE/cnot.s
index 5049c9919ec01..486b24c319813 100644
--- a/llvm/test/MC/AArch64/SVE/cnot.s
+++ b/llvm/test/MC/AArch64/SVE/cnot.s
@@ -13,25 +13,25 @@ cnot    z31.b, p7/m, z31.b
 // CHECK-INST: cnot	z31.b, p7/m, z31.b
 // CHECK-ENCODING: [0xff,0xbf,0x1b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 1b 04 <unknown>
+// CHECK-UNKNOWN: 041bbfff <unknown>
 
 cnot    z31.h, p7/m, z31.h
 // CHECK-INST: cnot	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x5b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 5b 04 <unknown>
+// CHECK-UNKNOWN: 045bbfff <unknown>
 
 cnot    z31.s, p7/m, z31.s
 // CHECK-INST: cnot	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x9b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 9b 04 <unknown>
+// CHECK-UNKNOWN: 049bbfff <unknown>
 
 cnot    z31.d, p7/m, z31.d
 // CHECK-INST: cnot	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xdb,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf db 04 <unknown>
+// CHECK-UNKNOWN: 04dbbfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 cnot    z4.d, p7/m, z31.d
 // CHECK-INST: cnot	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xdb,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf db 04 <unknown>
+// CHECK-UNKNOWN: 04dbbfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 cnot    z4.d, p7/m, z31.d
 // CHECK-INST: cnot	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xdb,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf db 04 <unknown>
+// CHECK-UNKNOWN: 04dbbfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cnt.s b/llvm/test/MC/AArch64/SVE/cnt.s
index bba166a349d50..c06ffa42e6bdc 100644
--- a/llvm/test/MC/AArch64/SVE/cnt.s
+++ b/llvm/test/MC/AArch64/SVE/cnt.s
@@ -13,25 +13,25 @@ cnt     z31.b, p7/m, z31.b
 // CHECK-INST: cnt	z31.b, p7/m, z31.b
 // CHECK-ENCODING: [0xff,0xbf,0x1a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 1a 04 <unknown>
+// CHECK-UNKNOWN: 041abfff <unknown>
 
 cnt     z31.h, p7/m, z31.h
 // CHECK-INST: cnt	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x5a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 5a 04 <unknown>
+// CHECK-UNKNOWN: 045abfff <unknown>
 
 cnt     z31.s, p7/m, z31.s
 // CHECK-INST: cnt	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x9a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 9a 04 <unknown>
+// CHECK-UNKNOWN: 049abfff <unknown>
 
 cnt     z31.d, p7/m, z31.d
 // CHECK-INST: cnt	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xda,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf da 04 <unknown>
+// CHECK-UNKNOWN: 04dabfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 cnt     z4.d, p7/m, z31.d
 // CHECK-INST: cnt	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xda,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf da 04 <unknown>
+// CHECK-UNKNOWN: 04dabfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 cnt     z4.d, p7/m, z31.d
 // CHECK-INST: cnt	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xda,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf da 04 <unknown>
+// CHECK-UNKNOWN: 04dabfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cntb.s b/llvm/test/MC/AArch64/SVE/cntb.s
index b454ab4f80302..c32c4e61552dd 100644
--- a/llvm/test/MC/AArch64/SVE/cntb.s
+++ b/llvm/test/MC/AArch64/SVE/cntb.s
@@ -13,34 +13,34 @@ cntb  x0
 // CHECK-INST: cntb	x0
 // CHECK-ENCODING: [0xe0,0xe3,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 20 04 <unknown>
+// CHECK-UNKNOWN: 0420e3e0 <unknown>
 
 cntb  x0, all
 // CHECK-INST: cntb	x0
 // CHECK-ENCODING: [0xe0,0xe3,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 20 04 <unknown>
+// CHECK-UNKNOWN: 0420e3e0 <unknown>
 
 cntb  x0, all, mul #1
 // CHECK-INST: cntb	x0
 // CHECK-ENCODING: [0xe0,0xe3,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 20 04 <unknown>
+// CHECK-UNKNOWN: 0420e3e0 <unknown>
 
 cntb  x0, all, mul #16
 // CHECK-INST: cntb	x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xe3,0x2f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 2f 04 <unknown>
+// CHECK-UNKNOWN: 042fe3e0 <unknown>
 
 cntb  x0, pow2
 // CHECK-INST: cntb	x0, pow2
 // CHECK-ENCODING: [0x00,0xe0,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 20 04 <unknown>
+// CHECK-UNKNOWN: 0420e000 <unknown>
 
 cntb  x0, #28
 // CHECK-INST: cntb	x0, #28
 // CHECK-ENCODING: [0x80,0xe3,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e3 20 04 <unknown>
+// CHECK-UNKNOWN: 0420e380 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cntd.s b/llvm/test/MC/AArch64/SVE/cntd.s
index b018990cba9a1..b236ea7ad6f75 100644
--- a/llvm/test/MC/AArch64/SVE/cntd.s
+++ b/llvm/test/MC/AArch64/SVE/cntd.s
@@ -13,34 +13,34 @@ cntd  x0
 // CHECK-INST: cntd	x0
 // CHECK-ENCODING: [0xe0,0xe3,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0e3e0 <unknown>
 
 cntd  x0, all
 // CHECK-INST: cntd	x0
 // CHECK-ENCODING: [0xe0,0xe3,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0e3e0 <unknown>
 
 cntd  x0, all, mul #1
 // CHECK-INST: cntd	x0
 // CHECK-ENCODING: [0xe0,0xe3,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0e3e0 <unknown>
 
 cntd  x0, all, mul #16
 // CHECK-INST: cntd	x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xe3,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 ef 04 <unknown>
+// CHECK-UNKNOWN: 04efe3e0 <unknown>
 
 cntd  x0, pow2
 // CHECK-INST: cntd	x0, pow2
 // CHECK-ENCODING: [0x00,0xe0,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0e000 <unknown>
 
 cntd  x0, #28
 // CHECK-INST: cntd	x0, #28
 // CHECK-ENCODING: [0x80,0xe3,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e3 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0e380 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cnth.s b/llvm/test/MC/AArch64/SVE/cnth.s
index fdcbe5dee1a27..031ab9e4bf495 100644
--- a/llvm/test/MC/AArch64/SVE/cnth.s
+++ b/llvm/test/MC/AArch64/SVE/cnth.s
@@ -13,34 +13,34 @@ cnth  x0
 // CHECK-INST: cnth	x0
 // CHECK-ENCODING: [0xe0,0xe3,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 60 04 <unknown>
+// CHECK-UNKNOWN: 0460e3e0 <unknown>
 
 cnth  x0, all
 // CHECK-INST: cnth	x0
 // CHECK-ENCODING: [0xe0,0xe3,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 60 04 <unknown>
+// CHECK-UNKNOWN: 0460e3e0 <unknown>
 
 cnth  x0, all, mul #1
 // CHECK-INST: cnth	x0
 // CHECK-ENCODING: [0xe0,0xe3,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 60 04 <unknown>
+// CHECK-UNKNOWN: 0460e3e0 <unknown>
 
 cnth  x0, all, mul #16
 // CHECK-INST: cnth	x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xe3,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fe3e0 <unknown>
 
 cnth  x0, pow2
 // CHECK-INST: cnth	x0, pow2
 // CHECK-ENCODING: [0x00,0xe0,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 60 04 <unknown>
+// CHECK-UNKNOWN: 0460e000 <unknown>
 
 cnth  x0, #28
 // CHECK-INST: cnth	x0, #28
 // CHECK-ENCODING: [0x80,0xe3,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e3 60 04 <unknown>
+// CHECK-UNKNOWN: 0460e380 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cntp.s b/llvm/test/MC/AArch64/SVE/cntp.s
index ae8d53629283b..ce70f800cda56 100644
--- a/llvm/test/MC/AArch64/SVE/cntp.s
+++ b/llvm/test/MC/AArch64/SVE/cntp.s
@@ -13,22 +13,22 @@ cntp  x0, p15, p0.b
 // CHECK-INST: cntp	x0, p15, p0.b
 // CHECK-ENCODING: [0x00,0xbc,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 bc 20 25 <unknown>
+// CHECK-UNKNOWN: 2520bc00 <unknown>
 
 cntp  x0, p15, p0.h
 // CHECK-INST: cntp	x0, p15, p0.h
 // CHECK-ENCODING: [0x00,0xbc,0x60,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 bc 60 25 <unknown>
+// CHECK-UNKNOWN: 2560bc00 <unknown>
 
 cntp  x0, p15, p0.s
 // CHECK-INST: cntp	x0, p15, p0.s
 // CHECK-ENCODING: [0x00,0xbc,0xa0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 bc a0 25 <unknown>
+// CHECK-UNKNOWN: 25a0bc00 <unknown>
 
 cntp  x0, p15, p0.d
 // CHECK-INST: cntp	x0, p15, p0.d
 // CHECK-ENCODING: [0x00,0xbc,0xe0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 bc e0 25 <unknown>
+// CHECK-UNKNOWN: 25e0bc00 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cntw.s b/llvm/test/MC/AArch64/SVE/cntw.s
index c20f27887a9a6..16ab187beedf4 100644
--- a/llvm/test/MC/AArch64/SVE/cntw.s
+++ b/llvm/test/MC/AArch64/SVE/cntw.s
@@ -13,34 +13,34 @@ cntw  x0
 // CHECK-INST: cntw	x0
 // CHECK-ENCODING: [0xe0,0xe3,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0e3e0 <unknown>
 
 cntw  x0, all
 // CHECK-INST: cntw	x0
 // CHECK-ENCODING: [0xe0,0xe3,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0e3e0 <unknown>
 
 cntw  x0, all, mul #1
 // CHECK-INST: cntw	x0
 // CHECK-ENCODING: [0xe0,0xe3,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0e3e0 <unknown>
 
 cntw  x0, all, mul #16
 // CHECK-INST: cntw	x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xe3,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 af 04 <unknown>
+// CHECK-UNKNOWN: 04afe3e0 <unknown>
 
 cntw  x0, pow2
 // CHECK-INST: cntw	x0, pow2
 // CHECK-ENCODING: [0x00,0xe0,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0e000 <unknown>
 
 cntw  x0, #28
 // CHECK-INST: cntw	x0, #28
 // CHECK-ENCODING: [0x80,0xe3,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e3 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0e380 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/compact.s b/llvm/test/MC/AArch64/SVE/compact.s
index ce901eddda5a8..ff815980781d7 100644
--- a/llvm/test/MC/AArch64/SVE/compact.s
+++ b/llvm/test/MC/AArch64/SVE/compact.s
@@ -13,10 +13,10 @@ compact z31.s, p7, z31.s
 // CHECK-INST: compact z31.s, p7, z31.s
 // CHECK-ENCODING: [0xff,0x9f,0xa1,0x05]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 9f a1 05 <unknown>
+// CHECK-UNKNOWN: 05a19fff <unknown>
 
 compact z31.d, p7, z31.d
 // CHECK-INST: compact z31.d, p7, z31.d
 // CHECK-ENCODING: [0xff,0x9f,0xe1,0x05]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 9f e1 05 <unknown>
+// CHECK-UNKNOWN: 05e19fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/cpy.s b/llvm/test/MC/AArch64/SVE/cpy.s
index a8cacfa275af7..ff22c28fdf87a 100644
--- a/llvm/test/MC/AArch64/SVE/cpy.s
+++ b/llvm/test/MC/AArch64/SVE/cpy.s
@@ -13,223 +13,223 @@ cpy     z0.b, p0/m, w0
 // CHECK-INST: mov     z0.b, p0/m, w0
 // CHECK-ENCODING: [0x00,0xa0,0x28,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 28 05 <unknown>
+// CHECK-UNKNOWN: 0528a000 <unknown>
 
 cpy     z0.h, p0/m, w0
 // CHECK-INST: mov     z0.h, p0/m, w0
 // CHECK-ENCODING: [0x00,0xa0,0x68,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 68 05 <unknown>
+// CHECK-UNKNOWN: 0568a000 <unknown>
 
 cpy     z0.s, p0/m, w0
 // CHECK-INST: mov     z0.s, p0/m, w0
 // CHECK-ENCODING: [0x00,0xa0,0xa8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 a8 05 <unknown>
+// CHECK-UNKNOWN: 05a8a000 <unknown>
 
 cpy     z0.d, p0/m, x0
 // CHECK-INST: mov     z0.d, p0/m, x0
 // CHECK-ENCODING: [0x00,0xa0,0xe8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 e8 05 <unknown>
+// CHECK-UNKNOWN: 05e8a000 <unknown>
 
 cpy     z31.b, p7/m, wsp
 // CHECK-INST: mov     z31.b, p7/m, wsp
 // CHECK-ENCODING: [0xff,0xbf,0x28,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 28 05 <unknown>
+// CHECK-UNKNOWN: 0528bfff <unknown>
 
 cpy     z31.h, p7/m, wsp
 // CHECK-INST: mov     z31.h, p7/m, wsp
 // CHECK-ENCODING: [0xff,0xbf,0x68,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 68 05 <unknown>
+// CHECK-UNKNOWN: 0568bfff <unknown>
 
 cpy     z31.s, p7/m, wsp
 // CHECK-INST: mov     z31.s, p7/m, wsp
 // CHECK-ENCODING: [0xff,0xbf,0xa8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf a8 05 <unknown>
+// CHECK-UNKNOWN: 05a8bfff <unknown>
 
 cpy     z31.d, p7/m, sp
 // CHECK-INST: mov     z31.d, p7/m, sp
 // CHECK-ENCODING: [0xff,0xbf,0xe8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf e8 05 <unknown>
+// CHECK-UNKNOWN: 05e8bfff <unknown>
 
 cpy     z0.b, p0/m, b0
 // CHECK-INST: mov     z0.b, p0/m, b0
 // CHECK-ENCODING: [0x00,0x80,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 20 05 <unknown>
+// CHECK-UNKNOWN: 05208000 <unknown>
 
 cpy     z31.b, p7/m, b31
 // CHECK-INST: mov     z31.b, p7/m, b31
 // CHECK-ENCODING: [0xff,0x9f,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f 20 05 <unknown>
+// CHECK-UNKNOWN: 05209fff <unknown>
 
 cpy     z0.h, p0/m, h0
 // CHECK-INST: mov     z0.h, p0/m, h0
 // CHECK-ENCODING: [0x00,0x80,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 60 05 <unknown>
+// CHECK-UNKNOWN: 05608000 <unknown>
 
 cpy     z31.h, p7/m, h31
 // CHECK-INST: mov     z31.h, p7/m, h31
 // CHECK-ENCODING: [0xff,0x9f,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f 60 05 <unknown>
+// CHECK-UNKNOWN: 05609fff <unknown>
 
 cpy     z0.s, p0/m, s0
 // CHECK-INST: mov     z0.s, p0/m, s0
 // CHECK-ENCODING: [0x00,0x80,0xa0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 a0 05 <unknown>
+// CHECK-UNKNOWN: 05a08000 <unknown>
 
 cpy     z31.s, p7/m, s31
 // CHECK-INST: mov     z31.s, p7/m, s31
 // CHECK-ENCODING: [0xff,0x9f,0xa0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f a0 05 <unknown>
+// CHECK-UNKNOWN: 05a09fff <unknown>
 
 cpy     z0.d, p0/m, d0
 // CHECK-INST: mov     z0.d, p0/m, d0
 // CHECK-ENCODING: [0x00,0x80,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 e0 05 <unknown>
+// CHECK-UNKNOWN: 05e08000 <unknown>
 
 cpy     z31.d, p7/m, d31
 // CHECK-INST: mov     z31.d, p7/m, d31
 // CHECK-ENCODING: [0xff,0x9f,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f e0 05 <unknown>
+// CHECK-UNKNOWN: 05e09fff <unknown>
 
 cpy     z5.b, p0/z, #-128
 // CHECK-INST: mov     z5.b, p0/z, #-128
 // CHECK-ENCODING: [0x05,0x10,0x10,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 10 10 05  <unknown>
+// CHECK-UNKNOWN: 05101005  <unknown>
 
 cpy     z5.b, p0/z, #127
 // CHECK-INST: mov     z5.b, p0/z, #127
 // CHECK-ENCODING: [0xe5,0x0f,0x10,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 0f 10 05  <unknown>
+// CHECK-UNKNOWN: 05100fe5  <unknown>
 
 cpy     z5.b, p0/z, #255
 // CHECK-INST: mov     z5.b, p0/z, #-1
 // CHECK-ENCODING: [0xe5,0x1f,0x10,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 1f 10 05  <unknown>
+// CHECK-UNKNOWN: 05101fe5  <unknown>
 
 cpy     z21.h, p0/z, #-128
 // CHECK-INST: mov     z21.h, p0/z, #-128
 // CHECK-ENCODING: [0x15,0x10,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 10 50 05  <unknown>
+// CHECK-UNKNOWN: 05501015  <unknown>
 
 cpy     z21.h, p0/z, #-128, lsl #8
 // CHECK-INST: mov     z21.h, p0/z, #-32768
 // CHECK-ENCODING: [0x15,0x30,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 30 50 05  <unknown>
+// CHECK-UNKNOWN: 05503015  <unknown>
 
 cpy     z21.h, p0/z, #-32768
 // CHECK-INST: mov     z21.h, p0/z, #-32768
 // CHECK-ENCODING: [0x15,0x30,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 30 50 05  <unknown>
+// CHECK-UNKNOWN: 05503015  <unknown>
 
 cpy     z21.h, p0/z, #127
 // CHECK-INST: mov     z21.h, p0/z, #127
 // CHECK-ENCODING: [0xf5,0x0f,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 0f 50 05  <unknown>
+// CHECK-UNKNOWN: 05500ff5  <unknown>
 
 cpy     z21.h, p0/z, #127, lsl #8
 // CHECK-INST: mov     z21.h, p0/z, #32512
 // CHECK-ENCODING: [0xf5,0x2f,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 2f 50 05  <unknown>
+// CHECK-UNKNOWN: 05502ff5  <unknown>
 
 cpy     z21.h, p0/z, #32512
 // CHECK-INST: mov     z21.h, p0/z, #32512
 // CHECK-ENCODING: [0xf5,0x2f,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 2f 50 05  <unknown>
+// CHECK-UNKNOWN: 05502ff5  <unknown>
 
 cpy     z21.s, p0/z, #-128
 // CHECK-INST: mov     z21.s, p0/z, #-128
 // CHECK-ENCODING: [0x15,0x10,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 10 90 05  <unknown>
+// CHECK-UNKNOWN: 05901015  <unknown>
 
 cpy     z21.s, p0/z, #-128, lsl #8
 // CHECK-INST: mov     z21.s, p0/z, #-32768
 // CHECK-ENCODING: [0x15,0x30,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 30 90 05  <unknown>
+// CHECK-UNKNOWN: 05903015  <unknown>
 
 cpy     z21.s, p0/z, #-32768
 // CHECK-INST: mov     z21.s, p0/z, #-32768
 // CHECK-ENCODING: [0x15,0x30,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 30 90 05  <unknown>
+// CHECK-UNKNOWN: 05903015  <unknown>
 
 cpy     z21.s, p0/z, #127
 // CHECK-INST: mov     z21.s, p0/z, #127
 // CHECK-ENCODING: [0xf5,0x0f,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 0f 90 05  <unknown>
+// CHECK-UNKNOWN: 05900ff5  <unknown>
 
 cpy     z21.s, p0/z, #127, lsl #8
 // CHECK-INST: mov     z21.s, p0/z, #32512
 // CHECK-ENCODING: [0xf5,0x2f,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 2f 90 05  <unknown>
+// CHECK-UNKNOWN: 05902ff5  <unknown>
 
 cpy     z21.s, p0/z, #32512
 // CHECK-INST: mov     z21.s, p0/z, #32512
 // CHECK-ENCODING: [0xf5,0x2f,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 2f 90 05  <unknown>
+// CHECK-UNKNOWN: 05902ff5  <unknown>
 
 cpy     z21.d, p0/z, #-128
 // CHECK-INST: mov     z21.d, p0/z, #-128
 // CHECK-ENCODING: [0x15,0x10,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 10 d0 05  <unknown>
+// CHECK-UNKNOWN: 05d01015  <unknown>
 
 cpy     z21.d, p0/z, #-128, lsl #8
 // CHECK-INST: mov     z21.d, p0/z, #-32768
 // CHECK-ENCODING: [0x15,0x30,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 30 d0 05  <unknown>
+// CHECK-UNKNOWN: 05d03015  <unknown>
 
 cpy     z21.d, p0/z, #-32768
 // CHECK-INST: mov     z21.d, p0/z, #-32768
 // CHECK-ENCODING: [0x15,0x30,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 30 d0 05  <unknown>
+// CHECK-UNKNOWN: 05d03015  <unknown>
 
 cpy     z21.d, p0/z, #127
 // CHECK-INST: mov     z21.d, p0/z, #127
 // CHECK-ENCODING: [0xf5,0x0f,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 0f d0 05  <unknown>
+// CHECK-UNKNOWN: 05d00ff5  <unknown>
 
 cpy     z21.d, p0/z, #127, lsl #8
 // CHECK-INST: mov     z21.d, p0/z, #32512
 // CHECK-ENCODING: [0xf5,0x2f,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 2f d0 05  <unknown>
+// CHECK-UNKNOWN: 05d02ff5  <unknown>
 
 cpy     z21.d, p0/z, #32512
 // CHECK-INST: mov     z21.d, p0/z, #32512
 // CHECK-ENCODING: [0xf5,0x2f,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 2f d0 05  <unknown>
+// CHECK-UNKNOWN: 05d02ff5  <unknown>
 
 // --------------------------------------------------------------------------//
 // Tests where the negative immediate is in bounds when interpreted
@@ -239,19 +239,19 @@ cpy z0.b, p0/z, #-129
 // CHECK-INST: mov     z0.b, p0/z, #127
 // CHECK-ENCODING: [0xe0,0x0f,0x10,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 0f 10 05  <unknown>
+// CHECK-UNKNOWN: 05100fe0  <unknown>
 
 cpy z0.h, p0/z, #-33024
 // CHECK-INST: mov     z0.h, p0/z, #32512
 // CHECK-ENCODING: [0xe0,0x2f,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 2f 50 05  <unknown>
+// CHECK-UNKNOWN: 05502fe0  <unknown>
 
 cpy z0.h, p0/z, #-129, lsl #8
 // CHECK-INST: mov     z0.h, p0/z, #32512
 // CHECK-ENCODING: [0xe0,0x2f,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 2f 50 05  <unknown>
+// CHECK-UNKNOWN: 05502fe0  <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -262,43 +262,43 @@ cpy     z5.b, p15/m, #-128
 // CHECK-INST: mov     z5.b, p15/m, #-128
 // CHECK-ENCODING: [0x05,0x50,0x1f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 50 1f 05  <unknown>
+// CHECK-UNKNOWN: 051f5005  <unknown>
 
 cpy     z21.h, p15/m, #-128
 // CHECK-INST: mov     z21.h, p15/m, #-128
 // CHECK-ENCODING: [0x15,0x50,0x5f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 50 5f 05  <unknown>
+// CHECK-UNKNOWN: 055f5015  <unknown>
 
 cpy     z21.h, p15/m, #-128, lsl #8
 // CHECK-INST: mov     z21.h, p15/m, #-32768
 // CHECK-ENCODING: [0x15,0x70,0x5f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 70 5f 05  <unknown>
+// CHECK-UNKNOWN: 055f7015  <unknown>
 
 cpy     z21.s, p15/m, #-128
 // CHECK-INST: mov     z21.s, p15/m, #-128
 // CHECK-ENCODING: [0x15,0x50,0x9f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 50 9f 05  <unknown>
+// CHECK-UNKNOWN: 059f5015  <unknown>
 
 cpy     z21.s, p15/m, #-128, lsl #8
 // CHECK-INST: mov     z21.s, p15/m, #-32768
 // CHECK-ENCODING: [0x15,0x70,0x9f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 70 9f 05  <unknown>
+// CHECK-UNKNOWN: 059f7015  <unknown>
 
 cpy     z21.d, p15/m, #-128
 // CHECK-INST: mov     z21.d, p15/m, #-128
 // CHECK-ENCODING: [0x15,0x50,0xdf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 50 df 05  <unknown>
+// CHECK-UNKNOWN: 05df5015  <unknown>
 
 cpy     z21.d, p15/m, #-128, lsl #8
 // CHECK-INST: mov     z21.d, p15/m, #-32768
 // CHECK-ENCODING: [0x15,0x70,0xdf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 70 df 05  <unknown>
+// CHECK-UNKNOWN: 05df7015  <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -308,70 +308,70 @@ movprfx z31.d, p7/z, z6.d
 // CHECK-INST: movprfx	z31.d, p7/z, z6.d
 // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cdf <unknown>
 
 cpy     z31.d, p7/m, sp
 // CHECK-INST: mov	z31.d, p7/m, sp
 // CHECK-ENCODING: [0xff,0xbf,0xe8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf e8 05 <unknown>
+// CHECK-UNKNOWN: 05e8bfff <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 cpy     z31.d, p7/m, sp
 // CHECK-INST: mov	z31.d, p7/m, sp
 // CHECK-ENCODING: [0xff,0xbf,0xe8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf e8 05 <unknown>
+// CHECK-UNKNOWN: 05e8bfff <unknown>
 
 movprfx z21.d, p7/z, z28.d
 // CHECK-INST: movprfx	z21.d, p7/z, z28.d
 // CHECK-ENCODING: [0x95,0x3f,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 3f d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03f95 <unknown>
 
 cpy     z21.d, p7/m, #-128, lsl #8
 // CHECK-INST: mov	z21.d, p7/m, #-32768
 // CHECK-ENCODING: [0x15,0x70,0xd7,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 70 d7 05 <unknown>
+// CHECK-UNKNOWN: 05d77015 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 cpy     z21.d, p15/m, #-128, lsl #8
 // CHECK-INST: mov	z21.d, p15/m, #-32768
 // CHECK-ENCODING: [0x15,0x70,0xdf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 70 df 05 <unknown>
+// CHECK-UNKNOWN: 05df7015 <unknown>
 
 movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 cpy     z4.d, p7/m, d31
 // CHECK-INST: mov	z4.d, p7/m, d31
 // CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 9f e0 05 <unknown>
+// CHECK-UNKNOWN: 05e09fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 cpy     z4.d, p7/m, d31
 // CHECK-INST: mov	z4.d, p7/m, d31
 // CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 9f e0 05 <unknown>
+// CHECK-UNKNOWN: 05e09fe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ctermeq.s b/llvm/test/MC/AArch64/SVE/ctermeq.s
index 8ff4c1b3d711b..c6603ed74b989 100644
--- a/llvm/test/MC/AArch64/SVE/ctermeq.s
+++ b/llvm/test/MC/AArch64/SVE/ctermeq.s
@@ -13,22 +13,22 @@ ctermeq w30, wzr
 // CHECK-INST: ctermeq	w30, wzr
 // CHECK-ENCODING: [0xc0,0x23,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 23 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf23c0 <unknown>
 
 ctermeq wzr, w30
 // CHECK-INST: ctermeq	wzr, w30
 // CHECK-ENCODING: [0xe0,0x23,0xbe,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 23 be 25 <unknown>
+// CHECK-UNKNOWN: 25be23e0 <unknown>
 
 ctermeq x30, xzr
 // CHECK-INST: ctermeq	x30, xzr
 // CHECK-ENCODING: [0xc0,0x23,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 23 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff23c0 <unknown>
 
 ctermeq xzr, x30
 // CHECK-INST: ctermeq	xzr, x30
 // CHECK-ENCODING: [0xe0,0x23,0xfe,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 23 fe 25 <unknown>
+// CHECK-UNKNOWN: 25fe23e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ctermne.s b/llvm/test/MC/AArch64/SVE/ctermne.s
index c3755136d03de..6265b25848584 100644
--- a/llvm/test/MC/AArch64/SVE/ctermne.s
+++ b/llvm/test/MC/AArch64/SVE/ctermne.s
@@ -13,22 +13,22 @@ ctermne w30, wzr
 // CHECK-INST: ctermne	w30, wzr
 // CHECK-ENCODING: [0xd0,0x23,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: d0 23 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf23d0 <unknown>
 
 ctermne wzr, w30
 // CHECK-INST: ctermne	wzr, w30
 // CHECK-ENCODING: [0xf0,0x23,0xbe,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f0 23 be 25 <unknown>
+// CHECK-UNKNOWN: 25be23f0 <unknown>
 
 ctermne x30, xzr
 // CHECK-INST: ctermne	x30, xzr
 // CHECK-ENCODING: [0xd0,0x23,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: d0 23 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff23d0 <unknown>
 
 ctermne xzr, x30
 // CHECK-INST: ctermne	xzr, x30
 // CHECK-ENCODING: [0xf0,0x23,0xfe,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f0 23 fe 25 <unknown>
+// CHECK-UNKNOWN: 25fe23f0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/decb.s b/llvm/test/MC/AArch64/SVE/decb.s
index 2ef0846729d05..d616e85b35629 100644
--- a/llvm/test/MC/AArch64/SVE/decb.s
+++ b/llvm/test/MC/AArch64/SVE/decb.s
@@ -13,118 +13,118 @@ decb    x0
 // CHECK-INST: decb    x0
 // CHECK-ENCODING: [0xe0,0xe7,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e7e0 <unknown>
 
 decb    x0, all
 // CHECK-INST: decb    x0
 // CHECK-ENCODING: [0xe0,0xe7,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e7e0 <unknown>
 
 decb    x0, all, mul #1
 // CHECK-INST: decb    x0
 // CHECK-ENCODING: [0xe0,0xe7,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e7e0 <unknown>
 
 decb    x0, all, mul #16
 // CHECK-INST: decb    x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xe7,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 3f 04 <unknown>
+// CHECK-UNKNOWN: 043fe7e0 <unknown>
 
 decb    x0, pow2
 // CHECK-INST: decb    x0, pow2
 // CHECK-ENCODING: [0x00,0xe4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e400 <unknown>
 
 decb    x0, vl1
 // CHECK-INST: decb    x0, vl1
 // CHECK-ENCODING: [0x20,0xe4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e420 <unknown>
 
 decb    x0, vl2
 // CHECK-INST: decb    x0, vl2
 // CHECK-ENCODING: [0x40,0xe4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e440 <unknown>
 
 decb    x0, vl3
 // CHECK-INST: decb    x0, vl3
 // CHECK-ENCODING: [0x60,0xe4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e460 <unknown>
 
 decb    x0, vl4
 // CHECK-INST: decb    x0, vl4
 // CHECK-ENCODING: [0x80,0xe4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e480 <unknown>
 
 decb    x0, vl5
 // CHECK-INST: decb    x0, vl5
 // CHECK-ENCODING: [0xa0,0xe4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e4a0 <unknown>
 
 decb    x0, vl6
 // CHECK-INST: decb    x0, vl6
 // CHECK-ENCODING: [0xc0,0xe4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e4c0 <unknown>
 
 decb    x0, vl7
 // CHECK-INST: decb    x0, vl7
 // CHECK-ENCODING: [0xe0,0xe4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e4e0 <unknown>
 
 decb    x0, vl8
 // CHECK-INST: decb    x0, vl8
 // CHECK-ENCODING: [0x00,0xe5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e500 <unknown>
 
 decb    x0, vl16
 // CHECK-INST: decb    x0, vl16
 // CHECK-ENCODING: [0x20,0xe5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e520 <unknown>
 
 decb    x0, vl32
 // CHECK-INST: decb    x0, vl32
 // CHECK-ENCODING: [0x40,0xe5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e540 <unknown>
 
 decb    x0, vl64
 // CHECK-INST: decb    x0, vl64
 // CHECK-ENCODING: [0x60,0xe5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e560 <unknown>
 
 decb    x0, vl128
 // CHECK-INST: decb    x0, vl128
 // CHECK-ENCODING: [0x80,0xe5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e580 <unknown>
 
 decb    x0, vl256
 // CHECK-INST: decb    x0, vl256
 // CHECK-ENCODING: [0xa0,0xe5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e5a0 <unknown>
 
 decb    x0, #14
 // CHECK-INST: decb    x0, #14
 // CHECK-ENCODING: [0xc0,0xe5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e5c0 <unknown>
 
 decb    x0, #28
 // CHECK-INST: decb    x0, #28
 // CHECK-ENCODING: [0x80,0xe7,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e7 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e780 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/decd.s b/llvm/test/MC/AArch64/SVE/decd.s
index d4a316b1bd0c2..ed80be97629c8 100644
--- a/llvm/test/MC/AArch64/SVE/decd.s
+++ b/llvm/test/MC/AArch64/SVE/decd.s
@@ -13,118 +13,118 @@ decd    x0
 // CHECK-INST: decd    x0
 // CHECK-ENCODING: [0xe0,0xe7,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e7e0 <unknown>
 
 decd    x0, all
 // CHECK-INST: decd    x0
 // CHECK-ENCODING: [0xe0,0xe7,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e7e0 <unknown>
 
 decd    x0, all, mul #1
 // CHECK-INST: decd    x0
 // CHECK-ENCODING: [0xe0,0xe7,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e7e0 <unknown>
 
 decd    x0, all, mul #16
 // CHECK-INST: decd    x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xe7,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ffe7e0 <unknown>
 
 decd    x0, pow2
 // CHECK-INST: decd    x0, pow2
 // CHECK-ENCODING: [0x00,0xe4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e400 <unknown>
 
 decd    x0, vl1
 // CHECK-INST: decd    x0, vl1
 // CHECK-ENCODING: [0x20,0xe4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e420 <unknown>
 
 decd    x0, vl2
 // CHECK-INST: decd    x0, vl2
 // CHECK-ENCODING: [0x40,0xe4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e440 <unknown>
 
 decd    x0, vl3
 // CHECK-INST: decd    x0, vl3
 // CHECK-ENCODING: [0x60,0xe4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e460 <unknown>
 
 decd    x0, vl4
 // CHECK-INST: decd    x0, vl4
 // CHECK-ENCODING: [0x80,0xe4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e480 <unknown>
 
 decd    x0, vl5
 // CHECK-INST: decd    x0, vl5
 // CHECK-ENCODING: [0xa0,0xe4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e4a0 <unknown>
 
 decd    x0, vl6
 // CHECK-INST: decd    x0, vl6
 // CHECK-ENCODING: [0xc0,0xe4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e4c0 <unknown>
 
 decd    x0, vl7
 // CHECK-INST: decd    x0, vl7
 // CHECK-ENCODING: [0xe0,0xe4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e4e0 <unknown>
 
 decd    x0, vl8
 // CHECK-INST: decd    x0, vl8
 // CHECK-ENCODING: [0x00,0xe5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e500 <unknown>
 
 decd    x0, vl16
 // CHECK-INST: decd    x0, vl16
 // CHECK-ENCODING: [0x20,0xe5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e520 <unknown>
 
 decd    x0, vl32
 // CHECK-INST: decd    x0, vl32
 // CHECK-ENCODING: [0x40,0xe5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e540 <unknown>
 
 decd    x0, vl64
 // CHECK-INST: decd    x0, vl64
 // CHECK-ENCODING: [0x60,0xe5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e560 <unknown>
 
 decd    x0, vl128
 // CHECK-INST: decd    x0, vl128
 // CHECK-ENCODING: [0x80,0xe5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e580 <unknown>
 
 decd    x0, vl256
 // CHECK-INST: decd    x0, vl256
 // CHECK-ENCODING: [0xa0,0xe5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e5a0 <unknown>
 
 decd    x0, #14
 // CHECK-INST: decd    x0, #14
 // CHECK-ENCODING: [0xc0,0xe5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e5c0 <unknown>
 
 decd    x0, #28
 // CHECK-INST: decd    x0, #28
 // CHECK-ENCODING: [0x80,0xe7,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e7 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e780 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/dech.s b/llvm/test/MC/AArch64/SVE/dech.s
index 8b766ff32fe8c..aa11a5b7d6176 100644
--- a/llvm/test/MC/AArch64/SVE/dech.s
+++ b/llvm/test/MC/AArch64/SVE/dech.s
@@ -13,118 +13,118 @@ dech    x0
 // CHECK-INST: dech    x0
 // CHECK-ENCODING: [0xe0,0xe7,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e7e0 <unknown>
 
 dech    x0, all
 // CHECK-INST: dech    x0
 // CHECK-ENCODING: [0xe0,0xe7,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e7e0 <unknown>
 
 dech    x0, all, mul #1
 // CHECK-INST: dech    x0
 // CHECK-ENCODING: [0xe0,0xe7,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e7e0 <unknown>
 
 dech    x0, all, mul #16
 // CHECK-INST: dech    x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xe7,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 7f 04 <unknown>
+// CHECK-UNKNOWN: 047fe7e0 <unknown>
 
 dech    x0, pow2
 // CHECK-INST: dech    x0, pow2
 // CHECK-ENCODING: [0x00,0xe4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e400 <unknown>
 
 dech    x0, vl1
 // CHECK-INST: dech    x0, vl1
 // CHECK-ENCODING: [0x20,0xe4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e420 <unknown>
 
 dech    x0, vl2
 // CHECK-INST: dech    x0, vl2
 // CHECK-ENCODING: [0x40,0xe4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e440 <unknown>
 
 dech    x0, vl3
 // CHECK-INST: dech    x0, vl3
 // CHECK-ENCODING: [0x60,0xe4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e460 <unknown>
 
 dech    x0, vl4
 // CHECK-INST: dech    x0, vl4
 // CHECK-ENCODING: [0x80,0xe4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e480 <unknown>
 
 dech    x0, vl5
 // CHECK-INST: dech    x0, vl5
 // CHECK-ENCODING: [0xa0,0xe4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e4a0 <unknown>
 
 dech    x0, vl6
 // CHECK-INST: dech    x0, vl6
 // CHECK-ENCODING: [0xc0,0xe4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e4c0 <unknown>
 
 dech    x0, vl7
 // CHECK-INST: dech    x0, vl7
 // CHECK-ENCODING: [0xe0,0xe4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e4e0 <unknown>
 
 dech    x0, vl8
 // CHECK-INST: dech    x0, vl8
 // CHECK-ENCODING: [0x00,0xe5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e500 <unknown>
 
 dech    x0, vl16
 // CHECK-INST: dech    x0, vl16
 // CHECK-ENCODING: [0x20,0xe5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e520 <unknown>
 
 dech    x0, vl32
 // CHECK-INST: dech    x0, vl32
 // CHECK-ENCODING: [0x40,0xe5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e540 <unknown>
 
 dech    x0, vl64
 // CHECK-INST: dech    x0, vl64
 // CHECK-ENCODING: [0x60,0xe5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e560 <unknown>
 
 dech    x0, vl128
 // CHECK-INST: dech    x0, vl128
 // CHECK-ENCODING: [0x80,0xe5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e580 <unknown>
 
 dech    x0, vl256
 // CHECK-INST: dech    x0, vl256
 // CHECK-ENCODING: [0xa0,0xe5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e5a0 <unknown>
 
 dech    x0, #14
 // CHECK-INST: dech    x0, #14
 // CHECK-ENCODING: [0xc0,0xe5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e5c0 <unknown>
 
 dech    x0, #28
 // CHECK-INST: dech    x0, #28
 // CHECK-ENCODING: [0x80,0xe7,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e7 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e780 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/decp.s b/llvm/test/MC/AArch64/SVE/decp.s
index 7682e90393fff..9c6ae5e49bbcd 100644
--- a/llvm/test/MC/AArch64/SVE/decp.s
+++ b/llvm/test/MC/AArch64/SVE/decp.s
@@ -13,85 +13,85 @@ decp    x0, p0.b
 // CHECK-INST: decp    x0, p0.b
 // CHECK-ENCODING: [0x00,0x88,0x2d,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 88 2d 25 <unknown>
+// CHECK-UNKNOWN: 252d8800 <unknown>
 
 decp    x0, p0.h
 // CHECK-INST: decp    x0, p0.h
 // CHECK-ENCODING: [0x00,0x88,0x6d,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 88 6d 25 <unknown>
+// CHECK-UNKNOWN: 256d8800 <unknown>
 
 decp    x0, p0.s
 // CHECK-INST: decp    x0, p0.s
 // CHECK-ENCODING: [0x00,0x88,0xad,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 88 ad 25 <unknown>
+// CHECK-UNKNOWN: 25ad8800 <unknown>
 
 decp    x0, p0.d
 // CHECK-INST: decp    x0, p0.d
 // CHECK-ENCODING: [0x00,0x88,0xed,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 88 ed 25 <unknown>
+// CHECK-UNKNOWN: 25ed8800 <unknown>
 
 decp    xzr, p15.b
 // CHECK-INST: decp    xzr, p15.b
 // CHECK-ENCODING: [0xff,0x89,0x2d,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 2d 25 <unknown>
+// CHECK-UNKNOWN: 252d89ff <unknown>
 
 decp    xzr, p15.h
 // CHECK-INST: decp    xzr, p15.h
 // CHECK-ENCODING: [0xff,0x89,0x6d,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 6d 25 <unknown>
+// CHECK-UNKNOWN: 256d89ff <unknown>
 
 decp    xzr, p15.s
 // CHECK-INST: decp    xzr, p15.s
 // CHECK-ENCODING: [0xff,0x89,0xad,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 ad 25 <unknown>
+// CHECK-UNKNOWN: 25ad89ff <unknown>
 
 decp    xzr, p15.d
 // CHECK-INST: decp    xzr, p15.d
 // CHECK-ENCODING: [0xff,0x89,0xed,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 ed 25 <unknown>
+// CHECK-UNKNOWN: 25ed89ff <unknown>
 
 decp    z31.h, p15
 // CHECK-INST: decp    z31.h, p15.h
 // CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 6d 25 <unknown>
+// CHECK-UNKNOWN: 256d81ff <unknown>
 
 decp    z31.h, p15.h
 // CHECK-INST: decp    z31.h, p15.h
 // CHECK-ENCODING: [0xff,0x81,0x6d,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 6d 25 <unknown>
+// CHECK-UNKNOWN: 256d81ff <unknown>
 
 decp    z31.s, p15
 // CHECK-INST: decp    z31.s, p15.s
 // CHECK-ENCODING: [0xff,0x81,0xad,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 ad 25 <unknown>
+// CHECK-UNKNOWN: 25ad81ff <unknown>
 
 decp    z31.s, p15.s
 // CHECK-INST: decp    z31.s, p15.s
 // CHECK-ENCODING: [0xff,0x81,0xad,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 ad 25 <unknown>
+// CHECK-UNKNOWN: 25ad81ff <unknown>
 
 decp    z31.d, p15
 // CHECK-INST: decp    z31.d, p15.d
 // CHECK-ENCODING: [0xff,0x81,0xed,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 ed 25 <unknown>
+// CHECK-UNKNOWN: 25ed81ff <unknown>
 
 decp    z31.d, p15.d
 // CHECK-INST: decp    z31.d, p15.d
 // CHECK-ENCODING: [0xff,0x81,0xed,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 ed 25 <unknown>
+// CHECK-UNKNOWN: 25ed81ff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -101,10 +101,10 @@ movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 decp    z31.d, p15.d
 // CHECK-INST: decp	z31.d, p15
 // CHECK-ENCODING: [0xff,0x81,0xed,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 ed 25 <unknown>
+// CHECK-UNKNOWN: 25ed81ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/decw.s b/llvm/test/MC/AArch64/SVE/decw.s
index 2cf6e195bf46d..8855d25553c55 100644
--- a/llvm/test/MC/AArch64/SVE/decw.s
+++ b/llvm/test/MC/AArch64/SVE/decw.s
@@ -13,118 +13,118 @@ decw    x0
 // CHECK-INST: decw    x0
 // CHECK-ENCODING: [0xe0,0xe7,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e7e0 <unknown>
 
 decw    x0, all
 // CHECK-INST: decw    x0
 // CHECK-ENCODING: [0xe0,0xe7,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e7e0 <unknown>
 
 decw    x0, all, mul #1
 // CHECK-INST: decw    x0
 // CHECK-ENCODING: [0xe0,0xe7,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e7e0 <unknown>
 
 decw    x0, all, mul #16
 // CHECK-INST: decw    x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xe7,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e7 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bfe7e0 <unknown>
 
 decw    x0, pow2
 // CHECK-INST: decw    x0, pow2
 // CHECK-ENCODING: [0x00,0xe4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e400 <unknown>
 
 decw    x0, vl1
 // CHECK-INST: decw    x0, vl1
 // CHECK-ENCODING: [0x20,0xe4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e420 <unknown>
 
 decw    x0, vl2
 // CHECK-INST: decw    x0, vl2
 // CHECK-ENCODING: [0x40,0xe4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e440 <unknown>
 
 decw    x0, vl3
 // CHECK-INST: decw    x0, vl3
 // CHECK-ENCODING: [0x60,0xe4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e460 <unknown>
 
 decw    x0, vl4
 // CHECK-INST: decw    x0, vl4
 // CHECK-ENCODING: [0x80,0xe4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e480 <unknown>
 
 decw    x0, vl5
 // CHECK-INST: decw    x0, vl5
 // CHECK-ENCODING: [0xa0,0xe4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e4a0 <unknown>
 
 decw    x0, vl6
 // CHECK-INST: decw    x0, vl6
 // CHECK-ENCODING: [0xc0,0xe4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e4c0 <unknown>
 
 decw    x0, vl7
 // CHECK-INST: decw    x0, vl7
 // CHECK-ENCODING: [0xe0,0xe4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e4e0 <unknown>
 
 decw    x0, vl8
 // CHECK-INST: decw    x0, vl8
 // CHECK-ENCODING: [0x00,0xe5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e500 <unknown>
 
 decw    x0, vl16
 // CHECK-INST: decw    x0, vl16
 // CHECK-ENCODING: [0x20,0xe5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e520 <unknown>
 
 decw    x0, vl32
 // CHECK-INST: decw    x0, vl32
 // CHECK-ENCODING: [0x40,0xe5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e540 <unknown>
 
 decw    x0, vl64
 // CHECK-INST: decw    x0, vl64
 // CHECK-ENCODING: [0x60,0xe5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e560 <unknown>
 
 decw    x0, vl128
 // CHECK-INST: decw    x0, vl128
 // CHECK-ENCODING: [0x80,0xe5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e580 <unknown>
 
 decw    x0, vl256
 // CHECK-INST: decw    x0, vl256
 // CHECK-ENCODING: [0xa0,0xe5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e5a0 <unknown>
 
 decw    x0, #14
 // CHECK-INST: decw    x0, #14
 // CHECK-ENCODING: [0xc0,0xe5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e5c0 <unknown>
 
 decw    x0, #28
 // CHECK-INST: decw    x0, #28
 // CHECK-ENCODING: [0x80,0xe7,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e7 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e780 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/dup.s b/llvm/test/MC/AArch64/SVE/dup.s
index c1adcd7f503f0..5c7c0ec0d0249 100644
--- a/llvm/test/MC/AArch64/SVE/dup.s
+++ b/llvm/test/MC/AArch64/SVE/dup.s
@@ -13,235 +13,235 @@ dup     z0.b, w0
 // CHECK-INST: mov     z0.b, w0
 // CHECK-ENCODING: [0x00,0x38,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 38 20 05 <unknown>
+// CHECK-UNKNOWN: 05203800 <unknown>
 
 dup     z0.h, w0
 // CHECK-INST: mov     z0.h, w0
 // CHECK-ENCODING: [0x00,0x38,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 38 60 05 <unknown>
+// CHECK-UNKNOWN: 05603800 <unknown>
 
 dup     z0.s, w0
 // CHECK-INST: mov     z0.s, w0
 // CHECK-ENCODING: [0x00,0x38,0xa0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 38 a0 05 <unknown>
+// CHECK-UNKNOWN: 05a03800 <unknown>
 
 dup     z0.d, x0
 // CHECK-INST: mov     z0.d, x0
 // CHECK-ENCODING: [0x00,0x38,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 38 e0 05 <unknown>
+// CHECK-UNKNOWN: 05e03800 <unknown>
 
 dup     z31.h, wsp
 // CHECK-INST: mov     z31.h, wsp
 // CHECK-ENCODING: [0xff,0x3b,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b 60 05 <unknown>
+// CHECK-UNKNOWN: 05603bff <unknown>
 
 dup     z31.s, wsp
 // CHECK-INST: mov     z31.s, wsp
 // CHECK-ENCODING: [0xff,0x3b,0xa0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b a0 05 <unknown>
+// CHECK-UNKNOWN: 05a03bff <unknown>
 
 dup     z31.d, sp
 // CHECK-INST: mov     z31.d, sp
 // CHECK-ENCODING: [0xff,0x3b,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b e0 05 <unknown>
+// CHECK-UNKNOWN: 05e03bff <unknown>
 
 dup     z31.b, wsp
 // CHECK-INST: mov     z31.b, wsp
 // CHECK-ENCODING: [0xff,0x3b,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b 20 05 <unknown>
+// CHECK-UNKNOWN: 05203bff <unknown>
 
 dup     z5.b, #-128
 // CHECK-INST: mov     z5.b, #-128
 // CHECK-ENCODING: [0x05,0xd0,0x38,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 d0 38 25 <unknown>
+// CHECK-UNKNOWN: 2538d005 <unknown>
 
 dup     z5.b, #127
 // CHECK-INST: mov     z5.b, #127
 // CHECK-ENCODING: [0xe5,0xcf,0x38,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 cf 38 25 <unknown>
+// CHECK-UNKNOWN: 2538cfe5 <unknown>
 
 dup     z5.b, #255
 // CHECK-INST: mov     z5.b, #-1
 // CHECK-ENCODING: [0xe5,0xdf,0x38,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 df 38 25 <unknown>
+// CHECK-UNKNOWN: 2538dfe5 <unknown>
 
 dup     z21.h, #-128
 // CHECK-INST: mov     z21.h, #-128
 // CHECK-ENCODING: [0x15,0xd0,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 d0 78 25 <unknown>
+// CHECK-UNKNOWN: 2578d015 <unknown>
 
 dup     z21.h, #-128, lsl #8
 // CHECK-INST: mov     z21.h, #-32768
 // CHECK-ENCODING: [0x15,0xf0,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 f0 78 25 <unknown>
+// CHECK-UNKNOWN: 2578f015 <unknown>
 
 dup     z21.h, #-32768
 // CHECK-INST: mov     z21.h, #-32768
 // CHECK-ENCODING: [0x15,0xf0,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 f0 78 25 <unknown>
+// CHECK-UNKNOWN: 2578f015 <unknown>
 
 dup     z21.h, #127
 // CHECK-INST: mov     z21.h, #127
 // CHECK-ENCODING: [0xf5,0xcf,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 cf 78 25 <unknown>
+// CHECK-UNKNOWN: 2578cff5 <unknown>
 
 dup     z21.h, #127, lsl #8
 // CHECK-INST: mov     z21.h, #32512
 // CHECK-ENCODING: [0xf5,0xef,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 ef 78 25 <unknown>
+// CHECK-UNKNOWN: 2578eff5 <unknown>
 
 dup     z21.h, #32512
 // CHECK-INST: mov     z21.h, #32512
 // CHECK-ENCODING: [0xf5,0xef,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 ef 78 25 <unknown>
+// CHECK-UNKNOWN: 2578eff5 <unknown>
 
 dup     z21.s, #-128
 // CHECK-INST: mov     z21.s, #-128
 // CHECK-ENCODING: [0x15,0xd0,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 d0 b8 25 <unknown>
+// CHECK-UNKNOWN: 25b8d015 <unknown>
 
 dup     z21.s, #-128, lsl #8
 // CHECK-INST: mov     z21.s, #-32768
 // CHECK-ENCODING: [0x15,0xf0,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 f0 b8 25 <unknown>
+// CHECK-UNKNOWN: 25b8f015 <unknown>
 
 dup     z21.s, #-32768
 // CHECK-INST: mov     z21.s, #-32768
 // CHECK-ENCODING: [0x15,0xf0,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 f0 b8 25 <unknown>
+// CHECK-UNKNOWN: 25b8f015 <unknown>
 
 dup     z21.s, #127
 // CHECK-INST: mov     z21.s, #127
 // CHECK-ENCODING: [0xf5,0xcf,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 cf b8 25 <unknown>
+// CHECK-UNKNOWN: 25b8cff5 <unknown>
 
 dup     z21.s, #127, lsl #8
 // CHECK-INST: mov     z21.s, #32512
 // CHECK-ENCODING: [0xf5,0xef,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 ef b8 25 <unknown>
+// CHECK-UNKNOWN: 25b8eff5 <unknown>
 
 dup     z21.s, #32512
 // CHECK-INST: mov     z21.s, #32512
 // CHECK-ENCODING: [0xf5,0xef,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 ef b8 25 <unknown>
+// CHECK-UNKNOWN: 25b8eff5 <unknown>
 
 dup     z21.d, #-128
 // CHECK-INST: mov     z21.d, #-128
 // CHECK-ENCODING: [0x15,0xd0,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 d0 f8 25 <unknown>
+// CHECK-UNKNOWN: 25f8d015 <unknown>
 
 dup     z21.d, #-128, lsl #8
 // CHECK-INST: mov     z21.d, #-32768
 // CHECK-ENCODING: [0x15,0xf0,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 f0 f8 25 <unknown>
+// CHECK-UNKNOWN: 25f8f015 <unknown>
 
 dup     z21.d, #-32768
 // CHECK-INST: mov     z21.d, #-32768
 // CHECK-ENCODING: [0x15,0xf0,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 f0 f8 25 <unknown>
+// CHECK-UNKNOWN: 25f8f015 <unknown>
 
 dup     z21.d, #127
 // CHECK-INST: mov     z21.d, #127
 // CHECK-ENCODING: [0xf5,0xcf,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 cf f8 25 <unknown>
+// CHECK-UNKNOWN: 25f8cff5 <unknown>
 
 dup     z21.d, #127, lsl #8
 // CHECK-INST: mov     z21.d, #32512
 // CHECK-ENCODING: [0xf5,0xef,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 ef f8 25 <unknown>
+// CHECK-UNKNOWN: 25f8eff5 <unknown>
 
 dup     z21.d, #32512
 // CHECK-INST: mov     z21.d, #32512
 // CHECK-ENCODING: [0xf5,0xef,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 ef f8 25 <unknown>
+// CHECK-UNKNOWN: 25f8eff5 <unknown>
 
 dup     z0.b, z0.b[0]
 // CHECK-INST: mov     z0.b, b0
 // CHECK-ENCODING: [0x00,0x20,0x21,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 21 05 <unknown>
+// CHECK-UNKNOWN: 05212000 <unknown>
 
 dup     z0.h, z0.h[0]
 // CHECK-INST: mov     z0.h, h0
 // CHECK-ENCODING: [0x00,0x20,0x22,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 22 05 <unknown>
+// CHECK-UNKNOWN: 05222000 <unknown>
 
 dup     z0.s, z0.s[0]
 // CHECK-INST: mov     z0.s, s0
 // CHECK-ENCODING: [0x00,0x20,0x24,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 24 05 <unknown>
+// CHECK-UNKNOWN: 05242000 <unknown>
 
 dup     z0.d, z0.d[0]
 // CHECK-INST: mov     z0.d, d0
 // CHECK-ENCODING: [0x00,0x20,0x28,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 28 05 <unknown>
+// CHECK-UNKNOWN: 05282000 <unknown>
 
 dup     z0.q, z0.q[0]
 // CHECK-INST: mov     z0.q, q0
 // CHECK-ENCODING: [0x00,0x20,0x30,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 30 05 <unknown>
+// CHECK-UNKNOWN: 05302000 <unknown>
 
 dup     z31.b, z31.b[63]
 // CHECK-INST: mov     z31.b, z31.b[63]
 // CHECK-ENCODING: [0xff,0x23,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 23 ff 05 <unknown>
+// CHECK-UNKNOWN: 05ff23ff <unknown>
 
 dup     z31.h, z31.h[31]
 // CHECK-INST: mov     z31.h, z31.h[31]
 // CHECK-ENCODING: [0xff,0x23,0xfe,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 23 fe 05 <unknown>
+// CHECK-UNKNOWN: 05fe23ff <unknown>
 
 dup     z31.s, z31.s[15]
 // CHECK-INST: mov     z31.s, z31.s[15]
 // CHECK-ENCODING: [0xff,0x23,0xfc,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 23 fc 05 <unknown>
+// CHECK-UNKNOWN: 05fc23ff <unknown>
 
 dup     z31.d, z31.d[7]
 // CHECK-INST: mov     z31.d, z31.d[7]
 // CHECK-ENCODING: [0xff,0x23,0xf8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 23 f8 05 <unknown>
+// CHECK-UNKNOWN: 05f823ff <unknown>
 
 dup     z5.q, z17.q[3]
 // CHECK-INST: mov     z5.q, z17.q[3]
 // CHECK-ENCODING: [0x25,0x22,0xf0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 22 f0 05 <unknown>
+// CHECK-UNKNOWN: 05f02225 <unknown>
 
 // --------------------------------------------------------------------------//
 // Tests where the negative immediate is in bounds when interpreted
@@ -251,16 +251,16 @@ dup     z0.b, #-129
 // CHECK-INST: mov     z0.b, #127
 // CHECK-ENCODING: [0xe0,0xcf,0x38,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf 38 25 <unknown>
+// CHECK-UNKNOWN: 2538cfe0 <unknown>
 
 dup     z0.h, #-33024
 // CHECK-INST: mov     z0.h, #32512
 // CHECK-ENCODING: [0xe0,0xef,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ef 78 25 <unknown>
+// CHECK-UNKNOWN: 2578efe0 <unknown>
 
 dup     z0.h, #-129, lsl #8
 // CHECK-INST: mov     z0.h, #32512
 // CHECK-ENCODING: [0xe0,0xef,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ef 78 25 <unknown>
+// CHECK-UNKNOWN: 2578efe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/dupm.s b/llvm/test/MC/AArch64/SVE/dupm.s
index da7bea7f2560b..b9150015c37de 100644
--- a/llvm/test/MC/AArch64/SVE/dupm.s
+++ b/llvm/test/MC/AArch64/SVE/dupm.s
@@ -13,58 +13,58 @@ dupm     z5.b, #0xf9
 // CHECK-INST: dupm     z5.b, #0xf9
 // CHECK-ENCODING: [0xa5,0x2e,0xc0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a5 2e c0 05 <unknown>
+// CHECK-UNKNOWN: 05c02ea5 <unknown>
 
 dupm     z5.h, #0xf9f9
 // CHECK-INST: dupm     z5.b, #0xf9
 // CHECK-ENCODING: [0xa5,0x2e,0xc0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a5 2e c0 05 <unknown>
+// CHECK-UNKNOWN: 05c02ea5 <unknown>
 
 dupm     z5.s, #0xf9f9f9f9
 // CHECK-INST: dupm     z5.b, #0xf9
 // CHECK-ENCODING: [0xa5,0x2e,0xc0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a5 2e c0 05 <unknown>
+// CHECK-UNKNOWN: 05c02ea5 <unknown>
 
 dupm     z5.d, #0xf9f9f9f9f9f9f9f9
 // CHECK-INST: dupm     z5.b, #0xf9
 // CHECK-ENCODING: [0xa5,0x2e,0xc0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a5 2e c0 05 <unknown>
+// CHECK-UNKNOWN: 05c02ea5 <unknown>
 
 dupm     z23.h, #0xfff9
 // CHECK-INST: dupm     z23.h, #0xfff9
 // CHECK-ENCODING: [0xb7,0x6d,0xc0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 6d c0 05 <unknown>
+// CHECK-UNKNOWN: 05c06db7 <unknown>
 
 dupm     z23.s, #0xfff9fff9
 // CHECK-INST: dupm     z23.h, #0xfff9
 // CHECK-ENCODING: [0xb7,0x6d,0xc0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 6d c0 05 <unknown>
+// CHECK-UNKNOWN: 05c06db7 <unknown>
 
 dupm     z23.d, #0xfff9fff9fff9fff9
 // CHECK-INST: dupm     z23.h, #0xfff9
 // CHECK-ENCODING: [0xb7,0x6d,0xc0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 6d c0 05 <unknown>
+// CHECK-UNKNOWN: 05c06db7 <unknown>
 
 dupm     z0.s, #0xfffffff9
 // CHECK-INST: dupm     z0.s, #0xfffffff9
 // CHECK-ENCODING: [0xa0,0xeb,0xc0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 eb c0 05 <unknown>
+// CHECK-UNKNOWN: 05c0eba0 <unknown>
 
 dupm     z0.d, #0xfffffff9fffffff9
 // CHECK-INST: dupm     z0.s, #0xfffffff9
 // CHECK-ENCODING: [0xa0,0xeb,0xc0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 eb c0 05 <unknown>
+// CHECK-UNKNOWN: 05c0eba0 <unknown>
 
 dupm     z0.d, #0xfffffffffffffff9
 // CHECK-INST: dupm     z0.d, #0xfffffffffffffff9
 // CHECK-ENCODING: [0xa0,0xef,0xc3,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ef c3 05 <unknown>
+// CHECK-UNKNOWN: 05c3efa0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/eon.s b/llvm/test/MC/AArch64/SVE/eon.s
index d4cdd17566bc6..df5f7369a3ebc 100644
--- a/llvm/test/MC/AArch64/SVE/eon.s
+++ b/llvm/test/MC/AArch64/SVE/eon.s
@@ -13,49 +13,49 @@ eon     z5.b, z5.b, #0xf9
 // CHECK-INST: eor     z5.b, z5.b, #0x6
 // CHECK-ENCODING: [0x25,0x3e,0x40,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 3e 40 05 <unknown>
+// CHECK-UNKNOWN: 05403e25 <unknown>
 
 eon     z23.h, z23.h, #0xfff9
 // CHECK-INST: eor     z23.h, z23.h, #0x6
 // CHECK-ENCODING: [0x37,0x7c,0x40,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 37 7c 40 05 <unknown>
+// CHECK-UNKNOWN: 05407c37 <unknown>
 
 eon     z0.s, z0.s, #0xfffffff9
 // CHECK-INST: eor     z0.s, z0.s, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x40,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 40 05 <unknown>
+// CHECK-UNKNOWN: 0540f820 <unknown>
 
 eon     z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-INST: eor     z0.d, z0.d, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x43,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 43 05 <unknown>
+// CHECK-UNKNOWN: 0543f820 <unknown>
 
 eon     z5.b, z5.b, #0x6
 // CHECK-INST: eor     z5.b, z5.b, #0xf9
 // CHECK-ENCODING: [0xa5,0x2e,0x40,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a5 2e 40 05 <unknown>
+// CHECK-UNKNOWN: 05402ea5 <unknown>
 
 eon     z23.h, z23.h, #0x6
 // CHECK-INST: eor     z23.h, z23.h, #0xfff9
 // CHECK-ENCODING: [0xb7,0x6d,0x40,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 6d 40 05 <unknown>
+// CHECK-UNKNOWN: 05406db7 <unknown>
 
 eon     z0.s, z0.s, #0x6
 // CHECK-INST: eor     z0.s, z0.s, #0xfffffff9
 // CHECK-ENCODING: [0xa0,0xeb,0x40,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 eb 40 05 <unknown>
+// CHECK-UNKNOWN: 0540eba0 <unknown>
 
 eon     z0.d, z0.d, #0x6
 // CHECK-INST: eor     z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-ENCODING: [0xa0,0xef,0x43,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ef 43 05 <unknown>
+// CHECK-UNKNOWN: 0543efa0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -65,10 +65,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 eon     z0.d, z0.d, #0x6
 // CHECK-INST: eor	z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-ENCODING: [0xa0,0xef,0x43,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ef 43 05 <unknown>
+// CHECK-UNKNOWN: 0543efa0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/eor.s b/llvm/test/MC/AArch64/SVE/eor.s
index 08610b0bae874..2116a25d41b09 100644
--- a/llvm/test/MC/AArch64/SVE/eor.s
+++ b/llvm/test/MC/AArch64/SVE/eor.s
@@ -13,103 +13,103 @@ eor     z5.b, z5.b, #0xf9
 // CHECK-INST: eor     z5.b, z5.b, #0xf9
 // CHECK-ENCODING: [0xa5,0x2e,0x40,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a5 2e 40 05 <unknown>
+// CHECK-UNKNOWN: 05402ea5 <unknown>
 
 eor     z23.h, z23.h, #0xfff9
 // CHECK-INST: eor     z23.h, z23.h, #0xfff9
 // CHECK-ENCODING: [0xb7,0x6d,0x40,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 6d 40 05 <unknown>
+// CHECK-UNKNOWN: 05406db7 <unknown>
 
 eor     z0.s, z0.s, #0xfffffff9
 // CHECK-INST: eor     z0.s, z0.s, #0xfffffff9
 // CHECK-ENCODING: [0xa0,0xeb,0x40,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 eb 40 05 <unknown>
+// CHECK-UNKNOWN: 0540eba0 <unknown>
 
 eor     z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-INST: eor     z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-ENCODING: [0xa0,0xef,0x43,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ef 43 05 <unknown>
+// CHECK-UNKNOWN: 0543efa0 <unknown>
 
 eor     z5.b, z5.b, #0x6
 // CHECK-INST: eor     z5.b, z5.b, #0x6
 // CHECK-ENCODING: [0x25,0x3e,0x40,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 3e 40 05 <unknown>
+// CHECK-UNKNOWN: 05403e25 <unknown>
 
 eor     z23.h, z23.h, #0x6
 // CHECK-INST: eor     z23.h, z23.h, #0x6
 // CHECK-ENCODING: [0x37,0x7c,0x40,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 37 7c 40 05 <unknown>
+// CHECK-UNKNOWN: 05407c37 <unknown>
 
 eor     z0.s, z0.s, #0x6
 // CHECK-INST: eor     z0.s, z0.s, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x40,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 40 05 <unknown>
+// CHECK-UNKNOWN: 0540f820 <unknown>
 
 eor     z0.d, z0.d, #0x6
 // CHECK-INST: eor     z0.d, z0.d, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x43,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 43 05 <unknown>
+// CHECK-UNKNOWN: 0543f820 <unknown>
 
 eor     z23.d, z13.d, z8.d
 // CHECK-INST: eor     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x31,0xa8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 31 a8 04 <unknown>
+// CHECK-UNKNOWN: 04a831b7 <unknown>
 
 eor     z0.d, z0.d, z0.d
 // CHECK-INST: eor     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a03000 <unknown>
 
 eor     z31.s, p7/m, z31.s, z31.s
 // CHECK-INST: eor     z31.s, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1f,0x99,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 99 04 <unknown>
+// CHECK-UNKNOWN: 04991fff <unknown>
 
 eor     z31.h, p7/m, z31.h, z31.h
 // CHECK-INST: eor     z31.h, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x1f,0x59,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 59 04 <unknown>
+// CHECK-UNKNOWN: 04591fff <unknown>
 
 eor     z31.d, p7/m, z31.d, z31.d
 // CHECK-INST: eor     z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xd9,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f d9 04 <unknown>
+// CHECK-UNKNOWN: 04d91fff <unknown>
 
 eor     z31.b, p7/m, z31.b, z31.b
 // CHECK-INST: eor     z31.b, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x1f,0x19,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 19 04 <unknown>
+// CHECK-UNKNOWN: 04191fff <unknown>
 
 eor     p0.b, p0/z, p0.b, p1.b
 // CHECK-INST: eor     p0.b, p0/z, p0.b, p1.b
 // CHECK-ENCODING: [0x00,0x42,0x01,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 42 01 25 <unknown>
+// CHECK-UNKNOWN: 25014200 <unknown>
 
 eor     p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: not     p0.b, p0/z, p0.b
 // CHECK-ENCODING: [0x00,0x42,0x00,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 42 00 25 <unknown>
+// CHECK-UNKNOWN: 25004200 <unknown>
 
 eor     p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: not     p15.b, p15/z, p15.b
 // CHECK-ENCODING: [0xef,0x7f,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7f 0f 25 <unknown>
+// CHECK-UNKNOWN: 250f7fef <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -119,19 +119,19 @@ eor     z0.s, z0.s, z0.s
 // CHECK-INST: eor     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a03000 <unknown>
 
 eor     z0.h, z0.h, z0.h
 // CHECK-INST: eor     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a03000 <unknown>
 
 eor     z0.b, z0.b, z0.b
 // CHECK-INST: eor     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a03000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -141,34 +141,34 @@ movprfx z4.b, p7/z, z6.b
 // CHECK-INST: movprfx	z4.b, p7/z, z6.b
 // CHECK-ENCODING: [0xc4,0x3c,0x10,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c 10 04 <unknown>
+// CHECK-UNKNOWN: 04103cc4 <unknown>
 
 eor     z4.b, p7/m, z4.b, z31.b
 // CHECK-INST: eor	z4.b, p7/m, z4.b, z31.b
 // CHECK-ENCODING: [0xe4,0x1f,0x19,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f 19 04 <unknown>
+// CHECK-UNKNOWN: 04191fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 eor     z4.b, p7/m, z4.b, z31.b
 // CHECK-INST: eor	z4.b, p7/m, z4.b, z31.b
 // CHECK-ENCODING: [0xe4,0x1f,0x19,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f 19 04 <unknown>
+// CHECK-UNKNOWN: 04191fe4 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 eor     z0.d, z0.d, #0x6
 // CHECK-INST: eor	z0.d, z0.d, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x43,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 43 05 <unknown>
+// CHECK-UNKNOWN: 0543f820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/eors.s b/llvm/test/MC/AArch64/SVE/eors.s
index 451abec4ee638..0f45f8ebba331 100644
--- a/llvm/test/MC/AArch64/SVE/eors.s
+++ b/llvm/test/MC/AArch64/SVE/eors.s
@@ -13,16 +13,16 @@ eors    p0.b, p0/z, p0.b, p1.b
 // CHECK-INST: eors    p0.b, p0/z, p0.b, p1.b
 // CHECK-ENCODING: [0x00,0x42,0x41,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 42 41 25 <unknown>
+// CHECK-UNKNOWN: 25414200 <unknown>
 
 eors    p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: nots    p0.b, p0/z, p0.b
 // CHECK-ENCODING: [0x00,0x42,0x40,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 42 40 25 <unknown>
+// CHECK-UNKNOWN: 25404200 <unknown>
 
 eors    p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: nots    p15.b, p15/z, p15.b
 // CHECK-ENCODING: [0xef,0x7f,0x4f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7f 4f 25 <unknown>
+// CHECK-UNKNOWN: 254f7fef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/eorv.s b/llvm/test/MC/AArch64/SVE/eorv.s
index dcb098da83667..8cdf77bc732ff 100644
--- a/llvm/test/MC/AArch64/SVE/eorv.s
+++ b/llvm/test/MC/AArch64/SVE/eorv.s
@@ -13,22 +13,22 @@ eorv b0, p7, z31.b
 // CHECK-INST: eorv	b0, p7, z31.b
 // CHECK-ENCODING: [0xe0,0x3f,0x19,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 19 04 <unknown>
+// CHECK-UNKNOWN: 04193fe0 <unknown>
 
 eorv h0, p7, z31.h
 // CHECK-INST: eorv	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x59,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 59 04 <unknown>
+// CHECK-UNKNOWN: 04593fe0 <unknown>
 
 eorv s0, p7, z31.s
 // CHECK-INST: eorv	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x99,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 99 04 <unknown>
+// CHECK-UNKNOWN: 04993fe0 <unknown>
 
 eorv d0, p7, z31.d
 // CHECK-INST: eorv	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xd9,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f d9 04 <unknown>
+// CHECK-UNKNOWN: 04d93fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ext.s b/llvm/test/MC/AArch64/SVE/ext.s
index d31044e4c7b0c..be1187904fe4f 100644
--- a/llvm/test/MC/AArch64/SVE/ext.s
+++ b/llvm/test/MC/AArch64/SVE/ext.s
@@ -13,13 +13,13 @@ ext z31.b, z31.b, z0.b, #0
 // CHECK-INST: ext	z31.b, z31.b, z0.b, #0
 // CHECK-ENCODING: [0x1f,0x00,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 00 20 05 <unknown>
+// CHECK-UNKNOWN: 0520001f <unknown>
 
 ext z31.b, z31.b, z0.b, #255
 // CHECK-INST: ext	z31.b, z31.b, z0.b, #255
 // CHECK-ENCODING: [0x1f,0x1c,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 1c 3f 05 <unknown>
+// CHECK-UNKNOWN: 053f1c1f <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -29,10 +29,10 @@ movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 ext z31.b, z31.b, z0.b, #255
 // CHECK-INST: ext	z31.b, z31.b, z0.b, #255
 // CHECK-ENCODING: [0x1f,0x1c,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 1c 3f 05 <unknown>
+// CHECK-UNKNOWN: 053f1c1f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fabd.s b/llvm/test/MC/AArch64/SVE/fabd.s
index cb9f76fe5ac57..f80a04c3a767e 100644
--- a/llvm/test/MC/AArch64/SVE/fabd.s
+++ b/llvm/test/MC/AArch64/SVE/fabd.s
@@ -13,19 +13,19 @@ fabd    z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: fabd	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x48,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 48 65 <unknown>
+// CHECK-UNKNOWN: 65489fe0 <unknown>
 
 fabd    z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: fabd	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0x88,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 88 65 <unknown>
+// CHECK-UNKNOWN: 65889fe0 <unknown>
 
 fabd    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fabd	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c8 65 <unknown>
+// CHECK-UNKNOWN: 65c89fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fabd    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fabd	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c8 65 <unknown>
+// CHECK-UNKNOWN: 65c89fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fabd    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fabd	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc8,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c8 65 <unknown>
+// CHECK-UNKNOWN: 65c89fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fabs.s b/llvm/test/MC/AArch64/SVE/fabs.s
index 68e5994f0c2e5..d1aa17be968a8 100644
--- a/llvm/test/MC/AArch64/SVE/fabs.s
+++ b/llvm/test/MC/AArch64/SVE/fabs.s
@@ -13,19 +13,19 @@ fabs    z31.h, p7/m, z31.h
 // CHECK-INST: fabs	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x5c,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 5c 04 <unknown>
+// CHECK-UNKNOWN: 045cbfff <unknown>
 
 fabs    z31.s, p7/m, z31.s
 // CHECK-INST: fabs	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x9c,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 9c 04 <unknown>
+// CHECK-UNKNOWN: 049cbfff <unknown>
 
 fabs    z31.d, p7/m, z31.d
 // CHECK-INST: fabs	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xdc,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf dc 04 <unknown>
+// CHECK-UNKNOWN: 04dcbfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 fabs    z4.d, p7/m, z31.d
 // CHECK-INST: fabs	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xdc,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf dc 04 <unknown>
+// CHECK-UNKNOWN: 04dcbfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 fabs    z4.d, p7/m, z31.d
 // CHECK-INST: fabs	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xdc,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf dc 04 <unknown>
+// CHECK-UNKNOWN: 04dcbfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/facge.s b/llvm/test/MC/AArch64/SVE/facge.s
index 47471ebae7c97..35a3700e40726 100644
--- a/llvm/test/MC/AArch64/SVE/facge.s
+++ b/llvm/test/MC/AArch64/SVE/facge.s
@@ -13,16 +13,16 @@ facge   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: facge	p0.h, p0/z, z0.h, z1.h
 // CHECK-ENCODING: [0x10,0xc0,0x41,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 c0 41 65 <unknown>
+// CHECK-UNKNOWN: 6541c010 <unknown>
 
 facge   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: facge	p0.s, p0/z, z0.s, z1.s
 // CHECK-ENCODING: [0x10,0xc0,0x81,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 c0 81 65 <unknown>
+// CHECK-UNKNOWN: 6581c010 <unknown>
 
 facge   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: facge	p0.d, p0/z, z0.d, z1.d
 // CHECK-ENCODING: [0x10,0xc0,0xc1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 c0 c1 65 <unknown>
+// CHECK-UNKNOWN: 65c1c010 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/facgt.s b/llvm/test/MC/AArch64/SVE/facgt.s
index a8e6fb805329a..126230d32c573 100644
--- a/llvm/test/MC/AArch64/SVE/facgt.s
+++ b/llvm/test/MC/AArch64/SVE/facgt.s
@@ -13,16 +13,16 @@ facgt   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: facgt	p0.h, p0/z, z0.h, z1.h
 // CHECK-ENCODING: [0x10,0xe0,0x41,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 e0 41 65 <unknown>
+// CHECK-UNKNOWN: 6541e010 <unknown>
 
 facgt   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: facgt	p0.s, p0/z, z0.s, z1.s
 // CHECK-ENCODING: [0x10,0xe0,0x81,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 e0 81 65 <unknown>
+// CHECK-UNKNOWN: 6581e010 <unknown>
 
 facgt   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: facgt	p0.d, p0/z, z0.d, z1.d
 // CHECK-ENCODING: [0x10,0xe0,0xc1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 e0 c1 65 <unknown>
+// CHECK-UNKNOWN: 65c1e010 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/facle.s b/llvm/test/MC/AArch64/SVE/facle.s
index 88ef32ec3f486..4b3f633e9b89c 100644
--- a/llvm/test/MC/AArch64/SVE/facle.s
+++ b/llvm/test/MC/AArch64/SVE/facle.s
@@ -13,16 +13,16 @@ facle   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: facge	p0.h, p0/z, z1.h, z0.h
 // CHECK-ENCODING: [0x30,0xc0,0x40,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 c0 40 65 <unknown>
+// CHECK-UNKNOWN: 6540c030 <unknown>
 
 facle   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: facge	p0.s, p0/z, z1.s, z0.s
 // CHECK-ENCODING: [0x30,0xc0,0x80,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 c0 80 65 <unknown>
+// CHECK-UNKNOWN: 6580c030 <unknown>
 
 facle   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: facge	p0.d, p0/z, z1.d, z0.d
 // CHECK-ENCODING: [0x30,0xc0,0xc0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 c0 c0 65 <unknown>
+// CHECK-UNKNOWN: 65c0c030 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/faclt.s b/llvm/test/MC/AArch64/SVE/faclt.s
index d41d19d7893c9..b885cd7c9256b 100644
--- a/llvm/test/MC/AArch64/SVE/faclt.s
+++ b/llvm/test/MC/AArch64/SVE/faclt.s
@@ -13,16 +13,16 @@ faclt   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: facgt	p0.h, p0/z, z1.h, z0.h
 // CHECK-ENCODING: [0x30,0xe0,0x40,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 e0 40 65 <unknown>
+// CHECK-UNKNOWN: 6540e030 <unknown>
 
 faclt   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: facgt	p0.s, p0/z, z1.s, z0.s
 // CHECK-ENCODING: [0x30,0xe0,0x80,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 e0 80 65 <unknown>
+// CHECK-UNKNOWN: 6580e030 <unknown>
 
 faclt   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: facgt	p0.d, p0/z, z1.d, z0.d
 // CHECK-ENCODING: [0x30,0xe0,0xc0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 e0 c0 65 <unknown>
+// CHECK-UNKNOWN: 65c0e030 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fadd.s b/llvm/test/MC/AArch64/SVE/fadd.s
index 9707789c9a934..bd02d2f4fef75 100644
--- a/llvm/test/MC/AArch64/SVE/fadd.s
+++ b/llvm/test/MC/AArch64/SVE/fadd.s
@@ -13,85 +13,85 @@ fadd    z0.h, p0/m, z0.h, #0.500000000000000
 // CHECK-INST: fadd    z0.h, p0/m, z0.h, #0.5
 // CHECK-ENCODING: [0x00,0x80,0x58,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 58 65 <unknown>
+// CHECK-UNKNOWN: 65588000 <unknown>
 
 fadd    z0.h, p0/m, z0.h, #0.5
 // CHECK-INST: fadd    z0.h, p0/m, z0.h, #0.5
 // CHECK-ENCODING: [0x00,0x80,0x58,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 58 65 <unknown>
+// CHECK-UNKNOWN: 65588000 <unknown>
 
 fadd    z0.s, p0/m, z0.s, #0.5
 // CHECK-INST: fadd    z0.s, p0/m, z0.s, #0.5
 // CHECK-ENCODING: [0x00,0x80,0x98,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 98 65 <unknown>
+// CHECK-UNKNOWN: 65988000 <unknown>
 
 fadd    z0.d, p0/m, z0.d, #0.5
 // CHECK-INST: fadd    z0.d, p0/m, z0.d, #0.5
 // CHECK-ENCODING: [0x00,0x80,0xd8,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 d8 65 <unknown>
+// CHECK-UNKNOWN: 65d88000 <unknown>
 
 fadd    z31.h, p7/m, z31.h, #1.000000000000000
 // CHECK-INST: fadd    z31.h, p7/m, z31.h, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x58,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 58 65 <unknown>
+// CHECK-UNKNOWN: 65589c3f <unknown>
 
 fadd    z31.h, p7/m, z31.h, #1.0
 // CHECK-INST: fadd    z31.h, p7/m, z31.h, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x58,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 58 65 <unknown>
+// CHECK-UNKNOWN: 65589c3f <unknown>
 
 fadd    z31.s, p7/m, z31.s, #1.0
 // CHECK-INST: fadd    z31.s, p7/m, z31.s, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x98,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 98 65 <unknown>
+// CHECK-UNKNOWN: 65989c3f <unknown>
 
 fadd    z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fadd    z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c d8 65 <unknown>
+// CHECK-UNKNOWN: 65d89c3f <unknown>
 
 fadd    z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: fadd	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x40,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 40 65 <unknown>
+// CHECK-UNKNOWN: 65409fe0 <unknown>
 
 fadd    z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: fadd	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0x80,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 80 65 <unknown>
+// CHECK-UNKNOWN: 65809fe0 <unknown>
 
 fadd    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fadd	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c0 65 <unknown>
+// CHECK-UNKNOWN: 65c09fe0 <unknown>
 
 fadd z0.h, z1.h, z31.h
 // CHECK-INST: fadd	z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x00,0x5f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 5f 65 <unknown>
+// CHECK-UNKNOWN: 655f0020 <unknown>
 
 fadd z0.s, z1.s, z31.s
 // CHECK-INST: fadd	z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x00,0x9f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 9f 65 <unknown>
+// CHECK-UNKNOWN: 659f0020 <unknown>
 
 fadd z0.d, z1.d, z31.d
 // CHECK-INST: fadd	z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x00,0xdf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 df 65 <unknown>
+// CHECK-UNKNOWN: 65df0020 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -101,46 +101,46 @@ movprfx z31.d, p7/z, z6.d
 // CHECK-INST: movprfx	z31.d, p7/z, z6.d
 // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cdf <unknown>
 
 fadd    z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fadd	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c d8 65 <unknown>
+// CHECK-UNKNOWN: 65d89c3f <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 fadd    z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fadd	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xd8,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c d8 65 <unknown>
+// CHECK-UNKNOWN: 65d89c3f <unknown>
 
 movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fadd    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fadd	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c0 65 <unknown>
+// CHECK-UNKNOWN: 65c09fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fadd    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fadd	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c0 65 <unknown>
+// CHECK-UNKNOWN: 65c09fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fadda.s b/llvm/test/MC/AArch64/SVE/fadda.s
index 21842758f4d01..f4c9f6749da52 100644
--- a/llvm/test/MC/AArch64/SVE/fadda.s
+++ b/llvm/test/MC/AArch64/SVE/fadda.s
@@ -13,16 +13,16 @@ fadda h0, p7, h0, z31.h
 // CHECK-INST: fadda	h0, p7, h0, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x58,0x65]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: e0 3f 58 65 <unknown>
+// CHECK-UNKNOWN: 65583fe0 <unknown>
 
 fadda s0, p7, s0, z31.s
 // CHECK-INST: fadda	s0, p7, s0, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x98,0x65]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: e0 3f 98 65 <unknown>
+// CHECK-UNKNOWN: 65983fe0 <unknown>
 
 fadda d0, p7, d0, z31.d
 // CHECK-INST: fadda	d0, p7, d0, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xd8,0x65]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: e0 3f d8 65 <unknown>
+// CHECK-UNKNOWN: 65d83fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/faddv.s b/llvm/test/MC/AArch64/SVE/faddv.s
index 7a575aa82a338..f38fbbee0f3f5 100644
--- a/llvm/test/MC/AArch64/SVE/faddv.s
+++ b/llvm/test/MC/AArch64/SVE/faddv.s
@@ -13,16 +13,16 @@ faddv h0, p7, z31.h
 // CHECK-INST: faddv	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x40,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 40 65 <unknown>
+// CHECK-UNKNOWN: 65403fe0 <unknown>
 
 faddv s0, p7, z31.s
 // CHECK-INST: faddv	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x80,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 80 65 <unknown>
+// CHECK-UNKNOWN: 65803fe0 <unknown>
 
 faddv d0, p7, z31.d
 // CHECK-INST: faddv	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xc0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f c0 65 <unknown>
+// CHECK-UNKNOWN: 65c03fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fcadd.s b/llvm/test/MC/AArch64/SVE/fcadd.s
index f160176ea1ca4..402b21bd47cc8 100644
--- a/llvm/test/MC/AArch64/SVE/fcadd.s
+++ b/llvm/test/MC/AArch64/SVE/fcadd.s
@@ -13,37 +13,37 @@ fcadd   z0.h, p0/m, z0.h, z0.h, #90
 // CHECK-INST: fcadd   z0.h, p0/m, z0.h, z0.h, #90
 // CHECK-ENCODING: [0x00,0x80,0x40,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 40 64 <unknown>
+// CHECK-UNKNOWN: 64408000 <unknown>
 
 fcadd   z0.s, p0/m, z0.s, z0.s, #90
 // CHECK-INST: fcadd   z0.s, p0/m, z0.s, z0.s, #90
 // CHECK-ENCODING: [0x00,0x80,0x80,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 80 64 <unknown>
+// CHECK-UNKNOWN: 64808000 <unknown>
 
 fcadd   z0.d, p0/m, z0.d, z0.d, #90
 // CHECK-INST: fcadd   z0.d, p0/m, z0.d, z0.d, #90
 // CHECK-ENCODING: [0x00,0x80,0xc0,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 c0 64 <unknown>
+// CHECK-UNKNOWN: 64c08000 <unknown>
 
 fcadd   z31.h, p7/m, z31.h, z31.h, #270
 // CHECK-INST: fcadd   z31.h, p7/m, z31.h, z31.h, #270
 // CHECK-ENCODING: [0xff,0x9f,0x41,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f 41 64 <unknown>
+// CHECK-UNKNOWN: 64419fff <unknown>
 
 fcadd   z31.s, p7/m, z31.s, z31.s, #270
 // CHECK-INST: fcadd   z31.s, p7/m, z31.s, z31.s, #270
 // CHECK-ENCODING: [0xff,0x9f,0x81,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f 81 64 <unknown>
+// CHECK-UNKNOWN: 64819fff <unknown>
 
 fcadd   z31.d, p7/m, z31.d, z31.d, #270
 // CHECK-INST: fcadd   z31.d, p7/m, z31.d, z31.d, #270
 // CHECK-ENCODING: [0xff,0x9f,0xc1,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f c1 64 <unknown>
+// CHECK-UNKNOWN: 64c19fff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -53,22 +53,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 fcadd   z4.d, p7/m, z4.d, z31.d, #270
 // CHECK-INST: fcadd	z4.d, p7/m, z4.d, z31.d, #270
 // CHECK-ENCODING: [0xe4,0x9f,0xc1,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 9f c1 64 <unknown>
+// CHECK-UNKNOWN: 64c19fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 fcadd   z4.d, p7/m, z4.d, z31.d, #270
 // CHECK-INST: fcadd	z4.d, p7/m, z4.d, z31.d, #270
 // CHECK-ENCODING: [0xe4,0x9f,0xc1,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 9f c1 64 <unknown>
+// CHECK-UNKNOWN: 64c19fe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fcmeq.s b/llvm/test/MC/AArch64/SVE/fcmeq.s
index 44da5140650e9..5da8a03e8e941 100644
--- a/llvm/test/MC/AArch64/SVE/fcmeq.s
+++ b/llvm/test/MC/AArch64/SVE/fcmeq.s
@@ -13,34 +13,34 @@ fcmeq   p0.h, p0/z, z0.h, #0.0
 // CHECK-INST: fcmeq	p0.h, p0/z, z0.h, #0.0
 // CHECK-ENCODING: [0x00,0x20,0x52,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 52 65 <unknown>
+// CHECK-UNKNOWN: 65522000 <unknown>
 
 fcmeq   p0.s, p0/z, z0.s, #0.0
 // CHECK-INST: fcmeq	p0.s, p0/z, z0.s, #0.0
 // CHECK-ENCODING: [0x00,0x20,0x92,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 92 65 <unknown>
+// CHECK-UNKNOWN: 65922000 <unknown>
 
 fcmeq   p0.d, p0/z, z0.d, #0.0
 // CHECK-INST: fcmeq	p0.d, p0/z, z0.d, #0.0
 // CHECK-ENCODING: [0x00,0x20,0xd2,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 d2 65 <unknown>
+// CHECK-UNKNOWN: 65d22000 <unknown>
 
 fcmeq   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: fcmeq	p0.h, p0/z, z0.h, z1.h
 // CHECK-ENCODING: [0x00,0x60,0x41,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 41 65 <unknown>
+// CHECK-UNKNOWN: 65416000 <unknown>
 
 fcmeq   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: fcmeq	p0.s, p0/z, z0.s, z1.s
 // CHECK-ENCODING: [0x00,0x60,0x81,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 81 65 <unknown>
+// CHECK-UNKNOWN: 65816000 <unknown>
 
 fcmeq   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: fcmeq	p0.d, p0/z, z0.d, z1.d
 // CHECK-ENCODING: [0x00,0x60,0xc1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 c1 65 <unknown>
+// CHECK-UNKNOWN: 65c16000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fcmge.s b/llvm/test/MC/AArch64/SVE/fcmge.s
index 8a2bf6c8e01d4..f9d26ca007822 100644
--- a/llvm/test/MC/AArch64/SVE/fcmge.s
+++ b/llvm/test/MC/AArch64/SVE/fcmge.s
@@ -13,34 +13,34 @@ fcmge   p0.h, p0/z, z0.h, #0.0
 // CHECK-INST: fcmge	p0.h, p0/z, z0.h, #0.0
 // CHECK-ENCODING: [0x00,0x20,0x50,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 50 65 <unknown>
+// CHECK-UNKNOWN: 65502000 <unknown>
 
 fcmge   p0.s, p0/z, z0.s, #0.0
 // CHECK-INST: fcmge	p0.s, p0/z, z0.s, #0.0
 // CHECK-ENCODING: [0x00,0x20,0x90,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 90 65 <unknown>
+// CHECK-UNKNOWN: 65902000 <unknown>
 
 fcmge   p0.d, p0/z, z0.d, #0.0
 // CHECK-INST: fcmge	p0.d, p0/z, z0.d, #0.0
 // CHECK-ENCODING: [0x00,0x20,0xd0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 d0 65 <unknown>
+// CHECK-UNKNOWN: 65d02000 <unknown>
 
 fcmge   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: fcmge	p0.h, p0/z, z0.h, z1.h
 // CHECK-ENCODING: [0x00,0x40,0x41,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 41 65 <unknown>
+// CHECK-UNKNOWN: 65414000 <unknown>
 
 fcmge   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: fcmge	p0.s, p0/z, z0.s, z1.s
 // CHECK-ENCODING: [0x00,0x40,0x81,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 81 65 <unknown>
+// CHECK-UNKNOWN: 65814000 <unknown>
 
 fcmge   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: fcmge	p0.d, p0/z, z0.d, z1.d
 // CHECK-ENCODING: [0x00,0x40,0xc1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 c1 65 <unknown>
+// CHECK-UNKNOWN: 65c14000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fcmgt.s b/llvm/test/MC/AArch64/SVE/fcmgt.s
index 1a70bc69252b7..70d21630f9293 100644
--- a/llvm/test/MC/AArch64/SVE/fcmgt.s
+++ b/llvm/test/MC/AArch64/SVE/fcmgt.s
@@ -13,34 +13,34 @@ fcmgt   p0.h, p0/z, z0.h, #0.0
 // CHECK-INST: fcmgt	p0.h, p0/z, z0.h, #0.0
 // CHECK-ENCODING: [0x10,0x20,0x50,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 50 65 <unknown>
+// CHECK-UNKNOWN: 65502010 <unknown>
 
 fcmgt   p0.s, p0/z, z0.s, #0.0
 // CHECK-INST: fcmgt	p0.s, p0/z, z0.s, #0.0
 // CHECK-ENCODING: [0x10,0x20,0x90,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 90 65 <unknown>
+// CHECK-UNKNOWN: 65902010 <unknown>
 
 fcmgt   p0.d, p0/z, z0.d, #0.0
 // CHECK-INST: fcmgt	p0.d, p0/z, z0.d, #0.0
 // CHECK-ENCODING: [0x10,0x20,0xd0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 d0 65 <unknown>
+// CHECK-UNKNOWN: 65d02010 <unknown>
 
 fcmgt   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: fcmgt	p0.h, p0/z, z0.h, z1.h
 // CHECK-ENCODING: [0x10,0x40,0x41,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 40 41 65 <unknown>
+// CHECK-UNKNOWN: 65414010 <unknown>
 
 fcmgt   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: fcmgt	p0.s, p0/z, z0.s, z1.s
 // CHECK-ENCODING: [0x10,0x40,0x81,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 40 81 65 <unknown>
+// CHECK-UNKNOWN: 65814010 <unknown>
 
 fcmgt   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: fcmgt	p0.d, p0/z, z0.d, z1.d
 // CHECK-ENCODING: [0x10,0x40,0xc1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 40 c1 65 <unknown>
+// CHECK-UNKNOWN: 65c14010 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fcmla.s b/llvm/test/MC/AArch64/SVE/fcmla.s
index 5d741b6ee654b..1b67e35684041 100644
--- a/llvm/test/MC/AArch64/SVE/fcmla.s
+++ b/llvm/test/MC/AArch64/SVE/fcmla.s
@@ -13,97 +13,97 @@ fcmla   z0.h, p0/m, z0.h, z0.h, #0
 // CHECK-INST: fcmla z0.h, p0/m, z0.h, z0.h, #0
 // CHECK-ENCODING: [0x00,0x00,0x40,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 40 64 <unknown>
+// CHECK-UNKNOWN: 64400000 <unknown>
 
 fcmla   z0.s, p0/m, z0.s, z0.s, #0
 // CHECK-INST: fcmla z0.s, p0/m, z0.s, z0.s, #0
 // CHECK-ENCODING: [0x00,0x00,0x80,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 80 64 <unknown>
+// CHECK-UNKNOWN: 64800000 <unknown>
 
 fcmla   z0.d, p0/m, z0.d, z0.d, #0
 // CHECK-INST: fcmla z0.d, p0/m, z0.d, z0.d, #0
 // CHECK-ENCODING: [0x00,0x00,0xc0,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 c0 64 <unknown>
+// CHECK-UNKNOWN: 64c00000 <unknown>
 
 fcmla   z0.h, p0/m, z1.h, z2.h, #90
 // CHECK-INST: fcmla z0.h, p0/m, z1.h, z2.h, #90
 // CHECK-ENCODING: [0x20,0x20,0x42,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 20 42 64 <unknown>
+// CHECK-UNKNOWN: 64422020 <unknown>
 
 fcmla   z0.s, p0/m, z1.s, z2.s, #90
 // CHECK-INST: fcmla z0.s, p0/m, z1.s, z2.s, #90
 // CHECK-ENCODING: [0x20,0x20,0x82,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 20 82 64 <unknown>
+// CHECK-UNKNOWN: 64822020 <unknown>
 
 fcmla   z0.d, p0/m, z1.d, z2.d, #90
 // CHECK-INST: fcmla z0.d, p0/m, z1.d, z2.d, #90
 // CHECK-ENCODING: [0x20,0x20,0xc2,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 20 c2 64 <unknown>
+// CHECK-UNKNOWN: 64c22020 <unknown>
 
 fcmla   z29.h, p7/m, z30.h, z31.h, #180
 // CHECK-INST: fcmla z29.h, p7/m, z30.h, z31.h, #180
 // CHECK-ENCODING: [0xdd,0x5f,0x5f,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: dd 5f 5f 64 <unknown>
+// CHECK-UNKNOWN: 645f5fdd <unknown>
 
 fcmla   z29.s, p7/m, z30.s, z31.s, #180
 // CHECK-INST: fcmla z29.s, p7/m, z30.s, z31.s, #180
 // CHECK-ENCODING: [0xdd,0x5f,0x9f,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: dd 5f 9f 64 <unknown>
+// CHECK-UNKNOWN: 649f5fdd <unknown>
 
 fcmla   z29.d, p7/m, z30.d, z31.d, #180
 // CHECK-INST: fcmla z29.d, p7/m, z30.d, z31.d, #180
 // CHECK-ENCODING: [0xdd,0x5f,0xdf,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: dd 5f df 64 <unknown>
+// CHECK-UNKNOWN: 64df5fdd <unknown>
 
 fcmla   z31.h, p7/m, z31.h, z31.h, #270
 // CHECK-INST: fcmla z31.h, p7/m, z31.h, z31.h, #270
 // CHECK-ENCODING: [0xff,0x7f,0x5f,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 7f 5f 64 <unknown>
+// CHECK-UNKNOWN: 645f7fff <unknown>
 
 fcmla   z31.s, p7/m, z31.s, z31.s, #270
 // CHECK-INST: fcmla z31.s, p7/m, z31.s, z31.s, #270
 // CHECK-ENCODING: [0xff,0x7f,0x9f,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 7f 9f 64 <unknown>
+// CHECK-UNKNOWN: 649f7fff <unknown>
 
 fcmla   z31.d, p7/m, z31.d, z31.d, #270
 // CHECK-INST: fcmla z31.d, p7/m, z31.d, z31.d, #270
 // CHECK-ENCODING: [0xff,0x7f,0xdf,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 7f df 64 <unknown>
+// CHECK-UNKNOWN: 64df7fff <unknown>
 
 fcmla   z0.h, z0.h, z0.h[0], #0
 // CHECK-INST: fcmla   z0.h, z0.h, z0.h[0], #0
 // CHECK-ENCODING: [0x00,0x10,0xa0,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 10 a0 64 <unknown>
+// CHECK-UNKNOWN: 64a01000 <unknown>
 
 fcmla   z23.s, z13.s, z8.s[0], #270
 // CHECK-INST: fcmla   z23.s, z13.s, z8.s[0], #270
 // CHECK-ENCODING: [0xb7,0x1d,0xe8,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 1d e8 64 <unknown>
+// CHECK-UNKNOWN: 64e81db7 <unknown>
 
 fcmla   z31.h, z31.h, z7.h[3], #270
 // CHECK-INST: fcmla   z31.h, z31.h, z7.h[3], #270
 // CHECK-ENCODING: [0xff,0x1f,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf1fff <unknown>
 
 fcmla   z21.s, z10.s, z5.s[1], #90
 // CHECK-INST: fcmla   z21.s, z10.s, z5.s[1], #90
 // CHECK-ENCODING: [0x55,0x15,0xf5,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 15 f5 64 <unknown>
+// CHECK-UNKNOWN: 64f51555 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -113,34 +113,34 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 fcmla   z4.d, p7/m, z31.d, z31.d, #270
 // CHECK-INST: fcmla	z4.d, p7/m, z31.d, z31.d, #270
 // CHECK-ENCODING: [0xe4,0x7f,0xdf,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 7f df 64 <unknown>
+// CHECK-UNKNOWN: 64df7fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 fcmla   z4.d, p7/m, z31.d, z31.d, #270
 // CHECK-INST: fcmla	z4.d, p7/m, z31.d, z31.d, #270
 // CHECK-ENCODING: [0xe4,0x7f,0xdf,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 7f df 64 <unknown>
+// CHECK-UNKNOWN: 64df7fe4 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 fcmla   z21.s, z10.s, z5.s[1], #90
 // CHECK-INST: fcmla	z21.s, z10.s, z5.s[1], #90
 // CHECK-ENCODING: [0x55,0x15,0xf5,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 15 f5 64 <unknown>
+// CHECK-UNKNOWN: 64f51555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fcmle.s b/llvm/test/MC/AArch64/SVE/fcmle.s
index 9c7221d5766a6..5d59787e40283 100644
--- a/llvm/test/MC/AArch64/SVE/fcmle.s
+++ b/llvm/test/MC/AArch64/SVE/fcmle.s
@@ -13,34 +13,34 @@ fcmle   p0.h, p0/z, z0.h, #0.0
 // CHECK-INST: fcmle	p0.h, p0/z, z0.h, #0.0
 // CHECK-ENCODING: [0x10,0x20,0x51,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 51 65 <unknown>
+// CHECK-UNKNOWN: 65512010 <unknown>
 
 fcmle   p0.s, p0/z, z0.s, #0.0
 // CHECK-INST: fcmle	p0.s, p0/z, z0.s, #0.0
 // CHECK-ENCODING: [0x10,0x20,0x91,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 91 65 <unknown>
+// CHECK-UNKNOWN: 65912010 <unknown>
 
 fcmle   p0.d, p0/z, z0.d, #0.0
 // CHECK-INST: fcmle	p0.d, p0/z, z0.d, #0.0
 // CHECK-ENCODING: [0x10,0x20,0xd1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 20 d1 65 <unknown>
+// CHECK-UNKNOWN: 65d12010 <unknown>
 
 fcmle   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: fcmge	p0.h, p0/z, z1.h, z0.h
 // CHECK-ENCODING: [0x20,0x40,0x40,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 40 40 65 <unknown>
+// CHECK-UNKNOWN: 65404020 <unknown>
 
 fcmle   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: fcmge	p0.s, p0/z, z1.s, z0.s
 // CHECK-ENCODING: [0x20,0x40,0x80,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 40 80 65 <unknown>
+// CHECK-UNKNOWN: 65804020 <unknown>
 
 fcmle   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: fcmge	p0.d, p0/z, z1.d, z0.d
 // CHECK-ENCODING: [0x20,0x40,0xc0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 40 c0 65 <unknown>
+// CHECK-UNKNOWN: 65c04020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fcmlt.s b/llvm/test/MC/AArch64/SVE/fcmlt.s
index 9bf8078b422d8..0462c3562f6a0 100644
--- a/llvm/test/MC/AArch64/SVE/fcmlt.s
+++ b/llvm/test/MC/AArch64/SVE/fcmlt.s
@@ -13,34 +13,34 @@ fcmlt   p0.h, p0/z, z0.h, #0.0
 // CHECK-INST: fcmlt	p0.h, p0/z, z0.h, #0.0
 // CHECK-ENCODING: [0x00,0x20,0x51,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 51 65 <unknown>
+// CHECK-UNKNOWN: 65512000 <unknown>
 
 fcmlt   p0.s, p0/z, z0.s, #0.0
 // CHECK-INST: fcmlt	p0.s, p0/z, z0.s, #0.0
 // CHECK-ENCODING: [0x00,0x20,0x91,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 91 65 <unknown>
+// CHECK-UNKNOWN: 65912000 <unknown>
 
 fcmlt   p0.d, p0/z, z0.d, #0.0
 // CHECK-INST: fcmlt	p0.d, p0/z, z0.d, #0.0
 // CHECK-ENCODING: [0x00,0x20,0xd1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 d1 65 <unknown>
+// CHECK-UNKNOWN: 65d12000 <unknown>
 
 fcmlt   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: fcmgt	p0.h, p0/z, z1.h, z0.h
 // CHECK-ENCODING: [0x30,0x40,0x40,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 40 40 65 <unknown>
+// CHECK-UNKNOWN: 65404030 <unknown>
 
 fcmlt   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: fcmgt	p0.s, p0/z, z1.s, z0.s
 // CHECK-ENCODING: [0x30,0x40,0x80,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 40 80 65 <unknown>
+// CHECK-UNKNOWN: 65804030 <unknown>
 
 fcmlt   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: fcmgt	p0.d, p0/z, z1.d, z0.d
 // CHECK-ENCODING: [0x30,0x40,0xc0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 30 40 c0 65 <unknown>
+// CHECK-UNKNOWN: 65c04030 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fcmne.s b/llvm/test/MC/AArch64/SVE/fcmne.s
index db6a659383542..6556f1815e678 100644
--- a/llvm/test/MC/AArch64/SVE/fcmne.s
+++ b/llvm/test/MC/AArch64/SVE/fcmne.s
@@ -13,34 +13,34 @@ fcmne   p0.h, p0/z, z0.h, #0.0
 // CHECK-INST: fcmne	p0.h, p0/z, z0.h, #0.0
 // CHECK-ENCODING: [0x00,0x20,0x53,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 53 65 <unknown>
+// CHECK-UNKNOWN: 65532000 <unknown>
 
 fcmne   p0.s, p0/z, z0.s, #0.0
 // CHECK-INST: fcmne	p0.s, p0/z, z0.s, #0.0
 // CHECK-ENCODING: [0x00,0x20,0x93,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 93 65 <unknown>
+// CHECK-UNKNOWN: 65932000 <unknown>
 
 fcmne   p0.d, p0/z, z0.d, #0.0
 // CHECK-INST: fcmne	p0.d, p0/z, z0.d, #0.0
 // CHECK-ENCODING: [0x00,0x20,0xd3,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 d3 65 <unknown>
+// CHECK-UNKNOWN: 65d32000 <unknown>
 
 fcmne   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: fcmne	p0.h, p0/z, z0.h, z1.h
 // CHECK-ENCODING: [0x10,0x60,0x41,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 60 41 65 <unknown>
+// CHECK-UNKNOWN: 65416010 <unknown>
 
 fcmne   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: fcmne	p0.s, p0/z, z0.s, z1.s
 // CHECK-ENCODING: [0x10,0x60,0x81,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 60 81 65 <unknown>
+// CHECK-UNKNOWN: 65816010 <unknown>
 
 fcmne   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: fcmne	p0.d, p0/z, z0.d, z1.d
 // CHECK-ENCODING: [0x10,0x60,0xc1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 60 c1 65 <unknown>
+// CHECK-UNKNOWN: 65c16010 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fcmuo.s b/llvm/test/MC/AArch64/SVE/fcmuo.s
index 67ac28671e944..15a21323fa819 100644
--- a/llvm/test/MC/AArch64/SVE/fcmuo.s
+++ b/llvm/test/MC/AArch64/SVE/fcmuo.s
@@ -13,17 +13,17 @@ fcmuo   p0.h, p0/z, z0.h, z1.h
 // CHECK-INST: fcmuo	p0.h, p0/z, z0.h, z1.h
 // CHECK-ENCODING: [0x00,0xc0,0x41,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 41 65 <unknown>
+// CHECK-UNKNOWN: 6541c000 <unknown>
 
 fcmuo   p0.s, p0/z, z0.s, z1.s
 // CHECK-INST: fcmuo	p0.s, p0/z, z0.s, z1.s
 // CHECK-ENCODING: [0x00,0xc0,0x81,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 81 65 <unknown>
+// CHECK-UNKNOWN: 6581c000 <unknown>
 
 fcmuo   p0.d, p0/z, z0.d, z1.d
 // CHECK-INST: fcmuo	p0.d, p0/z, z0.d, z1.d
 // CHECK-ENCODING: [0x00,0xc0,0xc1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 c1 65 <unknown>
+// CHECK-UNKNOWN: 65c1c000 <unknown>
 

diff  --git a/llvm/test/MC/AArch64/SVE/fcpy.s b/llvm/test/MC/AArch64/SVE/fcpy.s
index 4db71967e9799..0f9be5a48a8f1 100644
--- a/llvm/test/MC/AArch64/SVE/fcpy.s
+++ b/llvm/test/MC/AArch64/SVE/fcpy.s
@@ -13,1549 +13,1549 @@ fcpy z0.h, p0/m, #-0.12500000
 // CHECK-INST: fmov z0.h, p0/m, #-0.12500000
 // CHECK-ENCODING: [0x00,0xd8,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d8 50 05 <unknown>
+// CHECK-UNKNOWN: 0550d800 <unknown>
 
 fcpy z0.s, p0/m, #-0.12500000
 // CHECK-INST: fmov z0.s, p0/m, #-0.12500000
 // CHECK-ENCODING: [0x00,0xd8,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d8 90 05 <unknown>
+// CHECK-UNKNOWN: 0590d800 <unknown>
 
 fcpy z0.d, p0/m, #-0.12500000
 // CHECK-INST: fmov z0.d, p0/m, #-0.12500000
 // CHECK-ENCODING: [0x00,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d800 <unknown>
 
 fcpy z0.d, p0/m, #-0.13281250
 // CHECK-INST: fmov z0.d, p0/m, #-0.13281250
 // CHECK-ENCODING: [0x20,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d820 <unknown>
 
 fcpy z0.d, p0/m, #-0.14062500
 // CHECK-INST: fmov z0.d, p0/m, #-0.14062500
 // CHECK-ENCODING: [0x40,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d840 <unknown>
 
 fcpy z0.d, p0/m, #-0.14843750
 // CHECK-INST: fmov z0.d, p0/m, #-0.14843750
 // CHECK-ENCODING: [0x60,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d860 <unknown>
 
 fcpy z0.d, p0/m, #-0.15625000
 // CHECK-INST: fmov z0.d, p0/m, #-0.15625000
 // CHECK-ENCODING: [0x80,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d880 <unknown>
 
 fcpy z0.d, p0/m, #-0.16406250
 // CHECK-INST: fmov z0.d, p0/m, #-0.16406250
 // CHECK-ENCODING: [0xa0,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d8a0 <unknown>
 
 fcpy z0.d, p0/m, #-0.17187500
 // CHECK-INST: fmov z0.d, p0/m, #-0.17187500
 // CHECK-ENCODING: [0xc0,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d8c0 <unknown>
 
 fcpy z0.d, p0/m, #-0.17968750
 // CHECK-INST: fmov z0.d, p0/m, #-0.17968750
 // CHECK-ENCODING: [0xe0,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d8e0 <unknown>
 
 fcpy z0.d, p0/m, #-0.18750000
 // CHECK-INST: fmov z0.d, p0/m, #-0.18750000
 // CHECK-ENCODING: [0x00,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d900 <unknown>
 
 fcpy z0.d, p0/m, #-0.19531250
 // CHECK-INST: fmov z0.d, p0/m, #-0.19531250
 // CHECK-ENCODING: [0x20,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d920 <unknown>
 
 fcpy z0.d, p0/m, #-0.20312500
 // CHECK-INST: fmov z0.d, p0/m, #-0.20312500
 // CHECK-ENCODING: [0x40,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d940 <unknown>
 
 fcpy z0.d, p0/m, #-0.21093750
 // CHECK-INST: fmov z0.d, p0/m, #-0.21093750
 // CHECK-ENCODING: [0x60,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d960 <unknown>
 
 fcpy z0.d, p0/m, #-0.21875000
 // CHECK-INST: fmov z0.d, p0/m, #-0.21875000
 // CHECK-ENCODING: [0x80,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d980 <unknown>
 
 fcpy z0.d, p0/m, #-0.22656250
 // CHECK-INST: fmov z0.d, p0/m, #-0.22656250
 // CHECK-ENCODING: [0xa0,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d9a0 <unknown>
 
 fcpy z0.d, p0/m, #-0.23437500
 // CHECK-INST: fmov z0.d, p0/m, #-0.23437500
 // CHECK-ENCODING: [0xc0,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d9c0 <unknown>
 
 fcpy z0.d, p0/m, #-0.24218750
 // CHECK-INST: fmov z0.d, p0/m, #-0.24218750
 // CHECK-ENCODING: [0xe0,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d9e0 <unknown>
 
 fcpy z0.d, p0/m, #-0.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-0.25000000
 // CHECK-ENCODING: [0x00,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0da00 <unknown>
 
 fcpy z0.d, p0/m, #-0.26562500
 // CHECK-INST: fmov z0.d, p0/m, #-0.26562500
 // CHECK-ENCODING: [0x20,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0da20 <unknown>
 
 fcpy z0.d, p0/m, #-0.28125000
 // CHECK-INST: fmov z0.d, p0/m, #-0.28125000
 // CHECK-ENCODING: [0x40,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0da40 <unknown>
 
 fcpy z0.d, p0/m, #-0.29687500
 // CHECK-INST: fmov z0.d, p0/m, #-0.29687500
 // CHECK-ENCODING: [0x60,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0da60 <unknown>
 
 fcpy z0.d, p0/m, #-0.31250000
 // CHECK-INST: fmov z0.d, p0/m, #-0.31250000
 // CHECK-ENCODING: [0x80,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0da80 <unknown>
 
 fcpy z0.d, p0/m, #-0.32812500
 // CHECK-INST: fmov z0.d, p0/m, #-0.32812500
 // CHECK-ENCODING: [0xa0,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0daa0 <unknown>
 
 fcpy z0.d, p0/m, #-0.34375000
 // CHECK-INST: fmov z0.d, p0/m, #-0.34375000
 // CHECK-ENCODING: [0xc0,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dac0 <unknown>
 
 fcpy z0.d, p0/m, #-0.35937500
 // CHECK-INST: fmov z0.d, p0/m, #-0.35937500
 // CHECK-ENCODING: [0xe0,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dae0 <unknown>
 
 fcpy z0.d, p0/m, #-0.37500000
 // CHECK-INST: fmov z0.d, p0/m, #-0.37500000
 // CHECK-ENCODING: [0x00,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0db00 <unknown>
 
 fcpy z0.d, p0/m, #-0.39062500
 // CHECK-INST: fmov z0.d, p0/m, #-0.39062500
 // CHECK-ENCODING: [0x20,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0db20 <unknown>
 
 fcpy z0.d, p0/m, #-0.40625000
 // CHECK-INST: fmov z0.d, p0/m, #-0.40625000
 // CHECK-ENCODING: [0x40,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0db40 <unknown>
 
 fcpy z0.d, p0/m, #-0.42187500
 // CHECK-INST: fmov z0.d, p0/m, #-0.42187500
 // CHECK-ENCODING: [0x60,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0db60 <unknown>
 
 fcpy z0.d, p0/m, #-0.43750000
 // CHECK-INST: fmov z0.d, p0/m, #-0.43750000
 // CHECK-ENCODING: [0x80,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0db80 <unknown>
 
 fcpy z0.d, p0/m, #-0.45312500
 // CHECK-INST: fmov z0.d, p0/m, #-0.45312500
 // CHECK-ENCODING: [0xa0,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dba0 <unknown>
 
 fcpy z0.d, p0/m, #-0.46875000
 // CHECK-INST: fmov z0.d, p0/m, #-0.46875000
 // CHECK-ENCODING: [0xc0,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dbc0 <unknown>
 
 fcpy z0.d, p0/m, #-0.48437500
 // CHECK-INST: fmov z0.d, p0/m, #-0.48437500
 // CHECK-ENCODING: [0xe0,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dbe0 <unknown>
 
 fcpy z0.d, p0/m, #-0.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-0.50000000
 // CHECK-ENCODING: [0x00,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dc00 <unknown>
 
 fcpy z0.d, p0/m, #-0.53125000
 // CHECK-INST: fmov z0.d, p0/m, #-0.53125000
 // CHECK-ENCODING: [0x20,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dc20 <unknown>
 
 fcpy z0.d, p0/m, #-0.56250000
 // CHECK-INST: fmov z0.d, p0/m, #-0.56250000
 // CHECK-ENCODING: [0x40,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dc40 <unknown>
 
 fcpy z0.d, p0/m, #-0.59375000
 // CHECK-INST: fmov z0.d, p0/m, #-0.59375000
 // CHECK-ENCODING: [0x60,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dc60 <unknown>
 
 fcpy z0.d, p0/m, #-0.62500000
 // CHECK-INST: fmov z0.d, p0/m, #-0.62500000
 // CHECK-ENCODING: [0x80,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dc80 <unknown>
 
 fcpy z0.d, p0/m, #-0.65625000
 // CHECK-INST: fmov z0.d, p0/m, #-0.65625000
 // CHECK-ENCODING: [0xa0,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dca0 <unknown>
 
 fcpy z0.d, p0/m, #-0.68750000
 // CHECK-INST: fmov z0.d, p0/m, #-0.68750000
 // CHECK-ENCODING: [0xc0,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dcc0 <unknown>
 
 fcpy z0.d, p0/m, #-0.71875000
 // CHECK-INST: fmov z0.d, p0/m, #-0.71875000
 // CHECK-ENCODING: [0xe0,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dce0 <unknown>
 
 fcpy z0.d, p0/m, #-0.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-0.75000000
 // CHECK-ENCODING: [0x00,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dd00 <unknown>
 
 fcpy z0.d, p0/m, #-0.78125000
 // CHECK-INST: fmov z0.d, p0/m, #-0.78125000
 // CHECK-ENCODING: [0x20,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dd20 <unknown>
 
 fcpy z0.d, p0/m, #-0.81250000
 // CHECK-INST: fmov z0.d, p0/m, #-0.81250000
 // CHECK-ENCODING: [0x40,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dd40 <unknown>
 
 fcpy z0.d, p0/m, #-0.84375000
 // CHECK-INST: fmov z0.d, p0/m, #-0.84375000
 // CHECK-ENCODING: [0x60,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dd60 <unknown>
 
 fcpy z0.d, p0/m, #-0.87500000
 // CHECK-INST: fmov z0.d, p0/m, #-0.87500000
 // CHECK-ENCODING: [0x80,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dd80 <unknown>
 
 fcpy z0.d, p0/m, #-0.90625000
 // CHECK-INST: fmov z0.d, p0/m, #-0.90625000
 // CHECK-ENCODING: [0xa0,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dda0 <unknown>
 
 fcpy z0.d, p0/m, #-0.93750000
 // CHECK-INST: fmov z0.d, p0/m, #-0.93750000
 // CHECK-ENCODING: [0xc0,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ddc0 <unknown>
 
 fcpy z0.d, p0/m, #-0.96875000
 // CHECK-INST: fmov z0.d, p0/m, #-0.96875000
 // CHECK-ENCODING: [0xe0,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dde0 <unknown>
 
 fcpy z0.d, p0/m, #-1.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-1.00000000
 // CHECK-ENCODING: [0x00,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0de00 <unknown>
 
 fcpy z0.d, p0/m, #-1.06250000
 // CHECK-INST: fmov z0.d, p0/m, #-1.06250000
 // CHECK-ENCODING: [0x20,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0de20 <unknown>
 
 fcpy z0.d, p0/m, #-1.12500000
 // CHECK-INST: fmov z0.d, p0/m, #-1.12500000
 // CHECK-ENCODING: [0x40,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0de40 <unknown>
 
 fcpy z0.d, p0/m, #-1.18750000
 // CHECK-INST: fmov z0.d, p0/m, #-1.18750000
 // CHECK-ENCODING: [0x60,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0de60 <unknown>
 
 fcpy z0.d, p0/m, #-1.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-1.25000000
 // CHECK-ENCODING: [0x80,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0de80 <unknown>
 
 fcpy z0.d, p0/m, #-1.31250000
 // CHECK-INST: fmov z0.d, p0/m, #-1.31250000
 // CHECK-ENCODING: [0xa0,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dea0 <unknown>
 
 fcpy z0.d, p0/m, #-1.37500000
 // CHECK-INST: fmov z0.d, p0/m, #-1.37500000
 // CHECK-ENCODING: [0xc0,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dec0 <unknown>
 
 fcpy z0.d, p0/m, #-1.43750000
 // CHECK-INST: fmov z0.d, p0/m, #-1.43750000
 // CHECK-ENCODING: [0xe0,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dee0 <unknown>
 
 fcpy z0.d, p0/m, #-1.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-1.50000000
 // CHECK-ENCODING: [0x00,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0df00 <unknown>
 
 fcpy z0.d, p0/m, #-1.56250000
 // CHECK-INST: fmov z0.d, p0/m, #-1.56250000
 // CHECK-ENCODING: [0x20,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0df20 <unknown>
 
 fcpy z0.d, p0/m, #-1.62500000
 // CHECK-INST: fmov z0.d, p0/m, #-1.62500000
 // CHECK-ENCODING: [0x40,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0df40 <unknown>
 
 fcpy z0.d, p0/m, #-1.68750000
 // CHECK-INST: fmov z0.d, p0/m, #-1.68750000
 // CHECK-ENCODING: [0x60,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0df60 <unknown>
 
 fcpy z0.d, p0/m, #-1.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-1.75000000
 // CHECK-ENCODING: [0x80,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0df80 <unknown>
 
 fcpy z0.d, p0/m, #-1.81250000
 // CHECK-INST: fmov z0.d, p0/m, #-1.81250000
 // CHECK-ENCODING: [0xa0,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dfa0 <unknown>
 
 fcpy z0.d, p0/m, #-1.87500000
 // CHECK-INST: fmov z0.d, p0/m, #-1.87500000
 // CHECK-ENCODING: [0xc0,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dfc0 <unknown>
 
 fcpy z0.d, p0/m, #-1.93750000
 // CHECK-INST: fmov z0.d, p0/m, #-1.93750000
 // CHECK-ENCODING: [0xe0,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dfe0 <unknown>
 
 fcpy z0.d, p0/m, #-2.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-2.00000000
 // CHECK-ENCODING: [0x00,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d000 <unknown>
 
 fcpy z0.d, p0/m, #-2.12500000
 // CHECK-INST: fmov z0.d, p0/m, #-2.12500000
 // CHECK-ENCODING: [0x20,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d020 <unknown>
 
 fcpy z0.d, p0/m, #-2.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-2.25000000
 // CHECK-ENCODING: [0x40,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d040 <unknown>
 
 fcpy z0.d, p0/m, #-2.37500000
 // CHECK-INST: fmov z0.d, p0/m, #-2.37500000
 // CHECK-ENCODING: [0x60,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d060 <unknown>
 
 fcpy z0.d, p0/m, #-2.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-2.50000000
 // CHECK-ENCODING: [0x80,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d080 <unknown>
 
 fcpy z0.d, p0/m, #-2.62500000
 // CHECK-INST: fmov z0.d, p0/m, #-2.62500000
 // CHECK-ENCODING: [0xa0,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d0a0 <unknown>
 
 fcpy z0.d, p0/m, #-2.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-2.75000000
 // CHECK-ENCODING: [0xc0,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d0c0 <unknown>
 
 fcpy z0.d, p0/m, #-2.87500000
 // CHECK-INST: fmov z0.d, p0/m, #-2.87500000
 // CHECK-ENCODING: [0xe0,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d0e0 <unknown>
 
 fcpy z0.d, p0/m, #-3.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-3.00000000
 // CHECK-ENCODING: [0x00,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d100 <unknown>
 
 fcpy z0.d, p0/m, #-3.12500000
 // CHECK-INST: fmov z0.d, p0/m, #-3.12500000
 // CHECK-ENCODING: [0x20,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d120 <unknown>
 
 fcpy z0.d, p0/m, #-3.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-3.25000000
 // CHECK-ENCODING: [0x40,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d140 <unknown>
 
 fcpy z0.d, p0/m, #-3.37500000
 // CHECK-INST: fmov z0.d, p0/m, #-3.37500000
 // CHECK-ENCODING: [0x60,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d160 <unknown>
 
 fcpy z0.d, p0/m, #-3.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-3.50000000
 // CHECK-ENCODING: [0x80,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d180 <unknown>
 
 fcpy z0.d, p0/m, #-3.62500000
 // CHECK-INST: fmov z0.d, p0/m, #-3.62500000
 // CHECK-ENCODING: [0xa0,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d1a0 <unknown>
 
 fcpy z0.d, p0/m, #-3.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-3.75000000
 // CHECK-ENCODING: [0xc0,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d1c0 <unknown>
 
 fcpy z0.d, p0/m, #-3.87500000
 // CHECK-INST: fmov z0.d, p0/m, #-3.87500000
 // CHECK-ENCODING: [0xe0,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d1e0 <unknown>
 
 fcpy z0.d, p0/m, #-4.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-4.00000000
 // CHECK-ENCODING: [0x00,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d200 <unknown>
 
 fcpy z0.d, p0/m, #-4.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-4.25000000
 // CHECK-ENCODING: [0x20,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d220 <unknown>
 
 fcpy z0.d, p0/m, #-4.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-4.50000000
 // CHECK-ENCODING: [0x40,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d240 <unknown>
 
 fcpy z0.d, p0/m, #-4.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-4.75000000
 // CHECK-ENCODING: [0x60,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d260 <unknown>
 
 fcpy z0.d, p0/m, #-5.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-5.00000000
 // CHECK-ENCODING: [0x80,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d280 <unknown>
 
 fcpy z0.d, p0/m, #-5.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-5.25000000
 // CHECK-ENCODING: [0xa0,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d2a0 <unknown>
 
 fcpy z0.d, p0/m, #-5.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-5.50000000
 // CHECK-ENCODING: [0xc0,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d2c0 <unknown>
 
 fcpy z0.d, p0/m, #-5.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-5.75000000
 // CHECK-ENCODING: [0xe0,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d2e0 <unknown>
 
 fcpy z0.d, p0/m, #-6.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-6.00000000
 // CHECK-ENCODING: [0x00,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d300 <unknown>
 
 fcpy z0.d, p0/m, #-6.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-6.25000000
 // CHECK-ENCODING: [0x20,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d320 <unknown>
 
 fcpy z0.d, p0/m, #-6.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-6.50000000
 // CHECK-ENCODING: [0x40,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d340 <unknown>
 
 fcpy z0.d, p0/m, #-6.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-6.75000000
 // CHECK-ENCODING: [0x60,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d360 <unknown>
 
 fcpy z0.d, p0/m, #-7.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-7.00000000
 // CHECK-ENCODING: [0x80,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d380 <unknown>
 
 fcpy z0.d, p0/m, #-7.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-7.25000000
 // CHECK-ENCODING: [0xa0,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d3a0 <unknown>
 
 fcpy z0.d, p0/m, #-7.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-7.50000000
 // CHECK-ENCODING: [0xc0,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d3c0 <unknown>
 
 fcpy z0.d, p0/m, #-7.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-7.75000000
 // CHECK-ENCODING: [0xe0,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d3e0 <unknown>
 
 fcpy z0.d, p0/m, #-8.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-8.00000000
 // CHECK-ENCODING: [0x00,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d400 <unknown>
 
 fcpy z0.d, p0/m, #-8.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-8.50000000
 // CHECK-ENCODING: [0x20,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d420 <unknown>
 
 fcpy z0.d, p0/m, #-9.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-9.00000000
 // CHECK-ENCODING: [0x40,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d440 <unknown>
 
 fcpy z0.d, p0/m, #-9.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-9.50000000
 // CHECK-ENCODING: [0x60,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d460 <unknown>
 
 fcpy z0.d, p0/m, #-10.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-10.00000000
 // CHECK-ENCODING: [0x80,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d480 <unknown>
 
 fcpy z0.d, p0/m, #-10.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-10.50000000
 // CHECK-ENCODING: [0xa0,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d4a0 <unknown>
 
 fcpy z0.d, p0/m, #-11.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-11.00000000
 // CHECK-ENCODING: [0xc0,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d4c0 <unknown>
 
 fcpy z0.d, p0/m, #-11.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-11.50000000
 // CHECK-ENCODING: [0xe0,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d4e0 <unknown>
 
 fcpy z0.d, p0/m, #-12.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-12.00000000
 // CHECK-ENCODING: [0x00,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d500 <unknown>
 
 fcpy z0.d, p0/m, #-12.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-12.50000000
 // CHECK-ENCODING: [0x20,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d520 <unknown>
 
 fcpy z0.d, p0/m, #-13.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-13.00000000
 // CHECK-ENCODING: [0x40,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d540 <unknown>
 
 fcpy z0.d, p0/m, #-13.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-13.50000000
 // CHECK-ENCODING: [0x60,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d560 <unknown>
 
 fcpy z0.d, p0/m, #-14.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-14.00000000
 // CHECK-ENCODING: [0x80,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d580 <unknown>
 
 fcpy z0.d, p0/m, #-14.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-14.50000000
 // CHECK-ENCODING: [0xa0,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d5a0 <unknown>
 
 fcpy z0.d, p0/m, #-15.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-15.00000000
 // CHECK-ENCODING: [0xc0,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d5c0 <unknown>
 
 fcpy z0.d, p0/m, #-15.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-15.50000000
 // CHECK-ENCODING: [0xe0,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d5e0 <unknown>
 
 fcpy z0.d, p0/m, #-16.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-16.00000000
 // CHECK-ENCODING: [0x00,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d600 <unknown>
 
 fcpy z0.d, p0/m, #-17.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-17.00000000
 // CHECK-ENCODING: [0x20,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d620 <unknown>
 
 fcpy z0.d, p0/m, #-18.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-18.00000000
 // CHECK-ENCODING: [0x40,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d640 <unknown>
 
 fcpy z0.d, p0/m, #-19.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-19.00000000
 // CHECK-ENCODING: [0x60,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d660 <unknown>
 
 fcpy z0.d, p0/m, #-20.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-20.00000000
 // CHECK-ENCODING: [0x80,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d680 <unknown>
 
 fcpy z0.d, p0/m, #-21.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-21.00000000
 // CHECK-ENCODING: [0xa0,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d6a0 <unknown>
 
 fcpy z0.d, p0/m, #-22.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-22.00000000
 // CHECK-ENCODING: [0xc0,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d6c0 <unknown>
 
 fcpy z0.d, p0/m, #-23.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-23.00000000
 // CHECK-ENCODING: [0xe0,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d6e0 <unknown>
 
 fcpy z0.d, p0/m, #-24.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-24.00000000
 // CHECK-ENCODING: [0x00,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d700 <unknown>
 
 fcpy z0.d, p0/m, #-25.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-25.00000000
 // CHECK-ENCODING: [0x20,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d720 <unknown>
 
 fcpy z0.d, p0/m, #-26.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-26.00000000
 // CHECK-ENCODING: [0x40,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d740 <unknown>
 
 fcpy z0.d, p0/m, #-27.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-27.00000000
 // CHECK-ENCODING: [0x60,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d760 <unknown>
 
 fcpy z0.d, p0/m, #-28.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-28.00000000
 // CHECK-ENCODING: [0x80,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d780 <unknown>
 
 fcpy z0.d, p0/m, #-29.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-29.00000000
 // CHECK-ENCODING: [0xa0,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d7a0 <unknown>
 
 fcpy z0.d, p0/m, #-30.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-30.00000000
 // CHECK-ENCODING: [0xc0,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d7c0 <unknown>
 
 fcpy z0.d, p0/m, #-31.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-31.00000000
 // CHECK-ENCODING: [0xe0,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d7e0 <unknown>
 
 fcpy z0.d, p0/m, #0.12500000
 // CHECK-INST: fmov z0.d, p0/m, #0.12500000
 // CHECK-ENCODING: [0x00,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c800 <unknown>
 
 fcpy z0.d, p0/m, #0.13281250
 // CHECK-INST: fmov z0.d, p0/m, #0.13281250
 // CHECK-ENCODING: [0x20,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c820 <unknown>
 
 fcpy z0.d, p0/m, #0.14062500
 // CHECK-INST: fmov z0.d, p0/m, #0.14062500
 // CHECK-ENCODING: [0x40,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c840 <unknown>
 
 fcpy z0.d, p0/m, #0.14843750
 // CHECK-INST: fmov z0.d, p0/m, #0.14843750
 // CHECK-ENCODING: [0x60,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c860 <unknown>
 
 fcpy z0.d, p0/m, #0.15625000
 // CHECK-INST: fmov z0.d, p0/m, #0.15625000
 // CHECK-ENCODING: [0x80,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c880 <unknown>
 
 fcpy z0.d, p0/m, #0.16406250
 // CHECK-INST: fmov z0.d, p0/m, #0.16406250
 // CHECK-ENCODING: [0xa0,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c8a0 <unknown>
 
 fcpy z0.d, p0/m, #0.17187500
 // CHECK-INST: fmov z0.d, p0/m, #0.17187500
 // CHECK-ENCODING: [0xc0,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c8c0 <unknown>
 
 fcpy z0.d, p0/m, #0.17968750
 // CHECK-INST: fmov z0.d, p0/m, #0.17968750
 // CHECK-ENCODING: [0xe0,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c8e0 <unknown>
 
 fcpy z0.d, p0/m, #0.18750000
 // CHECK-INST: fmov z0.d, p0/m, #0.18750000
 // CHECK-ENCODING: [0x00,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c900 <unknown>
 
 fcpy z0.d, p0/m, #0.19531250
 // CHECK-INST: fmov z0.d, p0/m, #0.19531250
 // CHECK-ENCODING: [0x20,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c920 <unknown>
 
 fcpy z0.d, p0/m, #0.20312500
 // CHECK-INST: fmov z0.d, p0/m, #0.20312500
 // CHECK-ENCODING: [0x40,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c940 <unknown>
 
 fcpy z0.d, p0/m, #0.21093750
 // CHECK-INST: fmov z0.d, p0/m, #0.21093750
 // CHECK-ENCODING: [0x60,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c960 <unknown>
 
 fcpy z0.d, p0/m, #0.21875000
 // CHECK-INST: fmov z0.d, p0/m, #0.21875000
 // CHECK-ENCODING: [0x80,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c980 <unknown>
 
 fcpy z0.d, p0/m, #0.22656250
 // CHECK-INST: fmov z0.d, p0/m, #0.22656250
 // CHECK-ENCODING: [0xa0,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c9a0 <unknown>
 
 fcpy z0.d, p0/m, #0.23437500
 // CHECK-INST: fmov z0.d, p0/m, #0.23437500
 // CHECK-ENCODING: [0xc0,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c9c0 <unknown>
 
 fcpy z0.d, p0/m, #0.24218750
 // CHECK-INST: fmov z0.d, p0/m, #0.24218750
 // CHECK-ENCODING: [0xe0,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c9e0 <unknown>
 
 fcpy z0.d, p0/m, #0.25000000
 // CHECK-INST: fmov z0.d, p0/m, #0.25000000
 // CHECK-ENCODING: [0x00,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ca00 <unknown>
 
 fcpy z0.d, p0/m, #0.26562500
 // CHECK-INST: fmov z0.d, p0/m, #0.26562500
 // CHECK-ENCODING: [0x20,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ca20 <unknown>
 
 fcpy z0.d, p0/m, #0.28125000
 // CHECK-INST: fmov z0.d, p0/m, #0.28125000
 // CHECK-ENCODING: [0x40,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ca40 <unknown>
 
 fcpy z0.d, p0/m, #0.29687500
 // CHECK-INST: fmov z0.d, p0/m, #0.29687500
 // CHECK-ENCODING: [0x60,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ca60 <unknown>
 
 fcpy z0.d, p0/m, #0.31250000
 // CHECK-INST: fmov z0.d, p0/m, #0.31250000
 // CHECK-ENCODING: [0x80,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ca80 <unknown>
 
 fcpy z0.d, p0/m, #0.32812500
 // CHECK-INST: fmov z0.d, p0/m, #0.32812500
 // CHECK-ENCODING: [0xa0,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0caa0 <unknown>
 
 fcpy z0.d, p0/m, #0.34375000
 // CHECK-INST: fmov z0.d, p0/m, #0.34375000
 // CHECK-ENCODING: [0xc0,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cac0 <unknown>
 
 fcpy z0.d, p0/m, #0.35937500
 // CHECK-INST: fmov z0.d, p0/m, #0.35937500
 // CHECK-ENCODING: [0xe0,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cae0 <unknown>
 
 fcpy z0.d, p0/m, #0.37500000
 // CHECK-INST: fmov z0.d, p0/m, #0.37500000
 // CHECK-ENCODING: [0x00,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cb00 <unknown>
 
 fcpy z0.d, p0/m, #0.39062500
 // CHECK-INST: fmov z0.d, p0/m, #0.39062500
 // CHECK-ENCODING: [0x20,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cb20 <unknown>
 
 fcpy z0.d, p0/m, #0.40625000
 // CHECK-INST: fmov z0.d, p0/m, #0.40625000
 // CHECK-ENCODING: [0x40,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cb40 <unknown>
 
 fcpy z0.d, p0/m, #0.42187500
 // CHECK-INST: fmov z0.d, p0/m, #0.42187500
 // CHECK-ENCODING: [0x60,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cb60 <unknown>
 
 fcpy z0.d, p0/m, #0.43750000
 // CHECK-INST: fmov z0.d, p0/m, #0.43750000
 // CHECK-ENCODING: [0x80,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cb80 <unknown>
 
 fcpy z0.d, p0/m, #0.45312500
 // CHECK-INST: fmov z0.d, p0/m, #0.45312500
 // CHECK-ENCODING: [0xa0,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cba0 <unknown>
 
 fcpy z0.d, p0/m, #0.46875000
 // CHECK-INST: fmov z0.d, p0/m, #0.46875000
 // CHECK-ENCODING: [0xc0,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cbc0 <unknown>
 
 fcpy z0.d, p0/m, #0.48437500
 // CHECK-INST: fmov z0.d, p0/m, #0.48437500
 // CHECK-ENCODING: [0xe0,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cbe0 <unknown>
 
 fcpy z0.d, p0/m, #0.50000000
 // CHECK-INST: fmov z0.d, p0/m, #0.50000000
 // CHECK-ENCODING: [0x00,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cc00 <unknown>
 
 fcpy z0.d, p0/m, #0.53125000
 // CHECK-INST: fmov z0.d, p0/m, #0.53125000
 // CHECK-ENCODING: [0x20,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cc20 <unknown>
 
 fcpy z0.d, p0/m, #0.56250000
 // CHECK-INST: fmov z0.d, p0/m, #0.56250000
 // CHECK-ENCODING: [0x40,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cc40 <unknown>
 
 fcpy z0.d, p0/m, #0.59375000
 // CHECK-INST: fmov z0.d, p0/m, #0.59375000
 // CHECK-ENCODING: [0x60,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cc60 <unknown>
 
 fcpy z0.d, p0/m, #0.62500000
 // CHECK-INST: fmov z0.d, p0/m, #0.62500000
 // CHECK-ENCODING: [0x80,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cc80 <unknown>
 
 fcpy z0.d, p0/m, #0.65625000
 // CHECK-INST: fmov z0.d, p0/m, #0.65625000
 // CHECK-ENCODING: [0xa0,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cca0 <unknown>
 
 fcpy z0.d, p0/m, #0.68750000
 // CHECK-INST: fmov z0.d, p0/m, #0.68750000
 // CHECK-ENCODING: [0xc0,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ccc0 <unknown>
 
 fcpy z0.d, p0/m, #0.71875000
 // CHECK-INST: fmov z0.d, p0/m, #0.71875000
 // CHECK-ENCODING: [0xe0,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cce0 <unknown>
 
 fcpy z0.d, p0/m, #0.75000000
 // CHECK-INST: fmov z0.d, p0/m, #0.75000000
 // CHECK-ENCODING: [0x00,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cd00 <unknown>
 
 fcpy z0.d, p0/m, #0.78125000
 // CHECK-INST: fmov z0.d, p0/m, #0.78125000
 // CHECK-ENCODING: [0x20,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cd20 <unknown>
 
 fcpy z0.d, p0/m, #0.81250000
 // CHECK-INST: fmov z0.d, p0/m, #0.81250000
 // CHECK-ENCODING: [0x40,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cd40 <unknown>
 
 fcpy z0.d, p0/m, #0.84375000
 // CHECK-INST: fmov z0.d, p0/m, #0.84375000
 // CHECK-ENCODING: [0x60,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cd60 <unknown>
 
 fcpy z0.d, p0/m, #0.87500000
 // CHECK-INST: fmov z0.d, p0/m, #0.87500000
 // CHECK-ENCODING: [0x80,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cd80 <unknown>
 
 fcpy z0.d, p0/m, #0.90625000
 // CHECK-INST: fmov z0.d, p0/m, #0.90625000
 // CHECK-ENCODING: [0xa0,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cda0 <unknown>
 
 fcpy z0.d, p0/m, #0.93750000
 // CHECK-INST: fmov z0.d, p0/m, #0.93750000
 // CHECK-ENCODING: [0xc0,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cdc0 <unknown>
 
 fcpy z0.d, p0/m, #0.96875000
 // CHECK-INST: fmov z0.d, p0/m, #0.96875000
 // CHECK-ENCODING: [0xe0,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cde0 <unknown>
 
 fcpy z0.d, p0/m, #1.00000000
 // CHECK-INST: fmov z0.d, p0/m, #1.00000000
 // CHECK-ENCODING: [0x00,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ce00 <unknown>
 
 fcpy z0.d, p0/m, #1.06250000
 // CHECK-INST: fmov z0.d, p0/m, #1.06250000
 // CHECK-ENCODING: [0x20,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ce20 <unknown>
 
 fcpy z0.d, p0/m, #1.12500000
 // CHECK-INST: fmov z0.d, p0/m, #1.12500000
 // CHECK-ENCODING: [0x40,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ce40 <unknown>
 
 fcpy z0.d, p0/m, #1.18750000
 // CHECK-INST: fmov z0.d, p0/m, #1.18750000
 // CHECK-ENCODING: [0x60,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ce60 <unknown>
 
 fcpy z0.d, p0/m, #1.25000000
 // CHECK-INST: fmov z0.d, p0/m, #1.25000000
 // CHECK-ENCODING: [0x80,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ce80 <unknown>
 
 fcpy z0.d, p0/m, #1.31250000
 // CHECK-INST: fmov z0.d, p0/m, #1.31250000
 // CHECK-ENCODING: [0xa0,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cea0 <unknown>
 
 fcpy z0.d, p0/m, #1.37500000
 // CHECK-INST: fmov z0.d, p0/m, #1.37500000
 // CHECK-ENCODING: [0xc0,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cec0 <unknown>
 
 fcpy z0.d, p0/m, #1.43750000
 // CHECK-INST: fmov z0.d, p0/m, #1.43750000
 // CHECK-ENCODING: [0xe0,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cee0 <unknown>
 
 fcpy z0.d, p0/m, #1.50000000
 // CHECK-INST: fmov z0.d, p0/m, #1.50000000
 // CHECK-ENCODING: [0x00,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cf00 <unknown>
 
 fcpy z0.d, p0/m, #1.56250000
 // CHECK-INST: fmov z0.d, p0/m, #1.56250000
 // CHECK-ENCODING: [0x20,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cf20 <unknown>
 
 fcpy z0.d, p0/m, #1.62500000
 // CHECK-INST: fmov z0.d, p0/m, #1.62500000
 // CHECK-ENCODING: [0x40,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cf40 <unknown>
 
 fcpy z0.d, p0/m, #1.68750000
 // CHECK-INST: fmov z0.d, p0/m, #1.68750000
 // CHECK-ENCODING: [0x60,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cf60 <unknown>
 
 fcpy z0.d, p0/m, #1.75000000
 // CHECK-INST: fmov z0.d, p0/m, #1.75000000
 // CHECK-ENCODING: [0x80,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cf80 <unknown>
 
 fcpy z0.d, p0/m, #1.81250000
 // CHECK-INST: fmov z0.d, p0/m, #1.81250000
 // CHECK-ENCODING: [0xa0,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cfa0 <unknown>
 
 fcpy z0.d, p0/m, #1.87500000
 // CHECK-INST: fmov z0.d, p0/m, #1.87500000
 // CHECK-ENCODING: [0xc0,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cfc0 <unknown>
 
 fcpy z0.d, p0/m, #1.93750000
 // CHECK-INST: fmov z0.d, p0/m, #1.93750000
 // CHECK-ENCODING: [0xe0,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cfe0 <unknown>
 
 fcpy z0.d, p0/m, #2.00000000
 // CHECK-INST: fmov z0.d, p0/m, #2.00000000
 // CHECK-ENCODING: [0x00,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c000 <unknown>
 
 fcpy z0.d, p0/m, #2.12500000
 // CHECK-INST: fmov z0.d, p0/m, #2.12500000
 // CHECK-ENCODING: [0x20,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c020 <unknown>
 
 fcpy z0.d, p0/m, #2.25000000
 // CHECK-INST: fmov z0.d, p0/m, #2.25000000
 // CHECK-ENCODING: [0x40,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c040 <unknown>
 
 fcpy z0.d, p0/m, #2.37500000
 // CHECK-INST: fmov z0.d, p0/m, #2.37500000
 // CHECK-ENCODING: [0x60,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c060 <unknown>
 
 fcpy z0.d, p0/m, #2.50000000
 // CHECK-INST: fmov z0.d, p0/m, #2.50000000
 // CHECK-ENCODING: [0x80,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c080 <unknown>
 
 fcpy z0.d, p0/m, #2.62500000
 // CHECK-INST: fmov z0.d, p0/m, #2.62500000
 // CHECK-ENCODING: [0xa0,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c0a0 <unknown>
 
 fcpy z0.d, p0/m, #2.75000000
 // CHECK-INST: fmov z0.d, p0/m, #2.75000000
 // CHECK-ENCODING: [0xc0,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c0c0 <unknown>
 
 fcpy z0.d, p0/m, #2.87500000
 // CHECK-INST: fmov z0.d, p0/m, #2.87500000
 // CHECK-ENCODING: [0xe0,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c0e0 <unknown>
 
 fcpy z0.d, p0/m, #3.00000000
 // CHECK-INST: fmov z0.d, p0/m, #3.00000000
 // CHECK-ENCODING: [0x00,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c100 <unknown>
 
 fcpy z0.d, p0/m, #3.12500000
 // CHECK-INST: fmov z0.d, p0/m, #3.12500000
 // CHECK-ENCODING: [0x20,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c120 <unknown>
 
 fcpy z0.d, p0/m, #3.25000000
 // CHECK-INST: fmov z0.d, p0/m, #3.25000000
 // CHECK-ENCODING: [0x40,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c140 <unknown>
 
 fcpy z0.d, p0/m, #3.37500000
 // CHECK-INST: fmov z0.d, p0/m, #3.37500000
 // CHECK-ENCODING: [0x60,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c160 <unknown>
 
 fcpy z0.d, p0/m, #3.50000000
 // CHECK-INST: fmov z0.d, p0/m, #3.50000000
 // CHECK-ENCODING: [0x80,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c180 <unknown>
 
 fcpy z0.d, p0/m, #3.62500000
 // CHECK-INST: fmov z0.d, p0/m, #3.62500000
 // CHECK-ENCODING: [0xa0,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c1a0 <unknown>
 
 fcpy z0.d, p0/m, #3.75000000
 // CHECK-INST: fmov z0.d, p0/m, #3.75000000
 // CHECK-ENCODING: [0xc0,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c1c0 <unknown>
 
 fcpy z0.d, p0/m, #3.87500000
 // CHECK-INST: fmov z0.d, p0/m, #3.87500000
 // CHECK-ENCODING: [0xe0,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c1e0 <unknown>
 
 fcpy z0.d, p0/m, #4.00000000
 // CHECK-INST: fmov z0.d, p0/m, #4.00000000
 // CHECK-ENCODING: [0x00,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c200 <unknown>
 
 fcpy z0.d, p0/m, #4.25000000
 // CHECK-INST: fmov z0.d, p0/m, #4.25000000
 // CHECK-ENCODING: [0x20,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c220 <unknown>
 
 fcpy z0.d, p0/m, #4.50000000
 // CHECK-INST: fmov z0.d, p0/m, #4.50000000
 // CHECK-ENCODING: [0x40,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c240 <unknown>
 
 fcpy z0.d, p0/m, #4.75000000
 // CHECK-INST: fmov z0.d, p0/m, #4.75000000
 // CHECK-ENCODING: [0x60,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c260 <unknown>
 
 fcpy z0.d, p0/m, #5.00000000
 // CHECK-INST: fmov z0.d, p0/m, #5.00000000
 // CHECK-ENCODING: [0x80,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c280 <unknown>
 
 fcpy z0.d, p0/m, #5.25000000
 // CHECK-INST: fmov z0.d, p0/m, #5.25000000
 // CHECK-ENCODING: [0xa0,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c2a0 <unknown>
 
 fcpy z0.d, p0/m, #5.50000000
 // CHECK-INST: fmov z0.d, p0/m, #5.50000000
 // CHECK-ENCODING: [0xc0,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c2c0 <unknown>
 
 fcpy z0.d, p0/m, #5.75000000
 // CHECK-INST: fmov z0.d, p0/m, #5.75000000
 // CHECK-ENCODING: [0xe0,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c2e0 <unknown>
 
 fcpy z0.d, p0/m, #6.00000000
 // CHECK-INST: fmov z0.d, p0/m, #6.00000000
 // CHECK-ENCODING: [0x00,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c300 <unknown>
 
 fcpy z0.d, p0/m, #6.25000000
 // CHECK-INST: fmov z0.d, p0/m, #6.25000000
 // CHECK-ENCODING: [0x20,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c320 <unknown>
 
 fcpy z0.d, p0/m, #6.50000000
 // CHECK-INST: fmov z0.d, p0/m, #6.50000000
 // CHECK-ENCODING: [0x40,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c340 <unknown>
 
 fcpy z0.d, p0/m, #6.75000000
 // CHECK-INST: fmov z0.d, p0/m, #6.75000000
 // CHECK-ENCODING: [0x60,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c360 <unknown>
 
 fcpy z0.d, p0/m, #7.00000000
 // CHECK-INST: fmov z0.d, p0/m, #7.00000000
 // CHECK-ENCODING: [0x80,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c380 <unknown>
 
 fcpy z0.d, p0/m, #7.25000000
 // CHECK-INST: fmov z0.d, p0/m, #7.25000000
 // CHECK-ENCODING: [0xa0,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c3a0 <unknown>
 
 fcpy z0.d, p0/m, #7.50000000
 // CHECK-INST: fmov z0.d, p0/m, #7.50000000
 // CHECK-ENCODING: [0xc0,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c3c0 <unknown>
 
 fcpy z0.d, p0/m, #7.75000000
 // CHECK-INST: fmov z0.d, p0/m, #7.75000000
 // CHECK-ENCODING: [0xe0,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c3e0 <unknown>
 
 fcpy z0.d, p0/m, #8.00000000
 // CHECK-INST: fmov z0.d, p0/m, #8.00000000
 // CHECK-ENCODING: [0x00,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c400 <unknown>
 
 fcpy z0.d, p0/m, #8.50000000
 // CHECK-INST: fmov z0.d, p0/m, #8.50000000
 // CHECK-ENCODING: [0x20,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c420 <unknown>
 
 fcpy z0.d, p0/m, #9.00000000
 // CHECK-INST: fmov z0.d, p0/m, #9.00000000
 // CHECK-ENCODING: [0x40,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c440 <unknown>
 
 fcpy z0.d, p0/m, #9.50000000
 // CHECK-INST: fmov z0.d, p0/m, #9.50000000
 // CHECK-ENCODING: [0x60,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c460 <unknown>
 
 fcpy z0.d, p0/m, #10.00000000
 // CHECK-INST: fmov z0.d, p0/m, #10.00000000
 // CHECK-ENCODING: [0x80,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c480 <unknown>
 
 fcpy z0.d, p0/m, #10.50000000
 // CHECK-INST: fmov z0.d, p0/m, #10.50000000
 // CHECK-ENCODING: [0xa0,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c4a0 <unknown>
 
 fcpy z0.d, p0/m, #11.00000000
 // CHECK-INST: fmov z0.d, p0/m, #11.00000000
 // CHECK-ENCODING: [0xc0,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c4c0 <unknown>
 
 fcpy z0.d, p0/m, #11.50000000
 // CHECK-INST: fmov z0.d, p0/m, #11.50000000
 // CHECK-ENCODING: [0xe0,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c4e0 <unknown>
 
 fcpy z0.d, p0/m, #12.00000000
 // CHECK-INST: fmov z0.d, p0/m, #12.00000000
 // CHECK-ENCODING: [0x00,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c500 <unknown>
 
 fcpy z0.d, p0/m, #12.50000000
 // CHECK-INST: fmov z0.d, p0/m, #12.50000000
 // CHECK-ENCODING: [0x20,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c520 <unknown>
 
 fcpy z0.d, p0/m, #13.00000000
 // CHECK-INST: fmov z0.d, p0/m, #13.00000000
 // CHECK-ENCODING: [0x40,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c540 <unknown>
 
 fcpy z0.d, p0/m, #13.50000000
 // CHECK-INST: fmov z0.d, p0/m, #13.50000000
 // CHECK-ENCODING: [0x60,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c560 <unknown>
 
 fcpy z0.d, p0/m, #14.00000000
 // CHECK-INST: fmov z0.d, p0/m, #14.00000000
 // CHECK-ENCODING: [0x80,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c580 <unknown>
 
 fcpy z0.d, p0/m, #14.50000000
 // CHECK-INST: fmov z0.d, p0/m, #14.50000000
 // CHECK-ENCODING: [0xa0,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c5a0 <unknown>
 
 fcpy z0.d, p0/m, #15.00000000
 // CHECK-INST: fmov z0.d, p0/m, #15.00000000
 // CHECK-ENCODING: [0xc0,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c5c0 <unknown>
 
 fcpy z0.d, p0/m, #15.50000000
 // CHECK-INST: fmov z0.d, p0/m, #15.50000000
 // CHECK-ENCODING: [0xe0,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c5e0 <unknown>
 
 fcpy z0.d, p0/m, #16.00000000
 // CHECK-INST: fmov z0.d, p0/m, #16.00000000
 // CHECK-ENCODING: [0x00,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c600 <unknown>
 
 fcpy z0.d, p0/m, #17.00000000
 // CHECK-INST: fmov z0.d, p0/m, #17.00000000
 // CHECK-ENCODING: [0x20,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c620 <unknown>
 
 fcpy z0.d, p0/m, #18.00000000
 // CHECK-INST: fmov z0.d, p0/m, #18.00000000
 // CHECK-ENCODING: [0x40,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c640 <unknown>
 
 fcpy z0.d, p0/m, #19.00000000
 // CHECK-INST: fmov z0.d, p0/m, #19.00000000
 // CHECK-ENCODING: [0x60,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c660 <unknown>
 
 fcpy z0.d, p0/m, #20.00000000
 // CHECK-INST: fmov z0.d, p0/m, #20.00000000
 // CHECK-ENCODING: [0x80,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c680 <unknown>
 
 fcpy z0.d, p0/m, #21.00000000
 // CHECK-INST: fmov z0.d, p0/m, #21.00000000
 // CHECK-ENCODING: [0xa0,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c6a0 <unknown>
 
 fcpy z0.d, p0/m, #22.00000000
 // CHECK-INST: fmov z0.d, p0/m, #22.00000000
 // CHECK-ENCODING: [0xc0,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c6c0 <unknown>
 
 fcpy z0.d, p0/m, #23.00000000
 // CHECK-INST: fmov z0.d, p0/m, #23.00000000
 // CHECK-ENCODING: [0xe0,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c6e0 <unknown>
 
 fcpy z0.d, p0/m, #24.00000000
 // CHECK-INST: fmov z0.d, p0/m, #24.00000000
 // CHECK-ENCODING: [0x00,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c700 <unknown>
 
 fcpy z0.d, p0/m, #25.00000000
 // CHECK-INST: fmov z0.d, p0/m, #25.00000000
 // CHECK-ENCODING: [0x20,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c720 <unknown>
 
 fcpy z0.d, p0/m, #26.00000000
 // CHECK-INST: fmov z0.d, p0/m, #26.00000000
 // CHECK-ENCODING: [0x40,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c740 <unknown>
 
 fcpy z0.d, p0/m, #27.00000000
 // CHECK-INST: fmov z0.d, p0/m, #27.00000000
 // CHECK-ENCODING: [0x60,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c760 <unknown>
 
 fcpy z0.d, p0/m, #28.00000000
 // CHECK-INST: fmov z0.d, p0/m, #28.00000000
 // CHECK-ENCODING: [0x80,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c780 <unknown>
 
 fcpy z0.d, p0/m, #29.00000000
 // CHECK-INST: fmov z0.d, p0/m, #29.00000000
 // CHECK-ENCODING: [0xa0,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c7a0 <unknown>
 
 fcpy z0.d, p0/m, #30.00000000
 // CHECK-INST: fmov z0.d, p0/m, #30.00000000
 // CHECK-ENCODING: [0xc0,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c7c0 <unknown>
 
 fcpy z0.d, p0/m, #31.00000000
 // CHECK-INST: fmov z0.d, p0/m, #31.00000000
 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c7e0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -1565,22 +1565,22 @@ movprfx z0.d, p0/z, z7.d
 // CHECK-INST: movprfx	z0.d, p0/z, z7.d
 // CHECK-ENCODING: [0xe0,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020e0 <unknown>
 
 fcpy z0.d, p0/m, #31.00000000
 // CHECK-INST: fmov	z0.d, p0/m, #31.00000000
 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c7e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fcpy z0.d, p0/m, #31.00000000
 // CHECK-INST: fmov	z0.d, p0/m, #31.00000000
 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c7e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fcvt.s b/llvm/test/MC/AArch64/SVE/fcvt.s
index 191d33d72fa20..07d6d48a49092 100644
--- a/llvm/test/MC/AArch64/SVE/fcvt.s
+++ b/llvm/test/MC/AArch64/SVE/fcvt.s
@@ -13,37 +13,37 @@ fcvt    z0.h, p0/m, z0.s
 // CHECK-INST: fcvt    z0.h, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x88,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 88 65 <unknown>
+// CHECK-UNKNOWN: 6588a000 <unknown>
 
 fcvt    z0.h, p0/m, z0.d
 // CHECK-INST: fcvt    z0.h, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xc8,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 c8 65 <unknown>
+// CHECK-UNKNOWN: 65c8a000 <unknown>
 
 fcvt    z0.s, p0/m, z0.h
 // CHECK-INST: fcvt    z0.s, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x89,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 89 65 <unknown>
+// CHECK-UNKNOWN: 6589a000 <unknown>
 
 fcvt    z0.s, p0/m, z0.d
 // CHECK-INST: fcvt    z0.s, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xca,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 ca 65 <unknown>
+// CHECK-UNKNOWN: 65caa000 <unknown>
 
 fcvt    z0.d, p0/m, z0.h
 // CHECK-INST: fcvt    z0.d, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0xc9,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 c9 65 <unknown>
+// CHECK-UNKNOWN: 65c9a000 <unknown>
 
 fcvt    z0.d, p0/m, z0.s
 // CHECK-INST: fcvt    z0.d, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0xcb,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 cb 65 <unknown>
+// CHECK-UNKNOWN: 65cba000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -53,22 +53,22 @@ movprfx z5.d, p0/z, z7.d
 // CHECK-INST: movprfx	z5.d, p0/z, z7.d
 // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020e5 <unknown>
 
 fcvt    z5.d, p0/m, z0.s
 // CHECK-INST: fcvt	z5.d, p0/m, z0.s
 // CHECK-ENCODING: [0x05,0xa0,0xcb,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 a0 cb 65 <unknown>
+// CHECK-UNKNOWN: 65cba005 <unknown>
 
 movprfx z5, z7
 // CHECK-INST: movprfx	z5, z7
 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce5 <unknown>
 
 fcvt    z5.d, p0/m, z0.s
 // CHECK-INST: fcvt	z5.d, p0/m, z0.s
 // CHECK-ENCODING: [0x05,0xa0,0xcb,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 a0 cb 65 <unknown>
+// CHECK-UNKNOWN: 65cba005 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fcvtzs.s b/llvm/test/MC/AArch64/SVE/fcvtzs.s
index ce95266730f89..18f01dc062623 100644
--- a/llvm/test/MC/AArch64/SVE/fcvtzs.s
+++ b/llvm/test/MC/AArch64/SVE/fcvtzs.s
@@ -13,43 +13,43 @@ fcvtzs  z0.h, p0/m, z0.h
 // CHECK-INST: fcvtzs  z0.h, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x5a,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 5a 65 <unknown>
+// CHECK-UNKNOWN: 655aa000 <unknown>
 
 fcvtzs  z0.s, p0/m, z0.h
 // CHECK-INST: fcvtzs  z0.s, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x5c,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 5c 65 <unknown>
+// CHECK-UNKNOWN: 655ca000 <unknown>
 
 fcvtzs  z0.s, p0/m, z0.s
 // CHECK-INST: fcvtzs  z0.s, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x9c,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 9c 65 <unknown>
+// CHECK-UNKNOWN: 659ca000 <unknown>
 
 fcvtzs  z0.s, p0/m, z0.d
 // CHECK-INST: fcvtzs  z0.s, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd8,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d8 65 <unknown>
+// CHECK-UNKNOWN: 65d8a000 <unknown>
 
 fcvtzs  z0.d, p0/m, z0.h
 // CHECK-INST: fcvtzs  z0.d, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x5e,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 5e 65 <unknown>
+// CHECK-UNKNOWN: 655ea000 <unknown>
 
 fcvtzs  z0.d, p0/m, z0.s
 // CHECK-INST: fcvtzs  z0.d, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0xdc,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 dc 65 <unknown>
+// CHECK-UNKNOWN: 65dca000 <unknown>
 
 fcvtzs  z0.d, p0/m, z0.d
 // CHECK-INST: fcvtzs  z0.d, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xde,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 de 65 <unknown>
+// CHECK-UNKNOWN: 65dea000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -59,22 +59,22 @@ movprfx z5.d, p0/z, z7.d
 // CHECK-INST: movprfx	z5.d, p0/z, z7.d
 // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020e5 <unknown>
 
 fcvtzs  z5.d, p0/m, z0.d
 // CHECK-INST: fcvtzs	z5.d, p0/m, z0.d
 // CHECK-ENCODING: [0x05,0xa0,0xde,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 a0 de 65 <unknown>
+// CHECK-UNKNOWN: 65dea005 <unknown>
 
 movprfx z5, z7
 // CHECK-INST: movprfx	z5, z7
 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce5 <unknown>
 
 fcvtzs  z5.d, p0/m, z0.d
 // CHECK-INST: fcvtzs	z5.d, p0/m, z0.d
 // CHECK-ENCODING: [0x05,0xa0,0xde,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 a0 de 65 <unknown>
+// CHECK-UNKNOWN: 65dea005 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fcvtzu.s b/llvm/test/MC/AArch64/SVE/fcvtzu.s
index 1b8f0dfbca806..80031ed7c3730 100644
--- a/llvm/test/MC/AArch64/SVE/fcvtzu.s
+++ b/llvm/test/MC/AArch64/SVE/fcvtzu.s
@@ -13,43 +13,43 @@ fcvtzu  z0.h, p0/m, z0.h
 // CHECK-INST: fcvtzu  z0.h, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x5b,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 5b 65 <unknown>
+// CHECK-UNKNOWN: 655ba000 <unknown>
 
 fcvtzu  z0.s, p0/m, z0.h
 // CHECK-INST: fcvtzu  z0.s, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x5d,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 5d 65 <unknown>
+// CHECK-UNKNOWN: 655da000 <unknown>
 
 fcvtzu  z0.s, p0/m, z0.s
 // CHECK-INST: fcvtzu  z0.s, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x9d,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 9d 65 <unknown>
+// CHECK-UNKNOWN: 659da000 <unknown>
 
 fcvtzu  z0.s, p0/m, z0.d
 // CHECK-INST: fcvtzu  z0.s, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd9,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d9 65 <unknown>
+// CHECK-UNKNOWN: 65d9a000 <unknown>
 
 fcvtzu  z0.d, p0/m, z0.h
 // CHECK-INST: fcvtzu  z0.d, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x5f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 5f 65 <unknown>
+// CHECK-UNKNOWN: 655fa000 <unknown>
 
 fcvtzu  z0.d, p0/m, z0.s
 // CHECK-INST: fcvtzu  z0.d, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0xdd,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 dd 65 <unknown>
+// CHECK-UNKNOWN: 65dda000 <unknown>
 
 fcvtzu  z0.d, p0/m, z0.d
 // CHECK-INST: fcvtzu  z0.d, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xdf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 df 65 <unknown>
+// CHECK-UNKNOWN: 65dfa000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -59,22 +59,22 @@ movprfx z5.d, p0/z, z7.d
 // CHECK-INST: movprfx	z5.d, p0/z, z7.d
 // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020e5 <unknown>
 
 fcvtzu  z5.d, p0/m, z0.d
 // CHECK-INST: fcvtzu	z5.d, p0/m, z0.d
 // CHECK-ENCODING: [0x05,0xa0,0xdf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 a0 df 65 <unknown>
+// CHECK-UNKNOWN: 65dfa005 <unknown>
 
 movprfx z5, z7
 // CHECK-INST: movprfx	z5, z7
 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce5 <unknown>
 
 fcvtzu  z5.d, p0/m, z0.d
 // CHECK-INST: fcvtzu	z5.d, p0/m, z0.d
 // CHECK-ENCODING: [0x05,0xa0,0xdf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 a0 df 65 <unknown>
+// CHECK-UNKNOWN: 65dfa005 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fdiv.s b/llvm/test/MC/AArch64/SVE/fdiv.s
index 8ca4ad6800a7f..4ac0e27918c32 100644
--- a/llvm/test/MC/AArch64/SVE/fdiv.s
+++ b/llvm/test/MC/AArch64/SVE/fdiv.s
@@ -13,19 +13,19 @@ fdiv    z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: fdiv	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x4d,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 4d 65 <unknown>
+// CHECK-UNKNOWN: 654d9fe0 <unknown>
 
 fdiv    z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: fdiv	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0x8d,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 8d 65 <unknown>
+// CHECK-UNKNOWN: 658d9fe0 <unknown>
 
 fdiv    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fdiv	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f cd 65 <unknown>
+// CHECK-UNKNOWN: 65cd9fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fdiv    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fdiv	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f cd 65 <unknown>
+// CHECK-UNKNOWN: 65cd9fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fdiv    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fdiv	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xcd,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f cd 65 <unknown>
+// CHECK-UNKNOWN: 65cd9fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fdivr.s b/llvm/test/MC/AArch64/SVE/fdivr.s
index 6c565857b78da..3d9969b980f69 100644
--- a/llvm/test/MC/AArch64/SVE/fdivr.s
+++ b/llvm/test/MC/AArch64/SVE/fdivr.s
@@ -13,19 +13,19 @@ fdivr   z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: fdivr	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x4c,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 4c 65 <unknown>
+// CHECK-UNKNOWN: 654c9fe0 <unknown>
 
 fdivr   z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: fdivr	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0x8c,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 8c 65 <unknown>
+// CHECK-UNKNOWN: 658c9fe0 <unknown>
 
 fdivr   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fdivr	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f cc 65 <unknown>
+// CHECK-UNKNOWN: 65cc9fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fdivr   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fdivr	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f cc 65 <unknown>
+// CHECK-UNKNOWN: 65cc9fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fdivr   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fdivr	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xcc,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f cc 65 <unknown>
+// CHECK-UNKNOWN: 65cc9fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fdup.s b/llvm/test/MC/AArch64/SVE/fdup.s
index 2909d9273ecf3..0f55f6ca0f33f 100644
--- a/llvm/test/MC/AArch64/SVE/fdup.s
+++ b/llvm/test/MC/AArch64/SVE/fdup.s
@@ -13,1546 +13,1546 @@ fdup z0.h, #-0.12500000
 // CHECK-INST: fmov z0.h, #-0.12500000
 // CHECK-ENCODING: [0x00,0xd8,0x79,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d8 79 25 <unknown>
+// CHECK-UNKNOWN: 2579d800 <unknown>
 
 fdup z0.s, #-0.12500000
 // CHECK-INST: fmov z0.s, #-0.12500000
 // CHECK-ENCODING: [0x00,0xd8,0xb9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d8 b9 25 <unknown>
+// CHECK-UNKNOWN: 25b9d800 <unknown>
 
 fdup z0.d, #-0.12500000
 // CHECK-INST: fmov z0.d, #-0.12500000
 // CHECK-ENCODING: [0x00,0xd8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d800 <unknown>
 
 fdup z0.d, #-0.13281250
 // CHECK-INST: fmov z0.d, #-0.13281250
 // CHECK-ENCODING: [0x20,0xd8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d820 <unknown>
 
 fdup z0.d, #-0.14062500
 // CHECK-INST: fmov z0.d, #-0.14062500
 // CHECK-ENCODING: [0x40,0xd8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d840 <unknown>
 
 fdup z0.d, #-0.14843750
 // CHECK-INST: fmov z0.d, #-0.14843750
 // CHECK-ENCODING: [0x60,0xd8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d860 <unknown>
 
 fdup z0.d, #-0.15625000
 // CHECK-INST: fmov z0.d, #-0.15625000
 // CHECK-ENCODING: [0x80,0xd8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d880 <unknown>
 
 fdup z0.d, #-0.16406250
 // CHECK-INST: fmov z0.d, #-0.16406250
 // CHECK-ENCODING: [0xa0,0xd8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d8a0 <unknown>
 
 fdup z0.d, #-0.17187500
 // CHECK-INST: fmov z0.d, #-0.17187500
 // CHECK-ENCODING: [0xc0,0xd8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d8c0 <unknown>
 
 fdup z0.d, #-0.17968750
 // CHECK-INST: fmov z0.d, #-0.17968750
 // CHECK-ENCODING: [0xe0,0xd8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d8e0 <unknown>
 
 fdup z0.d, #-0.18750000
 // CHECK-INST: fmov z0.d, #-0.18750000
 // CHECK-ENCODING: [0x00,0xd9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d900 <unknown>
 
 fdup z0.d, #-0.19531250
 // CHECK-INST: fmov z0.d, #-0.19531250
 // CHECK-ENCODING: [0x20,0xd9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d920 <unknown>
 
 fdup z0.d, #-0.20312500
 // CHECK-INST: fmov z0.d, #-0.20312500
 // CHECK-ENCODING: [0x40,0xd9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d940 <unknown>
 
 fdup z0.d, #-0.21093750
 // CHECK-INST: fmov z0.d, #-0.21093750
 // CHECK-ENCODING: [0x60,0xd9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d960 <unknown>
 
 fdup z0.d, #-0.21875000
 // CHECK-INST: fmov z0.d, #-0.21875000
 // CHECK-ENCODING: [0x80,0xd9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d980 <unknown>
 
 fdup z0.d, #-0.22656250
 // CHECK-INST: fmov z0.d, #-0.22656250
 // CHECK-ENCODING: [0xa0,0xd9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d9a0 <unknown>
 
 fdup z0.d, #-0.23437500
 // CHECK-INST: fmov z0.d, #-0.23437500
 // CHECK-ENCODING: [0xc0,0xd9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d9c0 <unknown>
 
 fdup z0.d, #-0.24218750
 // CHECK-INST: fmov z0.d, #-0.24218750
 // CHECK-ENCODING: [0xe0,0xd9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d9e0 <unknown>
 
 fdup z0.d, #-0.25000000
 // CHECK-INST: fmov z0.d, #-0.25000000
 // CHECK-ENCODING: [0x00,0xda,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 da f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9da00 <unknown>
 
 fdup z0.d, #-0.26562500
 // CHECK-INST: fmov z0.d, #-0.26562500
 // CHECK-ENCODING: [0x20,0xda,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 da f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9da20 <unknown>
 
 fdup z0.d, #-0.28125000
 // CHECK-INST: fmov z0.d, #-0.28125000
 // CHECK-ENCODING: [0x40,0xda,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 da f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9da40 <unknown>
 
 fdup z0.d, #-0.29687500
 // CHECK-INST: fmov z0.d, #-0.29687500
 // CHECK-ENCODING: [0x60,0xda,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 da f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9da60 <unknown>
 
 fdup z0.d, #-0.31250000
 // CHECK-INST: fmov z0.d, #-0.31250000
 // CHECK-ENCODING: [0x80,0xda,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 da f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9da80 <unknown>
 
 fdup z0.d, #-0.32812500
 // CHECK-INST: fmov z0.d, #-0.32812500
 // CHECK-ENCODING: [0xa0,0xda,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 da f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9daa0 <unknown>
 
 fdup z0.d, #-0.34375000
 // CHECK-INST: fmov z0.d, #-0.34375000
 // CHECK-ENCODING: [0xc0,0xda,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 da f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dac0 <unknown>
 
 fdup z0.d, #-0.35937500
 // CHECK-INST: fmov z0.d, #-0.35937500
 // CHECK-ENCODING: [0xe0,0xda,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 da f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dae0 <unknown>
 
 fdup z0.d, #-0.37500000
 // CHECK-INST: fmov z0.d, #-0.37500000
 // CHECK-ENCODING: [0x00,0xdb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 db f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9db00 <unknown>
 
 fdup z0.d, #-0.39062500
 // CHECK-INST: fmov z0.d, #-0.39062500
 // CHECK-ENCODING: [0x20,0xdb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 db f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9db20 <unknown>
 
 fdup z0.d, #-0.40625000
 // CHECK-INST: fmov z0.d, #-0.40625000
 // CHECK-ENCODING: [0x40,0xdb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 db f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9db40 <unknown>
 
 fdup z0.d, #-0.42187500
 // CHECK-INST: fmov z0.d, #-0.42187500
 // CHECK-ENCODING: [0x60,0xdb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 db f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9db60 <unknown>
 
 fdup z0.d, #-0.43750000
 // CHECK-INST: fmov z0.d, #-0.43750000
 // CHECK-ENCODING: [0x80,0xdb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 db f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9db80 <unknown>
 
 fdup z0.d, #-0.45312500
 // CHECK-INST: fmov z0.d, #-0.45312500
 // CHECK-ENCODING: [0xa0,0xdb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 db f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dba0 <unknown>
 
 fdup z0.d, #-0.46875000
 // CHECK-INST: fmov z0.d, #-0.46875000
 // CHECK-ENCODING: [0xc0,0xdb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 db f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dbc0 <unknown>
 
 fdup z0.d, #-0.48437500
 // CHECK-INST: fmov z0.d, #-0.48437500
 // CHECK-ENCODING: [0xe0,0xdb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 db f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dbe0 <unknown>
 
 fdup z0.d, #-0.50000000
 // CHECK-INST: fmov z0.d, #-0.50000000
 // CHECK-ENCODING: [0x00,0xdc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 dc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dc00 <unknown>
 
 fdup z0.d, #-0.53125000
 // CHECK-INST: fmov z0.d, #-0.53125000
 // CHECK-ENCODING: [0x20,0xdc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 dc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dc20 <unknown>
 
 fdup z0.d, #-0.56250000
 // CHECK-INST: fmov z0.d, #-0.56250000
 // CHECK-ENCODING: [0x40,0xdc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 dc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dc40 <unknown>
 
 fdup z0.d, #-0.59375000
 // CHECK-INST: fmov z0.d, #-0.59375000
 // CHECK-ENCODING: [0x60,0xdc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 dc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dc60 <unknown>
 
 fdup z0.d, #-0.62500000
 // CHECK-INST: fmov z0.d, #-0.62500000
 // CHECK-ENCODING: [0x80,0xdc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 dc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dc80 <unknown>
 
 fdup z0.d, #-0.65625000
 // CHECK-INST: fmov z0.d, #-0.65625000
 // CHECK-ENCODING: [0xa0,0xdc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 dc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dca0 <unknown>
 
 fdup z0.d, #-0.68750000
 // CHECK-INST: fmov z0.d, #-0.68750000
 // CHECK-ENCODING: [0xc0,0xdc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 dc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dcc0 <unknown>
 
 fdup z0.d, #-0.71875000
 // CHECK-INST: fmov z0.d, #-0.71875000
 // CHECK-ENCODING: [0xe0,0xdc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 dc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dce0 <unknown>
 
 fdup z0.d, #-0.75000000
 // CHECK-INST: fmov z0.d, #-0.75000000
 // CHECK-ENCODING: [0x00,0xdd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 dd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dd00 <unknown>
 
 fdup z0.d, #-0.78125000
 // CHECK-INST: fmov z0.d, #-0.78125000
 // CHECK-ENCODING: [0x20,0xdd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 dd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dd20 <unknown>
 
 fdup z0.d, #-0.81250000
 // CHECK-INST: fmov z0.d, #-0.81250000
 // CHECK-ENCODING: [0x40,0xdd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 dd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dd40 <unknown>
 
 fdup z0.d, #-0.84375000
 // CHECK-INST: fmov z0.d, #-0.84375000
 // CHECK-ENCODING: [0x60,0xdd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 dd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dd60 <unknown>
 
 fdup z0.d, #-0.87500000
 // CHECK-INST: fmov z0.d, #-0.87500000
 // CHECK-ENCODING: [0x80,0xdd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 dd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dd80 <unknown>
 
 fdup z0.d, #-0.90625000
 // CHECK-INST: fmov z0.d, #-0.90625000
 // CHECK-ENCODING: [0xa0,0xdd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 dd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dda0 <unknown>
 
 fdup z0.d, #-0.93750000
 // CHECK-INST: fmov z0.d, #-0.93750000
 // CHECK-ENCODING: [0xc0,0xdd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 dd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9ddc0 <unknown>
 
 fdup z0.d, #-0.96875000
 // CHECK-INST: fmov z0.d, #-0.96875000
 // CHECK-ENCODING: [0xe0,0xdd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 dd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dde0 <unknown>
 
 fdup z0.d, #-1.00000000
 // CHECK-INST: fmov z0.d, #-1.00000000
 // CHECK-ENCODING: [0x00,0xde,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 de f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9de00 <unknown>
 
 fdup z0.d, #-1.06250000
 // CHECK-INST: fmov z0.d, #-1.06250000
 // CHECK-ENCODING: [0x20,0xde,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 de f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9de20 <unknown>
 
 fdup z0.d, #-1.12500000
 // CHECK-INST: fmov z0.d, #-1.12500000
 // CHECK-ENCODING: [0x40,0xde,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 de f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9de40 <unknown>
 
 fdup z0.d, #-1.18750000
 // CHECK-INST: fmov z0.d, #-1.18750000
 // CHECK-ENCODING: [0x60,0xde,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 de f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9de60 <unknown>
 
 fdup z0.d, #-1.25000000
 // CHECK-INST: fmov z0.d, #-1.25000000
 // CHECK-ENCODING: [0x80,0xde,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 de f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9de80 <unknown>
 
 fdup z0.d, #-1.31250000
 // CHECK-INST: fmov z0.d, #-1.31250000
 // CHECK-ENCODING: [0xa0,0xde,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 de f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dea0 <unknown>
 
 fdup z0.d, #-1.37500000
 // CHECK-INST: fmov z0.d, #-1.37500000
 // CHECK-ENCODING: [0xc0,0xde,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 de f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dec0 <unknown>
 
 fdup z0.d, #-1.43750000
 // CHECK-INST: fmov z0.d, #-1.43750000
 // CHECK-ENCODING: [0xe0,0xde,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 de f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dee0 <unknown>
 
 fdup z0.d, #-1.50000000
 // CHECK-INST: fmov z0.d, #-1.50000000
 // CHECK-ENCODING: [0x00,0xdf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 df f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9df00 <unknown>
 
 fdup z0.d, #-1.56250000
 // CHECK-INST: fmov z0.d, #-1.56250000
 // CHECK-ENCODING: [0x20,0xdf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 df f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9df20 <unknown>
 
 fdup z0.d, #-1.62500000
 // CHECK-INST: fmov z0.d, #-1.62500000
 // CHECK-ENCODING: [0x40,0xdf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 df f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9df40 <unknown>
 
 fdup z0.d, #-1.68750000
 // CHECK-INST: fmov z0.d, #-1.68750000
 // CHECK-ENCODING: [0x60,0xdf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 df f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9df60 <unknown>
 
 fdup z0.d, #-1.75000000
 // CHECK-INST: fmov z0.d, #-1.75000000
 // CHECK-ENCODING: [0x80,0xdf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 df f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9df80 <unknown>
 
 fdup z0.d, #-1.81250000
 // CHECK-INST: fmov z0.d, #-1.81250000
 // CHECK-ENCODING: [0xa0,0xdf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 df f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dfa0 <unknown>
 
 fdup z0.d, #-1.87500000
 // CHECK-INST: fmov z0.d, #-1.87500000
 // CHECK-ENCODING: [0xc0,0xdf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 df f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dfc0 <unknown>
 
 fdup z0.d, #-1.93750000
 // CHECK-INST: fmov z0.d, #-1.93750000
 // CHECK-ENCODING: [0xe0,0xdf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 df f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9dfe0 <unknown>
 
 fdup z0.d, #-2.00000000
 // CHECK-INST: fmov z0.d, #-2.00000000
 // CHECK-ENCODING: [0x00,0xd0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d000 <unknown>
 
 fdup z0.d, #-2.12500000
 // CHECK-INST: fmov z0.d, #-2.12500000
 // CHECK-ENCODING: [0x20,0xd0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d020 <unknown>
 
 fdup z0.d, #-2.25000000
 // CHECK-INST: fmov z0.d, #-2.25000000
 // CHECK-ENCODING: [0x40,0xd0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d040 <unknown>
 
 fdup z0.d, #-2.37500000
 // CHECK-INST: fmov z0.d, #-2.37500000
 // CHECK-ENCODING: [0x60,0xd0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d060 <unknown>
 
 fdup z0.d, #-2.50000000
 // CHECK-INST: fmov z0.d, #-2.50000000
 // CHECK-ENCODING: [0x80,0xd0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d080 <unknown>
 
 fdup z0.d, #-2.62500000
 // CHECK-INST: fmov z0.d, #-2.62500000
 // CHECK-ENCODING: [0xa0,0xd0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d0a0 <unknown>
 
 fdup z0.d, #-2.75000000
 // CHECK-INST: fmov z0.d, #-2.75000000
 // CHECK-ENCODING: [0xc0,0xd0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d0c0 <unknown>
 
 fdup z0.d, #-2.87500000
 // CHECK-INST: fmov z0.d, #-2.87500000
 // CHECK-ENCODING: [0xe0,0xd0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d0e0 <unknown>
 
 fdup z0.d, #-3.00000000
 // CHECK-INST: fmov z0.d, #-3.00000000
 // CHECK-ENCODING: [0x00,0xd1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d100 <unknown>
 
 fdup z0.d, #-3.12500000
 // CHECK-INST: fmov z0.d, #-3.12500000
 // CHECK-ENCODING: [0x20,0xd1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d120 <unknown>
 
 fdup z0.d, #-3.25000000
 // CHECK-INST: fmov z0.d, #-3.25000000
 // CHECK-ENCODING: [0x40,0xd1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d140 <unknown>
 
 fdup z0.d, #-3.37500000
 // CHECK-INST: fmov z0.d, #-3.37500000
 // CHECK-ENCODING: [0x60,0xd1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d160 <unknown>
 
 fdup z0.d, #-3.50000000
 // CHECK-INST: fmov z0.d, #-3.50000000
 // CHECK-ENCODING: [0x80,0xd1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d180 <unknown>
 
 fdup z0.d, #-3.62500000
 // CHECK-INST: fmov z0.d, #-3.62500000
 // CHECK-ENCODING: [0xa0,0xd1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d1a0 <unknown>
 
 fdup z0.d, #-3.75000000
 // CHECK-INST: fmov z0.d, #-3.75000000
 // CHECK-ENCODING: [0xc0,0xd1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d1c0 <unknown>
 
 fdup z0.d, #-3.87500000
 // CHECK-INST: fmov z0.d, #-3.87500000
 // CHECK-ENCODING: [0xe0,0xd1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d1e0 <unknown>
 
 fdup z0.d, #-4.00000000
 // CHECK-INST: fmov z0.d, #-4.00000000
 // CHECK-ENCODING: [0x00,0xd2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d200 <unknown>
 
 fdup z0.d, #-4.25000000
 // CHECK-INST: fmov z0.d, #-4.25000000
 // CHECK-ENCODING: [0x20,0xd2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d220 <unknown>
 
 fdup z0.d, #-4.50000000
 // CHECK-INST: fmov z0.d, #-4.50000000
 // CHECK-ENCODING: [0x40,0xd2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d240 <unknown>
 
 fdup z0.d, #-4.75000000
 // CHECK-INST: fmov z0.d, #-4.75000000
 // CHECK-ENCODING: [0x60,0xd2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d260 <unknown>
 
 fdup z0.d, #-5.00000000
 // CHECK-INST: fmov z0.d, #-5.00000000
 // CHECK-ENCODING: [0x80,0xd2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d280 <unknown>
 
 fdup z0.d, #-5.25000000
 // CHECK-INST: fmov z0.d, #-5.25000000
 // CHECK-ENCODING: [0xa0,0xd2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d2a0 <unknown>
 
 fdup z0.d, #-5.50000000
 // CHECK-INST: fmov z0.d, #-5.50000000
 // CHECK-ENCODING: [0xc0,0xd2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d2c0 <unknown>
 
 fdup z0.d, #-5.75000000
 // CHECK-INST: fmov z0.d, #-5.75000000
 // CHECK-ENCODING: [0xe0,0xd2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d2e0 <unknown>
 
 fdup z0.d, #-6.00000000
 // CHECK-INST: fmov z0.d, #-6.00000000
 // CHECK-ENCODING: [0x00,0xd3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d300 <unknown>
 
 fdup z0.d, #-6.25000000
 // CHECK-INST: fmov z0.d, #-6.25000000
 // CHECK-ENCODING: [0x20,0xd3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d320 <unknown>
 
 fdup z0.d, #-6.50000000
 // CHECK-INST: fmov z0.d, #-6.50000000
 // CHECK-ENCODING: [0x40,0xd3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d340 <unknown>
 
 fdup z0.d, #-6.75000000
 // CHECK-INST: fmov z0.d, #-6.75000000
 // CHECK-ENCODING: [0x60,0xd3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d360 <unknown>
 
 fdup z0.d, #-7.00000000
 // CHECK-INST: fmov z0.d, #-7.00000000
 // CHECK-ENCODING: [0x80,0xd3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d380 <unknown>
 
 fdup z0.d, #-7.25000000
 // CHECK-INST: fmov z0.d, #-7.25000000
 // CHECK-ENCODING: [0xa0,0xd3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d3a0 <unknown>
 
 fdup z0.d, #-7.50000000
 // CHECK-INST: fmov z0.d, #-7.50000000
 // CHECK-ENCODING: [0xc0,0xd3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d3c0 <unknown>
 
 fdup z0.d, #-7.75000000
 // CHECK-INST: fmov z0.d, #-7.75000000
 // CHECK-ENCODING: [0xe0,0xd3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d3e0 <unknown>
 
 fdup z0.d, #-8.00000000
 // CHECK-INST: fmov z0.d, #-8.00000000
 // CHECK-ENCODING: [0x00,0xd4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d400 <unknown>
 
 fdup z0.d, #-8.50000000
 // CHECK-INST: fmov z0.d, #-8.50000000
 // CHECK-ENCODING: [0x20,0xd4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d420 <unknown>
 
 fdup z0.d, #-9.00000000
 // CHECK-INST: fmov z0.d, #-9.00000000
 // CHECK-ENCODING: [0x40,0xd4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d440 <unknown>
 
 fdup z0.d, #-9.50000000
 // CHECK-INST: fmov z0.d, #-9.50000000
 // CHECK-ENCODING: [0x60,0xd4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d460 <unknown>
 
 fdup z0.d, #-10.00000000
 // CHECK-INST: fmov z0.d, #-10.00000000
 // CHECK-ENCODING: [0x80,0xd4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d480 <unknown>
 
 fdup z0.d, #-10.50000000
 // CHECK-INST: fmov z0.d, #-10.50000000
 // CHECK-ENCODING: [0xa0,0xd4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d4a0 <unknown>
 
 fdup z0.d, #-11.00000000
 // CHECK-INST: fmov z0.d, #-11.00000000
 // CHECK-ENCODING: [0xc0,0xd4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d4c0 <unknown>
 
 fdup z0.d, #-11.50000000
 // CHECK-INST: fmov z0.d, #-11.50000000
 // CHECK-ENCODING: [0xe0,0xd4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d4e0 <unknown>
 
 fdup z0.d, #-12.00000000
 // CHECK-INST: fmov z0.d, #-12.00000000
 // CHECK-ENCODING: [0x00,0xd5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d500 <unknown>
 
 fdup z0.d, #-12.50000000
 // CHECK-INST: fmov z0.d, #-12.50000000
 // CHECK-ENCODING: [0x20,0xd5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d520 <unknown>
 
 fdup z0.d, #-13.00000000
 // CHECK-INST: fmov z0.d, #-13.00000000
 // CHECK-ENCODING: [0x40,0xd5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d540 <unknown>
 
 fdup z0.d, #-13.50000000
 // CHECK-INST: fmov z0.d, #-13.50000000
 // CHECK-ENCODING: [0x60,0xd5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d560 <unknown>
 
 fdup z0.d, #-14.00000000
 // CHECK-INST: fmov z0.d, #-14.00000000
 // CHECK-ENCODING: [0x80,0xd5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d580 <unknown>
 
 fdup z0.d, #-14.50000000
 // CHECK-INST: fmov z0.d, #-14.50000000
 // CHECK-ENCODING: [0xa0,0xd5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d5a0 <unknown>
 
 fdup z0.d, #-15.00000000
 // CHECK-INST: fmov z0.d, #-15.00000000
 // CHECK-ENCODING: [0xc0,0xd5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d5c0 <unknown>
 
 fdup z0.d, #-15.50000000
 // CHECK-INST: fmov z0.d, #-15.50000000
 // CHECK-ENCODING: [0xe0,0xd5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d5e0 <unknown>
 
 fdup z0.d, #-16.00000000
 // CHECK-INST: fmov z0.d, #-16.00000000
 // CHECK-ENCODING: [0x00,0xd6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d600 <unknown>
 
 fdup z0.d, #-17.00000000
 // CHECK-INST: fmov z0.d, #-17.00000000
 // CHECK-ENCODING: [0x20,0xd6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d620 <unknown>
 
 fdup z0.d, #-18.00000000
 // CHECK-INST: fmov z0.d, #-18.00000000
 // CHECK-ENCODING: [0x40,0xd6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d640 <unknown>
 
 fdup z0.d, #-19.00000000
 // CHECK-INST: fmov z0.d, #-19.00000000
 // CHECK-ENCODING: [0x60,0xd6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d660 <unknown>
 
 fdup z0.d, #-20.00000000
 // CHECK-INST: fmov z0.d, #-20.00000000
 // CHECK-ENCODING: [0x80,0xd6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d680 <unknown>
 
 fdup z0.d, #-21.00000000
 // CHECK-INST: fmov z0.d, #-21.00000000
 // CHECK-ENCODING: [0xa0,0xd6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d6a0 <unknown>
 
 fdup z0.d, #-22.00000000
 // CHECK-INST: fmov z0.d, #-22.00000000
 // CHECK-ENCODING: [0xc0,0xd6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d6c0 <unknown>
 
 fdup z0.d, #-23.00000000
 // CHECK-INST: fmov z0.d, #-23.00000000
 // CHECK-ENCODING: [0xe0,0xd6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d6e0 <unknown>
 
 fdup z0.d, #-24.00000000
 // CHECK-INST: fmov z0.d, #-24.00000000
 // CHECK-ENCODING: [0x00,0xd7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d700 <unknown>
 
 fdup z0.d, #-25.00000000
 // CHECK-INST: fmov z0.d, #-25.00000000
 // CHECK-ENCODING: [0x20,0xd7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d720 <unknown>
 
 fdup z0.d, #-26.00000000
 // CHECK-INST: fmov z0.d, #-26.00000000
 // CHECK-ENCODING: [0x40,0xd7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d740 <unknown>
 
 fdup z0.d, #-27.00000000
 // CHECK-INST: fmov z0.d, #-27.00000000
 // CHECK-ENCODING: [0x60,0xd7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d760 <unknown>
 
 fdup z0.d, #-28.00000000
 // CHECK-INST: fmov z0.d, #-28.00000000
 // CHECK-ENCODING: [0x80,0xd7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d780 <unknown>
 
 fdup z0.d, #-29.00000000
 // CHECK-INST: fmov z0.d, #-29.00000000
 // CHECK-ENCODING: [0xa0,0xd7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d7a0 <unknown>
 
 fdup z0.d, #-30.00000000
 // CHECK-INST: fmov z0.d, #-30.00000000
 // CHECK-ENCODING: [0xc0,0xd7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d7c0 <unknown>
 
 fdup z0.d, #-31.00000000
 // CHECK-INST: fmov z0.d, #-31.00000000
 // CHECK-ENCODING: [0xe0,0xd7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d7e0 <unknown>
 
 fdup z0.d, #0.12500000
 // CHECK-INST: fmov z0.d, #0.12500000
 // CHECK-ENCODING: [0x00,0xc8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c800 <unknown>
 
 fdup z0.d, #0.13281250
 // CHECK-INST: fmov z0.d, #0.13281250
 // CHECK-ENCODING: [0x20,0xc8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c820 <unknown>
 
 fdup z0.d, #0.14062500
 // CHECK-INST: fmov z0.d, #0.14062500
 // CHECK-ENCODING: [0x40,0xc8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c840 <unknown>
 
 fdup z0.d, #0.14843750
 // CHECK-INST: fmov z0.d, #0.14843750
 // CHECK-ENCODING: [0x60,0xc8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c860 <unknown>
 
 fdup z0.d, #0.15625000
 // CHECK-INST: fmov z0.d, #0.15625000
 // CHECK-ENCODING: [0x80,0xc8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c880 <unknown>
 
 fdup z0.d, #0.16406250
 // CHECK-INST: fmov z0.d, #0.16406250
 // CHECK-ENCODING: [0xa0,0xc8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c8a0 <unknown>
 
 fdup z0.d, #0.17187500
 // CHECK-INST: fmov z0.d, #0.17187500
 // CHECK-ENCODING: [0xc0,0xc8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c8c0 <unknown>
 
 fdup z0.d, #0.17968750
 // CHECK-INST: fmov z0.d, #0.17968750
 // CHECK-ENCODING: [0xe0,0xc8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c8e0 <unknown>
 
 fdup z0.d, #0.18750000
 // CHECK-INST: fmov z0.d, #0.18750000
 // CHECK-ENCODING: [0x00,0xc9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c900 <unknown>
 
 fdup z0.d, #0.19531250
 // CHECK-INST: fmov z0.d, #0.19531250
 // CHECK-ENCODING: [0x20,0xc9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c920 <unknown>
 
 fdup z0.d, #0.20312500
 // CHECK-INST: fmov z0.d, #0.20312500
 // CHECK-ENCODING: [0x40,0xc9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c940 <unknown>
 
 fdup z0.d, #0.21093750
 // CHECK-INST: fmov z0.d, #0.21093750
 // CHECK-ENCODING: [0x60,0xc9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c960 <unknown>
 
 fdup z0.d, #0.21875000
 // CHECK-INST: fmov z0.d, #0.21875000
 // CHECK-ENCODING: [0x80,0xc9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c980 <unknown>
 
 fdup z0.d, #0.22656250
 // CHECK-INST: fmov z0.d, #0.22656250
 // CHECK-ENCODING: [0xa0,0xc9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c9a0 <unknown>
 
 fdup z0.d, #0.23437500
 // CHECK-INST: fmov z0.d, #0.23437500
 // CHECK-ENCODING: [0xc0,0xc9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c9c0 <unknown>
 
 fdup z0.d, #0.24218750
 // CHECK-INST: fmov z0.d, #0.24218750
 // CHECK-ENCODING: [0xe0,0xc9,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c9 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c9e0 <unknown>
 
 fdup z0.d, #0.25000000
 // CHECK-INST: fmov z0.d, #0.25000000
 // CHECK-ENCODING: [0x00,0xca,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 ca f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9ca00 <unknown>
 
 fdup z0.d, #0.26562500
 // CHECK-INST: fmov z0.d, #0.26562500
 // CHECK-ENCODING: [0x20,0xca,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 ca f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9ca20 <unknown>
 
 fdup z0.d, #0.28125000
 // CHECK-INST: fmov z0.d, #0.28125000
 // CHECK-ENCODING: [0x40,0xca,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 ca f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9ca40 <unknown>
 
 fdup z0.d, #0.29687500
 // CHECK-INST: fmov z0.d, #0.29687500
 // CHECK-ENCODING: [0x60,0xca,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 ca f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9ca60 <unknown>
 
 fdup z0.d, #0.31250000
 // CHECK-INST: fmov z0.d, #0.31250000
 // CHECK-ENCODING: [0x80,0xca,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 ca f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9ca80 <unknown>
 
 fdup z0.d, #0.32812500
 // CHECK-INST: fmov z0.d, #0.32812500
 // CHECK-ENCODING: [0xa0,0xca,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ca f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9caa0 <unknown>
 
 fdup z0.d, #0.34375000
 // CHECK-INST: fmov z0.d, #0.34375000
 // CHECK-ENCODING: [0xc0,0xca,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 ca f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cac0 <unknown>
 
 fdup z0.d, #0.35937500
 // CHECK-INST: fmov z0.d, #0.35937500
 // CHECK-ENCODING: [0xe0,0xca,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ca f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cae0 <unknown>
 
 fdup z0.d, #0.37500000
 // CHECK-INST: fmov z0.d, #0.37500000
 // CHECK-ENCODING: [0x00,0xcb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cb f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cb00 <unknown>
 
 fdup z0.d, #0.39062500
 // CHECK-INST: fmov z0.d, #0.39062500
 // CHECK-ENCODING: [0x20,0xcb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 cb f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cb20 <unknown>
 
 fdup z0.d, #0.40625000
 // CHECK-INST: fmov z0.d, #0.40625000
 // CHECK-ENCODING: [0x40,0xcb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 cb f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cb40 <unknown>
 
 fdup z0.d, #0.42187500
 // CHECK-INST: fmov z0.d, #0.42187500
 // CHECK-ENCODING: [0x60,0xcb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 cb f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cb60 <unknown>
 
 fdup z0.d, #0.43750000
 // CHECK-INST: fmov z0.d, #0.43750000
 // CHECK-ENCODING: [0x80,0xcb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 cb f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cb80 <unknown>
 
 fdup z0.d, #0.45312500
 // CHECK-INST: fmov z0.d, #0.45312500
 // CHECK-ENCODING: [0xa0,0xcb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 cb f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cba0 <unknown>
 
 fdup z0.d, #0.46875000
 // CHECK-INST: fmov z0.d, #0.46875000
 // CHECK-ENCODING: [0xc0,0xcb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 cb f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cbc0 <unknown>
 
 fdup z0.d, #0.48437500
 // CHECK-INST: fmov z0.d, #0.48437500
 // CHECK-ENCODING: [0xe0,0xcb,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cbe0 <unknown>
 
 fdup z0.d, #0.50000000
 // CHECK-INST: fmov z0.d, #0.50000000
 // CHECK-ENCODING: [0x00,0xcc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cc00 <unknown>
 
 fdup z0.d, #0.53125000
 // CHECK-INST: fmov z0.d, #0.53125000
 // CHECK-ENCODING: [0x20,0xcc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 cc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cc20 <unknown>
 
 fdup z0.d, #0.56250000
 // CHECK-INST: fmov z0.d, #0.56250000
 // CHECK-ENCODING: [0x40,0xcc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 cc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cc40 <unknown>
 
 fdup z0.d, #0.59375000
 // CHECK-INST: fmov z0.d, #0.59375000
 // CHECK-ENCODING: [0x60,0xcc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 cc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cc60 <unknown>
 
 fdup z0.d, #0.62500000
 // CHECK-INST: fmov z0.d, #0.62500000
 // CHECK-ENCODING: [0x80,0xcc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 cc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cc80 <unknown>
 
 fdup z0.d, #0.65625000
 // CHECK-INST: fmov z0.d, #0.65625000
 // CHECK-ENCODING: [0xa0,0xcc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 cc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cca0 <unknown>
 
 fdup z0.d, #0.68750000
 // CHECK-INST: fmov z0.d, #0.68750000
 // CHECK-ENCODING: [0xc0,0xcc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 cc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9ccc0 <unknown>
 
 fdup z0.d, #0.71875000
 // CHECK-INST: fmov z0.d, #0.71875000
 // CHECK-ENCODING: [0xe0,0xcc,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cc f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cce0 <unknown>
 
 fdup z0.d, #0.75000000
 // CHECK-INST: fmov z0.d, #0.75000000
 // CHECK-ENCODING: [0x00,0xcd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cd00 <unknown>
 
 fdup z0.d, #0.78125000
 // CHECK-INST: fmov z0.d, #0.78125000
 // CHECK-ENCODING: [0x20,0xcd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 cd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cd20 <unknown>
 
 fdup z0.d, #0.81250000
 // CHECK-INST: fmov z0.d, #0.81250000
 // CHECK-ENCODING: [0x40,0xcd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 cd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cd40 <unknown>
 
 fdup z0.d, #0.84375000
 // CHECK-INST: fmov z0.d, #0.84375000
 // CHECK-ENCODING: [0x60,0xcd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 cd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cd60 <unknown>
 
 fdup z0.d, #0.87500000
 // CHECK-INST: fmov z0.d, #0.87500000
 // CHECK-ENCODING: [0x80,0xcd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 cd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cd80 <unknown>
 
 fdup z0.d, #0.90625000
 // CHECK-INST: fmov z0.d, #0.90625000
 // CHECK-ENCODING: [0xa0,0xcd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 cd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cda0 <unknown>
 
 fdup z0.d, #0.93750000
 // CHECK-INST: fmov z0.d, #0.93750000
 // CHECK-ENCODING: [0xc0,0xcd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 cd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cdc0 <unknown>
 
 fdup z0.d, #0.96875000
 // CHECK-INST: fmov z0.d, #0.96875000
 // CHECK-ENCODING: [0xe0,0xcd,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cd f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cde0 <unknown>
 
 fdup z0.d, #1.00000000
 // CHECK-INST: fmov z0.d, #1.00000000
 // CHECK-ENCODING: [0x00,0xce,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 ce f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9ce00 <unknown>
 
 fdup z0.d, #1.06250000
 // CHECK-INST: fmov z0.d, #1.06250000
 // CHECK-ENCODING: [0x20,0xce,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 ce f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9ce20 <unknown>
 
 fdup z0.d, #1.12500000
 // CHECK-INST: fmov z0.d, #1.12500000
 // CHECK-ENCODING: [0x40,0xce,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 ce f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9ce40 <unknown>
 
 fdup z0.d, #1.18750000
 // CHECK-INST: fmov z0.d, #1.18750000
 // CHECK-ENCODING: [0x60,0xce,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 ce f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9ce60 <unknown>
 
 fdup z0.d, #1.25000000
 // CHECK-INST: fmov z0.d, #1.25000000
 // CHECK-ENCODING: [0x80,0xce,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 ce f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9ce80 <unknown>
 
 fdup z0.d, #1.31250000
 // CHECK-INST: fmov z0.d, #1.31250000
 // CHECK-ENCODING: [0xa0,0xce,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ce f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cea0 <unknown>
 
 fdup z0.d, #1.37500000
 // CHECK-INST: fmov z0.d, #1.37500000
 // CHECK-ENCODING: [0xc0,0xce,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 ce f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cec0 <unknown>
 
 fdup z0.d, #1.43750000
 // CHECK-INST: fmov z0.d, #1.43750000
 // CHECK-ENCODING: [0xe0,0xce,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ce f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cee0 <unknown>
 
 fdup z0.d, #1.50000000
 // CHECK-INST: fmov z0.d, #1.50000000
 // CHECK-ENCODING: [0x00,0xcf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cf f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cf00 <unknown>
 
 fdup z0.d, #1.56250000
 // CHECK-INST: fmov z0.d, #1.56250000
 // CHECK-ENCODING: [0x20,0xcf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 cf f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cf20 <unknown>
 
 fdup z0.d, #1.62500000
 // CHECK-INST: fmov z0.d, #1.62500000
 // CHECK-ENCODING: [0x40,0xcf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 cf f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cf40 <unknown>
 
 fdup z0.d, #1.68750000
 // CHECK-INST: fmov z0.d, #1.68750000
 // CHECK-ENCODING: [0x60,0xcf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 cf f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cf60 <unknown>
 
 fdup z0.d, #1.75000000
 // CHECK-INST: fmov z0.d, #1.75000000
 // CHECK-ENCODING: [0x80,0xcf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 cf f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cf80 <unknown>
 
 fdup z0.d, #1.81250000
 // CHECK-INST: fmov z0.d, #1.81250000
 // CHECK-ENCODING: [0xa0,0xcf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 cf f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cfa0 <unknown>
 
 fdup z0.d, #1.87500000
 // CHECK-INST: fmov z0.d, #1.87500000
 // CHECK-ENCODING: [0xc0,0xcf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 cf f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cfc0 <unknown>
 
 fdup z0.d, #1.93750000
 // CHECK-INST: fmov z0.d, #1.93750000
 // CHECK-ENCODING: [0xe0,0xcf,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9cfe0 <unknown>
 
 fdup z0.d, #2.00000000
 // CHECK-INST: fmov z0.d, #2.00000000
 // CHECK-ENCODING: [0x00,0xc0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c000 <unknown>
 
 fdup z0.d, #2.12500000
 // CHECK-INST: fmov z0.d, #2.12500000
 // CHECK-ENCODING: [0x20,0xc0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c020 <unknown>
 
 fdup z0.d, #2.25000000
 // CHECK-INST: fmov z0.d, #2.25000000
 // CHECK-ENCODING: [0x40,0xc0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c040 <unknown>
 
 fdup z0.d, #2.37500000
 // CHECK-INST: fmov z0.d, #2.37500000
 // CHECK-ENCODING: [0x60,0xc0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c060 <unknown>
 
 fdup z0.d, #2.50000000
 // CHECK-INST: fmov z0.d, #2.50000000
 // CHECK-ENCODING: [0x80,0xc0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c080 <unknown>
 
 fdup z0.d, #2.62500000
 // CHECK-INST: fmov z0.d, #2.62500000
 // CHECK-ENCODING: [0xa0,0xc0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c0a0 <unknown>
 
 fdup z0.d, #2.75000000
 // CHECK-INST: fmov z0.d, #2.75000000
 // CHECK-ENCODING: [0xc0,0xc0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c0c0 <unknown>
 
 fdup z0.d, #2.87500000
 // CHECK-INST: fmov z0.d, #2.87500000
 // CHECK-ENCODING: [0xe0,0xc0,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c0 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c0e0 <unknown>
 
 fdup z0.d, #3.00000000
 // CHECK-INST: fmov z0.d, #3.00000000
 // CHECK-ENCODING: [0x00,0xc1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c100 <unknown>
 
 fdup z0.d, #3.12500000
 // CHECK-INST: fmov z0.d, #3.12500000
 // CHECK-ENCODING: [0x20,0xc1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c120 <unknown>
 
 fdup z0.d, #3.25000000
 // CHECK-INST: fmov z0.d, #3.25000000
 // CHECK-ENCODING: [0x40,0xc1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c140 <unknown>
 
 fdup z0.d, #3.37500000
 // CHECK-INST: fmov z0.d, #3.37500000
 // CHECK-ENCODING: [0x60,0xc1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c160 <unknown>
 
 fdup z0.d, #3.50000000
 // CHECK-INST: fmov z0.d, #3.50000000
 // CHECK-ENCODING: [0x80,0xc1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c180 <unknown>
 
 fdup z0.d, #3.62500000
 // CHECK-INST: fmov z0.d, #3.62500000
 // CHECK-ENCODING: [0xa0,0xc1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c1a0 <unknown>
 
 fdup z0.d, #3.75000000
 // CHECK-INST: fmov z0.d, #3.75000000
 // CHECK-ENCODING: [0xc0,0xc1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c1c0 <unknown>
 
 fdup z0.d, #3.87500000
 // CHECK-INST: fmov z0.d, #3.87500000
 // CHECK-ENCODING: [0xe0,0xc1,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c1 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c1e0 <unknown>
 
 fdup z0.d, #4.00000000
 // CHECK-INST: fmov z0.d, #4.00000000
 // CHECK-ENCODING: [0x00,0xc2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c200 <unknown>
 
 fdup z0.d, #4.25000000
 // CHECK-INST: fmov z0.d, #4.25000000
 // CHECK-ENCODING: [0x20,0xc2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c220 <unknown>
 
 fdup z0.d, #4.50000000
 // CHECK-INST: fmov z0.d, #4.50000000
 // CHECK-ENCODING: [0x40,0xc2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c240 <unknown>
 
 fdup z0.d, #4.75000000
 // CHECK-INST: fmov z0.d, #4.75000000
 // CHECK-ENCODING: [0x60,0xc2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c260 <unknown>
 
 fdup z0.d, #5.00000000
 // CHECK-INST: fmov z0.d, #5.00000000
 // CHECK-ENCODING: [0x80,0xc2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c280 <unknown>
 
 fdup z0.d, #5.25000000
 // CHECK-INST: fmov z0.d, #5.25000000
 // CHECK-ENCODING: [0xa0,0xc2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c2a0 <unknown>
 
 fdup z0.d, #5.50000000
 // CHECK-INST: fmov z0.d, #5.50000000
 // CHECK-ENCODING: [0xc0,0xc2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c2c0 <unknown>
 
 fdup z0.d, #5.75000000
 // CHECK-INST: fmov z0.d, #5.75000000
 // CHECK-ENCODING: [0xe0,0xc2,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c2 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c2e0 <unknown>
 
 fdup z0.d, #6.00000000
 // CHECK-INST: fmov z0.d, #6.00000000
 // CHECK-ENCODING: [0x00,0xc3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c300 <unknown>
 
 fdup z0.d, #6.25000000
 // CHECK-INST: fmov z0.d, #6.25000000
 // CHECK-ENCODING: [0x20,0xc3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c320 <unknown>
 
 fdup z0.d, #6.50000000
 // CHECK-INST: fmov z0.d, #6.50000000
 // CHECK-ENCODING: [0x40,0xc3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c340 <unknown>
 
 fdup z0.d, #6.75000000
 // CHECK-INST: fmov z0.d, #6.75000000
 // CHECK-ENCODING: [0x60,0xc3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c360 <unknown>
 
 fdup z0.d, #7.00000000
 // CHECK-INST: fmov z0.d, #7.00000000
 // CHECK-ENCODING: [0x80,0xc3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c380 <unknown>
 
 fdup z0.d, #7.25000000
 // CHECK-INST: fmov z0.d, #7.25000000
 // CHECK-ENCODING: [0xa0,0xc3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c3a0 <unknown>
 
 fdup z0.d, #7.50000000
 // CHECK-INST: fmov z0.d, #7.50000000
 // CHECK-ENCODING: [0xc0,0xc3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c3c0 <unknown>
 
 fdup z0.d, #7.75000000
 // CHECK-INST: fmov z0.d, #7.75000000
 // CHECK-ENCODING: [0xe0,0xc3,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c3e0 <unknown>
 
 fdup z0.d, #8.00000000
 // CHECK-INST: fmov z0.d, #8.00000000
 // CHECK-ENCODING: [0x00,0xc4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c400 <unknown>
 
 fdup z0.d, #8.50000000
 // CHECK-INST: fmov z0.d, #8.50000000
 // CHECK-ENCODING: [0x20,0xc4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c420 <unknown>
 
 fdup z0.d, #9.00000000
 // CHECK-INST: fmov z0.d, #9.00000000
 // CHECK-ENCODING: [0x40,0xc4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c440 <unknown>
 
 fdup z0.d, #9.50000000
 // CHECK-INST: fmov z0.d, #9.50000000
 // CHECK-ENCODING: [0x60,0xc4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c460 <unknown>
 
 fdup z0.d, #10.00000000
 // CHECK-INST: fmov z0.d, #10.00000000
 // CHECK-ENCODING: [0x80,0xc4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c480 <unknown>
 
 fdup z0.d, #10.50000000
 // CHECK-INST: fmov z0.d, #10.50000000
 // CHECK-ENCODING: [0xa0,0xc4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c4a0 <unknown>
 
 fdup z0.d, #11.00000000
 // CHECK-INST: fmov z0.d, #11.00000000
 // CHECK-ENCODING: [0xc0,0xc4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c4c0 <unknown>
 
 fdup z0.d, #11.50000000
 // CHECK-INST: fmov z0.d, #11.50000000
 // CHECK-ENCODING: [0xe0,0xc4,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c4 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c4e0 <unknown>
 
 fdup z0.d, #12.00000000
 // CHECK-INST: fmov z0.d, #12.00000000
 // CHECK-ENCODING: [0x00,0xc5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c500 <unknown>
 
 fdup z0.d, #12.50000000
 // CHECK-INST: fmov z0.d, #12.50000000
 // CHECK-ENCODING: [0x20,0xc5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c520 <unknown>
 
 fdup z0.d, #13.00000000
 // CHECK-INST: fmov z0.d, #13.00000000
 // CHECK-ENCODING: [0x40,0xc5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c540 <unknown>
 
 fdup z0.d, #13.50000000
 // CHECK-INST: fmov z0.d, #13.50000000
 // CHECK-ENCODING: [0x60,0xc5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c560 <unknown>
 
 fdup z0.d, #14.00000000
 // CHECK-INST: fmov z0.d, #14.00000000
 // CHECK-ENCODING: [0x80,0xc5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c580 <unknown>
 
 fdup z0.d, #14.50000000
 // CHECK-INST: fmov z0.d, #14.50000000
 // CHECK-ENCODING: [0xa0,0xc5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c5a0 <unknown>
 
 fdup z0.d, #15.00000000
 // CHECK-INST: fmov z0.d, #15.00000000
 // CHECK-ENCODING: [0xc0,0xc5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c5c0 <unknown>
 
 fdup z0.d, #15.50000000
 // CHECK-INST: fmov z0.d, #15.50000000
 // CHECK-ENCODING: [0xe0,0xc5,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c5 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c5e0 <unknown>
 
 fdup z0.d, #16.00000000
 // CHECK-INST: fmov z0.d, #16.00000000
 // CHECK-ENCODING: [0x00,0xc6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c600 <unknown>
 
 fdup z0.d, #17.00000000
 // CHECK-INST: fmov z0.d, #17.00000000
 // CHECK-ENCODING: [0x20,0xc6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c620 <unknown>
 
 fdup z0.d, #18.00000000
 // CHECK-INST: fmov z0.d, #18.00000000
 // CHECK-ENCODING: [0x40,0xc6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c640 <unknown>
 
 fdup z0.d, #19.00000000
 // CHECK-INST: fmov z0.d, #19.00000000
 // CHECK-ENCODING: [0x60,0xc6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c660 <unknown>
 
 fdup z0.d, #20.00000000
 // CHECK-INST: fmov z0.d, #20.00000000
 // CHECK-ENCODING: [0x80,0xc6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c680 <unknown>
 
 fdup z0.d, #21.00000000
 // CHECK-INST: fmov z0.d, #21.00000000
 // CHECK-ENCODING: [0xa0,0xc6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c6a0 <unknown>
 
 fdup z0.d, #22.00000000
 // CHECK-INST: fmov z0.d, #22.00000000
 // CHECK-ENCODING: [0xc0,0xc6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c6c0 <unknown>
 
 fdup z0.d, #23.00000000
 // CHECK-INST: fmov z0.d, #23.00000000
 // CHECK-ENCODING: [0xe0,0xc6,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c6 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c6e0 <unknown>
 
 fdup z0.d, #24.00000000
 // CHECK-INST: fmov z0.d, #24.00000000
 // CHECK-ENCODING: [0x00,0xc7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c700 <unknown>
 
 fdup z0.d, #25.00000000
 // CHECK-INST: fmov z0.d, #25.00000000
 // CHECK-ENCODING: [0x20,0xc7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c720 <unknown>
 
 fdup z0.d, #26.00000000
 // CHECK-INST: fmov z0.d, #26.00000000
 // CHECK-ENCODING: [0x40,0xc7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c740 <unknown>
 
 fdup z0.d, #27.00000000
 // CHECK-INST: fmov z0.d, #27.00000000
 // CHECK-ENCODING: [0x60,0xc7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c760 <unknown>
 
 fdup z0.d, #28.00000000
 // CHECK-INST: fmov z0.d, #28.00000000
 // CHECK-ENCODING: [0x80,0xc7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c780 <unknown>
 
 fdup z0.d, #29.00000000
 // CHECK-INST: fmov z0.d, #29.00000000
 // CHECK-ENCODING: [0xa0,0xc7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c7a0 <unknown>
 
 fdup z0.d, #30.00000000
 // CHECK-INST: fmov z0.d, #30.00000000
 // CHECK-ENCODING: [0xc0,0xc7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c7c0 <unknown>
 
 fdup z0.d, #31.00000000
 // CHECK-INST: fmov z0.d, #31.00000000
 // CHECK-ENCODING: [0xe0,0xc7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c7e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fexpa.s b/llvm/test/MC/AArch64/SVE/fexpa.s
index 6f6804e9085a5..1171efc2d6466 100644
--- a/llvm/test/MC/AArch64/SVE/fexpa.s
+++ b/llvm/test/MC/AArch64/SVE/fexpa.s
@@ -13,16 +13,16 @@ fexpa z0.h, z31.h
 // CHECK-INST: fexpa	z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0xbb,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: e0 bb 60 04 <unknown>
+// CHECK-UNKNOWN: 0460bbe0 <unknown>
 
 fexpa z0.s, z31.s
 // CHECK-INST: fexpa	z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0xbb,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: e0 bb a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0bbe0 <unknown>
 
 fexpa z0.d, z31.d
 // CHECK-INST: fexpa	z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0xbb,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: e0 bb e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0bbe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fmad.s b/llvm/test/MC/AArch64/SVE/fmad.s
index 37c3b1c8f494a..3ebbcd71a50b6 100644
--- a/llvm/test/MC/AArch64/SVE/fmad.s
+++ b/llvm/test/MC/AArch64/SVE/fmad.s
@@ -13,19 +13,19 @@ fmad z0.h, p7/m, z1.h, z31.h
 // CHECK-INST: fmad	z0.h, p7/m, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x9c,0x7f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 9c 7f 65 <unknown>
+// CHECK-UNKNOWN: 657f9c20 <unknown>
 
 fmad z0.s, p7/m, z1.s, z31.s
 // CHECK-INST: fmad	z0.s, p7/m, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x9c,0xbf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 9c bf 65 <unknown>
+// CHECK-UNKNOWN: 65bf9c20 <unknown>
 
 fmad z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fmad	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x9c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 9c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff9c20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fmad z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fmad	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x9c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 9c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff9c20 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fmad z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fmad	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x9c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 9c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff9c20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fmax.s b/llvm/test/MC/AArch64/SVE/fmax.s
index 6e6f9bd500f2a..158e9fc1399cf 100644
--- a/llvm/test/MC/AArch64/SVE/fmax.s
+++ b/llvm/test/MC/AArch64/SVE/fmax.s
@@ -13,61 +13,61 @@ fmax    z0.h, p0/m, z0.h, #0.000000000000000
 // CHECK-INST: fmax    z0.h, p0/m, z0.h, #0.0
 // CHECK-ENCODING: [0x00,0x80,0x5e,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 5e 65 <unknown>
+// CHECK-UNKNOWN: 655e8000 <unknown>
 
 fmax    z0.h, p0/m, z0.h, #0.0
 // CHECK-INST: fmax    z0.h, p0/m, z0.h, #0.0
 // CHECK-ENCODING: [0x00,0x80,0x5e,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 5e 65 <unknown>
+// CHECK-UNKNOWN: 655e8000 <unknown>
 
 fmax    z0.s, p0/m, z0.s, #0.0
 // CHECK-INST: fmax    z0.s, p0/m, z0.s, #0.0
 // CHECK-ENCODING: [0x00,0x80,0x9e,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 9e 65 <unknown>
+// CHECK-UNKNOWN: 659e8000 <unknown>
 
 fmax    z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fmax    z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xde,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c de 65 <unknown>
+// CHECK-UNKNOWN: 65de9c3f <unknown>
 
 fmax    z31.h, p7/m, z31.h, #1.0
 // CHECK-INST: fmax    z31.h, p7/m, z31.h, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x5e,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 5e 65 <unknown>
+// CHECK-UNKNOWN: 655e9c3f <unknown>
 
 fmax    z31.s, p7/m, z31.s, #1.0
 // CHECK-INST: fmax    z31.s, p7/m, z31.s, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x9e,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 9e 65 <unknown>
+// CHECK-UNKNOWN: 659e9c3f <unknown>
 
 fmax    z0.d, p0/m, z0.d, #0.0
 // CHECK-INST: fmax    z0.d, p0/m, z0.d, #0.0
 // CHECK-ENCODING: [0x00,0x80,0xde,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 de 65 <unknown>
+// CHECK-UNKNOWN: 65de8000 <unknown>
 
 fmax    z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: fmax	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x46,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 46 65 <unknown>
+// CHECK-UNKNOWN: 65469fe0 <unknown>
 
 fmax    z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: fmax	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0x86,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 86 65 <unknown>
+// CHECK-UNKNOWN: 65869fe0 <unknown>
 
 fmax    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmax	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c6 65 <unknown>
+// CHECK-UNKNOWN: 65c69fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -77,46 +77,46 @@ movprfx z0.d, p0/z, z7.d
 // CHECK-INST: movprfx	z0.d, p0/z, z7.d
 // CHECK-ENCODING: [0xe0,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020e0 <unknown>
 
 fmax    z0.d, p0/m, z0.d, #0.0
 // CHECK-INST: fmax	z0.d, p0/m, z0.d, #0.0
 // CHECK-ENCODING: [0x00,0x80,0xde,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 de 65 <unknown>
+// CHECK-UNKNOWN: 65de8000 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fmax    z0.d, p0/m, z0.d, #0.0
 // CHECK-INST: fmax	z0.d, p0/m, z0.d, #0.0
 // CHECK-ENCODING: [0x00,0x80,0xde,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 de 65 <unknown>
+// CHECK-UNKNOWN: 65de8000 <unknown>
 
 movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fmax    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmax	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c6 65 <unknown>
+// CHECK-UNKNOWN: 65c69fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fmax    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmax	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc6,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c6 65 <unknown>
+// CHECK-UNKNOWN: 65c69fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fmaxnm.s b/llvm/test/MC/AArch64/SVE/fmaxnm.s
index 1339293de94aa..d2d6971566426 100644
--- a/llvm/test/MC/AArch64/SVE/fmaxnm.s
+++ b/llvm/test/MC/AArch64/SVE/fmaxnm.s
@@ -13,67 +13,67 @@ fmaxnm  z0.h, p0/m, z0.h, #0.000000000000000
 // CHECK-INST: fmaxnm	z0.h, p0/m, z0.h, #0.0
 // CHECK-ENCODING: [0x00,0x80,0x5c,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 5c 65 <unknown>
+// CHECK-UNKNOWN: 655c8000 <unknown>
 
 fmaxnm  z0.h, p0/m, z0.h, #0.0
 // CHECK-INST: fmaxnm	z0.h, p0/m, z0.h, #0.0
 // CHECK-ENCODING: [0x00,0x80,0x5c,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 5c 65 <unknown>
+// CHECK-UNKNOWN: 655c8000 <unknown>
 
 fmaxnm  z0.s, p0/m, z0.s, #0.0
 // CHECK-INST: fmaxnm	z0.s, p0/m, z0.s, #0.0
 // CHECK-ENCODING: [0x00,0x80,0x9c,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 9c 65 <unknown>
+// CHECK-UNKNOWN: 659c8000 <unknown>
 
 fmaxnm  z0.d, p0/m, z0.d, #0.0
 // CHECK-INST: fmaxnm	z0.d, p0/m, z0.d, #0.0
 // CHECK-ENCODING: [0x00,0x80,0xdc,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 dc 65 <unknown>
+// CHECK-UNKNOWN: 65dc8000 <unknown>
 
 fmaxnm  z31.h, p7/m, z31.h, #1.000000000000000
 // CHECK-INST: fmaxnm	z31.h, p7/m, z31.h, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x5c,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 5c 65 <unknown>
+// CHECK-UNKNOWN: 655c9c3f <unknown>
 
 fmaxnm  z31.h, p7/m, z31.h, #1.0
 // CHECK-INST: fmaxnm	z31.h, p7/m, z31.h, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x5c,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 5c 65 <unknown>
+// CHECK-UNKNOWN: 655c9c3f <unknown>
 
 fmaxnm  z31.s, p7/m, z31.s, #1.0
 // CHECK-INST: fmaxnm	z31.s, p7/m, z31.s, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x9c,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 9c 65 <unknown>
+// CHECK-UNKNOWN: 659c9c3f <unknown>
 
 fmaxnm  z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fmaxnm	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xdc,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c dc 65 <unknown>
+// CHECK-UNKNOWN: 65dc9c3f <unknown>
 
 fmaxnm  z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: fmaxnm	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x44,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 44 65 <unknown>
+// CHECK-UNKNOWN: 65449fe0 <unknown>
 
 fmaxnm  z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: fmaxnm	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0x84,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 84 65 <unknown>
+// CHECK-UNKNOWN: 65849fe0 <unknown>
 
 fmaxnm  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmaxnm	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c4 65 <unknown>
+// CHECK-UNKNOWN: 65c49fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -83,46 +83,46 @@ movprfx z31.d, p7/z, z6.d
 // CHECK-INST: movprfx	z31.d, p7/z, z6.d
 // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cdf <unknown>
 
 fmaxnm  z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fmaxnm	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xdc,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c dc 65 <unknown>
+// CHECK-UNKNOWN: 65dc9c3f <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 fmaxnm  z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fmaxnm	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xdc,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c dc 65 <unknown>
+// CHECK-UNKNOWN: 65dc9c3f <unknown>
 
 movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fmaxnm  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmaxnm	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c4 65 <unknown>
+// CHECK-UNKNOWN: 65c49fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fmaxnm  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmaxnm	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc4,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c4 65 <unknown>
+// CHECK-UNKNOWN: 65c49fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fmaxnmv.s b/llvm/test/MC/AArch64/SVE/fmaxnmv.s
index e4c3534be4672..433ca9999b931 100644
--- a/llvm/test/MC/AArch64/SVE/fmaxnmv.s
+++ b/llvm/test/MC/AArch64/SVE/fmaxnmv.s
@@ -13,16 +13,16 @@ fmaxnmv h0, p7, z31.h
 // CHECK-INST: fmaxnmv	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x44,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 44 65 <unknown>
+// CHECK-UNKNOWN: 65443fe0 <unknown>
 
 fmaxnmv s0, p7, z31.s
 // CHECK-INST: fmaxnmv	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x84,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 84 65 <unknown>
+// CHECK-UNKNOWN: 65843fe0 <unknown>
 
 fmaxnmv d0, p7, z31.d
 // CHECK-INST: fmaxnmv	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xc4,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f c4 65 <unknown>
+// CHECK-UNKNOWN: 65c43fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fmaxv.s b/llvm/test/MC/AArch64/SVE/fmaxv.s
index c9e45064d56a7..32cdf8b20247a 100644
--- a/llvm/test/MC/AArch64/SVE/fmaxv.s
+++ b/llvm/test/MC/AArch64/SVE/fmaxv.s
@@ -13,16 +13,16 @@ fmaxv h0, p7, z31.h
 // CHECK-INST: fmaxv	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x46,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 46 65 <unknown>
+// CHECK-UNKNOWN: 65463fe0 <unknown>
 
 fmaxv s0, p7, z31.s
 // CHECK-INST: fmaxv	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x86,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 86 65 <unknown>
+// CHECK-UNKNOWN: 65863fe0 <unknown>
 
 fmaxv d0, p7, z31.d
 // CHECK-INST: fmaxv	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xc6,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f c6 65 <unknown>
+// CHECK-UNKNOWN: 65c63fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fmin.s b/llvm/test/MC/AArch64/SVE/fmin.s
index 62cc67992c245..015520e93de44 100644
--- a/llvm/test/MC/AArch64/SVE/fmin.s
+++ b/llvm/test/MC/AArch64/SVE/fmin.s
@@ -13,67 +13,67 @@ fmin    z0.h, p0/m, z0.h, #0.000000000000000
 // CHECK-INST: fmin	z0.h, p0/m, z0.h, #0.0
 // CHECK-ENCODING: [0x00,0x80,0x5f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 5f 65 <unknown>
+// CHECK-UNKNOWN: 655f8000 <unknown>
 
 fmin    z0.h, p0/m, z0.h, #0.0
 // CHECK-INST: fmin	z0.h, p0/m, z0.h, #0.0
 // CHECK-ENCODING: [0x00,0x80,0x5f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 5f 65 <unknown>
+// CHECK-UNKNOWN: 655f8000 <unknown>
 
 fmin    z0.s, p0/m, z0.s, #0.0
 // CHECK-INST: fmin	z0.s, p0/m, z0.s, #0.0
 // CHECK-ENCODING: [0x00,0x80,0x9f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 9f 65 <unknown>
+// CHECK-UNKNOWN: 659f8000 <unknown>
 
 fmin    z0.d, p0/m, z0.d, #0.0
 // CHECK-INST: fmin	z0.d, p0/m, z0.d, #0.0
 // CHECK-ENCODING: [0x00,0x80,0xdf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 df 65 <unknown>
+// CHECK-UNKNOWN: 65df8000 <unknown>
 
 fmin    z31.h, p7/m, z31.h, #1.000000000000000
 // CHECK-INST: fmin	z31.h, p7/m, z31.h, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x5f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 5f 65 <unknown>
+// CHECK-UNKNOWN: 655f9c3f <unknown>
 
 fmin    z31.h, p7/m, z31.h, #1.0
 // CHECK-INST: fmin	z31.h, p7/m, z31.h, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x5f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 5f 65 <unknown>
+// CHECK-UNKNOWN: 655f9c3f <unknown>
 
 fmin    z31.s, p7/m, z31.s, #1.0
 // CHECK-INST: fmin	z31.s, p7/m, z31.s, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x9f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 9f 65 <unknown>
+// CHECK-UNKNOWN: 659f9c3f <unknown>
 
 fmin    z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fmin	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xdf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c df 65 <unknown>
+// CHECK-UNKNOWN: 65df9c3f <unknown>
 
 fmin    z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: fmin	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x47,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 47 65 <unknown>
+// CHECK-UNKNOWN: 65479fe0 <unknown>
 
 fmin    z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: fmin	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0x87,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 87 65 <unknown>
+// CHECK-UNKNOWN: 65879fe0 <unknown>
 
 fmin    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmin	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c7 65 <unknown>
+// CHECK-UNKNOWN: 65c79fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -83,46 +83,46 @@ movprfx z31.d, p7/z, z6.d
 // CHECK-INST: movprfx	z31.d, p7/z, z6.d
 // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cdf <unknown>
 
 fmin    z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fmin	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xdf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c df 65 <unknown>
+// CHECK-UNKNOWN: 65df9c3f <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 fmin    z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fmin	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xdf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c df 65 <unknown>
+// CHECK-UNKNOWN: 65df9c3f <unknown>
 
 movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fmin    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmin	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c7 65 <unknown>
+// CHECK-UNKNOWN: 65c79fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fmin    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmin	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc7,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c7 65 <unknown>
+// CHECK-UNKNOWN: 65c79fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fminnm.s b/llvm/test/MC/AArch64/SVE/fminnm.s
index e026c965aad02..4ad7bc4c6f34d 100644
--- a/llvm/test/MC/AArch64/SVE/fminnm.s
+++ b/llvm/test/MC/AArch64/SVE/fminnm.s
@@ -13,67 +13,67 @@ fminnm  z0.h, p0/m, z0.h, #0.000000000000000
 // CHECK-INST: fminnm	z0.h, p0/m, z0.h, #0.0
 // CHECK-ENCODING: [0x00,0x80,0x5d,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 5d 65 <unknown>
+// CHECK-UNKNOWN: 655d8000 <unknown>
 
 fminnm  z0.h, p0/m, z0.h, #0.0
 // CHECK-INST: fminnm	z0.h, p0/m, z0.h, #0.0
 // CHECK-ENCODING: [0x00,0x80,0x5d,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 5d 65 <unknown>
+// CHECK-UNKNOWN: 655d8000 <unknown>
 
 fminnm  z0.s, p0/m, z0.s, #0.0
 // CHECK-INST: fminnm	z0.s, p0/m, z0.s, #0.0
 // CHECK-ENCODING: [0x00,0x80,0x9d,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 9d 65 <unknown>
+// CHECK-UNKNOWN: 659d8000 <unknown>
 
 fminnm  z0.d, p0/m, z0.d, #0.0
 // CHECK-INST: fminnm	z0.d, p0/m, z0.d, #0.0
 // CHECK-ENCODING: [0x00,0x80,0xdd,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 dd 65 <unknown>
+// CHECK-UNKNOWN: 65dd8000 <unknown>
 
 fminnm  z31.h, p7/m, z31.h, #1.000000000000000
 // CHECK-INST: fminnm	z31.h, p7/m, z31.h, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x5d,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 5d 65 <unknown>
+// CHECK-UNKNOWN: 655d9c3f <unknown>
 
 fminnm  z31.h, p7/m, z31.h, #1.0
 // CHECK-INST: fminnm	z31.h, p7/m, z31.h, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x5d,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 5d 65 <unknown>
+// CHECK-UNKNOWN: 655d9c3f <unknown>
 
 fminnm  z31.s, p7/m, z31.s, #1.0
 // CHECK-INST: fminnm	z31.s, p7/m, z31.s, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x9d,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 9d 65 <unknown>
+// CHECK-UNKNOWN: 659d9c3f <unknown>
 
 fminnm  z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fminnm	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xdd,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c dd 65 <unknown>
+// CHECK-UNKNOWN: 65dd9c3f <unknown>
 
 fminnm  z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: fminnm	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x45,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 45 65 <unknown>
+// CHECK-UNKNOWN: 65459fe0 <unknown>
 
 fminnm  z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: fminnm	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0x85,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 85 65 <unknown>
+// CHECK-UNKNOWN: 65859fe0 <unknown>
 
 fminnm  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fminnm	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c5 65 <unknown>
+// CHECK-UNKNOWN: 65c59fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -83,46 +83,46 @@ movprfx z31.d, p7/z, z6.d
 // CHECK-INST: movprfx	z31.d, p7/z, z6.d
 // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cdf <unknown>
 
 fminnm  z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fminnm	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xdd,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c dd 65 <unknown>
+// CHECK-UNKNOWN: 65dd9c3f <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 fminnm  z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fminnm	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xdd,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c dd 65 <unknown>
+// CHECK-UNKNOWN: 65dd9c3f <unknown>
 
 movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fminnm  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fminnm	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c5 65 <unknown>
+// CHECK-UNKNOWN: 65c59fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fminnm  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fminnm	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc5,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c5 65 <unknown>
+// CHECK-UNKNOWN: 65c59fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fminnmv.s b/llvm/test/MC/AArch64/SVE/fminnmv.s
index 44eee8558c6a8..8648a223254f6 100644
--- a/llvm/test/MC/AArch64/SVE/fminnmv.s
+++ b/llvm/test/MC/AArch64/SVE/fminnmv.s
@@ -13,16 +13,16 @@ fminnmv h0, p7, z31.h
 // CHECK-INST: fminnmv	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x45,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 45 65 <unknown>
+// CHECK-UNKNOWN: 65453fe0 <unknown>
 
 fminnmv s0, p7, z31.s
 // CHECK-INST: fminnmv	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x85,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 85 65 <unknown>
+// CHECK-UNKNOWN: 65853fe0 <unknown>
 
 fminnmv d0, p7, z31.d
 // CHECK-INST: fminnmv	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xc5,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f c5 65 <unknown>
+// CHECK-UNKNOWN: 65c53fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fminv.s b/llvm/test/MC/AArch64/SVE/fminv.s
index 94017ad83b9f5..e0416cccc4954 100644
--- a/llvm/test/MC/AArch64/SVE/fminv.s
+++ b/llvm/test/MC/AArch64/SVE/fminv.s
@@ -13,16 +13,16 @@ fminv h0, p7, z31.h
 // CHECK-INST: fminv	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x47,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 47 65 <unknown>
+// CHECK-UNKNOWN: 65473fe0 <unknown>
 
 fminv s0, p7, z31.s
 // CHECK-INST: fminv	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x87,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 87 65 <unknown>
+// CHECK-UNKNOWN: 65873fe0 <unknown>
 
 fminv d0, p7, z31.d
 // CHECK-INST: fminv	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xc7,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f c7 65 <unknown>
+// CHECK-UNKNOWN: 65c73fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fmla.s b/llvm/test/MC/AArch64/SVE/fmla.s
index 91c9e46e30c9e..c900535b5cdea 100644
--- a/llvm/test/MC/AArch64/SVE/fmla.s
+++ b/llvm/test/MC/AArch64/SVE/fmla.s
@@ -13,37 +13,37 @@ fmla z0.h, p7/m, z1.h, z31.h
 // CHECK-INST: fmla	z0.h, p7/m, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x1c,0x7f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 1c 7f 65 <unknown>
+// CHECK-UNKNOWN: 657f1c20 <unknown>
 
 fmla z0.s, p7/m, z1.s, z31.s
 // CHECK-INST: fmla	z0.s, p7/m, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x1c,0xbf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 1c bf 65 <unknown>
+// CHECK-UNKNOWN: 65bf1c20 <unknown>
 
 fmla z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fmla	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x1c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 1c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff1c20 <unknown>
 
 fmla z0.h, z1.h, z7.h[7]
 // CHECK-INST: fmla	z0.h, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x00,0x7f,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 7f 64 <unknown>
+// CHECK-UNKNOWN: 647f0020 <unknown>
 
 fmla z0.s, z1.s, z7.s[3]
 // CHECK-INST: fmla	z0.s, z1.s, z7.s[3]
 // CHECK-ENCODING: [0x20,0x00,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf0020 <unknown>
 
 fmla z0.d, z1.d, z7.d[1]
 // CHECK-INST: fmla	z0.d, z1.d, z7.d[1]
 // CHECK-ENCODING: [0x20,0x00,0xf7,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 f7 64 <unknown>
+// CHECK-UNKNOWN: 64f70020 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -53,34 +53,34 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fmla z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fmla	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x1c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 1c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff1c20 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fmla z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fmla	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x1c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 1c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff1c20 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fmla z0.d, z1.d, z7.d[1]
 // CHECK-INST: fmla	z0.d, z1.d, z7.d[1]
 // CHECK-ENCODING: [0x20,0x00,0xf7,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 f7 64 <unknown>
+// CHECK-UNKNOWN: 64f70020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fmls.s b/llvm/test/MC/AArch64/SVE/fmls.s
index 67391c7704f35..47e45fec55a43 100644
--- a/llvm/test/MC/AArch64/SVE/fmls.s
+++ b/llvm/test/MC/AArch64/SVE/fmls.s
@@ -13,37 +13,37 @@ fmls z0.h, p7/m, z1.h, z31.h
 // CHECK-INST: fmls	z0.h, p7/m, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x3c,0x7f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 3c 7f 65 <unknown>
+// CHECK-UNKNOWN: 657f3c20 <unknown>
 
 fmls z0.s, p7/m, z1.s, z31.s
 // CHECK-INST: fmls	z0.s, p7/m, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x3c,0xbf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 3c bf 65 <unknown>
+// CHECK-UNKNOWN: 65bf3c20 <unknown>
 
 fmls z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fmls	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x3c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 3c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff3c20 <unknown>
 
 fmls z0.h, z1.h, z7.h[7]
 // CHECK-INST: fmls	z0.h, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x04,0x7f,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 04 7f 64 <unknown>
+// CHECK-UNKNOWN: 647f0420 <unknown>
 
 fmls z0.s, z1.s, z7.s[3]
 // CHECK-INST: fmls	z0.s, z1.s, z7.s[3]
 // CHECK-ENCODING: [0x20,0x04,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 04 bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf0420 <unknown>
 
 fmls z0.d, z1.d, z7.d[1]
 // CHECK-INST: fmls	z0.d, z1.d, z7.d[1]
 // CHECK-ENCODING: [0x20,0x04,0xf7,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 04 f7 64 <unknown>
+// CHECK-UNKNOWN: 64f70420 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -53,34 +53,34 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fmls z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fmls	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x3c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 3c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff3c20 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fmls z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fmls	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x3c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 3c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff3c20 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fmls z0.d, z1.d, z7.d[1]
 // CHECK-INST: fmls	z0.d, z1.d, z7.d[1]
 // CHECK-ENCODING: [0x20,0x04,0xf7,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 04 f7 64 <unknown>
+// CHECK-UNKNOWN: 64f70420 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fmov.s b/llvm/test/MC/AArch64/SVE/fmov.s
index d727bf4269729..b58fe8d652caa 100644
--- a/llvm/test/MC/AArch64/SVE/fmov.s
+++ b/llvm/test/MC/AArch64/SVE/fmov.s
@@ -13,1591 +13,1591 @@ fmov z0.h, #0.0
 // CHECK-INST: mov     z0.h, #0
 // CHECK-ENCODING: [0x00,0xc0,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 78 25
+// CHECK-UNKNOWN: 2578c000
 
 fmov z0.s, #0.0
 // CHECK-INST: mov     z0.s, #0
 // CHECK-ENCODING: [0x00,0xc0,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 b8 25
+// CHECK-UNKNOWN: 25b8c000
 
 fmov z0.d, #0.0
 // CHECK-INST: mov     z0.d, #0
 // CHECK-ENCODING: [0x00,0xc0,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 f8 25
+// CHECK-UNKNOWN: 25f8c000
 
 fmov z0.h, #-0.12500000
 // CHECK-INST: fmov z0.h, #-0.12500000
 // CHECK-ENCODING: [0x00,0xd8,0x79,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d8 79 25 <unknown>
+// CHECK-UNKNOWN: 2579d800 <unknown>
 
 fmov z0.s, #-0.12500000
 // CHECK-INST: fmov z0.s, #-0.12500000
 // CHECK-ENCODING: [0x00,0xd8,0xb9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d8 b9 25 <unknown>
+// CHECK-UNKNOWN: 25b9d800 <unknown>
 
 fmov z0.d, #-0.12500000
 // CHECK-INST: fmov z0.d, #-0.12500000
 // CHECK-ENCODING: [0x00,0xd8,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d8 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9d800 <unknown>
 
 fmov z0.d, #31.00000000
 // CHECK-INST: fmov z0.d, #31.00000000
 // CHECK-ENCODING: [0xe0,0xc7,0xf9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 f9 25 <unknown>
+// CHECK-UNKNOWN: 25f9c7e0 <unknown>
 
 fmov z0.h, p0/m, #-0.12500000
 // CHECK-INST: fmov z0.h, p0/m, #-0.12500000
 // CHECK-ENCODING: [0x00,0xd8,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d8 50 05 <unknown>
+// CHECK-UNKNOWN: 0550d800 <unknown>
 
 fmov z0.s, p0/m, #-0.12500000
 // CHECK-INST: fmov z0.s, p0/m, #-0.12500000
 // CHECK-ENCODING: [0x00,0xd8,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d8 90 05 <unknown>
+// CHECK-UNKNOWN: 0590d800 <unknown>
 
 fmov z0.d, p0/m, #-0.12500000
 // CHECK-INST: fmov z0.d, p0/m, #-0.12500000
 // CHECK-ENCODING: [0x00,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d800 <unknown>
 
 fmov z0.d, p0/m, #-0.13281250
 // CHECK-INST: fmov z0.d, p0/m, #-0.13281250
 // CHECK-ENCODING: [0x20,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d820 <unknown>
 
 fmov z0.d, p0/m, #-0.14062500
 // CHECK-INST: fmov z0.d, p0/m, #-0.14062500
 // CHECK-ENCODING: [0x40,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d840 <unknown>
 
 fmov z0.d, p0/m, #-0.14843750
 // CHECK-INST: fmov z0.d, p0/m, #-0.14843750
 // CHECK-ENCODING: [0x60,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d860 <unknown>
 
 fmov z0.d, p0/m, #-0.15625000
 // CHECK-INST: fmov z0.d, p0/m, #-0.15625000
 // CHECK-ENCODING: [0x80,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d880 <unknown>
 
 fmov z0.d, p0/m, #-0.16406250
 // CHECK-INST: fmov z0.d, p0/m, #-0.16406250
 // CHECK-ENCODING: [0xa0,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d8a0 <unknown>
 
 fmov z0.d, p0/m, #-0.17187500
 // CHECK-INST: fmov z0.d, p0/m, #-0.17187500
 // CHECK-ENCODING: [0xc0,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d8c0 <unknown>
 
 fmov z0.d, p0/m, #-0.17968750
 // CHECK-INST: fmov z0.d, p0/m, #-0.17968750
 // CHECK-ENCODING: [0xe0,0xd8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d8e0 <unknown>
 
 fmov z0.d, p0/m, #-0.18750000
 // CHECK-INST: fmov z0.d, p0/m, #-0.18750000
 // CHECK-ENCODING: [0x00,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d900 <unknown>
 
 fmov z0.d, p0/m, #-0.19531250
 // CHECK-INST: fmov z0.d, p0/m, #-0.19531250
 // CHECK-ENCODING: [0x20,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d920 <unknown>
 
 fmov z0.d, p0/m, #-0.20312500
 // CHECK-INST: fmov z0.d, p0/m, #-0.20312500
 // CHECK-ENCODING: [0x40,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d940 <unknown>
 
 fmov z0.d, p0/m, #-0.21093750
 // CHECK-INST: fmov z0.d, p0/m, #-0.21093750
 // CHECK-ENCODING: [0x60,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d960 <unknown>
 
 fmov z0.d, p0/m, #-0.21875000
 // CHECK-INST: fmov z0.d, p0/m, #-0.21875000
 // CHECK-ENCODING: [0x80,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d980 <unknown>
 
 fmov z0.d, p0/m, #-0.22656250
 // CHECK-INST: fmov z0.d, p0/m, #-0.22656250
 // CHECK-ENCODING: [0xa0,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d9a0 <unknown>
 
 fmov z0.d, p0/m, #-0.23437500
 // CHECK-INST: fmov z0.d, p0/m, #-0.23437500
 // CHECK-ENCODING: [0xc0,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d9c0 <unknown>
 
 fmov z0.d, p0/m, #-0.24218750
 // CHECK-INST: fmov z0.d, p0/m, #-0.24218750
 // CHECK-ENCODING: [0xe0,0xd9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d9e0 <unknown>
 
 fmov z0.d, p0/m, #-0.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-0.25000000
 // CHECK-ENCODING: [0x00,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0da00 <unknown>
 
 fmov z0.d, p0/m, #-0.26562500
 // CHECK-INST: fmov z0.d, p0/m, #-0.26562500
 // CHECK-ENCODING: [0x20,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0da20 <unknown>
 
 fmov z0.d, p0/m, #-0.28125000
 // CHECK-INST: fmov z0.d, p0/m, #-0.28125000
 // CHECK-ENCODING: [0x40,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0da40 <unknown>
 
 fmov z0.d, p0/m, #-0.29687500
 // CHECK-INST: fmov z0.d, p0/m, #-0.29687500
 // CHECK-ENCODING: [0x60,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0da60 <unknown>
 
 fmov z0.d, p0/m, #-0.31250000
 // CHECK-INST: fmov z0.d, p0/m, #-0.31250000
 // CHECK-ENCODING: [0x80,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0da80 <unknown>
 
 fmov z0.d, p0/m, #-0.32812500
 // CHECK-INST: fmov z0.d, p0/m, #-0.32812500
 // CHECK-ENCODING: [0xa0,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0daa0 <unknown>
 
 fmov z0.d, p0/m, #-0.34375000
 // CHECK-INST: fmov z0.d, p0/m, #-0.34375000
 // CHECK-ENCODING: [0xc0,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dac0 <unknown>
 
 fmov z0.d, p0/m, #-0.35937500
 // CHECK-INST: fmov z0.d, p0/m, #-0.35937500
 // CHECK-ENCODING: [0xe0,0xda,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 da d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dae0 <unknown>
 
 fmov z0.d, p0/m, #-0.37500000
 // CHECK-INST: fmov z0.d, p0/m, #-0.37500000
 // CHECK-ENCODING: [0x00,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0db00 <unknown>
 
 fmov z0.d, p0/m, #-0.39062500
 // CHECK-INST: fmov z0.d, p0/m, #-0.39062500
 // CHECK-ENCODING: [0x20,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0db20 <unknown>
 
 fmov z0.d, p0/m, #-0.40625000
 // CHECK-INST: fmov z0.d, p0/m, #-0.40625000
 // CHECK-ENCODING: [0x40,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0db40 <unknown>
 
 fmov z0.d, p0/m, #-0.42187500
 // CHECK-INST: fmov z0.d, p0/m, #-0.42187500
 // CHECK-ENCODING: [0x60,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0db60 <unknown>
 
 fmov z0.d, p0/m, #-0.43750000
 // CHECK-INST: fmov z0.d, p0/m, #-0.43750000
 // CHECK-ENCODING: [0x80,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0db80 <unknown>
 
 fmov z0.d, p0/m, #-0.45312500
 // CHECK-INST: fmov z0.d, p0/m, #-0.45312500
 // CHECK-ENCODING: [0xa0,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dba0 <unknown>
 
 fmov z0.d, p0/m, #-0.46875000
 // CHECK-INST: fmov z0.d, p0/m, #-0.46875000
 // CHECK-ENCODING: [0xc0,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dbc0 <unknown>
 
 fmov z0.d, p0/m, #-0.48437500
 // CHECK-INST: fmov z0.d, p0/m, #-0.48437500
 // CHECK-ENCODING: [0xe0,0xdb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 db d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dbe0 <unknown>
 
 fmov z0.d, p0/m, #-0.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-0.50000000
 // CHECK-ENCODING: [0x00,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dc00 <unknown>
 
 fmov z0.d, p0/m, #-0.53125000
 // CHECK-INST: fmov z0.d, p0/m, #-0.53125000
 // CHECK-ENCODING: [0x20,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dc20 <unknown>
 
 fmov z0.d, p0/m, #-0.56250000
 // CHECK-INST: fmov z0.d, p0/m, #-0.56250000
 // CHECK-ENCODING: [0x40,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dc40 <unknown>
 
 fmov z0.d, p0/m, #-0.59375000
 // CHECK-INST: fmov z0.d, p0/m, #-0.59375000
 // CHECK-ENCODING: [0x60,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dc60 <unknown>
 
 fmov z0.d, p0/m, #-0.62500000
 // CHECK-INST: fmov z0.d, p0/m, #-0.62500000
 // CHECK-ENCODING: [0x80,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dc80 <unknown>
 
 fmov z0.d, p0/m, #-0.65625000
 // CHECK-INST: fmov z0.d, p0/m, #-0.65625000
 // CHECK-ENCODING: [0xa0,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dca0 <unknown>
 
 fmov z0.d, p0/m, #-0.68750000
 // CHECK-INST: fmov z0.d, p0/m, #-0.68750000
 // CHECK-ENCODING: [0xc0,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dcc0 <unknown>
 
 fmov z0.d, p0/m, #-0.71875000
 // CHECK-INST: fmov z0.d, p0/m, #-0.71875000
 // CHECK-ENCODING: [0xe0,0xdc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 dc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dce0 <unknown>
 
 fmov z0.d, p0/m, #-0.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-0.75000000
 // CHECK-ENCODING: [0x00,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dd00 <unknown>
 
 fmov z0.d, p0/m, #-0.78125000
 // CHECK-INST: fmov z0.d, p0/m, #-0.78125000
 // CHECK-ENCODING: [0x20,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dd20 <unknown>
 
 fmov z0.d, p0/m, #-0.81250000
 // CHECK-INST: fmov z0.d, p0/m, #-0.81250000
 // CHECK-ENCODING: [0x40,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dd40 <unknown>
 
 fmov z0.d, p0/m, #-0.84375000
 // CHECK-INST: fmov z0.d, p0/m, #-0.84375000
 // CHECK-ENCODING: [0x60,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dd60 <unknown>
 
 fmov z0.d, p0/m, #-0.87500000
 // CHECK-INST: fmov z0.d, p0/m, #-0.87500000
 // CHECK-ENCODING: [0x80,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dd80 <unknown>
 
 fmov z0.d, p0/m, #-0.90625000
 // CHECK-INST: fmov z0.d, p0/m, #-0.90625000
 // CHECK-ENCODING: [0xa0,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dda0 <unknown>
 
 fmov z0.d, p0/m, #-0.93750000
 // CHECK-INST: fmov z0.d, p0/m, #-0.93750000
 // CHECK-ENCODING: [0xc0,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ddc0 <unknown>
 
 fmov z0.d, p0/m, #-0.96875000
 // CHECK-INST: fmov z0.d, p0/m, #-0.96875000
 // CHECK-ENCODING: [0xe0,0xdd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 dd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dde0 <unknown>
 
 fmov z0.d, p0/m, #-1.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-1.00000000
 // CHECK-ENCODING: [0x00,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0de00 <unknown>
 
 fmov z0.d, p0/m, #-1.06250000
 // CHECK-INST: fmov z0.d, p0/m, #-1.06250000
 // CHECK-ENCODING: [0x20,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0de20 <unknown>
 
 fmov z0.d, p0/m, #-1.12500000
 // CHECK-INST: fmov z0.d, p0/m, #-1.12500000
 // CHECK-ENCODING: [0x40,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0de40 <unknown>
 
 fmov z0.d, p0/m, #-1.18750000
 // CHECK-INST: fmov z0.d, p0/m, #-1.18750000
 // CHECK-ENCODING: [0x60,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0de60 <unknown>
 
 fmov z0.d, p0/m, #-1.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-1.25000000
 // CHECK-ENCODING: [0x80,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0de80 <unknown>
 
 fmov z0.d, p0/m, #-1.31250000
 // CHECK-INST: fmov z0.d, p0/m, #-1.31250000
 // CHECK-ENCODING: [0xa0,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dea0 <unknown>
 
 fmov z0.d, p0/m, #-1.37500000
 // CHECK-INST: fmov z0.d, p0/m, #-1.37500000
 // CHECK-ENCODING: [0xc0,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dec0 <unknown>
 
 fmov z0.d, p0/m, #-1.43750000
 // CHECK-INST: fmov z0.d, p0/m, #-1.43750000
 // CHECK-ENCODING: [0xe0,0xde,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 de d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dee0 <unknown>
 
 fmov z0.d, p0/m, #-1.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-1.50000000
 // CHECK-ENCODING: [0x00,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0df00 <unknown>
 
 fmov z0.d, p0/m, #-1.56250000
 // CHECK-INST: fmov z0.d, p0/m, #-1.56250000
 // CHECK-ENCODING: [0x20,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0df20 <unknown>
 
 fmov z0.d, p0/m, #-1.62500000
 // CHECK-INST: fmov z0.d, p0/m, #-1.62500000
 // CHECK-ENCODING: [0x40,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0df40 <unknown>
 
 fmov z0.d, p0/m, #-1.68750000
 // CHECK-INST: fmov z0.d, p0/m, #-1.68750000
 // CHECK-ENCODING: [0x60,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0df60 <unknown>
 
 fmov z0.d, p0/m, #-1.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-1.75000000
 // CHECK-ENCODING: [0x80,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0df80 <unknown>
 
 fmov z0.d, p0/m, #-1.81250000
 // CHECK-INST: fmov z0.d, p0/m, #-1.81250000
 // CHECK-ENCODING: [0xa0,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dfa0 <unknown>
 
 fmov z0.d, p0/m, #-1.87500000
 // CHECK-INST: fmov z0.d, p0/m, #-1.87500000
 // CHECK-ENCODING: [0xc0,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dfc0 <unknown>
 
 fmov z0.d, p0/m, #-1.93750000
 // CHECK-INST: fmov z0.d, p0/m, #-1.93750000
 // CHECK-ENCODING: [0xe0,0xdf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 df d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0dfe0 <unknown>
 
 fmov z0.d, p0/m, #-2.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-2.00000000
 // CHECK-ENCODING: [0x00,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d000 <unknown>
 
 fmov z0.d, p0/m, #-2.12500000
 // CHECK-INST: fmov z0.d, p0/m, #-2.12500000
 // CHECK-ENCODING: [0x20,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d020 <unknown>
 
 fmov z0.d, p0/m, #-2.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-2.25000000
 // CHECK-ENCODING: [0x40,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d040 <unknown>
 
 fmov z0.d, p0/m, #-2.37500000
 // CHECK-INST: fmov z0.d, p0/m, #-2.37500000
 // CHECK-ENCODING: [0x60,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d060 <unknown>
 
 fmov z0.d, p0/m, #-2.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-2.50000000
 // CHECK-ENCODING: [0x80,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d080 <unknown>
 
 fmov z0.d, p0/m, #-2.62500000
 // CHECK-INST: fmov z0.d, p0/m, #-2.62500000
 // CHECK-ENCODING: [0xa0,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d0a0 <unknown>
 
 fmov z0.d, p0/m, #-2.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-2.75000000
 // CHECK-ENCODING: [0xc0,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d0c0 <unknown>
 
 fmov z0.d, p0/m, #-2.87500000
 // CHECK-INST: fmov z0.d, p0/m, #-2.87500000
 // CHECK-ENCODING: [0xe0,0xd0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d0e0 <unknown>
 
 fmov z0.d, p0/m, #-3.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-3.00000000
 // CHECK-ENCODING: [0x00,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d100 <unknown>
 
 fmov z0.d, p0/m, #-3.12500000
 // CHECK-INST: fmov z0.d, p0/m, #-3.12500000
 // CHECK-ENCODING: [0x20,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d120 <unknown>
 
 fmov z0.d, p0/m, #-3.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-3.25000000
 // CHECK-ENCODING: [0x40,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d140 <unknown>
 
 fmov z0.d, p0/m, #-3.37500000
 // CHECK-INST: fmov z0.d, p0/m, #-3.37500000
 // CHECK-ENCODING: [0x60,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d160 <unknown>
 
 fmov z0.d, p0/m, #-3.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-3.50000000
 // CHECK-ENCODING: [0x80,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d180 <unknown>
 
 fmov z0.d, p0/m, #-3.62500000
 // CHECK-INST: fmov z0.d, p0/m, #-3.62500000
 // CHECK-ENCODING: [0xa0,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d1a0 <unknown>
 
 fmov z0.d, p0/m, #-3.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-3.75000000
 // CHECK-ENCODING: [0xc0,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d1c0 <unknown>
 
 fmov z0.d, p0/m, #-3.87500000
 // CHECK-INST: fmov z0.d, p0/m, #-3.87500000
 // CHECK-ENCODING: [0xe0,0xd1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d1e0 <unknown>
 
 fmov z0.d, p0/m, #-4.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-4.00000000
 // CHECK-ENCODING: [0x00,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d200 <unknown>
 
 fmov z0.d, p0/m, #-4.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-4.25000000
 // CHECK-ENCODING: [0x20,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d220 <unknown>
 
 fmov z0.d, p0/m, #-4.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-4.50000000
 // CHECK-ENCODING: [0x40,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d240 <unknown>
 
 fmov z0.d, p0/m, #-4.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-4.75000000
 // CHECK-ENCODING: [0x60,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d260 <unknown>
 
 fmov z0.d, p0/m, #-5.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-5.00000000
 // CHECK-ENCODING: [0x80,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d280 <unknown>
 
 fmov z0.d, p0/m, #-5.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-5.25000000
 // CHECK-ENCODING: [0xa0,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d2a0 <unknown>
 
 fmov z0.d, p0/m, #-5.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-5.50000000
 // CHECK-ENCODING: [0xc0,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d2c0 <unknown>
 
 fmov z0.d, p0/m, #-5.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-5.75000000
 // CHECK-ENCODING: [0xe0,0xd2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d2e0 <unknown>
 
 fmov z0.d, p0/m, #-6.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-6.00000000
 // CHECK-ENCODING: [0x00,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d300 <unknown>
 
 fmov z0.d, p0/m, #-6.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-6.25000000
 // CHECK-ENCODING: [0x20,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d320 <unknown>
 
 fmov z0.d, p0/m, #-6.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-6.50000000
 // CHECK-ENCODING: [0x40,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d340 <unknown>
 
 fmov z0.d, p0/m, #-6.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-6.75000000
 // CHECK-ENCODING: [0x60,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d360 <unknown>
 
 fmov z0.d, p0/m, #-7.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-7.00000000
 // CHECK-ENCODING: [0x80,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d380 <unknown>
 
 fmov z0.d, p0/m, #-7.25000000
 // CHECK-INST: fmov z0.d, p0/m, #-7.25000000
 // CHECK-ENCODING: [0xa0,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d3a0 <unknown>
 
 fmov z0.d, p0/m, #-7.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-7.50000000
 // CHECK-ENCODING: [0xc0,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d3c0 <unknown>
 
 fmov z0.d, p0/m, #-7.75000000
 // CHECK-INST: fmov z0.d, p0/m, #-7.75000000
 // CHECK-ENCODING: [0xe0,0xd3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d3e0 <unknown>
 
 fmov z0.d, p0/m, #-8.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-8.00000000
 // CHECK-ENCODING: [0x00,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d400 <unknown>
 
 fmov z0.d, p0/m, #-8.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-8.50000000
 // CHECK-ENCODING: [0x20,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d420 <unknown>
 
 fmov z0.d, p0/m, #-9.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-9.00000000
 // CHECK-ENCODING: [0x40,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d440 <unknown>
 
 fmov z0.d, p0/m, #-9.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-9.50000000
 // CHECK-ENCODING: [0x60,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d460 <unknown>
 
 fmov z0.d, p0/m, #-10.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-10.00000000
 // CHECK-ENCODING: [0x80,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d480 <unknown>
 
 fmov z0.d, p0/m, #-10.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-10.50000000
 // CHECK-ENCODING: [0xa0,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d4a0 <unknown>
 
 fmov z0.d, p0/m, #-11.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-11.00000000
 // CHECK-ENCODING: [0xc0,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d4c0 <unknown>
 
 fmov z0.d, p0/m, #-11.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-11.50000000
 // CHECK-ENCODING: [0xe0,0xd4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d4e0 <unknown>
 
 fmov z0.d, p0/m, #-12.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-12.00000000
 // CHECK-ENCODING: [0x00,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d500 <unknown>
 
 fmov z0.d, p0/m, #-12.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-12.50000000
 // CHECK-ENCODING: [0x20,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d520 <unknown>
 
 fmov z0.d, p0/m, #-13.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-13.00000000
 // CHECK-ENCODING: [0x40,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d540 <unknown>
 
 fmov z0.d, p0/m, #-13.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-13.50000000
 // CHECK-ENCODING: [0x60,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d560 <unknown>
 
 fmov z0.d, p0/m, #-14.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-14.00000000
 // CHECK-ENCODING: [0x80,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d580 <unknown>
 
 fmov z0.d, p0/m, #-14.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-14.50000000
 // CHECK-ENCODING: [0xa0,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d5a0 <unknown>
 
 fmov z0.d, p0/m, #-15.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-15.00000000
 // CHECK-ENCODING: [0xc0,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d5c0 <unknown>
 
 fmov z0.d, p0/m, #-15.50000000
 // CHECK-INST: fmov z0.d, p0/m, #-15.50000000
 // CHECK-ENCODING: [0xe0,0xd5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d5e0 <unknown>
 
 fmov z0.d, p0/m, #-16.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-16.00000000
 // CHECK-ENCODING: [0x00,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d600 <unknown>
 
 fmov z0.d, p0/m, #-17.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-17.00000000
 // CHECK-ENCODING: [0x20,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d620 <unknown>
 
 fmov z0.d, p0/m, #-18.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-18.00000000
 // CHECK-ENCODING: [0x40,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d640 <unknown>
 
 fmov z0.d, p0/m, #-19.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-19.00000000
 // CHECK-ENCODING: [0x60,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d660 <unknown>
 
 fmov z0.d, p0/m, #-20.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-20.00000000
 // CHECK-ENCODING: [0x80,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d680 <unknown>
 
 fmov z0.d, p0/m, #-21.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-21.00000000
 // CHECK-ENCODING: [0xa0,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d6a0 <unknown>
 
 fmov z0.d, p0/m, #-22.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-22.00000000
 // CHECK-ENCODING: [0xc0,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d6c0 <unknown>
 
 fmov z0.d, p0/m, #-23.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-23.00000000
 // CHECK-ENCODING: [0xe0,0xd6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d6e0 <unknown>
 
 fmov z0.d, p0/m, #-24.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-24.00000000
 // CHECK-ENCODING: [0x00,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d700 <unknown>
 
 fmov z0.d, p0/m, #-25.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-25.00000000
 // CHECK-ENCODING: [0x20,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d720 <unknown>
 
 fmov z0.d, p0/m, #-26.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-26.00000000
 // CHECK-ENCODING: [0x40,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d740 <unknown>
 
 fmov z0.d, p0/m, #-27.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-27.00000000
 // CHECK-ENCODING: [0x60,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d760 <unknown>
 
 fmov z0.d, p0/m, #-28.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-28.00000000
 // CHECK-ENCODING: [0x80,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d780 <unknown>
 
 fmov z0.d, p0/m, #-29.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-29.00000000
 // CHECK-ENCODING: [0xa0,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d7a0 <unknown>
 
 fmov z0.d, p0/m, #-30.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-30.00000000
 // CHECK-ENCODING: [0xc0,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d7c0 <unknown>
 
 fmov z0.d, p0/m, #-31.00000000
 // CHECK-INST: fmov z0.d, p0/m, #-31.00000000
 // CHECK-ENCODING: [0xe0,0xd7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 d7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0d7e0 <unknown>
 
 fmov z0.d, p0/m, #0.12500000
 // CHECK-INST: fmov z0.d, p0/m, #0.12500000
 // CHECK-ENCODING: [0x00,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c800 <unknown>
 
 fmov z0.d, p0/m, #0.13281250
 // CHECK-INST: fmov z0.d, p0/m, #0.13281250
 // CHECK-ENCODING: [0x20,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c820 <unknown>
 
 fmov z0.d, p0/m, #0.14062500
 // CHECK-INST: fmov z0.d, p0/m, #0.14062500
 // CHECK-ENCODING: [0x40,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c840 <unknown>
 
 fmov z0.d, p0/m, #0.14843750
 // CHECK-INST: fmov z0.d, p0/m, #0.14843750
 // CHECK-ENCODING: [0x60,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c860 <unknown>
 
 fmov z0.d, p0/m, #0.15625000
 // CHECK-INST: fmov z0.d, p0/m, #0.15625000
 // CHECK-ENCODING: [0x80,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c880 <unknown>
 
 fmov z0.d, p0/m, #0.16406250
 // CHECK-INST: fmov z0.d, p0/m, #0.16406250
 // CHECK-ENCODING: [0xa0,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c8a0 <unknown>
 
 fmov z0.d, p0/m, #0.17187500
 // CHECK-INST: fmov z0.d, p0/m, #0.17187500
 // CHECK-ENCODING: [0xc0,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c8c0 <unknown>
 
 fmov z0.d, p0/m, #0.17968750
 // CHECK-INST: fmov z0.d, p0/m, #0.17968750
 // CHECK-ENCODING: [0xe0,0xc8,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c8 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c8e0 <unknown>
 
 fmov z0.d, p0/m, #0.18750000
 // CHECK-INST: fmov z0.d, p0/m, #0.18750000
 // CHECK-ENCODING: [0x00,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c900 <unknown>
 
 fmov z0.d, p0/m, #0.19531250
 // CHECK-INST: fmov z0.d, p0/m, #0.19531250
 // CHECK-ENCODING: [0x20,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c920 <unknown>
 
 fmov z0.d, p0/m, #0.20312500
 // CHECK-INST: fmov z0.d, p0/m, #0.20312500
 // CHECK-ENCODING: [0x40,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c940 <unknown>
 
 fmov z0.d, p0/m, #0.21093750
 // CHECK-INST: fmov z0.d, p0/m, #0.21093750
 // CHECK-ENCODING: [0x60,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c960 <unknown>
 
 fmov z0.d, p0/m, #0.21875000
 // CHECK-INST: fmov z0.d, p0/m, #0.21875000
 // CHECK-ENCODING: [0x80,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c980 <unknown>
 
 fmov z0.d, p0/m, #0.22656250
 // CHECK-INST: fmov z0.d, p0/m, #0.22656250
 // CHECK-ENCODING: [0xa0,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c9a0 <unknown>
 
 fmov z0.d, p0/m, #0.23437500
 // CHECK-INST: fmov z0.d, p0/m, #0.23437500
 // CHECK-ENCODING: [0xc0,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c9c0 <unknown>
 
 fmov z0.d, p0/m, #0.24218750
 // CHECK-INST: fmov z0.d, p0/m, #0.24218750
 // CHECK-ENCODING: [0xe0,0xc9,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c9 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c9e0 <unknown>
 
 fmov z0.d, p0/m, #0.25000000
 // CHECK-INST: fmov z0.d, p0/m, #0.25000000
 // CHECK-ENCODING: [0x00,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ca00 <unknown>
 
 fmov z0.d, p0/m, #0.26562500
 // CHECK-INST: fmov z0.d, p0/m, #0.26562500
 // CHECK-ENCODING: [0x20,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ca20 <unknown>
 
 fmov z0.d, p0/m, #0.28125000
 // CHECK-INST: fmov z0.d, p0/m, #0.28125000
 // CHECK-ENCODING: [0x40,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ca40 <unknown>
 
 fmov z0.d, p0/m, #0.29687500
 // CHECK-INST: fmov z0.d, p0/m, #0.29687500
 // CHECK-ENCODING: [0x60,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ca60 <unknown>
 
 fmov z0.d, p0/m, #0.31250000
 // CHECK-INST: fmov z0.d, p0/m, #0.31250000
 // CHECK-ENCODING: [0x80,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ca80 <unknown>
 
 fmov z0.d, p0/m, #0.32812500
 // CHECK-INST: fmov z0.d, p0/m, #0.32812500
 // CHECK-ENCODING: [0xa0,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0caa0 <unknown>
 
 fmov z0.d, p0/m, #0.34375000
 // CHECK-INST: fmov z0.d, p0/m, #0.34375000
 // CHECK-ENCODING: [0xc0,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cac0 <unknown>
 
 fmov z0.d, p0/m, #0.35937500
 // CHECK-INST: fmov z0.d, p0/m, #0.35937500
 // CHECK-ENCODING: [0xe0,0xca,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ca d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cae0 <unknown>
 
 fmov z0.d, p0/m, #0.37500000
 // CHECK-INST: fmov z0.d, p0/m, #0.37500000
 // CHECK-ENCODING: [0x00,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cb00 <unknown>
 
 fmov z0.d, p0/m, #0.39062500
 // CHECK-INST: fmov z0.d, p0/m, #0.39062500
 // CHECK-ENCODING: [0x20,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cb20 <unknown>
 
 fmov z0.d, p0/m, #0.40625000
 // CHECK-INST: fmov z0.d, p0/m, #0.40625000
 // CHECK-ENCODING: [0x40,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cb40 <unknown>
 
 fmov z0.d, p0/m, #0.42187500
 // CHECK-INST: fmov z0.d, p0/m, #0.42187500
 // CHECK-ENCODING: [0x60,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cb60 <unknown>
 
 fmov z0.d, p0/m, #0.43750000
 // CHECK-INST: fmov z0.d, p0/m, #0.43750000
 // CHECK-ENCODING: [0x80,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cb80 <unknown>
 
 fmov z0.d, p0/m, #0.45312500
 // CHECK-INST: fmov z0.d, p0/m, #0.45312500
 // CHECK-ENCODING: [0xa0,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cba0 <unknown>
 
 fmov z0.d, p0/m, #0.46875000
 // CHECK-INST: fmov z0.d, p0/m, #0.46875000
 // CHECK-ENCODING: [0xc0,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cbc0 <unknown>
 
 fmov z0.d, p0/m, #0.48437500
 // CHECK-INST: fmov z0.d, p0/m, #0.48437500
 // CHECK-ENCODING: [0xe0,0xcb,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cbe0 <unknown>
 
 fmov z0.d, p0/m, #0.50000000
 // CHECK-INST: fmov z0.d, p0/m, #0.50000000
 // CHECK-ENCODING: [0x00,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cc00 <unknown>
 
 fmov z0.d, p0/m, #0.53125000
 // CHECK-INST: fmov z0.d, p0/m, #0.53125000
 // CHECK-ENCODING: [0x20,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cc20 <unknown>
 
 fmov z0.d, p0/m, #0.56250000
 // CHECK-INST: fmov z0.d, p0/m, #0.56250000
 // CHECK-ENCODING: [0x40,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cc40 <unknown>
 
 fmov z0.d, p0/m, #0.59375000
 // CHECK-INST: fmov z0.d, p0/m, #0.59375000
 // CHECK-ENCODING: [0x60,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cc60 <unknown>
 
 fmov z0.d, p0/m, #0.62500000
 // CHECK-INST: fmov z0.d, p0/m, #0.62500000
 // CHECK-ENCODING: [0x80,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cc80 <unknown>
 
 fmov z0.d, p0/m, #0.65625000
 // CHECK-INST: fmov z0.d, p0/m, #0.65625000
 // CHECK-ENCODING: [0xa0,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cca0 <unknown>
 
 fmov z0.d, p0/m, #0.68750000
 // CHECK-INST: fmov z0.d, p0/m, #0.68750000
 // CHECK-ENCODING: [0xc0,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ccc0 <unknown>
 
 fmov z0.d, p0/m, #0.71875000
 // CHECK-INST: fmov z0.d, p0/m, #0.71875000
 // CHECK-ENCODING: [0xe0,0xcc,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cc d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cce0 <unknown>
 
 fmov z0.d, p0/m, #0.75000000
 // CHECK-INST: fmov z0.d, p0/m, #0.75000000
 // CHECK-ENCODING: [0x00,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cd00 <unknown>
 
 fmov z0.d, p0/m, #0.78125000
 // CHECK-INST: fmov z0.d, p0/m, #0.78125000
 // CHECK-ENCODING: [0x20,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cd20 <unknown>
 
 fmov z0.d, p0/m, #0.81250000
 // CHECK-INST: fmov z0.d, p0/m, #0.81250000
 // CHECK-ENCODING: [0x40,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cd40 <unknown>
 
 fmov z0.d, p0/m, #0.84375000
 // CHECK-INST: fmov z0.d, p0/m, #0.84375000
 // CHECK-ENCODING: [0x60,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cd60 <unknown>
 
 fmov z0.d, p0/m, #0.87500000
 // CHECK-INST: fmov z0.d, p0/m, #0.87500000
 // CHECK-ENCODING: [0x80,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cd80 <unknown>
 
 fmov z0.d, p0/m, #0.90625000
 // CHECK-INST: fmov z0.d, p0/m, #0.90625000
 // CHECK-ENCODING: [0xa0,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cda0 <unknown>
 
 fmov z0.d, p0/m, #0.93750000
 // CHECK-INST: fmov z0.d, p0/m, #0.93750000
 // CHECK-ENCODING: [0xc0,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cdc0 <unknown>
 
 fmov z0.d, p0/m, #0.96875000
 // CHECK-INST: fmov z0.d, p0/m, #0.96875000
 // CHECK-ENCODING: [0xe0,0xcd,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cd d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cde0 <unknown>
 
 fmov z0.d, p0/m, #1.00000000
 // CHECK-INST: fmov z0.d, p0/m, #1.00000000
 // CHECK-ENCODING: [0x00,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ce00 <unknown>
 
 fmov z0.d, p0/m, #1.06250000
 // CHECK-INST: fmov z0.d, p0/m, #1.06250000
 // CHECK-ENCODING: [0x20,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ce20 <unknown>
 
 fmov z0.d, p0/m, #1.12500000
 // CHECK-INST: fmov z0.d, p0/m, #1.12500000
 // CHECK-ENCODING: [0x40,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ce40 <unknown>
 
 fmov z0.d, p0/m, #1.18750000
 // CHECK-INST: fmov z0.d, p0/m, #1.18750000
 // CHECK-ENCODING: [0x60,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ce60 <unknown>
 
 fmov z0.d, p0/m, #1.25000000
 // CHECK-INST: fmov z0.d, p0/m, #1.25000000
 // CHECK-ENCODING: [0x80,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0ce80 <unknown>
 
 fmov z0.d, p0/m, #1.31250000
 // CHECK-INST: fmov z0.d, p0/m, #1.31250000
 // CHECK-ENCODING: [0xa0,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cea0 <unknown>
 
 fmov z0.d, p0/m, #1.37500000
 // CHECK-INST: fmov z0.d, p0/m, #1.37500000
 // CHECK-ENCODING: [0xc0,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cec0 <unknown>
 
 fmov z0.d, p0/m, #1.43750000
 // CHECK-INST: fmov z0.d, p0/m, #1.43750000
 // CHECK-ENCODING: [0xe0,0xce,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ce d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cee0 <unknown>
 
 fmov z0.d, p0/m, #1.50000000
 // CHECK-INST: fmov z0.d, p0/m, #1.50000000
 // CHECK-ENCODING: [0x00,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cf00 <unknown>
 
 fmov z0.d, p0/m, #1.56250000
 // CHECK-INST: fmov z0.d, p0/m, #1.56250000
 // CHECK-ENCODING: [0x20,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cf20 <unknown>
 
 fmov z0.d, p0/m, #1.62500000
 // CHECK-INST: fmov z0.d, p0/m, #1.62500000
 // CHECK-ENCODING: [0x40,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cf40 <unknown>
 
 fmov z0.d, p0/m, #1.68750000
 // CHECK-INST: fmov z0.d, p0/m, #1.68750000
 // CHECK-ENCODING: [0x60,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cf60 <unknown>
 
 fmov z0.d, p0/m, #1.75000000
 // CHECK-INST: fmov z0.d, p0/m, #1.75000000
 // CHECK-ENCODING: [0x80,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cf80 <unknown>
 
 fmov z0.d, p0/m, #1.81250000
 // CHECK-INST: fmov z0.d, p0/m, #1.81250000
 // CHECK-ENCODING: [0xa0,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cfa0 <unknown>
 
 fmov z0.d, p0/m, #1.87500000
 // CHECK-INST: fmov z0.d, p0/m, #1.87500000
 // CHECK-ENCODING: [0xc0,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cfc0 <unknown>
 
 fmov z0.d, p0/m, #1.93750000
 // CHECK-INST: fmov z0.d, p0/m, #1.93750000
 // CHECK-ENCODING: [0xe0,0xcf,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0cfe0 <unknown>
 
 fmov z0.d, p0/m, #2.00000000
 // CHECK-INST: fmov z0.d, p0/m, #2.00000000
 // CHECK-ENCODING: [0x00,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c000 <unknown>
 
 fmov z0.d, p0/m, #2.12500000
 // CHECK-INST: fmov z0.d, p0/m, #2.12500000
 // CHECK-ENCODING: [0x20,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c020 <unknown>
 
 fmov z0.d, p0/m, #2.25000000
 // CHECK-INST: fmov z0.d, p0/m, #2.25000000
 // CHECK-ENCODING: [0x40,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c040 <unknown>
 
 fmov z0.d, p0/m, #2.37500000
 // CHECK-INST: fmov z0.d, p0/m, #2.37500000
 // CHECK-ENCODING: [0x60,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c060 <unknown>
 
 fmov z0.d, p0/m, #2.50000000
 // CHECK-INST: fmov z0.d, p0/m, #2.50000000
 // CHECK-ENCODING: [0x80,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c080 <unknown>
 
 fmov z0.d, p0/m, #2.62500000
 // CHECK-INST: fmov z0.d, p0/m, #2.62500000
 // CHECK-ENCODING: [0xa0,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c0a0 <unknown>
 
 fmov z0.d, p0/m, #2.75000000
 // CHECK-INST: fmov z0.d, p0/m, #2.75000000
 // CHECK-ENCODING: [0xc0,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c0c0 <unknown>
 
 fmov z0.d, p0/m, #2.87500000
 // CHECK-INST: fmov z0.d, p0/m, #2.87500000
 // CHECK-ENCODING: [0xe0,0xc0,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c0 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c0e0 <unknown>
 
 fmov z0.d, p0/m, #3.00000000
 // CHECK-INST: fmov z0.d, p0/m, #3.00000000
 // CHECK-ENCODING: [0x00,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c100 <unknown>
 
 fmov z0.d, p0/m, #3.12500000
 // CHECK-INST: fmov z0.d, p0/m, #3.12500000
 // CHECK-ENCODING: [0x20,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c120 <unknown>
 
 fmov z0.d, p0/m, #3.25000000
 // CHECK-INST: fmov z0.d, p0/m, #3.25000000
 // CHECK-ENCODING: [0x40,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c140 <unknown>
 
 fmov z0.d, p0/m, #3.37500000
 // CHECK-INST: fmov z0.d, p0/m, #3.37500000
 // CHECK-ENCODING: [0x60,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c160 <unknown>
 
 fmov z0.d, p0/m, #3.50000000
 // CHECK-INST: fmov z0.d, p0/m, #3.50000000
 // CHECK-ENCODING: [0x80,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c180 <unknown>
 
 fmov z0.d, p0/m, #3.62500000
 // CHECK-INST: fmov z0.d, p0/m, #3.62500000
 // CHECK-ENCODING: [0xa0,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c1a0 <unknown>
 
 fmov z0.d, p0/m, #3.75000000
 // CHECK-INST: fmov z0.d, p0/m, #3.75000000
 // CHECK-ENCODING: [0xc0,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c1c0 <unknown>
 
 fmov z0.d, p0/m, #3.87500000
 // CHECK-INST: fmov z0.d, p0/m, #3.87500000
 // CHECK-ENCODING: [0xe0,0xc1,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c1 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c1e0 <unknown>
 
 fmov z0.d, p0/m, #4.00000000
 // CHECK-INST: fmov z0.d, p0/m, #4.00000000
 // CHECK-ENCODING: [0x00,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c200 <unknown>
 
 fmov z0.d, p0/m, #4.25000000
 // CHECK-INST: fmov z0.d, p0/m, #4.25000000
 // CHECK-ENCODING: [0x20,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c220 <unknown>
 
 fmov z0.d, p0/m, #4.50000000
 // CHECK-INST: fmov z0.d, p0/m, #4.50000000
 // CHECK-ENCODING: [0x40,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c240 <unknown>
 
 fmov z0.d, p0/m, #4.75000000
 // CHECK-INST: fmov z0.d, p0/m, #4.75000000
 // CHECK-ENCODING: [0x60,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c260 <unknown>
 
 fmov z0.d, p0/m, #5.00000000
 // CHECK-INST: fmov z0.d, p0/m, #5.00000000
 // CHECK-ENCODING: [0x80,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c280 <unknown>
 
 fmov z0.d, p0/m, #5.25000000
 // CHECK-INST: fmov z0.d, p0/m, #5.25000000
 // CHECK-ENCODING: [0xa0,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c2a0 <unknown>
 
 fmov z0.d, p0/m, #5.50000000
 // CHECK-INST: fmov z0.d, p0/m, #5.50000000
 // CHECK-ENCODING: [0xc0,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c2c0 <unknown>
 
 fmov z0.d, p0/m, #5.75000000
 // CHECK-INST: fmov z0.d, p0/m, #5.75000000
 // CHECK-ENCODING: [0xe0,0xc2,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c2 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c2e0 <unknown>
 
 fmov z0.d, p0/m, #6.00000000
 // CHECK-INST: fmov z0.d, p0/m, #6.00000000
 // CHECK-ENCODING: [0x00,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c300 <unknown>
 
 fmov z0.d, p0/m, #6.25000000
 // CHECK-INST: fmov z0.d, p0/m, #6.25000000
 // CHECK-ENCODING: [0x20,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c320 <unknown>
 
 fmov z0.d, p0/m, #6.50000000
 // CHECK-INST: fmov z0.d, p0/m, #6.50000000
 // CHECK-ENCODING: [0x40,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c340 <unknown>
 
 fmov z0.d, p0/m, #6.75000000
 // CHECK-INST: fmov z0.d, p0/m, #6.75000000
 // CHECK-ENCODING: [0x60,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c360 <unknown>
 
 fmov z0.d, p0/m, #7.00000000
 // CHECK-INST: fmov z0.d, p0/m, #7.00000000
 // CHECK-ENCODING: [0x80,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c380 <unknown>
 
 fmov z0.d, p0/m, #7.25000000
 // CHECK-INST: fmov z0.d, p0/m, #7.25000000
 // CHECK-ENCODING: [0xa0,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c3a0 <unknown>
 
 fmov z0.d, p0/m, #7.50000000
 // CHECK-INST: fmov z0.d, p0/m, #7.50000000
 // CHECK-ENCODING: [0xc0,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c3c0 <unknown>
 
 fmov z0.d, p0/m, #7.75000000
 // CHECK-INST: fmov z0.d, p0/m, #7.75000000
 // CHECK-ENCODING: [0xe0,0xc3,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c3e0 <unknown>
 
 fmov z0.d, p0/m, #8.00000000
 // CHECK-INST: fmov z0.d, p0/m, #8.00000000
 // CHECK-ENCODING: [0x00,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c400 <unknown>
 
 fmov z0.d, p0/m, #8.50000000
 // CHECK-INST: fmov z0.d, p0/m, #8.50000000
 // CHECK-ENCODING: [0x20,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c420 <unknown>
 
 fmov z0.d, p0/m, #9.00000000
 // CHECK-INST: fmov z0.d, p0/m, #9.00000000
 // CHECK-ENCODING: [0x40,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c440 <unknown>
 
 fmov z0.d, p0/m, #9.50000000
 // CHECK-INST: fmov z0.d, p0/m, #9.50000000
 // CHECK-ENCODING: [0x60,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c460 <unknown>
 
 fmov z0.d, p0/m, #10.00000000
 // CHECK-INST: fmov z0.d, p0/m, #10.00000000
 // CHECK-ENCODING: [0x80,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c480 <unknown>
 
 fmov z0.d, p0/m, #10.50000000
 // CHECK-INST: fmov z0.d, p0/m, #10.50000000
 // CHECK-ENCODING: [0xa0,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c4a0 <unknown>
 
 fmov z0.d, p0/m, #11.00000000
 // CHECK-INST: fmov z0.d, p0/m, #11.00000000
 // CHECK-ENCODING: [0xc0,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c4c0 <unknown>
 
 fmov z0.d, p0/m, #11.50000000
 // CHECK-INST: fmov z0.d, p0/m, #11.50000000
 // CHECK-ENCODING: [0xe0,0xc4,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c4 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c4e0 <unknown>
 
 fmov z0.d, p0/m, #12.00000000
 // CHECK-INST: fmov z0.d, p0/m, #12.00000000
 // CHECK-ENCODING: [0x00,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c500 <unknown>
 
 fmov z0.d, p0/m, #12.50000000
 // CHECK-INST: fmov z0.d, p0/m, #12.50000000
 // CHECK-ENCODING: [0x20,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c520 <unknown>
 
 fmov z0.d, p0/m, #13.00000000
 // CHECK-INST: fmov z0.d, p0/m, #13.00000000
 // CHECK-ENCODING: [0x40,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c540 <unknown>
 
 fmov z0.d, p0/m, #13.50000000
 // CHECK-INST: fmov z0.d, p0/m, #13.50000000
 // CHECK-ENCODING: [0x60,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c560 <unknown>
 
 fmov z0.d, p0/m, #14.00000000
 // CHECK-INST: fmov z0.d, p0/m, #14.00000000
 // CHECK-ENCODING: [0x80,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c580 <unknown>
 
 fmov z0.d, p0/m, #14.50000000
 // CHECK-INST: fmov z0.d, p0/m, #14.50000000
 // CHECK-ENCODING: [0xa0,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c5a0 <unknown>
 
 fmov z0.d, p0/m, #15.00000000
 // CHECK-INST: fmov z0.d, p0/m, #15.00000000
 // CHECK-ENCODING: [0xc0,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c5c0 <unknown>
 
 fmov z0.d, p0/m, #15.50000000
 // CHECK-INST: fmov z0.d, p0/m, #15.50000000
 // CHECK-ENCODING: [0xe0,0xc5,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c5 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c5e0 <unknown>
 
 fmov z0.d, p0/m, #16.00000000
 // CHECK-INST: fmov z0.d, p0/m, #16.00000000
 // CHECK-ENCODING: [0x00,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c600 <unknown>
 
 fmov z0.d, p0/m, #17.00000000
 // CHECK-INST: fmov z0.d, p0/m, #17.00000000
 // CHECK-ENCODING: [0x20,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c620 <unknown>
 
 fmov z0.d, p0/m, #18.00000000
 // CHECK-INST: fmov z0.d, p0/m, #18.00000000
 // CHECK-ENCODING: [0x40,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c640 <unknown>
 
 fmov z0.d, p0/m, #19.00000000
 // CHECK-INST: fmov z0.d, p0/m, #19.00000000
 // CHECK-ENCODING: [0x60,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c660 <unknown>
 
 fmov z0.d, p0/m, #20.00000000
 // CHECK-INST: fmov z0.d, p0/m, #20.00000000
 // CHECK-ENCODING: [0x80,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c680 <unknown>
 
 fmov z0.d, p0/m, #21.00000000
 // CHECK-INST: fmov z0.d, p0/m, #21.00000000
 // CHECK-ENCODING: [0xa0,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c6a0 <unknown>
 
 fmov z0.d, p0/m, #22.00000000
 // CHECK-INST: fmov z0.d, p0/m, #22.00000000
 // CHECK-ENCODING: [0xc0,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c6c0 <unknown>
 
 fmov z0.d, p0/m, #23.00000000
 // CHECK-INST: fmov z0.d, p0/m, #23.00000000
 // CHECK-ENCODING: [0xe0,0xc6,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c6 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c6e0 <unknown>
 
 fmov z0.d, p0/m, #24.00000000
 // CHECK-INST: fmov z0.d, p0/m, #24.00000000
 // CHECK-ENCODING: [0x00,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c700 <unknown>
 
 fmov z0.d, p0/m, #25.00000000
 // CHECK-INST: fmov z0.d, p0/m, #25.00000000
 // CHECK-ENCODING: [0x20,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c720 <unknown>
 
 fmov z0.d, p0/m, #26.00000000
 // CHECK-INST: fmov z0.d, p0/m, #26.00000000
 // CHECK-ENCODING: [0x40,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c740 <unknown>
 
 fmov z0.d, p0/m, #27.00000000
 // CHECK-INST: fmov z0.d, p0/m, #27.00000000
 // CHECK-ENCODING: [0x60,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c760 <unknown>
 
 fmov z0.d, p0/m, #28.00000000
 // CHECK-INST: fmov z0.d, p0/m, #28.00000000
 // CHECK-ENCODING: [0x80,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c780 <unknown>
 
 fmov z0.d, p0/m, #29.00000000
 // CHECK-INST: fmov z0.d, p0/m, #29.00000000
 // CHECK-ENCODING: [0xa0,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c7a0 <unknown>
 
 fmov z0.d, p0/m, #30.00000000
 // CHECK-INST: fmov z0.d, p0/m, #30.00000000
 // CHECK-ENCODING: [0xc0,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c7c0 <unknown>
 
 fmov z0.d, p0/m, #31.00000000
 // CHECK-INST: fmov z0.d, p0/m, #31.00000000
 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c7e0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -1607,22 +1607,22 @@ movprfx z0.d, p0/z, z7.d
 // CHECK-INST: movprfx	z0.d, p0/z, z7.d
 // CHECK-ENCODING: [0xe0,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020e0 <unknown>
 
 fmov z0.d, p0/m, #31.00000000
 // CHECK-INST: fmov	z0.d, p0/m, #31.00000000
 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c7e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fmov z0.d, p0/m, #31.00000000
 // CHECK-INST: fmov	z0.d, p0/m, #31.00000000
 // CHECK-ENCODING: [0xe0,0xc7,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 d0 05 <unknown>
+// CHECK-UNKNOWN: 05d0c7e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fmsb.s b/llvm/test/MC/AArch64/SVE/fmsb.s
index 21e3d58ea0559..5394e3dd8b7ed 100644
--- a/llvm/test/MC/AArch64/SVE/fmsb.s
+++ b/llvm/test/MC/AArch64/SVE/fmsb.s
@@ -13,19 +13,19 @@ fmsb z0.h, p7/m, z1.h, z31.h
 // CHECK-INST: fmsb	z0.h, p7/m, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0xbc,0x7f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 bc 7f 65 <unknown>
+// CHECK-UNKNOWN: 657fbc20 <unknown>
 
 fmsb z0.s, p7/m, z1.s, z31.s
 // CHECK-INST: fmsb	z0.s, p7/m, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xbc,0xbf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 bc bf 65 <unknown>
+// CHECK-UNKNOWN: 65bfbc20 <unknown>
 
 fmsb z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fmsb	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xbc,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 bc ff 65 <unknown>
+// CHECK-UNKNOWN: 65ffbc20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fmsb z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fmsb	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xbc,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 bc ff 65 <unknown>
+// CHECK-UNKNOWN: 65ffbc20 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fmsb z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fmsb	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xbc,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 bc ff 65 <unknown>
+// CHECK-UNKNOWN: 65ffbc20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fmul.s b/llvm/test/MC/AArch64/SVE/fmul.s
index 26597d7996635..474203b2602cb 100644
--- a/llvm/test/MC/AArch64/SVE/fmul.s
+++ b/llvm/test/MC/AArch64/SVE/fmul.s
@@ -13,115 +13,115 @@ fmul    z0.h, p0/m, z0.h, #0.5000000000000
 // CHECK-INST: fmul    z0.h, p0/m, z0.h, #0.5
 // CHECK-ENCODING: [0x00,0x80,0x5a,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 5a 65 <unknown>
+// CHECK-UNKNOWN: 655a8000 <unknown>
 
 fmul    z0.h, p0/m, z0.h, #0.5
 // CHECK-INST: fmul    z0.h, p0/m, z0.h, #0.5
 // CHECK-ENCODING: [0x00,0x80,0x5a,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 5a 65 <unknown>
+// CHECK-UNKNOWN: 655a8000 <unknown>
 
 fmul    z0.s, p0/m, z0.s, #0.5
 // CHECK-INST: fmul    z0.s, p0/m, z0.s, #0.5
 // CHECK-ENCODING: [0x00,0x80,0x9a,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 9a 65 <unknown>
+// CHECK-UNKNOWN: 659a8000 <unknown>
 
 fmul    z0.d, p0/m, z0.d, #0.5
 // CHECK-INST: fmul    z0.d, p0/m, z0.d, #0.5
 // CHECK-ENCODING: [0x00,0x80,0xda,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 da 65 <unknown>
+// CHECK-UNKNOWN: 65da8000 <unknown>
 
 fmul    z31.h, p7/m, z31.h, #2.0
 // CHECK-INST: fmul    z31.h, p7/m, z31.h, #2.0
 // CHECK-ENCODING: [0x3f,0x9c,0x5a,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 5a 65 <unknown>
+// CHECK-UNKNOWN: 655a9c3f <unknown>
 
 fmul    z31.s, p7/m, z31.s, #2.0
 // CHECK-INST: fmul    z31.s, p7/m, z31.s, #2.0
 // CHECK-ENCODING: [0x3f,0x9c,0x9a,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 9a 65 <unknown>
+// CHECK-UNKNOWN: 659a9c3f <unknown>
 
 fmul    z31.d, p7/m, z31.d, #2.0
 // CHECK-INST: fmul    z31.d, p7/m, z31.d, #2.0
 // CHECK-ENCODING: [0x3f,0x9c,0xda,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c da 65 <unknown>
+// CHECK-UNKNOWN: 65da9c3f <unknown>
 
 fmul    z0.h, z0.h, z0.h[0]
 // CHECK-INST: fmul    z0.h, z0.h, z0.h[0]
 // CHECK-ENCODING: [0x00,0x20,0x20,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 20 64 <unknown>
+// CHECK-UNKNOWN: 64202000 <unknown>
 
 fmul    z0.s, z0.s, z0.s[0]
 // CHECK-INST: fmul    z0.s, z0.s, z0.s[0]
 // CHECK-ENCODING: [0x00,0x20,0xa0,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 a0 64 <unknown>
+// CHECK-UNKNOWN: 64a02000 <unknown>
 
 fmul    z0.d, z0.d, z0.d[0]
 // CHECK-INST: fmul    z0.d, z0.d, z0.d[0]
 // CHECK-ENCODING: [0x00,0x20,0xe0,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 e0 64 <unknown>
+// CHECK-UNKNOWN: 64e02000 <unknown>
 
 fmul    z31.h, z31.h, z7.h[7]
 // CHECK-INST: fmul    z31.h, z31.h, z7.h[7]
 // CHECK-ENCODING: [0xff,0x23,0x7f,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 23 7f 64 <unknown>
+// CHECK-UNKNOWN: 647f23ff <unknown>
 
 fmul    z31.s, z31.s, z7.s[3]
 // CHECK-INST: fmul    z31.s, z31.s, z7.s[3]
 // CHECK-ENCODING: [0xff,0x23,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 23 bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf23ff <unknown>
 
 fmul    z31.d, z31.d, z15.d[1]
 // CHECK-INST: fmul    z31.d, z31.d, z15.d[1]
 // CHECK-ENCODING: [0xff,0x23,0xff,0x64]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 23 ff 64 <unknown>
+// CHECK-UNKNOWN: 64ff23ff <unknown>
 
 fmul    z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: fmul	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x42,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 42 65 <unknown>
+// CHECK-UNKNOWN: 65429fe0 <unknown>
 
 fmul    z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: fmul	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0x82,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 82 65 <unknown>
+// CHECK-UNKNOWN: 65829fe0 <unknown>
 
 fmul    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmul	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c2 65 <unknown>
+// CHECK-UNKNOWN: 65c29fe0 <unknown>
 
 fmul z0.h, z1.h, z31.h
 // CHECK-INST: fmul	z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x08,0x5f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 08 5f 65 <unknown>
+// CHECK-UNKNOWN: 655f0820 <unknown>
 
 fmul z0.s, z1.s, z31.s
 // CHECK-INST: fmul	z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x08,0x9f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 08 9f 65 <unknown>
+// CHECK-UNKNOWN: 659f0820 <unknown>
 
 fmul z0.d, z1.d, z31.d
 // CHECK-INST: fmul	z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x08,0xdf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 08 df 65 <unknown>
+// CHECK-UNKNOWN: 65df0820 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -131,46 +131,46 @@ movprfx z31.d, p7/z, z6.d
 // CHECK-INST: movprfx	z31.d, p7/z, z6.d
 // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cdf <unknown>
 
 fmul    z31.d, p7/m, z31.d, #2.0
 // CHECK-INST: fmul	z31.d, p7/m, z31.d, #2.0
 // CHECK-ENCODING: [0x3f,0x9c,0xda,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c da 65 <unknown>
+// CHECK-UNKNOWN: 65da9c3f <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 fmul    z31.d, p7/m, z31.d, #2.0
 // CHECK-INST: fmul	z31.d, p7/m, z31.d, #2.0
 // CHECK-ENCODING: [0x3f,0x9c,0xda,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c da 65 <unknown>
+// CHECK-UNKNOWN: 65da9c3f <unknown>
 
 movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fmul    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmul	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c2 65 <unknown>
+// CHECK-UNKNOWN: 65c29fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fmul    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmul	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc2,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c2 65 <unknown>
+// CHECK-UNKNOWN: 65c29fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fmulx.s b/llvm/test/MC/AArch64/SVE/fmulx.s
index c2fb5bb95048a..e88d7a389fa7c 100644
--- a/llvm/test/MC/AArch64/SVE/fmulx.s
+++ b/llvm/test/MC/AArch64/SVE/fmulx.s
@@ -13,19 +13,19 @@ fmulx   z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: fmulx	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x4a,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 4a 65 <unknown>
+// CHECK-UNKNOWN: 654a9fe0 <unknown>
 
 fmulx   z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: fmulx	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0x8a,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 8a 65 <unknown>
+// CHECK-UNKNOWN: 658a9fe0 <unknown>
 
 fmulx   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmulx	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xca,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f ca 65 <unknown>
+// CHECK-UNKNOWN: 65ca9fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fmulx   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmulx	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xca,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f ca 65 <unknown>
+// CHECK-UNKNOWN: 65ca9fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fmulx   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fmulx	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xca,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f ca 65 <unknown>
+// CHECK-UNKNOWN: 65ca9fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fneg.s b/llvm/test/MC/AArch64/SVE/fneg.s
index f96b3bbe7f977..59ad7ee8799d1 100644
--- a/llvm/test/MC/AArch64/SVE/fneg.s
+++ b/llvm/test/MC/AArch64/SVE/fneg.s
@@ -13,19 +13,19 @@ fneg    z31.h, p7/m, z31.h
 // CHECK-INST: fneg	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x5d,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 5d 04 <unknown>
+// CHECK-UNKNOWN: 045dbfff <unknown>
 
 fneg    z31.s, p7/m, z31.s
 // CHECK-INST: fneg	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x9d,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 9d 04 <unknown>
+// CHECK-UNKNOWN: 049dbfff <unknown>
 
 fneg    z31.d, p7/m, z31.d
 // CHECK-INST: fneg	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xdd,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf dd 04 <unknown>
+// CHECK-UNKNOWN: 04ddbfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 fneg    z4.d, p7/m, z31.d
 // CHECK-INST: fneg	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xdd,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf dd 04 <unknown>
+// CHECK-UNKNOWN: 04ddbfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 fneg    z4.d, p7/m, z31.d
 // CHECK-INST: fneg	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xdd,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf dd 04 <unknown>
+// CHECK-UNKNOWN: 04ddbfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fnmad.s b/llvm/test/MC/AArch64/SVE/fnmad.s
index 2abb4a5f8093f..8fee93c2e20ed 100644
--- a/llvm/test/MC/AArch64/SVE/fnmad.s
+++ b/llvm/test/MC/AArch64/SVE/fnmad.s
@@ -13,19 +13,19 @@ fnmad z0.h, p7/m, z1.h, z31.h
 // CHECK-INST: fnmad	z0.h, p7/m, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0xdc,0x7f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 dc 7f 65 <unknown>
+// CHECK-UNKNOWN: 657fdc20 <unknown>
 
 fnmad z0.s, p7/m, z1.s, z31.s
 // CHECK-INST: fnmad	z0.s, p7/m, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xdc,0xbf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 dc bf 65 <unknown>
+// CHECK-UNKNOWN: 65bfdc20 <unknown>
 
 fnmad z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fnmad	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xdc,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 dc ff 65 <unknown>
+// CHECK-UNKNOWN: 65ffdc20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fnmad z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fnmad	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xdc,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 dc ff 65 <unknown>
+// CHECK-UNKNOWN: 65ffdc20 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fnmad z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fnmad	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xdc,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 dc ff 65 <unknown>
+// CHECK-UNKNOWN: 65ffdc20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fnmla.s b/llvm/test/MC/AArch64/SVE/fnmla.s
index cca341210429c..eb922ec94ba4f 100644
--- a/llvm/test/MC/AArch64/SVE/fnmla.s
+++ b/llvm/test/MC/AArch64/SVE/fnmla.s
@@ -13,19 +13,19 @@ fnmla z0.h, p7/m, z1.h, z31.h
 // CHECK-INST: fnmla	z0.h, p7/m, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x5c,0x7f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 5c 7f 65 <unknown>
+// CHECK-UNKNOWN: 657f5c20 <unknown>
 
 fnmla z0.s, p7/m, z1.s, z31.s
 // CHECK-INST: fnmla	z0.s, p7/m, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x5c,0xbf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 5c bf 65 <unknown>
+// CHECK-UNKNOWN: 65bf5c20 <unknown>
 
 fnmla z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fnmla	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x5c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 5c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff5c20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fnmla z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fnmla	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x5c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 5c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff5c20 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fnmla z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fnmla	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x5c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 5c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff5c20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fnmls.s b/llvm/test/MC/AArch64/SVE/fnmls.s
index 141018da7f8cd..b56aa4ab946a3 100644
--- a/llvm/test/MC/AArch64/SVE/fnmls.s
+++ b/llvm/test/MC/AArch64/SVE/fnmls.s
@@ -13,19 +13,19 @@ fnmls z0.h, p7/m, z1.h, z31.h
 // CHECK-INST: fnmls	z0.h, p7/m, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x7c,0x7f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 7c 7f 65 <unknown>
+// CHECK-UNKNOWN: 657f7c20 <unknown>
 
 fnmls z0.s, p7/m, z1.s, z31.s
 // CHECK-INST: fnmls	z0.s, p7/m, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x7c,0xbf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 7c bf 65 <unknown>
+// CHECK-UNKNOWN: 65bf7c20 <unknown>
 
 fnmls z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fnmls	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x7c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 7c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff7c20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fnmls z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fnmls	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x7c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 7c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff7c20 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fnmls z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fnmls	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x7c,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 7c ff 65 <unknown>
+// CHECK-UNKNOWN: 65ff7c20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fnmsb.s b/llvm/test/MC/AArch64/SVE/fnmsb.s
index cbeb3282488f9..f8e1218d6683f 100644
--- a/llvm/test/MC/AArch64/SVE/fnmsb.s
+++ b/llvm/test/MC/AArch64/SVE/fnmsb.s
@@ -13,19 +13,19 @@ fnmsb z0.h, p7/m, z1.h, z31.h
 // CHECK-INST: fnmsb	z0.h, p7/m, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0xfc,0x7f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fc 7f 65 <unknown>
+// CHECK-UNKNOWN: 657ffc20 <unknown>
 
 fnmsb z0.s, p7/m, z1.s, z31.s
 // CHECK-INST: fnmsb	z0.s, p7/m, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xfc,0xbf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fc bf 65 <unknown>
+// CHECK-UNKNOWN: 65bffc20 <unknown>
 
 fnmsb z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fnmsb	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xfc,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fc ff 65 <unknown>
+// CHECK-UNKNOWN: 65fffc20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fnmsb z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fnmsb	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xfc,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fc ff 65 <unknown>
+// CHECK-UNKNOWN: 65fffc20 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fnmsb z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: fnmsb	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xfc,0xff,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fc ff 65 <unknown>
+// CHECK-UNKNOWN: 65fffc20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/frecpe.s b/llvm/test/MC/AArch64/SVE/frecpe.s
index 153755757d986..79607519c491e 100644
--- a/llvm/test/MC/AArch64/SVE/frecpe.s
+++ b/llvm/test/MC/AArch64/SVE/frecpe.s
@@ -13,16 +13,16 @@ frecpe   z0.h, z31.h
 // CHECK-INST: frecpe	z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x33,0x4e,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 33 4e 65 <unknown>
+// CHECK-UNKNOWN: 654e33e0 <unknown>
 
 frecpe   z0.s, z31.s
 // CHECK-INST: frecpe	z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x33,0x8e,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 33 8e 65 <unknown>
+// CHECK-UNKNOWN: 658e33e0 <unknown>
 
 frecpe   z0.d, z31.d
 // CHECK-INST: frecpe	z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x33,0xce,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 33 ce 65 <unknown>
+// CHECK-UNKNOWN: 65ce33e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/frecps.s b/llvm/test/MC/AArch64/SVE/frecps.s
index 7aef78deabf5e..2ddd4b75a65b2 100644
--- a/llvm/test/MC/AArch64/SVE/frecps.s
+++ b/llvm/test/MC/AArch64/SVE/frecps.s
@@ -13,16 +13,16 @@ frecps z0.h, z1.h, z31.h
 // CHECK-INST: frecps	z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x18,0x5f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 18 5f 65 <unknown>
+// CHECK-UNKNOWN: 655f1820 <unknown>
 
 frecps z0.s, z1.s, z31.s
 // CHECK-INST: frecps	z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x18,0x9f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 18 9f 65 <unknown>
+// CHECK-UNKNOWN: 659f1820 <unknown>
 
 frecps z0.d, z1.d, z31.d
 // CHECK-INST: frecps	z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x18,0xdf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 18 df 65 <unknown>
+// CHECK-UNKNOWN: 65df1820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/frecpx.s b/llvm/test/MC/AArch64/SVE/frecpx.s
index deae634ef1ed6..b89254a2dbf55 100644
--- a/llvm/test/MC/AArch64/SVE/frecpx.s
+++ b/llvm/test/MC/AArch64/SVE/frecpx.s
@@ -13,19 +13,19 @@ frecpx   z31.h, p7/m, z31.h
 // CHECK-INST: frecpx	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x4c,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 4c 65 <unknown>
+// CHECK-UNKNOWN: 654cbfff <unknown>
 
 frecpx   z31.s, p7/m, z31.s
 // CHECK-INST: frecpx	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x8c,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 8c 65 <unknown>
+// CHECK-UNKNOWN: 658cbfff <unknown>
 
 frecpx   z31.d, p7/m, z31.d
 // CHECK-INST: frecpx	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xcc,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf cc 65 <unknown>
+// CHECK-UNKNOWN: 65ccbfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 frecpx   z4.d, p7/m, z31.d
 // CHECK-INST: frecpx	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xcc,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf cc 65 <unknown>
+// CHECK-UNKNOWN: 65ccbfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 frecpx   z4.d, p7/m, z31.d
 // CHECK-INST: frecpx	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xcc,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf cc 65 <unknown>
+// CHECK-UNKNOWN: 65ccbfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/frinta.s b/llvm/test/MC/AArch64/SVE/frinta.s
index ee4359d7df9b2..feb5e5b07fcd8 100644
--- a/llvm/test/MC/AArch64/SVE/frinta.s
+++ b/llvm/test/MC/AArch64/SVE/frinta.s
@@ -13,19 +13,19 @@ frinta   z31.h, p7/m, z31.h
 // CHECK-INST: frinta	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x44,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 44 65 <unknown>
+// CHECK-UNKNOWN: 6544bfff <unknown>
 
 frinta   z31.s, p7/m, z31.s
 // CHECK-INST: frinta	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x84,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 84 65 <unknown>
+// CHECK-UNKNOWN: 6584bfff <unknown>
 
 frinta   z31.d, p7/m, z31.d
 // CHECK-INST: frinta	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xc4,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf c4 65 <unknown>
+// CHECK-UNKNOWN: 65c4bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 frinta   z4.d, p7/m, z31.d
 // CHECK-INST: frinta	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc4,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c4 65 <unknown>
+// CHECK-UNKNOWN: 65c4bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 frinta   z4.d, p7/m, z31.d
 // CHECK-INST: frinta	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc4,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c4 65 <unknown>
+// CHECK-UNKNOWN: 65c4bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/frinti.s b/llvm/test/MC/AArch64/SVE/frinti.s
index ce240fab294c2..edb5ed35a8257 100644
--- a/llvm/test/MC/AArch64/SVE/frinti.s
+++ b/llvm/test/MC/AArch64/SVE/frinti.s
@@ -13,19 +13,19 @@ frinti   z31.h, p7/m, z31.h
 // CHECK-INST: frinti	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x47,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 47 65 <unknown>
+// CHECK-UNKNOWN: 6547bfff <unknown>
 
 frinti   z31.s, p7/m, z31.s
 // CHECK-INST: frinti	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x87,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 87 65 <unknown>
+// CHECK-UNKNOWN: 6587bfff <unknown>
 
 frinti   z31.d, p7/m, z31.d
 // CHECK-INST: frinti	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xc7,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf c7 65 <unknown>
+// CHECK-UNKNOWN: 65c7bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 frinti   z4.d, p7/m, z31.d
 // CHECK-INST: frinti	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc7,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c7 65 <unknown>
+// CHECK-UNKNOWN: 65c7bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 frinti   z4.d, p7/m, z31.d
 // CHECK-INST: frinti	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc7,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c7 65 <unknown>
+// CHECK-UNKNOWN: 65c7bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/frintm.s b/llvm/test/MC/AArch64/SVE/frintm.s
index 9886dfe060966..4a9891fbaca34 100644
--- a/llvm/test/MC/AArch64/SVE/frintm.s
+++ b/llvm/test/MC/AArch64/SVE/frintm.s
@@ -13,19 +13,19 @@ frintm   z31.h, p7/m, z31.h
 // CHECK-INST: frintm	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x42,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 42 65 <unknown>
+// CHECK-UNKNOWN: 6542bfff <unknown>
 
 frintm   z31.s, p7/m, z31.s
 // CHECK-INST: frintm	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x82,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 82 65 <unknown>
+// CHECK-UNKNOWN: 6582bfff <unknown>
 
 frintm   z31.d, p7/m, z31.d
 // CHECK-INST: frintm	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xc2,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf c2 65 <unknown>
+// CHECK-UNKNOWN: 65c2bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 frintm   z4.d, p7/m, z31.d
 // CHECK-INST: frintm	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc2,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c2 65 <unknown>
+// CHECK-UNKNOWN: 65c2bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 frintm   z4.d, p7/m, z31.d
 // CHECK-INST: frintm	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc2,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c2 65 <unknown>
+// CHECK-UNKNOWN: 65c2bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/frintn.s b/llvm/test/MC/AArch64/SVE/frintn.s
index c42df7bc05cf3..df7d91122a372 100644
--- a/llvm/test/MC/AArch64/SVE/frintn.s
+++ b/llvm/test/MC/AArch64/SVE/frintn.s
@@ -13,19 +13,19 @@ frintn   z31.h, p7/m, z31.h
 // CHECK-INST: frintn	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x40,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 40 65 <unknown>
+// CHECK-UNKNOWN: 6540bfff <unknown>
 
 frintn   z31.s, p7/m, z31.s
 // CHECK-INST: frintn	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x80,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 80 65 <unknown>
+// CHECK-UNKNOWN: 6580bfff <unknown>
 
 frintn   z31.d, p7/m, z31.d
 // CHECK-INST: frintn	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xc0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf c0 65 <unknown>
+// CHECK-UNKNOWN: 65c0bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 frintn   z4.d, p7/m, z31.d
 // CHECK-INST: frintn	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c0 65 <unknown>
+// CHECK-UNKNOWN: 65c0bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 frintn   z4.d, p7/m, z31.d
 // CHECK-INST: frintn	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c0 65 <unknown>
+// CHECK-UNKNOWN: 65c0bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/frintp.s b/llvm/test/MC/AArch64/SVE/frintp.s
index d1c58f012c934..b55c18a2e7200 100644
--- a/llvm/test/MC/AArch64/SVE/frintp.s
+++ b/llvm/test/MC/AArch64/SVE/frintp.s
@@ -13,19 +13,19 @@ frintp   z31.h, p7/m, z31.h
 // CHECK-INST: frintp	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x41,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 41 65 <unknown>
+// CHECK-UNKNOWN: 6541bfff <unknown>
 
 frintp   z31.s, p7/m, z31.s
 // CHECK-INST: frintp	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x81,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 81 65 <unknown>
+// CHECK-UNKNOWN: 6581bfff <unknown>
 
 frintp   z31.d, p7/m, z31.d
 // CHECK-INST: frintp	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xc1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf c1 65 <unknown>
+// CHECK-UNKNOWN: 65c1bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 frintp   z4.d, p7/m, z31.d
 // CHECK-INST: frintp	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c1 65 <unknown>
+// CHECK-UNKNOWN: 65c1bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 frintp   z4.d, p7/m, z31.d
 // CHECK-INST: frintp	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c1 65 <unknown>
+// CHECK-UNKNOWN: 65c1bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/frintx.s b/llvm/test/MC/AArch64/SVE/frintx.s
index f254e1f2a88e8..791cc45c848e4 100644
--- a/llvm/test/MC/AArch64/SVE/frintx.s
+++ b/llvm/test/MC/AArch64/SVE/frintx.s
@@ -13,19 +13,19 @@ frintx   z31.h, p7/m, z31.h
 // CHECK-INST: frintx	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x46,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 46 65 <unknown>
+// CHECK-UNKNOWN: 6546bfff <unknown>
 
 frintx   z31.s, p7/m, z31.s
 // CHECK-INST: frintx	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x86,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 86 65 <unknown>
+// CHECK-UNKNOWN: 6586bfff <unknown>
 
 frintx   z31.d, p7/m, z31.d
 // CHECK-INST: frintx	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xc6,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf c6 65 <unknown>
+// CHECK-UNKNOWN: 65c6bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 frintx   z4.d, p7/m, z31.d
 // CHECK-INST: frintx	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc6,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c6 65 <unknown>
+// CHECK-UNKNOWN: 65c6bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 frintx   z4.d, p7/m, z31.d
 // CHECK-INST: frintx	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc6,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c6 65 <unknown>
+// CHECK-UNKNOWN: 65c6bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/frintz.s b/llvm/test/MC/AArch64/SVE/frintz.s
index b67558d84a646..566f218081d4e 100644
--- a/llvm/test/MC/AArch64/SVE/frintz.s
+++ b/llvm/test/MC/AArch64/SVE/frintz.s
@@ -13,19 +13,19 @@ frintz   z31.h, p7/m, z31.h
 // CHECK-INST: frintz	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x43,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 43 65 <unknown>
+// CHECK-UNKNOWN: 6543bfff <unknown>
 
 frintz   z31.s, p7/m, z31.s
 // CHECK-INST: frintz	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x83,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 83 65 <unknown>
+// CHECK-UNKNOWN: 6583bfff <unknown>
 
 frintz   z31.d, p7/m, z31.d
 // CHECK-INST: frintz	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xc3,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf c3 65 <unknown>
+// CHECK-UNKNOWN: 65c3bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 frintz   z4.d, p7/m, z31.d
 // CHECK-INST: frintz	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc3,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c3 65 <unknown>
+// CHECK-UNKNOWN: 65c3bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 frintz   z4.d, p7/m, z31.d
 // CHECK-INST: frintz	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xc3,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf c3 65 <unknown>
+// CHECK-UNKNOWN: 65c3bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/frsqrte.s b/llvm/test/MC/AArch64/SVE/frsqrte.s
index f70573a7fdf5d..15c282badaf34 100644
--- a/llvm/test/MC/AArch64/SVE/frsqrte.s
+++ b/llvm/test/MC/AArch64/SVE/frsqrte.s
@@ -13,16 +13,16 @@ frsqrte  z0.h, z31.h
 // CHECK-INST: frsqrte	z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x33,0x4f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 33 4f 65 <unknown>
+// CHECK-UNKNOWN: 654f33e0 <unknown>
 
 frsqrte  z0.s, z31.s
 // CHECK-INST: frsqrte	z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x33,0x8f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 33 8f 65 <unknown>
+// CHECK-UNKNOWN: 658f33e0 <unknown>
 
 frsqrte  z0.d, z31.d
 // CHECK-INST: frsqrte	z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x33,0xcf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 33 cf 65 <unknown>
+// CHECK-UNKNOWN: 65cf33e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/frsqrts.s b/llvm/test/MC/AArch64/SVE/frsqrts.s
index 99bdfd627b6ff..dfe48d1aaba38 100644
--- a/llvm/test/MC/AArch64/SVE/frsqrts.s
+++ b/llvm/test/MC/AArch64/SVE/frsqrts.s
@@ -13,16 +13,16 @@ frsqrts z0.h, z1.h, z31.h
 // CHECK-INST: frsqrts	z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x1c,0x5f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 1c 5f 65 <unknown>
+// CHECK-UNKNOWN: 655f1c20 <unknown>
 
 frsqrts z0.s, z1.s, z31.s
 // CHECK-INST: frsqrts	z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x1c,0x9f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 1c 9f 65 <unknown>
+// CHECK-UNKNOWN: 659f1c20 <unknown>
 
 frsqrts z0.d, z1.d, z31.d
 // CHECK-INST: frsqrts	z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x1c,0xdf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 1c df 65 <unknown>
+// CHECK-UNKNOWN: 65df1c20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fscale.s b/llvm/test/MC/AArch64/SVE/fscale.s
index 03d1f688e62e4..2a12c778f751e 100644
--- a/llvm/test/MC/AArch64/SVE/fscale.s
+++ b/llvm/test/MC/AArch64/SVE/fscale.s
@@ -13,19 +13,19 @@ fscale  z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: fscale	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x49,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 49 65 <unknown>
+// CHECK-UNKNOWN: 65499fe0 <unknown>
 
 fscale  z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: fscale	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0x89,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 89 65 <unknown>
+// CHECK-UNKNOWN: 65899fe0 <unknown>
 
 fscale  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fscale	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c9 65 <unknown>
+// CHECK-UNKNOWN: 65c99fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fscale  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fscale	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c9 65 <unknown>
+// CHECK-UNKNOWN: 65c99fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fscale  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fscale	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc9,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c9 65 <unknown>
+// CHECK-UNKNOWN: 65c99fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fsqrt.s b/llvm/test/MC/AArch64/SVE/fsqrt.s
index 4bfbeef9a1805..00c4f28834983 100644
--- a/llvm/test/MC/AArch64/SVE/fsqrt.s
+++ b/llvm/test/MC/AArch64/SVE/fsqrt.s
@@ -13,19 +13,19 @@ fsqrt    z31.h, p7/m, z31.h
 // CHECK-INST: fsqrt	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x4d,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 4d 65 <unknown>
+// CHECK-UNKNOWN: 654dbfff <unknown>
 
 fsqrt    z31.s, p7/m, z31.s
 // CHECK-INST: fsqrt	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x8d,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 8d 65 <unknown>
+// CHECK-UNKNOWN: 658dbfff <unknown>
 
 fsqrt    z31.d, p7/m, z31.d
 // CHECK-INST: fsqrt	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xcd,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf cd 65 <unknown>
+// CHECK-UNKNOWN: 65cdbfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 fsqrt    z4.d, p7/m, z31.d
 // CHECK-INST: fsqrt	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xcd,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf cd 65 <unknown>
+// CHECK-UNKNOWN: 65cdbfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 fsqrt    z4.d, p7/m, z31.d
 // CHECK-INST: fsqrt	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xcd,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf cd 65 <unknown>
+// CHECK-UNKNOWN: 65cdbfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fsub.s b/llvm/test/MC/AArch64/SVE/fsub.s
index 2352ad83b51e7..6b72bcfafb143 100644
--- a/llvm/test/MC/AArch64/SVE/fsub.s
+++ b/llvm/test/MC/AArch64/SVE/fsub.s
@@ -13,85 +13,85 @@ fsub    z0.h, p0/m, z0.h, #0.500000000000000
 // CHECK-INST: fsub	z0.h, p0/m, z0.h, #0.5
 // CHECK-ENCODING: [0x00,0x80,0x59,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 59 65 <unknown>
+// CHECK-UNKNOWN: 65598000 <unknown>
 
 fsub    z0.h, p0/m, z0.h, #0.5
 // CHECK-INST: fsub	z0.h, p0/m, z0.h, #0.5
 // CHECK-ENCODING: [0x00,0x80,0x59,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 59 65 <unknown>
+// CHECK-UNKNOWN: 65598000 <unknown>
 
 fsub    z0.s, p0/m, z0.s, #0.5
 // CHECK-INST: fsub	z0.s, p0/m, z0.s, #0.5
 // CHECK-ENCODING: [0x00,0x80,0x99,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 99 65 <unknown>
+// CHECK-UNKNOWN: 65998000 <unknown>
 
 fsub    z0.d, p0/m, z0.d, #0.5
 // CHECK-INST: fsub	z0.d, p0/m, z0.d, #0.5
 // CHECK-ENCODING: [0x00,0x80,0xd9,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 d9 65 <unknown>
+// CHECK-UNKNOWN: 65d98000 <unknown>
 
 fsub    z31.h, p7/m, z31.h, #1.000000000000000
 // CHECK-INST: fsub	z31.h, p7/m, z31.h, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x59,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 59 65 <unknown>
+// CHECK-UNKNOWN: 65599c3f <unknown>
 
 fsub    z31.h, p7/m, z31.h, #1.0
 // CHECK-INST: fsub	z31.h, p7/m, z31.h, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x59,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 59 65 <unknown>
+// CHECK-UNKNOWN: 65599c3f <unknown>
 
 fsub    z31.s, p7/m, z31.s, #1.0
 // CHECK-INST: fsub	z31.s, p7/m, z31.s, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x99,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 99 65 <unknown>
+// CHECK-UNKNOWN: 65999c3f <unknown>
 
 fsub    z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fsub	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c d9 65 <unknown>
+// CHECK-UNKNOWN: 65d99c3f <unknown>
 
 fsub    z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: fsub	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x41,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 41 65 <unknown>
+// CHECK-UNKNOWN: 65419fe0 <unknown>
 
 fsub    z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: fsub	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0x81,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 81 65 <unknown>
+// CHECK-UNKNOWN: 65819fe0 <unknown>
 
 fsub    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fsub	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c1 65 <unknown>
+// CHECK-UNKNOWN: 65c19fe0 <unknown>
 
 fsub z0.h, z1.h, z31.h
 // CHECK-INST: fsub	z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x04,0x5f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 04 5f 65 <unknown>
+// CHECK-UNKNOWN: 655f0420 <unknown>
 
 fsub z0.s, z1.s, z31.s
 // CHECK-INST: fsub	z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x04,0x9f,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 04 9f 65 <unknown>
+// CHECK-UNKNOWN: 659f0420 <unknown>
 
 fsub z0.d, z1.d, z31.d
 // CHECK-INST: fsub	z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x04,0xdf,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 04 df 65 <unknown>
+// CHECK-UNKNOWN: 65df0420 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -101,46 +101,46 @@ movprfx z31.d, p7/z, z6.d
 // CHECK-INST: movprfx	z31.d, p7/z, z6.d
 // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cdf <unknown>
 
 fsub    z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fsub	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c d9 65 <unknown>
+// CHECK-UNKNOWN: 65d99c3f <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 fsub    z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fsub	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xd9,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c d9 65 <unknown>
+// CHECK-UNKNOWN: 65d99c3f <unknown>
 
 movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fsub    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fsub	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c1 65 <unknown>
+// CHECK-UNKNOWN: 65c19fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fsub    z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fsub	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c1 65 <unknown>
+// CHECK-UNKNOWN: 65c19fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/fsubr.s b/llvm/test/MC/AArch64/SVE/fsubr.s
index 413e7eb3f4924..5ee6ce8a58b97 100644
--- a/llvm/test/MC/AArch64/SVE/fsubr.s
+++ b/llvm/test/MC/AArch64/SVE/fsubr.s
@@ -13,67 +13,67 @@ fsubr   z0.h, p0/m, z0.h, #0.500000000000000
 // CHECK-INST: fsubr	z0.h, p0/m, z0.h, #0.5
 // CHECK-ENCODING: [0x00,0x80,0x5b,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 5b 65 <unknown>
+// CHECK-UNKNOWN: 655b8000 <unknown>
 
 fsubr   z0.h, p0/m, z0.h, #0.5
 // CHECK-INST: fsubr	z0.h, p0/m, z0.h, #0.5
 // CHECK-ENCODING: [0x00,0x80,0x5b,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 5b 65 <unknown>
+// CHECK-UNKNOWN: 655b8000 <unknown>
 
 fsubr   z0.s, p0/m, z0.s, #0.5
 // CHECK-INST: fsubr	z0.s, p0/m, z0.s, #0.5
 // CHECK-ENCODING: [0x00,0x80,0x9b,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 9b 65 <unknown>
+// CHECK-UNKNOWN: 659b8000 <unknown>
 
 fsubr   z0.d, p0/m, z0.d, #0.5
 // CHECK-INST: fsubr	z0.d, p0/m, z0.d, #0.5
 // CHECK-ENCODING: [0x00,0x80,0xdb,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 db 65 <unknown>
+// CHECK-UNKNOWN: 65db8000 <unknown>
 
 fsubr   z31.h, p7/m, z31.h, #1.000000000000000
 // CHECK-INST: fsubr	z31.h, p7/m, z31.h, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x5b,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 5b 65 <unknown>
+// CHECK-UNKNOWN: 655b9c3f <unknown>
 
 fsubr   z31.h, p7/m, z31.h, #1.0
 // CHECK-INST: fsubr	z31.h, p7/m, z31.h, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x5b,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 5b 65 <unknown>
+// CHECK-UNKNOWN: 655b9c3f <unknown>
 
 fsubr   z31.s, p7/m, z31.s, #1.0
 // CHECK-INST: fsubr	z31.s, p7/m, z31.s, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0x9b,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c 9b 65 <unknown>
+// CHECK-UNKNOWN: 659b9c3f <unknown>
 
 fsubr   z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fsubr	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c db 65 <unknown>
+// CHECK-UNKNOWN: 65db9c3f <unknown>
 
 fsubr   z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: fsubr	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x43,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 43 65 <unknown>
+// CHECK-UNKNOWN: 65439fe0 <unknown>
 
 fsubr   z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: fsubr	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0x83,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 83 65 <unknown>
+// CHECK-UNKNOWN: 65839fe0 <unknown>
 
 fsubr   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fsubr	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c3 65 <unknown>
+// CHECK-UNKNOWN: 65c39fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -83,46 +83,46 @@ movprfx z31.d, p7/z, z6.d
 // CHECK-INST: movprfx	z31.d, p7/z, z6.d
 // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cdf <unknown>
 
 fsubr   z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fsubr	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c db 65 <unknown>
+// CHECK-UNKNOWN: 65db9c3f <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 fsubr   z31.d, p7/m, z31.d, #1.0
 // CHECK-INST: fsubr	z31.d, p7/m, z31.d, #1.0
 // CHECK-ENCODING: [0x3f,0x9c,0xdb,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 3f 9c db 65 <unknown>
+// CHECK-UNKNOWN: 65db9c3f <unknown>
 
 movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 fsubr   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fsubr	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c3 65 <unknown>
+// CHECK-UNKNOWN: 65c39fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 fsubr   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: fsubr	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xc3,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f c3 65 <unknown>
+// CHECK-UNKNOWN: 65c39fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ftmad.s b/llvm/test/MC/AArch64/SVE/ftmad.s
index fb993f8d6c028..499a44395608f 100644
--- a/llvm/test/MC/AArch64/SVE/ftmad.s
+++ b/llvm/test/MC/AArch64/SVE/ftmad.s
@@ -11,19 +11,19 @@ ftmad z0.h, z0.h, z31.h, #7
 // CHECK-INST: ftmad	z0.h, z0.h, z31.h, #7
 // CHECK-ENCODING: [0xe0,0x83,0x57,0x65]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: e0 83 57 65 <unknown>
+// CHECK-UNKNOWN: 655783e0 <unknown>
 
 ftmad z0.s, z0.s, z31.s, #7
 // CHECK-INST: ftmad	z0.s, z0.s, z31.s, #7
 // CHECK-ENCODING: [0xe0,0x83,0x97,0x65]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: e0 83 97 65 <unknown>
+// CHECK-UNKNOWN: 659783e0 <unknown>
 
 ftmad z0.d, z0.d, z31.d, #7
 // CHECK-INST: ftmad	z0.d, z0.d, z31.d, #7
 // CHECK-ENCODING: [0xe0,0x83,0xd7,0x65]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: e0 83 d7 65 <unknown>
+// CHECK-UNKNOWN: 65d783e0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -33,10 +33,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 ftmad z0.d, z0.d, z31.d, #7
 // CHECK-INST: ftmad	z0.d, z0.d, z31.d, #7
 // CHECK-ENCODING: [0xe0,0x83,0xd7,0x65]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: e0 83 d7 65 <unknown>
+// CHECK-UNKNOWN: 65d783e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ftsmul.s b/llvm/test/MC/AArch64/SVE/ftsmul.s
index c76aeea29c650..d1d59a334d5a7 100644
--- a/llvm/test/MC/AArch64/SVE/ftsmul.s
+++ b/llvm/test/MC/AArch64/SVE/ftsmul.s
@@ -13,16 +13,16 @@ ftsmul z0.h, z1.h, z31.h
 // CHECK-INST: ftsmul	z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x0c,0x5f,0x65]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 20 0c 5f 65 <unknown>
+// CHECK-UNKNOWN: 655f0c20 <unknown>
 
 ftsmul z0.s, z1.s, z31.s
 // CHECK-INST: ftsmul	z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x0c,0x9f,0x65]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 20 0c 9f 65 <unknown>
+// CHECK-UNKNOWN: 659f0c20 <unknown>
 
 ftsmul z0.d, z1.d, z31.d
 // CHECK-INST: ftsmul	z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x0c,0xdf,0x65]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 20 0c df 65 <unknown>
+// CHECK-UNKNOWN: 65df0c20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ftssel.s b/llvm/test/MC/AArch64/SVE/ftssel.s
index 4f774f119c331..f631b667d761a 100644
--- a/llvm/test/MC/AArch64/SVE/ftssel.s
+++ b/llvm/test/MC/AArch64/SVE/ftssel.s
@@ -13,16 +13,16 @@ ftssel    z0.h, z1.h, z31.h
 // CHECK-INST: ftssel	z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0xb0,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 20 b0 7f 04 <unknown>
+// CHECK-UNKNOWN: 047fb020 <unknown>
 
 ftssel    z0.s, z1.s, z31.s
 // CHECK-INST: ftssel	z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xb0,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 20 b0 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bfb020 <unknown>
 
 ftssel    z0.d, z1.d, z31.d
 // CHECK-INST: ftssel	z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xb0,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 20 b0 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ffb020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/incb.s b/llvm/test/MC/AArch64/SVE/incb.s
index 46596c6ee3a45..3971327f69421 100644
--- a/llvm/test/MC/AArch64/SVE/incb.s
+++ b/llvm/test/MC/AArch64/SVE/incb.s
@@ -13,196 +13,196 @@ incb    x0
 // CHECK-INST: incb    x0
 // CHECK-ENCODING: [0xe0,0xe3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e3e0 <unknown>
 
 incb    x0, all
 // CHECK-INST: incb    x0
 // CHECK-ENCODING: [0xe0,0xe3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e3e0 <unknown>
 
 incb    x0, all, mul #1
 // CHECK-INST: incb    x0
 // CHECK-ENCODING: [0xe0,0xe3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e3e0 <unknown>
 
 incb    x0, all, mul #16
 // CHECK-INST: incb    x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xe3,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 3f 04 <unknown>
+// CHECK-UNKNOWN: 043fe3e0 <unknown>
 
 incb    x0, pow2
 // CHECK-INST: incb    x0, pow2
 // CHECK-ENCODING: [0x00,0xe0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e000 <unknown>
 
 incb    x0, vl1
 // CHECK-INST: incb    x0, vl1
 // CHECK-ENCODING: [0x20,0xe0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e020 <unknown>
 
 incb    x0, vl2
 // CHECK-INST: incb    x0, vl2
 // CHECK-ENCODING: [0x40,0xe0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e040 <unknown>
 
 incb    x0, vl3
 // CHECK-INST: incb    x0, vl3
 // CHECK-ENCODING: [0x60,0xe0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e060 <unknown>
 
 incb    x0, vl4
 // CHECK-INST: incb    x0, vl4
 // CHECK-ENCODING: [0x80,0xe0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e080 <unknown>
 
 incb    x0, vl5
 // CHECK-INST: incb    x0, vl5
 // CHECK-ENCODING: [0xa0,0xe0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e0a0 <unknown>
 
 incb    x0, vl6
 // CHECK-INST: incb    x0, vl6
 // CHECK-ENCODING: [0xc0,0xe0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e0c0 <unknown>
 
 incb    x0, vl7
 // CHECK-INST: incb    x0, vl7
 // CHECK-ENCODING: [0xe0,0xe0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e0e0 <unknown>
 
 incb    x0, vl8
 // CHECK-INST: incb    x0, vl8
 // CHECK-ENCODING: [0x00,0xe1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e100 <unknown>
 
 incb    x0, vl16
 // CHECK-INST: incb    x0, vl16
 // CHECK-ENCODING: [0x20,0xe1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e120 <unknown>
 
 incb    x0, vl32
 // CHECK-INST: incb    x0, vl32
 // CHECK-ENCODING: [0x40,0xe1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e140 <unknown>
 
 incb    x0, vl64
 // CHECK-INST: incb    x0, vl64
 // CHECK-ENCODING: [0x60,0xe1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e160 <unknown>
 
 incb    x0, vl128
 // CHECK-INST: incb    x0, vl128
 // CHECK-ENCODING: [0x80,0xe1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e180 <unknown>
 
 incb    x0, vl256
 // CHECK-INST: incb    x0, vl256
 // CHECK-ENCODING: [0xa0,0xe1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e1a0 <unknown>
 
 incb    x0, #14
 // CHECK-INST: incb    x0, #14
 // CHECK-ENCODING: [0xc0,0xe1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e1c0 <unknown>
 
 incb    x0, #15
 // CHECK-INST: incb    x0, #15
 // CHECK-ENCODING: [0xe0,0xe1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e1e0 <unknown>
 
 incb    x0, #16
 // CHECK-INST: incb    x0, #16
 // CHECK-ENCODING: [0x00,0xe2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e200 <unknown>
 
 incb    x0, #17
 // CHECK-INST: incb    x0, #17
 // CHECK-ENCODING: [0x20,0xe2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e220 <unknown>
 
 incb    x0, #18
 // CHECK-INST: incb    x0, #18
 // CHECK-ENCODING: [0x40,0xe2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e240 <unknown>
 
 incb    x0, #19
 // CHECK-INST: incb    x0, #19
 // CHECK-ENCODING: [0x60,0xe2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e260 <unknown>
 
 incb    x0, #20
 // CHECK-INST: incb    x0, #20
 // CHECK-ENCODING: [0x80,0xe2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e280 <unknown>
 
 incb    x0, #21
 // CHECK-INST: incb    x0, #21
 // CHECK-ENCODING: [0xa0,0xe2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e2a0 <unknown>
 
 incb    x0, #22
 // CHECK-INST: incb    x0, #22
 // CHECK-ENCODING: [0xc0,0xe2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e2c0 <unknown>
 
 incb    x0, #23
 // CHECK-INST: incb    x0, #23
 // CHECK-ENCODING: [0xe0,0xe2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e2e0 <unknown>
 
 incb    x0, #24
 // CHECK-INST: incb    x0, #24
 // CHECK-ENCODING: [0x00,0xe3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e300 <unknown>
 
 incb    x0, #25
 // CHECK-INST: incb    x0, #25
 // CHECK-ENCODING: [0x20,0xe3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e320 <unknown>
 
 incb    x0, #26
 // CHECK-INST: incb    x0, #26
 // CHECK-ENCODING: [0x40,0xe3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e340 <unknown>
 
 incb    x0, #27
 // CHECK-INST: incb    x0, #27
 // CHECK-ENCODING: [0x60,0xe3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e360 <unknown>
 
 incb    x0, #28
 // CHECK-INST: incb    x0, #28
 // CHECK-ENCODING: [0x80,0xe3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430e380 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/incd.s b/llvm/test/MC/AArch64/SVE/incd.s
index f0cd8ec235806..8e8e5f8f1a4d1 100644
--- a/llvm/test/MC/AArch64/SVE/incd.s
+++ b/llvm/test/MC/AArch64/SVE/incd.s
@@ -17,25 +17,25 @@ incd    z0.d
 // CHECK-INST: incd    z0.d
 // CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0c3e0 <unknown>
 
 incd    z0.d, all
 // CHECK-INST: incd    z0.d
 // CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0c3e0 <unknown>
 
 incd    z0.d, all, mul #1
 // CHECK-INST: incd    z0.d
 // CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0c3e0 <unknown>
 
 incd    z0.d, all, mul #16
 // CHECK-INST: incd    z0.d, all, mul #16
 // CHECK-ENCODING: [0xe0,0xc3,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ffc3e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,25 +46,25 @@ incd    x0
 // CHECK-INST: incd    x0
 // CHECK-ENCODING: [0xe0,0xe3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e3e0 <unknown>
 
 incd    x0, all
 // CHECK-INST: incd    x0
 // CHECK-ENCODING: [0xe0,0xe3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e3e0 <unknown>
 
 incd    x0, all, mul #1
 // CHECK-INST: incd    x0
 // CHECK-ENCODING: [0xe0,0xe3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e3e0 <unknown>
 
 incd    x0, all, mul #16
 // CHECK-INST: incd    x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xe3,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ffe3e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -75,97 +75,97 @@ incd    x0, pow2
 // CHECK-INST: incd    x0, pow2
 // CHECK-ENCODING: [0x00,0xe0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e000 <unknown>
 
 incd    x0, vl1
 // CHECK-INST: incd    x0, vl1
 // CHECK-ENCODING: [0x20,0xe0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e020 <unknown>
 
 incd    x0, vl2
 // CHECK-INST: incd    x0, vl2
 // CHECK-ENCODING: [0x40,0xe0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e040 <unknown>
 
 incd    x0, vl3
 // CHECK-INST: incd    x0, vl3
 // CHECK-ENCODING: [0x60,0xe0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e060 <unknown>
 
 incd    x0, vl4
 // CHECK-INST: incd    x0, vl4
 // CHECK-ENCODING: [0x80,0xe0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e080 <unknown>
 
 incd    x0, vl5
 // CHECK-INST: incd    x0, vl5
 // CHECK-ENCODING: [0xa0,0xe0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e0a0 <unknown>
 
 incd    x0, vl6
 // CHECK-INST: incd    x0, vl6
 // CHECK-ENCODING: [0xc0,0xe0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e0c0 <unknown>
 
 incd    x0, vl7
 // CHECK-INST: incd    x0, vl7
 // CHECK-ENCODING: [0xe0,0xe0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e0e0 <unknown>
 
 incd    x0, vl8
 // CHECK-INST: incd    x0, vl8
 // CHECK-ENCODING: [0x00,0xe1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e100 <unknown>
 
 incd    x0, vl16
 // CHECK-INST: incd    x0, vl16
 // CHECK-ENCODING: [0x20,0xe1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e120 <unknown>
 
 incd    x0, vl32
 // CHECK-INST: incd    x0, vl32
 // CHECK-ENCODING: [0x40,0xe1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e140 <unknown>
 
 incd    x0, vl64
 // CHECK-INST: incd    x0, vl64
 // CHECK-ENCODING: [0x60,0xe1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e160 <unknown>
 
 incd    x0, vl128
 // CHECK-INST: incd    x0, vl128
 // CHECK-ENCODING: [0x80,0xe1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e180 <unknown>
 
 incd    x0, vl256
 // CHECK-INST: incd    x0, vl256
 // CHECK-ENCODING: [0xa0,0xe1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e1a0 <unknown>
 
 incd    x0, #14
 // CHECK-INST: incd    x0, #14
 // CHECK-ENCODING: [0xc0,0xe1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e1c0 <unknown>
 
 incd    x0, #28
 // CHECK-INST: incd    x0, #28
 // CHECK-ENCODING: [0x80,0xe3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0e380 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -175,34 +175,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 incd    z0.d
 // CHECK-INST: incd	z0.d
 // CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0c3e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 incd    z0.d, all, mul #16
 // CHECK-INST: incd	z0.d, all, mul #16
 // CHECK-ENCODING: [0xe0,0xc3,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ffc3e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 incd    z0.d, all
 // CHECK-INST: incd	z0.d
 // CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0c3e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/inch.s b/llvm/test/MC/AArch64/SVE/inch.s
index ec56a9df038f9..e12196538111c 100644
--- a/llvm/test/MC/AArch64/SVE/inch.s
+++ b/llvm/test/MC/AArch64/SVE/inch.s
@@ -17,25 +17,25 @@ inch    z0.h
 // CHECK-INST: inch    z0.h
 // CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470c3e0 <unknown>
 
 inch    z0.h, all
 // CHECK-INST: inch    z0.h
 // CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470c3e0 <unknown>
 
 inch    z0.h, all, mul #1
 // CHECK-INST: inch    z0.h
 // CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470c3e0 <unknown>
 
 inch    z0.h, all, mul #16
 // CHECK-INST: inch    z0.h, all, mul #16
 // CHECK-ENCODING: [0xe0,0xc3,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 7f 04 <unknown>
+// CHECK-UNKNOWN: 047fc3e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,25 +46,25 @@ inch    x0
 // CHECK-INST: inch    x0
 // CHECK-ENCODING: [0xe0,0xe3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e3e0 <unknown>
 
 inch    x0, all
 // CHECK-INST: inch    x0
 // CHECK-ENCODING: [0xe0,0xe3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e3e0 <unknown>
 
 inch    x0, all, mul #1
 // CHECK-INST: inch    x0
 // CHECK-ENCODING: [0xe0,0xe3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e3e0 <unknown>
 
 inch    x0, all, mul #16
 // CHECK-INST: inch    x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xe3,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 7f 04 <unknown>
+// CHECK-UNKNOWN: 047fe3e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -75,97 +75,97 @@ inch    x0, pow2
 // CHECK-INST: inch    x0, pow2
 // CHECK-ENCODING: [0x00,0xe0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e000 <unknown>
 
 inch    x0, vl1
 // CHECK-INST: inch    x0, vl1
 // CHECK-ENCODING: [0x20,0xe0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e020 <unknown>
 
 inch    x0, vl2
 // CHECK-INST: inch    x0, vl2
 // CHECK-ENCODING: [0x40,0xe0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e040 <unknown>
 
 inch    x0, vl3
 // CHECK-INST: inch    x0, vl3
 // CHECK-ENCODING: [0x60,0xe0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e060 <unknown>
 
 inch    x0, vl4
 // CHECK-INST: inch    x0, vl4
 // CHECK-ENCODING: [0x80,0xe0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e080 <unknown>
 
 inch    x0, vl5
 // CHECK-INST: inch    x0, vl5
 // CHECK-ENCODING: [0xa0,0xe0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e0a0 <unknown>
 
 inch    x0, vl6
 // CHECK-INST: inch    x0, vl6
 // CHECK-ENCODING: [0xc0,0xe0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e0c0 <unknown>
 
 inch    x0, vl7
 // CHECK-INST: inch    x0, vl7
 // CHECK-ENCODING: [0xe0,0xe0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e0e0 <unknown>
 
 inch    x0, vl8
 // CHECK-INST: inch    x0, vl8
 // CHECK-ENCODING: [0x00,0xe1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e100 <unknown>
 
 inch    x0, vl16
 // CHECK-INST: inch    x0, vl16
 // CHECK-ENCODING: [0x20,0xe1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e120 <unknown>
 
 inch    x0, vl32
 // CHECK-INST: inch    x0, vl32
 // CHECK-ENCODING: [0x40,0xe1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e140 <unknown>
 
 inch    x0, vl64
 // CHECK-INST: inch    x0, vl64
 // CHECK-ENCODING: [0x60,0xe1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e160 <unknown>
 
 inch    x0, vl128
 // CHECK-INST: inch    x0, vl128
 // CHECK-ENCODING: [0x80,0xe1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e180 <unknown>
 
 inch    x0, vl256
 // CHECK-INST: inch    x0, vl256
 // CHECK-ENCODING: [0xa0,0xe1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e1a0 <unknown>
 
 inch    x0, #14
 // CHECK-INST: inch    x0, #14
 // CHECK-ENCODING: [0xc0,0xe1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e1c0 <unknown>
 
 inch    x0, #28
 // CHECK-INST: inch    x0, #28
 // CHECK-ENCODING: [0x80,0xe3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470e380 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -175,34 +175,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 inch    z0.h
 // CHECK-INST: inch	z0.h
 // CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470c3e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 inch    z0.h, all, mul #16
 // CHECK-INST: inch	z0.h, all, mul #16
 // CHECK-ENCODING: [0xe0,0xc3,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 7f 04 <unknown>
+// CHECK-UNKNOWN: 047fc3e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 inch    z0.h, all
 // CHECK-INST: inch	z0.h
 // CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470c3e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/incp.s b/llvm/test/MC/AArch64/SVE/incp.s
index 6cba4c035e44d..03557f07b3b6f 100644
--- a/llvm/test/MC/AArch64/SVE/incp.s
+++ b/llvm/test/MC/AArch64/SVE/incp.s
@@ -13,85 +13,85 @@ incp    x0, p0.b
 // CHECK-INST: incp    x0, p0.b
 // CHECK-ENCODING: [0x00,0x88,0x2c,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 88 2c 25 <unknown>
+// CHECK-UNKNOWN: 252c8800 <unknown>
 
 incp    x0, p0.h
 // CHECK-INST: incp    x0, p0.h
 // CHECK-ENCODING: [0x00,0x88,0x6c,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 88 6c 25 <unknown>
+// CHECK-UNKNOWN: 256c8800 <unknown>
 
 incp    x0, p0.s
 // CHECK-INST: incp    x0, p0.s
 // CHECK-ENCODING: [0x00,0x88,0xac,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 88 ac 25 <unknown>
+// CHECK-UNKNOWN: 25ac8800 <unknown>
 
 incp    x0, p0.d
 // CHECK-INST: incp    x0, p0.d
 // CHECK-ENCODING: [0x00,0x88,0xec,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 88 ec 25 <unknown>
+// CHECK-UNKNOWN: 25ec8800 <unknown>
 
 incp    xzr, p15.b
 // CHECK-INST: incp    xzr, p15.b
 // CHECK-ENCODING: [0xff,0x89,0x2c,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 2c 25 <unknown>
+// CHECK-UNKNOWN: 252c89ff <unknown>
 
 incp    xzr, p15.h
 // CHECK-INST: incp    xzr, p15.h
 // CHECK-ENCODING: [0xff,0x89,0x6c,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 6c 25 <unknown>
+// CHECK-UNKNOWN: 256c89ff <unknown>
 
 incp    xzr, p15.s
 // CHECK-INST: incp    xzr, p15.s
 // CHECK-ENCODING: [0xff,0x89,0xac,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 ac 25 <unknown>
+// CHECK-UNKNOWN: 25ac89ff <unknown>
 
 incp    xzr, p15.d
 // CHECK-INST: incp    xzr, p15.d
 // CHECK-ENCODING: [0xff,0x89,0xec,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 ec 25 <unknown>
+// CHECK-UNKNOWN: 25ec89ff <unknown>
 
 incp    z31.h, p15
 // CHECK-INST: incp    z31.h, p15.h
 // CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 6c 25 <unknown>
+// CHECK-UNKNOWN: 256c81ff <unknown>
 
 incp    z31.h, p15.h
 // CHECK-INST: incp    z31.h, p15.h
 // CHECK-ENCODING: [0xff,0x81,0x6c,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 6c 25 <unknown>
+// CHECK-UNKNOWN: 256c81ff <unknown>
 
 incp    z31.s, p15
 // CHECK-INST: incp    z31.s, p15.s
 // CHECK-ENCODING: [0xff,0x81,0xac,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 ac 25 <unknown>
+// CHECK-UNKNOWN: 25ac81ff <unknown>
 
 incp    z31.s, p15.s
 // CHECK-INST: incp    z31.s, p15.s
 // CHECK-ENCODING: [0xff,0x81,0xac,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 ac 25 <unknown>
+// CHECK-UNKNOWN: 25ac81ff <unknown>
 
 incp    z31.d, p15
 // CHECK-INST: incp    z31.d, p15.d
 // CHECK-ENCODING: [0xff,0x81,0xec,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 ec 25 <unknown>
+// CHECK-UNKNOWN: 25ec81ff <unknown>
 
 incp    z31.d, p15.d
 // CHECK-INST: incp    z31.d, p15.d
 // CHECK-ENCODING: [0xff,0x81,0xec,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 ec 25 <unknown>
+// CHECK-UNKNOWN: 25ec81ff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -101,10 +101,10 @@ movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 incp    z31.d, p15.d
 // CHECK-INST: incp	z31.d, p15.d
 // CHECK-ENCODING: [0xff,0x81,0xec,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 ec 25 <unknown>
+// CHECK-UNKNOWN: 25ec81ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/incw.s b/llvm/test/MC/AArch64/SVE/incw.s
index 5f9ac1738cee4..8b8aa55df364c 100644
--- a/llvm/test/MC/AArch64/SVE/incw.s
+++ b/llvm/test/MC/AArch64/SVE/incw.s
@@ -17,25 +17,25 @@ incw    z0.s
 // CHECK-INST: incw    z0.s
 // CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0c3e0 <unknown>
 
 incw    z0.s, all
 // CHECK-INST: incw    z0.s
 // CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0c3e0 <unknown>
 
 incw    z0.s, all, mul #1
 // CHECK-INST: incw    z0.s
 // CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0c3e0 <unknown>
 
 incw    z0.s, all, mul #16
 // CHECK-INST: incw    z0.s, all, mul #16
 // CHECK-ENCODING: [0xe0,0xc3,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bfc3e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,25 +46,25 @@ incw    x0
 // CHECK-INST: incw    x0
 // CHECK-ENCODING: [0xe0,0xe3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e3e0 <unknown>
 
 incw    x0, all
 // CHECK-INST: incw    x0
 // CHECK-ENCODING: [0xe0,0xe3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e3e0 <unknown>
 
 incw    x0, all, mul #1
 // CHECK-INST: incw    x0
 // CHECK-ENCODING: [0xe0,0xe3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e3e0 <unknown>
 
 incw    x0, all, mul #16
 // CHECK-INST: incw    x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xe3,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e3 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bfe3e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -76,97 +76,97 @@ incw    x0, pow2
 // CHECK-INST: incw    x0, pow2
 // CHECK-ENCODING: [0x00,0xe0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e000 <unknown>
 
 incw    x0, vl1
 // CHECK-INST: incw    x0, vl1
 // CHECK-ENCODING: [0x20,0xe0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e020 <unknown>
 
 incw    x0, vl2
 // CHECK-INST: incw    x0, vl2
 // CHECK-ENCODING: [0x40,0xe0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e040 <unknown>
 
 incw    x0, vl3
 // CHECK-INST: incw    x0, vl3
 // CHECK-ENCODING: [0x60,0xe0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e060 <unknown>
 
 incw    x0, vl4
 // CHECK-INST: incw    x0, vl4
 // CHECK-ENCODING: [0x80,0xe0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e080 <unknown>
 
 incw    x0, vl5
 // CHECK-INST: incw    x0, vl5
 // CHECK-ENCODING: [0xa0,0xe0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e0a0 <unknown>
 
 incw    x0, vl6
 // CHECK-INST: incw    x0, vl6
 // CHECK-ENCODING: [0xc0,0xe0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e0c0 <unknown>
 
 incw    x0, vl7
 // CHECK-INST: incw    x0, vl7
 // CHECK-ENCODING: [0xe0,0xe0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 e0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e0e0 <unknown>
 
 incw    x0, vl8
 // CHECK-INST: incw    x0, vl8
 // CHECK-ENCODING: [0x00,0xe1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e100 <unknown>
 
 incw    x0, vl16
 // CHECK-INST: incw    x0, vl16
 // CHECK-ENCODING: [0x20,0xe1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 e1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e120 <unknown>
 
 incw    x0, vl32
 // CHECK-INST: incw    x0, vl32
 // CHECK-ENCODING: [0x40,0xe1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 e1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e140 <unknown>
 
 incw    x0, vl64
 // CHECK-INST: incw    x0, vl64
 // CHECK-ENCODING: [0x60,0xe1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 e1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e160 <unknown>
 
 incw    x0, vl128
 // CHECK-INST: incw    x0, vl128
 // CHECK-ENCODING: [0x80,0xe1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e180 <unknown>
 
 incw    x0, vl256
 // CHECK-INST: incw    x0, vl256
 // CHECK-ENCODING: [0xa0,0xe1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 e1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e1a0 <unknown>
 
 incw    x0, #14
 // CHECK-INST: incw    x0, #14
 // CHECK-ENCODING: [0xc0,0xe1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 e1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e1c0 <unknown>
 
 incw    x0, #28
 // CHECK-INST: incw    x0, #28
 // CHECK-ENCODING: [0x80,0xe3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 e3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0e380 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -176,34 +176,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 incw    z0.s
 // CHECK-INST: incw	z0.s
 // CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0c3e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 incw    z0.s, all, mul #16
 // CHECK-INST: incw	z0.s, all, mul #16
 // CHECK-ENCODING: [0xe0,0xc3,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bfc3e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 incw    z0.s, all
 // CHECK-INST: incw	z0.s
 // CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0c3e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/index.s b/llvm/test/MC/AArch64/SVE/index.s
index f605010ba4325..2e14987c2c702 100644
--- a/llvm/test/MC/AArch64/SVE/index.s
+++ b/llvm/test/MC/AArch64/SVE/index.s
@@ -16,49 +16,49 @@ index   z0.b, #0, #0
 // CHECK-INST: index   z0.b, #0, #0
 // CHECK-ENCODING: [0x00,0x40,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 20 04 <unknown>
+// CHECK-UNKNOWN: 04204000 <unknown>
 
 index   z31.b, #-1, #-1
 // CHECK-INST: index   z31.b, #-1, #-1
 // CHECK-ENCODING: [0xff,0x43,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 43 3f 04 <unknown>
+// CHECK-UNKNOWN: 043f43ff <unknown>
 
 index   z0.h, #0, #0
 // CHECK-INST: index   z0.h, #0, #0
 // CHECK-ENCODING: [0x00,0x40,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 60 04 <unknown>
+// CHECK-UNKNOWN: 04604000 <unknown>
 
 index   z31.h, #-1, #-1
 // CHECK-INST: index   z31.h, #-1, #-1
 // CHECK-ENCODING: [0xff,0x43,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 43 7f 04 <unknown>
+// CHECK-UNKNOWN: 047f43ff <unknown>
 
 index   z0.s, #0, #0
 // CHECK-INST: index   z0.s, #0, #0
 // CHECK-ENCODING: [0x00,0x40,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a04000 <unknown>
 
 index   z31.s, #-1, #-1
 // CHECK-INST: index   z31.s, #-1, #-1
 // CHECK-ENCODING: [0xff,0x43,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 43 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf43ff <unknown>
 
 index   z0.d, #0, #0
 // CHECK-INST: index   z0.d, #0, #0
 // CHECK-ENCODING: [0x00,0x40,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e04000 <unknown>
 
 index   z31.d, #-1, #-1
 // CHECK-INST: index   z31.d, #-1, #-1
 // CHECK-ENCODING: [0xff,0x43,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 43 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff43ff <unknown>
 
 // --------------------------------------------------------------------------//
 // Index (immediate, scalar)
@@ -67,49 +67,49 @@ index   z31.b, #-1, wzr
 // CHECK-INST: index   z31.b, #-1, wzr
 // CHECK-ENCODING: [0xff,0x4b,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 4b 3f 04 <unknown>
+// CHECK-UNKNOWN: 043f4bff <unknown>
 
 index   z23.b, #13, w8
 // CHECK-INST: index   z23.b, #13, w8
 // CHECK-ENCODING: [0xb7,0x49,0x28,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 49 28 04 <unknown>
+// CHECK-UNKNOWN: 042849b7 <unknown>
 
 index   z31.h, #-1, wzr
 // CHECK-INST: index   z31.h, #-1, wzr
 // CHECK-ENCODING: [0xff,0x4b,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 4b 7f 04 <unknown>
+// CHECK-UNKNOWN: 047f4bff <unknown>
 
 index   z23.h, #13, w8
 // CHECK-INST: index   z23.h, #13, w8
 // CHECK-ENCODING: [0xb7,0x49,0x68,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 49 68 04 <unknown>
+// CHECK-UNKNOWN: 046849b7 <unknown>
 
 index   z31.s, #-1, wzr
 // CHECK-INST: index   z31.s, #-1, wzr
 // CHECK-ENCODING: [0xff,0x4b,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 4b bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf4bff <unknown>
 
 index   z23.s, #13, w8
 // CHECK-INST: index   z23.s, #13, w8
 // CHECK-ENCODING: [0xb7,0x49,0xa8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 49 a8 04 <unknown>
+// CHECK-UNKNOWN: 04a849b7 <unknown>
 
 index   z31.d, #-1, xzr
 // CHECK-INST: index   z31.d, #-1, xzr
 // CHECK-ENCODING: [0xff,0x4b,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 4b ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff4bff <unknown>
 
 index   z23.d, #13, x8
 // CHECK-INST: index   z23.d, #13, x8
 // CHECK-ENCODING: [0xb7,0x49,0xe8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 49 e8 04 <unknown>
+// CHECK-UNKNOWN: 04e849b7 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -119,49 +119,49 @@ index   z31.b, wzr, #-1
 // CHECK-INST: index   z31.b, wzr, #-1
 // CHECK-ENCODING: [0xff,0x47,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 47 3f 04 <unknown>
+// CHECK-UNKNOWN: 043f47ff <unknown>
 
 index   z23.b, w13, #8
 // CHECK-INST: index   z23.b, w13, #8
 // CHECK-ENCODING: [0xb7,0x45,0x28,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 45 28 04 <unknown>
+// CHECK-UNKNOWN: 042845b7 <unknown>
 
 index   z31.h, wzr, #-1
 // CHECK-INST: index   z31.h, wzr, #-1
 // CHECK-ENCODING: [0xff,0x47,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 47 7f 04 <unknown>
+// CHECK-UNKNOWN: 047f47ff <unknown>
 
 index   z23.h, w13, #8
 // CHECK-INST: index   z23.h, w13, #8
 // CHECK-ENCODING: [0xb7,0x45,0x68,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 45 68 04 <unknown>
+// CHECK-UNKNOWN: 046845b7 <unknown>
 
 index   z31.s, wzr, #-1
 // CHECK-INST: index   z31.s, wzr, #-1
 // CHECK-ENCODING: [0xff,0x47,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 47 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf47ff <unknown>
 
 index   z23.s, w13, #8
 // CHECK-INST: index   z23.s, w13, #8
 // CHECK-ENCODING: [0xb7,0x45,0xa8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 45 a8 04 <unknown>
+// CHECK-UNKNOWN: 04a845b7 <unknown>
 
 index   z31.d, xzr, #-1
 // CHECK-INST: index   z31.d, xzr, #-1
 // CHECK-ENCODING: [0xff,0x47,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 47 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff47ff <unknown>
 
 index   z23.d, x13, #8
 // CHECK-INST: index   z23.d, x13, #8
 // CHECK-ENCODING: [0xb7,0x45,0xe8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 45 e8 04 <unknown>
+// CHECK-UNKNOWN: 04e845b7 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -171,13 +171,13 @@ index   z31.b, wzr, wzr
 // CHECK-INST: index   z31.b, wzr, wzr
 // CHECK-ENCODING: [0xff,0x4f,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 4f 3f 04 <unknown>
+// CHECK-UNKNOWN: 043f4fff <unknown>
 
 index   z21.b, w10, w21
 // CHECK-INST: index   z21.b, w10, w21
 // CHECK-ENCODING: [0x55,0x4d,0x35,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 4d 35 04 <unknown>
+// CHECK-UNKNOWN: 04354d55 <unknown>
 
 index   z31.h, wzr, wzr
 // check-inst: index   z31.h, wzr, wzr
@@ -195,22 +195,22 @@ index   z31.s, wzr, wzr
 // CHECK-INST: index   z31.s, wzr, wzr
 // CHECK-ENCODING: [0xff,0x4f,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 4f bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf4fff <unknown>
 
 index   z21.s, w10, w21
 // CHECK-INST: index   z21.s, w10, w21
 // CHECK-ENCODING: [0x55,0x4d,0xb5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 4d b5 04 <unknown>
+// CHECK-UNKNOWN: 04b54d55 <unknown>
 
 index   z31.d, xzr, xzr
 // CHECK-INST: index   z31.d, xzr, xzr
 // CHECK-ENCODING: [0xff,0x4f,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 4f ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff4fff <unknown>
 
 index   z21.d, x10, x21
 // CHECK-INST: index   z21.d, x10, x21
 // CHECK-ENCODING: [0x55,0x4d,0xf5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 4d f5 04 <unknown>
+// CHECK-UNKNOWN: 04f54d55 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/insr.s b/llvm/test/MC/AArch64/SVE/insr.s
index 00c2427b8c6f2..09d2a9a6aeb4d 100644
--- a/llvm/test/MC/AArch64/SVE/insr.s
+++ b/llvm/test/MC/AArch64/SVE/insr.s
@@ -13,73 +13,73 @@ insr    z0.b, w0
 // CHECK-INST: insr    z0.b, w0
 // CHECK-ENCODING: [0x00,0x38,0x24,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 38 24 05 <unknown>
+// CHECK-UNKNOWN: 05243800 <unknown>
 
 insr    z0.h, w0
 // CHECK-INST: insr    z0.h, w0
 // CHECK-ENCODING: [0x00,0x38,0x64,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 38 64 05 <unknown>
+// CHECK-UNKNOWN: 05643800 <unknown>
 
 insr    z0.s, w0
 // CHECK-INST: insr    z0.s, w0
 // CHECK-ENCODING: [0x00,0x38,0xa4,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 38 a4 05 <unknown>
+// CHECK-UNKNOWN: 05a43800 <unknown>
 
 insr    z0.d, x0
 // CHECK-INST: insr    z0.d, x0
 // CHECK-ENCODING: [0x00,0x38,0xe4,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 38 e4 05 <unknown>
+// CHECK-UNKNOWN: 05e43800 <unknown>
 
 insr    z31.b, wzr
 // CHECK-INST: insr    z31.b, wzr
 // CHECK-ENCODING: [0xff,0x3b,0x24,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b 24 05 <unknown>
+// CHECK-UNKNOWN: 05243bff <unknown>
 
 insr    z31.h, wzr
 // CHECK-INST: insr    z31.h, wzr
 // CHECK-ENCODING: [0xff,0x3b,0x64,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b 64 05 <unknown>
+// CHECK-UNKNOWN: 05643bff <unknown>
 
 insr    z31.s, wzr
 // CHECK-INST: insr    z31.s, wzr
 // CHECK-ENCODING: [0xff,0x3b,0xa4,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b a4 05 <unknown>
+// CHECK-UNKNOWN: 05a43bff <unknown>
 
 insr    z31.d, xzr
 // CHECK-INST: insr    z31.d, xzr
 // CHECK-ENCODING: [0xff,0x3b,0xe4,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b e4 05 <unknown>
+// CHECK-UNKNOWN: 05e43bff <unknown>
 
 insr    z31.b, b31
 // CHECK-INST: insr    z31.b, b31
 // CHECK-ENCODING: [0xff,0x3b,0x34,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b 34 05 <unknown>
+// CHECK-UNKNOWN: 05343bff <unknown>
 
 insr    z31.h, h31
 // CHECK-INST: insr    z31.h, h31
 // CHECK-ENCODING: [0xff,0x3b,0x74,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b 74 05 <unknown>
+// CHECK-UNKNOWN: 05743bff <unknown>
 
 insr    z31.s, s31
 // CHECK-INST: insr    z31.s, s31
 // CHECK-ENCODING: [0xff,0x3b,0xb4,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b b4 05 <unknown>
+// CHECK-UNKNOWN: 05b43bff <unknown>
 
 insr    z31.d, d31
 // CHECK-INST: insr    z31.d, d31
 // CHECK-ENCODING: [0xff,0x3b,0xf4,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b f4 05 <unknown>
+// CHECK-UNKNOWN: 05f43bff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -89,22 +89,22 @@ movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 insr    z31.d, xzr
 // CHECK-INST: insr	z31.d, xzr
 // CHECK-ENCODING: [0xff,0x3b,0xe4,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b e4 05 <unknown>
+// CHECK-UNKNOWN: 05e43bff <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 insr    z4.d, d31
 // CHECK-INST: insr	z4.d, d31
 // CHECK-ENCODING: [0xe4,0x3b,0xf4,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 3b f4 05 <unknown>
+// CHECK-UNKNOWN: 05f43be4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/lasta.s b/llvm/test/MC/AArch64/SVE/lasta.s
index dd377c4a5825b..759509ff4b828 100644
--- a/llvm/test/MC/AArch64/SVE/lasta.s
+++ b/llvm/test/MC/AArch64/SVE/lasta.s
@@ -13,46 +13,46 @@ lasta   w0, p7, z31.b
 // CHECK-INST: lasta	w0, p7, z31.b
 // CHECK-ENCODING: [0xe0,0xbf,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf 20 05 <unknown>
+// CHECK-UNKNOWN: 0520bfe0 <unknown>
 
 lasta   w0, p7, z31.h
 // CHECK-INST: lasta	w0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0xbf,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf 60 05 <unknown>
+// CHECK-UNKNOWN: 0560bfe0 <unknown>
 
 lasta   w0, p7, z31.s
 // CHECK-INST: lasta	w0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0xbf,0xa0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf a0 05 <unknown>
+// CHECK-UNKNOWN: 05a0bfe0 <unknown>
 
 lasta   x0, p7, z31.d
 // CHECK-INST: lasta	x0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0xbf,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf e0 05 <unknown>
+// CHECK-UNKNOWN: 05e0bfe0 <unknown>
 
 lasta   b0, p7, z31.b
 // CHECK-INST: lasta	b0, p7, z31.b
 // CHECK-ENCODING: [0xe0,0x9f,0x22,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 22 05 <unknown>
+// CHECK-UNKNOWN: 05229fe0 <unknown>
 
 lasta   h0, p7, z31.h
 // CHECK-INST: lasta	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x62,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 62 05 <unknown>
+// CHECK-UNKNOWN: 05629fe0 <unknown>
 
 lasta   s0, p7, z31.s
 // CHECK-INST: lasta	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0xa2,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f a2 05 <unknown>
+// CHECK-UNKNOWN: 05a29fe0 <unknown>
 
 lasta   d0, p7, z31.d
 // CHECK-INST: lasta	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe2,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e2 05 <unknown>
+// CHECK-UNKNOWN: 05e29fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/lastb.s b/llvm/test/MC/AArch64/SVE/lastb.s
index 8671f33bbd5d8..b82e88204f1fa 100644
--- a/llvm/test/MC/AArch64/SVE/lastb.s
+++ b/llvm/test/MC/AArch64/SVE/lastb.s
@@ -13,46 +13,46 @@ lastb   w0, p7, z31.b
 // CHECK-INST: lastb	w0, p7, z31.b
 // CHECK-ENCODING: [0xe0,0xbf,0x21,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf 21 05 <unknown>
+// CHECK-UNKNOWN: 0521bfe0 <unknown>
 
 lastb   w0, p7, z31.h
 // CHECK-INST: lastb	w0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0xbf,0x61,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf 61 05 <unknown>
+// CHECK-UNKNOWN: 0561bfe0 <unknown>
 
 lastb   w0, p7, z31.s
 // CHECK-INST: lastb	w0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0xbf,0xa1,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf a1 05 <unknown>
+// CHECK-UNKNOWN: 05a1bfe0 <unknown>
 
 lastb   x0, p7, z31.d
 // CHECK-INST: lastb	x0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0xbf,0xe1,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bf e1 05 <unknown>
+// CHECK-UNKNOWN: 05e1bfe0 <unknown>
 
 lastb   b0, p7, z31.b
 // CHECK-INST: lastb	b0, p7, z31.b
 // CHECK-ENCODING: [0xe0,0x9f,0x23,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 23 05 <unknown>
+// CHECK-UNKNOWN: 05239fe0 <unknown>
 
 lastb   h0, p7, z31.h
 // CHECK-INST: lastb	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x63,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 63 05 <unknown>
+// CHECK-UNKNOWN: 05639fe0 <unknown>
 
 lastb   s0, p7, z31.s
 // CHECK-INST: lastb	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0xa3,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f a3 05 <unknown>
+// CHECK-UNKNOWN: 05a39fe0 <unknown>
 
 lastb   d0, p7, z31.d
 // CHECK-INST: lastb	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe3,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e3 05 <unknown>
+// CHECK-UNKNOWN: 05e39fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1b-sve-only.s b/llvm/test/MC/AArch64/SVE/ld1b-sve-only.s
index 832a7c5348b16..101bd90edea87 100644
--- a/llvm/test/MC/AArch64/SVE/ld1b-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/ld1b-sve-only.s
@@ -15,52 +15,52 @@ ld1b    { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-INST: ld1b    { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-ENCODING: [0x00,0x40,0x00,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 00 84 <unknown>
+// CHECK-UNKNOWN: 84004000 <unknown>
 
 ld1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ld1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x40,0x40,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 40 84 <unknown>
+// CHECK-UNKNOWN: 84404000 <unknown>
 
 ld1b    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ld1b    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0x5f,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff df 5f c4 <unknown>
+// CHECK-UNKNOWN: c45fdfff <unknown>
 
 ld1b    { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ld1b    { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x55,0x15,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 55 15 c4 <unknown>
+// CHECK-UNKNOWN: c4155555 <unknown>
 
 ld1b    { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ld1b    { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x55,0x55,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 55 55 c4 <unknown>
+// CHECK-UNKNOWN: c4555555 <unknown>
 
 ld1b    { z31.s }, p7/z, [z31.s, #31]
 // CHECK-INST: ld1b    { z31.s }, p7/z, [z31.s, #31]
 // CHECK-ENCODING: [0xff,0xdf,0x3f,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff df 3f 84 <unknown>
+// CHECK-UNKNOWN: 843fdfff <unknown>
 
 ld1b    { z0.s }, p0/z, [z0.s]
 // CHECK-INST: ld1b    { z0.s }, p0/z, [z0.s]
 // CHECK-ENCODING: [0x00,0xc0,0x20,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 20 84 <unknown>
+// CHECK-UNKNOWN: 8420c000 <unknown>
 
 ld1b    { z31.d }, p7/z, [z31.d, #31]
 // CHECK-INST: ld1b    { z31.d }, p7/z, [z31.d, #31]
 // CHECK-ENCODING: [0xff,0xdf,0x3f,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff df 3f c4 <unknown>
+// CHECK-UNKNOWN: c43fdfff <unknown>
 
 ld1b    { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ld1b    { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0xc0,0x20,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 20 c4 <unknown>
+// CHECK-UNKNOWN: c420c000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1b.s b/llvm/test/MC/AArch64/SVE/ld1b.s
index 65841821d66a6..292a7c515f4b0 100644
--- a/llvm/test/MC/AArch64/SVE/ld1b.s
+++ b/llvm/test/MC/AArch64/SVE/ld1b.s
@@ -13,130 +13,130 @@ ld1b     z0.b, p0/z, [x0]
 // CHECK-INST: ld1b     { z0.b }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x00,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 00 a4 <unknown>
+// CHECK-UNKNOWN: a400a000 <unknown>
 
 ld1b     z0.h, p0/z, [x0]
 // CHECK-INST: ld1b     { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x20,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 20 a4 <unknown>
+// CHECK-UNKNOWN: a420a000 <unknown>
 
 ld1b     z0.s, p0/z, [x0]
 // CHECK-INST: ld1b     { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x40,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 40 a4 <unknown>
+// CHECK-UNKNOWN: a440a000 <unknown>
 
 ld1b     z0.d, p0/z, [x0]
 // CHECK-INST: ld1b     { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x60,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 60 a4 <unknown>
+// CHECK-UNKNOWN: a460a000 <unknown>
 
 ld1b    { z0.b }, p0/z, [x0]
 // CHECK-INST: ld1b    { z0.b }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x00,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 00 a4 <unknown>
+// CHECK-UNKNOWN: a400a000 <unknown>
 
 ld1b    { z0.h }, p0/z, [x0]
 // CHECK-INST: ld1b    { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x20,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 20 a4 <unknown>
+// CHECK-UNKNOWN: a420a000 <unknown>
 
 ld1b    { z0.s }, p0/z, [x0]
 // CHECK-INST: ld1b    { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x40,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 40 a4 <unknown>
+// CHECK-UNKNOWN: a440a000 <unknown>
 
 ld1b    { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1b    { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x60,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 60 a4 <unknown>
+// CHECK-UNKNOWN: a460a000 <unknown>
 
 ld1b    { z31.b }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1b    { z31.b }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x0f,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 0f a4 <unknown>
+// CHECK-UNKNOWN: a40fbfff <unknown>
 
 ld1b    { z21.b }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1b    { z21.b }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x05,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 05 a4 <unknown>
+// CHECK-UNKNOWN: a405b555 <unknown>
 
 ld1b    { z31.h }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1b    { z31.h }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x2f,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 2f a4 <unknown>
+// CHECK-UNKNOWN: a42fbfff <unknown>
 
 ld1b    { z21.h }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1b    { z21.h }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x25,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 25 a4 <unknown>
+// CHECK-UNKNOWN: a425b555 <unknown>
 
 ld1b    { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1b    { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x4f,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 4f a4 <unknown>
+// CHECK-UNKNOWN: a44fbfff <unknown>
 
 ld1b    { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1b    { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x45,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 45 a4 <unknown>
+// CHECK-UNKNOWN: a445b555 <unknown>
 
 ld1b    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1b    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x6f,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 6f a4 <unknown>
+// CHECK-UNKNOWN: a46fbfff <unknown>
 
 ld1b    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1b    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x65,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 65 a4 <unknown>
+// CHECK-UNKNOWN: a465b555 <unknown>
 
 ld1b    { z0.b }, p0/z, [sp, x0]
 // CHECK-INST: ld1b    { z0.b }, p0/z, [sp, x0]
 // CHECK-ENCODING: [0xe0,0x43,0x00,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 43 00 a4 <unknown>
+// CHECK-UNKNOWN: a40043e0 <unknown>
 
 ld1b    { z0.b }, p0/z, [x0, x0]
 // CHECK-INST: ld1b    { z0.b }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x40,0x00,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 00 a4 <unknown>
+// CHECK-UNKNOWN: a4004000 <unknown>
 
 ld1b    { z0.b }, p0/z, [x0, x0, lsl #0]
 // CHECK-INST: ld1b    { z0.b }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x40,0x00,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 00 a4 <unknown>
+// CHECK-UNKNOWN: a4004000 <unknown>
 
 ld1b    { z5.h }, p3/z, [x17, x16]
 // CHECK-INST: ld1b    { z5.h }, p3/z, [x17, x16]
 // CHECK-ENCODING: [0x25,0x4e,0x30,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 4e 30 a4 <unknown>
+// CHECK-UNKNOWN: a4304e25 <unknown>
 
 ld1b    { z21.s }, p5/z, [x10, x21]
 // CHECK-INST: ld1b    { z21.s }, p5/z, [x10, x21]
 // CHECK-ENCODING: [0x55,0x55,0x55,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 55 55 a4 <unknown>
+// CHECK-UNKNOWN: a4555555 <unknown>
 
 ld1b    { z23.d }, p3/z, [x13, x8]
 // CHECK-INST: ld1b    { z23.d }, p3/z, [x13, x8]
 // CHECK-ENCODING: [0xb7,0x4d,0x68,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 4d 68 a4 <unknown>
+// CHECK-UNKNOWN: a4684db7 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1d-sve-only.s b/llvm/test/MC/AArch64/SVE/ld1d-sve-only.s
index 55efbe2f252e6..0d8009983c1e5 100644
--- a/llvm/test/MC/AArch64/SVE/ld1d-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/ld1d-sve-only.s
@@ -15,46 +15,46 @@ ld1d    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ld1d    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0xdf,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff df df c5 <unknown>
+// CHECK-UNKNOWN: c5dfdfff <unknown>
 
 ld1d    { z23.d }, p3/z, [x13, z8.d, lsl #3]
 // CHECK-INST: ld1d    { z23.d }, p3/z, [x13, z8.d, lsl #3]
 // CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: b7 cd e8 c5 <unknown>
+// CHECK-UNKNOWN: c5e8cdb7 <unknown>
 
 ld1d    { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ld1d    { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x55,0x95,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 55 95 c5 <unknown>
+// CHECK-UNKNOWN: c5955555 <unknown>
 
 ld1d    { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ld1d    { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x55,0xd5,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 55 d5 c5 <unknown>
+// CHECK-UNKNOWN: c5d55555 <unknown>
 
 ld1d    { z0.d }, p0/z, [x0, z0.d, uxtw #3]
 // CHECK-INST: ld1d    { z0.d }, p0/z, [x0, z0.d, uxtw #3]
 // CHECK-ENCODING: [0x00,0x40,0xa0,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 a0 c5 <unknown>
+// CHECK-UNKNOWN: c5a04000 <unknown>
 
 ld1d    { z0.d }, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-INST: ld1d    { z0.d }, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-ENCODING: [0x00,0x40,0xe0,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 e0 c5 <unknown>
+// CHECK-UNKNOWN: c5e04000 <unknown>
 
 ld1d    { z31.d }, p7/z, [z31.d, #248]
 // CHECK-INST: ld1d    { z31.d }, p7/z, [z31.d, #248]
 // CHECK-ENCODING: [0xff,0xdf,0xbf,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff df bf c5 <unknown>
+// CHECK-UNKNOWN: c5bfdfff <unknown>
 
 ld1d    { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ld1d    { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0xc0,0xa0,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 a0 c5 <unknown>
+// CHECK-UNKNOWN: c5a0c000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1d.s b/llvm/test/MC/AArch64/SVE/ld1d.s
index c4f53e306e378..01b02b5243ed3 100644
--- a/llvm/test/MC/AArch64/SVE/ld1d.s
+++ b/llvm/test/MC/AArch64/SVE/ld1d.s
@@ -13,34 +13,34 @@ ld1d     z0.d, p0/z, [x0]
 // CHECK-INST: ld1d     { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xe0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 e0 a5 <unknown>
+// CHECK-UNKNOWN: a5e0a000 <unknown>
 
 ld1d    { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1d    { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xe0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 e0 a5 <unknown>
+// CHECK-UNKNOWN: a5e0a000 <unknown>
 
 ld1d    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1d    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0xef,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf ef a5 <unknown>
+// CHECK-UNKNOWN: a5efbfff <unknown>
 
 ld1d    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1d    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xe5,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 e5 a5 <unknown>
+// CHECK-UNKNOWN: a5e5b555 <unknown>
 
 ld1d    { z23.d }, p3/z, [sp, x8, lsl #3]
 // CHECK-INST: ld1d    { z23.d }, p3/z, [sp, x8, lsl #3]
 // CHECK-ENCODING: [0xf7,0x4f,0xe8,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f7 4f e8 a5 <unknown>
+// CHECK-UNKNOWN: a5e84ff7 <unknown>
 
 ld1d    { z23.d }, p3/z, [x13, x8, lsl #3]
 // CHECK-INST: ld1d    { z23.d }, p3/z, [x13, x8, lsl #3]
 // CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 4d e8 a5 <unknown>
+// CHECK-UNKNOWN: a5e84db7 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1h-sve-only.s b/llvm/test/MC/AArch64/SVE/ld1h-sve-only.s
index b151259cca827..a03104e763e2b 100644
--- a/llvm/test/MC/AArch64/SVE/ld1h-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/ld1h-sve-only.s
@@ -15,82 +15,82 @@ ld1h    { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-INST: ld1h    { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-ENCODING: [0x00,0x40,0x80,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 80 84 <unknown>
+// CHECK-UNKNOWN: 84804000 <unknown>
 
 ld1h    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ld1h    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x40,0xc0,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 c0 84 <unknown>
+// CHECK-UNKNOWN: 84c04000 <unknown>
 
 ld1h    { z31.s }, p7/z, [sp, z31.s, uxtw #1]
 // CHECK-INST: ld1h    { z31.s }, p7/z, [sp, z31.s, uxtw #1]
 // CHECK-ENCODING: [0xff,0x5f,0xbf,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 5f bf 84 <unknown>
+// CHECK-UNKNOWN: 84bf5fff <unknown>
 
 ld1h    { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-INST: ld1h    { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-ENCODING: [0xff,0x5f,0xff,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 5f ff 84 <unknown>
+// CHECK-UNKNOWN: 84ff5fff <unknown>
 
 ld1h    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ld1h    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0xdf,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff df df c4 <unknown>
+// CHECK-UNKNOWN: c4dfdfff <unknown>
 
 ld1h    { z23.d }, p3/z, [x13, z8.d, lsl #1]
 // CHECK-INST: ld1h    { z23.d }, p3/z, [x13, z8.d, lsl #1]
 // CHECK-ENCODING: [0xb7,0xcd,0xe8,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: b7 cd e8 c4 <unknown>
+// CHECK-UNKNOWN: c4e8cdb7 <unknown>
 
 ld1h    { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ld1h    { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x55,0x95,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 55 95 c4 <unknown>
+// CHECK-UNKNOWN: c4955555 <unknown>
 
 ld1h    { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ld1h    { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x55,0xd5,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 55 d5 c4 <unknown>
+// CHECK-UNKNOWN: c4d55555 <unknown>
 
 ld1h    { z0.d }, p0/z, [x0, z0.d, uxtw #1]
 // CHECK-INST: ld1h    { z0.d }, p0/z, [x0, z0.d, uxtw #1]
 // CHECK-ENCODING: [0x00,0x40,0xa0,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 a0 c4 <unknown>
+// CHECK-UNKNOWN: c4a04000 <unknown>
 
 ld1h    { z0.d }, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-INST: ld1h    { z0.d }, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-ENCODING: [0x00,0x40,0xe0,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 e0 c4 <unknown>
+// CHECK-UNKNOWN: c4e04000 <unknown>
 
 ld1h    { z31.s }, p7/z, [z31.s, #62]
 // CHECK-INST: ld1h    { z31.s }, p7/z, [z31.s, #62]
 // CHECK-ENCODING: [0xff,0xdf,0xbf,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff df bf 84 <unknown>
+// CHECK-UNKNOWN: 84bfdfff <unknown>
 
 ld1h    { z0.s }, p0/z, [z0.s]
 // CHECK-INST: ld1h    { z0.s }, p0/z, [z0.s]
 // CHECK-ENCODING: [0x00,0xc0,0xa0,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 a0 84 <unknown>
+// CHECK-UNKNOWN: 84a0c000 <unknown>
 
 ld1h    { z31.d }, p7/z, [z31.d, #62]
 // CHECK-INST: ld1h    { z31.d }, p7/z, [z31.d, #62]
 // CHECK-ENCODING: [0xff,0xdf,0xbf,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff df bf c4 <unknown>
+// CHECK-UNKNOWN: c4bfdfff <unknown>
 
 ld1h    { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ld1h    { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0xc0,0xa0,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 a0 c4 <unknown>
+// CHECK-UNKNOWN: c4a0c000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1h.s b/llvm/test/MC/AArch64/SVE/ld1h.s
index a580bd7087e9b..e4b9efe95c15d 100644
--- a/llvm/test/MC/AArch64/SVE/ld1h.s
+++ b/llvm/test/MC/AArch64/SVE/ld1h.s
@@ -13,94 +13,94 @@ ld1h     z0.h, p0/z, [x0]
 // CHECK-INST: ld1h     { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xa0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 a0 a4 <unknown>
+// CHECK-UNKNOWN: a4a0a000 <unknown>
 
 ld1h     z0.s, p0/z, [x0]
 // CHECK-INST: ld1h     { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xc0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 c0 a4 <unknown>
+// CHECK-UNKNOWN: a4c0a000 <unknown>
 
 ld1h     z0.d, p0/z, [x0]
 // CHECK-INST: ld1h     { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xe0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 e0 a4 <unknown>
+// CHECK-UNKNOWN: a4e0a000 <unknown>
 
 ld1h    { z0.h }, p0/z, [x0]
 // CHECK-INST: ld1h    { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xa0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 a0 a4 <unknown>
+// CHECK-UNKNOWN: a4a0a000 <unknown>
 
 ld1h    { z0.s }, p0/z, [x0]
 // CHECK-INST: ld1h    { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xc0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 c0 a4 <unknown>
+// CHECK-UNKNOWN: a4c0a000 <unknown>
 
 ld1h    { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1h    { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xe0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 e0 a4 <unknown>
+// CHECK-UNKNOWN: a4e0a000 <unknown>
 
 ld1h    { z31.h }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1h    { z31.h }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0xaf,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf af a4 <unknown>
+// CHECK-UNKNOWN: a4afbfff <unknown>
 
 ld1h    { z21.h }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1h    { z21.h }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xa5,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 a5 a4 <unknown>
+// CHECK-UNKNOWN: a4a5b555 <unknown>
 
 ld1h    { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1h    { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0xcf,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf cf a4 <unknown>
+// CHECK-UNKNOWN: a4cfbfff <unknown>
 
 ld1h    { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1h    { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xc5,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 c5 a4 <unknown>
+// CHECK-UNKNOWN: a4c5b555 <unknown>
 
 ld1h    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1h    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0xef,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf ef a4 <unknown>
+// CHECK-UNKNOWN: a4efbfff <unknown>
 
 ld1h    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1h    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xe5,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 e5 a4 <unknown>
+// CHECK-UNKNOWN: a4e5b555 <unknown>
 
 ld1h    { z5.h }, p3/z, [sp, x16, lsl #1]
 // CHECK-INST: ld1h    { z5.h }, p3/z, [sp, x16, lsl #1]
 // CHECK-ENCODING: [0xe5,0x4f,0xb0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 4f b0 a4 <unknown>
+// CHECK-UNKNOWN: a4b04fe5 <unknown>
 
 ld1h    { z5.h }, p3/z, [x17, x16, lsl #1]
 // CHECK-INST: ld1h    { z5.h }, p3/z, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x4e,0xb0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 4e b0 a4 <unknown>
+// CHECK-UNKNOWN: a4b04e25 <unknown>
 
 ld1h    { z21.s }, p5/z, [x10, x21, lsl #1]
 // CHECK-INST: ld1h    { z21.s }, p5/z, [x10, x21, lsl #1]
 // CHECK-ENCODING: [0x55,0x55,0xd5,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 55 d5 a4 <unknown>
+// CHECK-UNKNOWN: a4d55555 <unknown>
 
 ld1h    { z23.d }, p3/z, [x13, x8, lsl #1]
 // CHECK-INST: ld1h    { z23.d }, p3/z, [x13, x8, lsl #1]
 // CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 4d e8 a4 <unknown>
+// CHECK-UNKNOWN: a4e84db7 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1rb.s b/llvm/test/MC/AArch64/SVE/ld1rb.s
index eef2b43399fd1..0de3873b927d4 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rb.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rb.s
@@ -13,46 +13,46 @@ ld1rb   { z0.b }, p0/z, [x0]
 // CHECK-INST: ld1rb   { z0.b }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0x80,0x40,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 40 84 <unknown>
+// CHECK-UNKNOWN: 84408000 <unknown>
 
 ld1rb   { z0.h }, p0/z, [x0]
 // CHECK-INST: ld1rb   { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x40,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 40 84 <unknown>
+// CHECK-UNKNOWN: 8440a000 <unknown>
 
 ld1rb   { z0.s }, p0/z, [x0]
 // CHECK-INST: ld1rb   { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xc0,0x40,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 40 84 <unknown>
+// CHECK-UNKNOWN: 8440c000 <unknown>
 
 ld1rb   { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1rb   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x40,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 40 84 <unknown>
+// CHECK-UNKNOWN: 8440e000 <unknown>
 
 ld1rb   { z31.b }, p7/z, [sp, #63]
 // CHECK-INST: ld1rb   { z31.b }, p7/z, [sp, #63]
 // CHECK-ENCODING: [0xff,0x9f,0x7f,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f 7f 84 <unknown>
+// CHECK-UNKNOWN: 847f9fff <unknown>
 
 ld1rb   { z31.h }, p7/z, [sp, #63]
 // CHECK-INST: ld1rb   { z31.h }, p7/z, [sp, #63]
 // CHECK-ENCODING: [0xff,0xbf,0x7f,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 7f 84 <unknown>
+// CHECK-UNKNOWN: 847fbfff <unknown>
 
 ld1rb   { z31.s }, p7/z, [sp, #63]
 // CHECK-INST: ld1rb   { z31.s }, p7/z, [sp, #63]
 // CHECK-ENCODING: [0xff,0xdf,0x7f,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 7f 84 <unknown>
+// CHECK-UNKNOWN: 847fdfff <unknown>
 
 ld1rb   { z31.d }, p7/z, [sp, #63]
 // CHECK-INST: ld1rb   { z31.d }, p7/z, [sp, #63]
 // CHECK-ENCODING: [0xff,0xff,0x7f,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 7f 84 <unknown>
+// CHECK-UNKNOWN: 847fffff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1rd.s b/llvm/test/MC/AArch64/SVE/ld1rd.s
index 1c7aa9f30cd59..3c46cea203f1d 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rd.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rd.s
@@ -13,10 +13,10 @@ ld1rd   { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1rd   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0e000 <unknown>
 
 ld1rd   { z31.d }, p7/z, [sp, #504]
 // CHECK-INST: ld1rd   { z31.d }, p7/z, [sp, #504]
 // CHECK-ENCODING: [0xff,0xff,0xff,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff ff 85 <unknown>
+// CHECK-UNKNOWN: 85ffffff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1rh.s b/llvm/test/MC/AArch64/SVE/ld1rh.s
index 419b9ff79c351..a51ae380a91f0 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rh.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rh.s
@@ -13,34 +13,34 @@ ld1rh   { z0.h }, p0/z, [x0]
 // CHECK-INST: ld1rh   { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xc0,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 c0 84 <unknown>
+// CHECK-UNKNOWN: 84c0a000 <unknown>
 
 ld1rh   { z0.s }, p0/z, [x0]
 // CHECK-INST: ld1rh   { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xc0,0xc0,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 c0 84 <unknown>
+// CHECK-UNKNOWN: 84c0c000 <unknown>
 
 ld1rh   { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1rh   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xc0,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 c0 84 <unknown>
+// CHECK-UNKNOWN: 84c0e000 <unknown>
 
 ld1rh   { z31.h }, p7/z, [sp, #126]
 // CHECK-INST: ld1rh   { z31.h }, p7/z, [sp, #126]
 // CHECK-ENCODING: [0xff,0xbf,0xff,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf ff 84 <unknown>
+// CHECK-UNKNOWN: 84ffbfff <unknown>
 
 ld1rh   { z31.s }, p7/z, [sp, #126]
 // CHECK-INST: ld1rh   { z31.s }, p7/z, [sp, #126]
 // CHECK-ENCODING: [0xff,0xdf,0xff,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df ff 84 <unknown>
+// CHECK-UNKNOWN: 84ffdfff <unknown>
 
 ld1rh   { z31.d }, p7/z, [sp, #126]
 // CHECK-INST: ld1rh   { z31.d }, p7/z, [sp, #126]
 // CHECK-ENCODING: [0xff,0xff,0xff,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff ff 84 <unknown>
+// CHECK-UNKNOWN: 84ffffff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1rqb.s b/llvm/test/MC/AArch64/SVE/ld1rqb.s
index c48883fb79d13..d53915b621d81 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rqb.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rqb.s
@@ -13,28 +13,28 @@ ld1rqb  { z0.b }, p0/z, [x0]
 // CHECK-INST: ld1rqb  { z0.b }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0x20,0x00,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 00 a4 <unknown>
+// CHECK-UNKNOWN: a4002000 <unknown>
 
 ld1rqb  { z0.b }, p0/z, [x0, x0]
 // CHECK-INST: ld1rqb  { z0.b }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x00,0x00,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 00 a4 <unknown>
+// CHECK-UNKNOWN: a4000000 <unknown>
 
 ld1rqb  { z31.b }, p7/z, [sp, #-16]
 // CHECK-INST: ld1rqb  { z31.b }, p7/z, [sp, #-16]
 // CHECK-ENCODING: [0xff,0x3f,0x0f,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3f 0f a4 <unknown>
+// CHECK-UNKNOWN: a40f3fff <unknown>
 
 ld1rqb  {  z23.b  }, p3/z, [x13, #-128]
 // CHECK-INST: ld1rqb  {  z23.b  }, p3/z, [x13, #-128]
 // CHECK-ENCODING: [0xb7,0x2d,0x08,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 2d 08 a4 <unknown>
+// CHECK-UNKNOWN: a4082db7 <unknown>
 
 ld1rqb  {  z21.b  }, p5/z, [x10, #112]
 // CHECK-INST: ld1rqb  {  z21.b  }, p5/z, [x10, #112]
 // CHECK-ENCODING: [0x55,0x35,0x07,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 35 07 a4 <unknown>
+// CHECK-UNKNOWN: a4073555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1rqd.s b/llvm/test/MC/AArch64/SVE/ld1rqd.s
index 500ee293407e0..b4bae89257182 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rqd.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rqd.s
@@ -13,28 +13,28 @@ ld1rqd  { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1rqd  { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0x20,0x80,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 80 a5 <unknown>
+// CHECK-UNKNOWN: a5802000 <unknown>
 
 ld1rqd  { z0.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-INST: ld1rqd  { z0.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x00,0x80,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 80 a5 <unknown>
+// CHECK-UNKNOWN: a5800000 <unknown>
 
 ld1rqd  { z31.d }, p7/z, [sp, #-16]
 // CHECK-INST: ld1rqd  { z31.d }, p7/z, [sp, #-16]
 // CHECK-ENCODING: [0xff,0x3f,0x8f,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3f 8f a5 <unknown>
+// CHECK-UNKNOWN: a58f3fff <unknown>
 
 ld1rqd  { z23.d }, p3/z, [x13, #-128]
 // CHECK-INST: ld1rqd  { z23.d }, p3/z, [x13, #-128]
 // CHECK-ENCODING: [0xb7,0x2d,0x88,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 2d 88 a5 <unknown>
+// CHECK-UNKNOWN: a5882db7 <unknown>
 
 ld1rqd  { z23.d }, p3/z, [x13, #112]
 // CHECK-INST: ld1rqd  { z23.d }, p3/z, [x13, #112]
 // CHECK-ENCODING: [0xb7,0x2d,0x87,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 2d 87 a5 <unknown>
+// CHECK-UNKNOWN: a5872db7 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1rqh.s b/llvm/test/MC/AArch64/SVE/ld1rqh.s
index 821aa55ab843c..286d678b3ab4e 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rqh.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rqh.s
@@ -13,28 +13,28 @@ ld1rqh  { z0.h }, p0/z, [x0]
 // CHECK-INST: ld1rqh  { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0x20,0x80,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 80 a4 <unknown>
+// CHECK-UNKNOWN: a4802000 <unknown>
 
 ld1rqh  { z0.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ld1rqh  { z0.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x00,0x80,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 80 a4 <unknown>
+// CHECK-UNKNOWN: a4800000 <unknown>
 
 ld1rqh  { z31.h }, p7/z, [sp, #-16]
 // CHECK-INST: ld1rqh  { z31.h }, p7/z, [sp, #-16]
 // CHECK-ENCODING: [0xff,0x3f,0x8f,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3f 8f a4 <unknown>
+// CHECK-UNKNOWN: a48f3fff <unknown>
 
 ld1rqh  { z23.h }, p3/z, [x13, #-128]
 // CHECK-INST: ld1rqh  { z23.h }, p3/z, [x13, #-128]
 // CHECK-ENCODING: [0xb7,0x2d,0x88,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 2d 88 a4 <unknown>
+// CHECK-UNKNOWN: a4882db7 <unknown>
 
 ld1rqh  { z23.h }, p3/z, [x13, #112]
 // CHECK-INST: ld1rqh  { z23.h }, p3/z, [x13, #112]
 // CHECK-ENCODING: [0xb7,0x2d,0x87,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 2d 87 a4 <unknown>
+// CHECK-UNKNOWN: a4872db7 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1rqw.s b/llvm/test/MC/AArch64/SVE/ld1rqw.s
index ae4f3db4b34ac..8018a168ae3a8 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rqw.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rqw.s
@@ -13,28 +13,28 @@ ld1rqw  { z0.s }, p0/z, [x0]
 // CHECK-INST: ld1rqw  { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0x20,0x00,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 00 a5 <unknown>
+// CHECK-UNKNOWN: a5002000 <unknown>
 
 ld1rqw  { z0.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ld1rqw  { z0.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x00,0x00,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 00 a5 <unknown>
+// CHECK-UNKNOWN: a5000000 <unknown>
 
 ld1rqw  { z31.s }, p7/z, [sp, #-16]
 // CHECK-INST: ld1rqw  { z31.s }, p7/z, [sp, #-16]
 // CHECK-ENCODING: [0xff,0x3f,0x0f,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3f 0f a5 <unknown>
+// CHECK-UNKNOWN: a50f3fff <unknown>
 
 ld1rqw  { z23.s }, p3/z, [x13, #-128]
 // CHECK-INST: ld1rqw  { z23.s }, p3/z, [x13, #-128]
 // CHECK-ENCODING: [0xb7,0x2d,0x08,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 2d 08 a5 <unknown>
+// CHECK-UNKNOWN: a5082db7 <unknown>
 
 ld1rqw  { z23.s }, p3/z, [x13, #112]
 // CHECK-INST: ld1rqw  { z23.s }, p3/z, [x13, #112]
 // CHECK-ENCODING: [0xb7,0x2d,0x07,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 2d 07 a5 <unknown>
+// CHECK-UNKNOWN: a5072db7 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1rsb.s b/llvm/test/MC/AArch64/SVE/ld1rsb.s
index 3738b50c81fe5..6566f4d4cd3f3 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rsb.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rsb.s
@@ -13,34 +13,34 @@ ld1rsb  { z0.h }, p0/z, [x0]
 // CHECK-INST: ld1rsb  { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xc0,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0c000 <unknown>
 
 ld1rsb  { z0.s }, p0/z, [x0]
 // CHECK-INST: ld1rsb  { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0a000 <unknown>
 
 ld1rsb  { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1rsb  { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0x80,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c08000 <unknown>
 
 ld1rsb  { z31.h }, p7/z, [sp, #63]
 // CHECK-INST: ld1rsb  { z31.h }, p7/z, [sp, #63]
 // CHECK-ENCODING: [0xff,0xdf,0xff,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df ff 85 <unknown>
+// CHECK-UNKNOWN: 85ffdfff <unknown>
 
 ld1rsb  { z31.s }, p7/z, [sp, #63]
 // CHECK-INST: ld1rsb  { z31.s }, p7/z, [sp, #63]
 // CHECK-ENCODING: [0xff,0xbf,0xff,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf ff 85 <unknown>
+// CHECK-UNKNOWN: 85ffbfff <unknown>
 
 ld1rsb  { z31.d }, p7/z, [sp, #63]
 // CHECK-INST: ld1rsb  { z31.d }, p7/z, [sp, #63]
 // CHECK-ENCODING: [0xff,0x9f,0xff,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f ff 85 <unknown>
+// CHECK-UNKNOWN: 85ff9fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1rsh.s b/llvm/test/MC/AArch64/SVE/ld1rsh.s
index 8464d50ffa018..e86e38767cdc7 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rsh.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rsh.s
@@ -13,22 +13,22 @@ ld1rsh  { z0.s }, p0/z, [x0]
 // CHECK-INST: ld1rsh  { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x40,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 40 85 <unknown>
+// CHECK-UNKNOWN: 8540a000 <unknown>
 
 ld1rsh  { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1rsh  { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0x80,0x40,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 40 85 <unknown>
+// CHECK-UNKNOWN: 85408000 <unknown>
 
 ld1rsh  { z31.s }, p7/z, [sp, #126]
 // CHECK-INST: ld1rsh  { z31.s }, p7/z, [sp, #126]
 // CHECK-ENCODING: [0xff,0xbf,0x7f,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 7f 85 <unknown>
+// CHECK-UNKNOWN: 857fbfff <unknown>
 
 ld1rsh  { z31.d }, p7/z, [sp, #126]
 // CHECK-INST: ld1rsh  { z31.d }, p7/z, [sp, #126]
 // CHECK-ENCODING: [0xff,0x9f,0x7f,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f 7f 85 <unknown>
+// CHECK-UNKNOWN: 857f9fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1rsw.s b/llvm/test/MC/AArch64/SVE/ld1rsw.s
index 4b54a670934dd..f0ccb9ab612da 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rsw.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rsw.s
@@ -13,10 +13,10 @@ ld1rsw  { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1rsw  { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0x80,0xc0,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 c0 84 <unknown>
+// CHECK-UNKNOWN: 84c08000 <unknown>
 
 ld1rsw  { z31.d }, p7/z, [sp, #252]
 // CHECK-INST: ld1rsw  { z31.d }, p7/z, [sp, #252]
 // CHECK-ENCODING: [0xff,0x9f,0xff,0x84]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f ff 84 <unknown>
+// CHECK-UNKNOWN: 84ff9fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1rw.s b/llvm/test/MC/AArch64/SVE/ld1rw.s
index 0b6e2e551a95a..7fd87b78e91ea 100644
--- a/llvm/test/MC/AArch64/SVE/ld1rw.s
+++ b/llvm/test/MC/AArch64/SVE/ld1rw.s
@@ -13,22 +13,22 @@ ld1rw   { z0.s }, p0/z, [x0]
 // CHECK-INST: ld1rw   { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xc0,0x40,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 40 85 <unknown>
+// CHECK-UNKNOWN: 8540c000 <unknown>
 
 ld1rw   { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1rw   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x40,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 40 85 <unknown>
+// CHECK-UNKNOWN: 8540e000 <unknown>
 
 ld1rw   { z31.s }, p7/z, [sp, #252]
 // CHECK-INST: ld1rw   { z31.s }, p7/z, [sp, #252]
 // CHECK-ENCODING: [0xff,0xdf,0x7f,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 7f 85 <unknown>
+// CHECK-UNKNOWN: 857fdfff <unknown>
 
 ld1rw   { z31.d }, p7/z, [sp, #252]
 // CHECK-INST: ld1rw   { z31.d }, p7/z, [sp, #252]
 // CHECK-ENCODING: [0xff,0xff,0x7f,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 7f 85 <unknown>
+// CHECK-UNKNOWN: 857fffff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1sb-sve-only.s b/llvm/test/MC/AArch64/SVE/ld1sb-sve-only.s
index 7bbc1397b3367..fb48af3588251 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sb-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sb-sve-only.s
@@ -15,46 +15,46 @@ ld1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ld1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x00,0x40,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 00 40 84 <unknown>
+// CHECK-UNKNOWN: 84400000 <unknown>
 
 ld1sb   { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ld1sb   { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0x9f,0x5f,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 9f 5f c4 <unknown>
+// CHECK-UNKNOWN: c45f9fff <unknown>
 
 ld1sb   { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ld1sb   { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x15,0x15,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 15 15 c4 <unknown>
+// CHECK-UNKNOWN: c4151555 <unknown>
 
 ld1sb   { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ld1sb   { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x15,0x55,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 15 55 c4 <unknown>
+// CHECK-UNKNOWN: c4551555 <unknown>
 
 ld1sb   { z31.s }, p7/z, [z31.s, #31]
 // CHECK-INST: ld1sb   { z31.s }, p7/z, [z31.s, #31]
 // CHECK-ENCODING: [0xff,0x9f,0x3f,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 9f 3f 84 <unknown>
+// CHECK-UNKNOWN: 843f9fff <unknown>
 
 ld1sb   { z0.s }, p0/z, [z0.s]
 // CHECK-INST: ld1sb   { z0.s }, p0/z, [z0.s]
 // CHECK-ENCODING: [0x00,0x80,0x20,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 20 84 <unknown>
+// CHECK-UNKNOWN: 84208000 <unknown>
 
 ld1sb   { z31.d }, p7/z, [z31.d, #31]
 // CHECK-INST: ld1sb   { z31.d }, p7/z, [z31.d, #31]
 // CHECK-ENCODING: [0xff,0x9f,0x3f,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 9f 3f c4 <unknown>
+// CHECK-UNKNOWN: c43f9fff <unknown>
 
 ld1sb   { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ld1sb   { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0x80,0x20,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 20 c4 <unknown>
+// CHECK-UNKNOWN: c4208000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1sb.s b/llvm/test/MC/AArch64/SVE/ld1sb.s
index 8b3e50ffbd02d..77f3196796d84 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sb.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sb.s
@@ -13,100 +13,100 @@ ld1sb   z0.h, p0/z, [x0]
 // CHECK-INST: ld1sb   { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xc0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 c0 a5 <unknown>
+// CHECK-UNKNOWN: a5c0a000 <unknown>
 
 ld1sb   z0.s, p0/z, [x0]
 // CHECK-INST: ld1sb   { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xa0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 a0 a5 <unknown>
+// CHECK-UNKNOWN: a5a0a000 <unknown>
 
 ld1sb   z0.d, p0/z, [x0]
 // CHECK-INST: ld1sb   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x80,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 80 a5 <unknown>
+// CHECK-UNKNOWN: a580a000 <unknown>
 
 ld1sb   { z0.h }, p0/z, [x0]
 // CHECK-INST: ld1sb   { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xc0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 c0 a5 <unknown>
+// CHECK-UNKNOWN: a5c0a000 <unknown>
 
 ld1sb   { z0.s }, p0/z, [x0]
 // CHECK-INST: ld1sb   { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xa0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 a0 a5 <unknown>
+// CHECK-UNKNOWN: a5a0a000 <unknown>
 
 ld1sb   { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1sb   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x80,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 80 a5 <unknown>
+// CHECK-UNKNOWN: a580a000 <unknown>
 
 ld1sb   { z31.h }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1sb   { z31.h }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0xcf,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf cf a5 <unknown>
+// CHECK-UNKNOWN: a5cfbfff <unknown>
 
 ld1sb   { z21.h }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1sb   { z21.h }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xc5,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 c5 a5 <unknown>
+// CHECK-UNKNOWN: a5c5b555 <unknown>
 
 ld1sb   { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1sb   { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0xaf,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf af a5 <unknown>
+// CHECK-UNKNOWN: a5afbfff <unknown>
 
 ld1sb   { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1sb   { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xa5,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 a5 a5 <unknown>
+// CHECK-UNKNOWN: a5a5b555 <unknown>
 
 ld1sb   { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1sb   { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x8f,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 8f a5 <unknown>
+// CHECK-UNKNOWN: a58fbfff <unknown>
 
 ld1sb   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1sb   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x85,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 85 a5 <unknown>
+// CHECK-UNKNOWN: a585b555 <unknown>
 
 ld1sb    { z0.h }, p0/z, [sp, x0]
 // CHECK-INST: ld1sb    { z0.h }, p0/z, [sp, x0]
 // CHECK-ENCODING: [0xe0,0x43,0xc0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 43 c0 a5 <unknown>
+// CHECK-UNKNOWN: a5c043e0 <unknown>
 
 ld1sb    { z0.h }, p0/z, [x0, x0]
 // CHECK-INST: ld1sb    { z0.h }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x40,0xc0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 c0 a5 <unknown>
+// CHECK-UNKNOWN: a5c04000 <unknown>
 
 ld1sb    { z0.h }, p0/z, [x0, x0, lsl #0]
 // CHECK-INST: ld1sb    { z0.h }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x40,0xc0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 c0 a5 <unknown>
+// CHECK-UNKNOWN: a5c04000 <unknown>
 
 ld1sb    { z21.s }, p5/z, [x10, x21]
 // CHECK-INST: ld1sb    { z21.s }, p5/z, [x10, x21]
 // CHECK-ENCODING: [0x55,0x55,0xb5,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 55 b5 a5 <unknown>
+// CHECK-UNKNOWN: a5b55555 <unknown>
 
 ld1sb    { z23.d }, p3/z, [x13, x8]
 // CHECK-INST: ld1sb    { z23.d }, p3/z, [x13, x8]
 // CHECK-ENCODING: [0xb7,0x4d,0x88,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 4d 88 a5 <unknown>
+// CHECK-UNKNOWN: a5884db7 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1sh-sve-only.s b/llvm/test/MC/AArch64/SVE/ld1sh-sve-only.s
index fa6f62f309ebd..16f901c3971e6 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sh-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sh-sve-only.s
@@ -15,82 +15,82 @@ ld1sh   { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-INST: ld1sh   { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-ENCODING: [0x00,0x00,0x80,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 00 80 84 <unknown>
+// CHECK-UNKNOWN: 84800000 <unknown>
 
 ld1sh   { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ld1sh   { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x00,0xc0,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 00 c0 84 <unknown>
+// CHECK-UNKNOWN: 84c00000 <unknown>
 
 ld1sh   { z31.s }, p7/z, [sp, z31.s, uxtw #1]
 // CHECK-INST: ld1sh   { z31.s }, p7/z, [sp, z31.s, uxtw #1]
 // CHECK-ENCODING: [0xff,0x1f,0xbf,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 1f bf 84 <unknown>
+// CHECK-UNKNOWN: 84bf1fff <unknown>
 
 ld1sh   { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-INST: ld1sh   { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-ENCODING: [0xff,0x1f,0xff,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 1f ff 84 <unknown>
+// CHECK-UNKNOWN: 84ff1fff <unknown>
 
 ld1sh   { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ld1sh   { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0x9f,0xdf,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 9f df c4 <unknown>
+// CHECK-UNKNOWN: c4df9fff <unknown>
 
 ld1sh   { z23.d }, p3/z, [x13, z8.d, lsl #1]
 // CHECK-INST: ld1sh   { z23.d }, p3/z, [x13, z8.d, lsl #1]
 // CHECK-ENCODING: [0xb7,0x8d,0xe8,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: b7 8d e8 c4 <unknown>
+// CHECK-UNKNOWN: c4e88db7 <unknown>
 
 ld1sh   { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ld1sh   { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x15,0x95,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 15 95 c4 <unknown>
+// CHECK-UNKNOWN: c4951555 <unknown>
 
 ld1sh   { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ld1sh   { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x15,0xd5,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 15 d5 c4 <unknown>
+// CHECK-UNKNOWN: c4d51555 <unknown>
 
 ld1sh   { z0.d }, p0/z, [x0, z0.d, uxtw #1]
 // CHECK-INST: ld1sh   { z0.d }, p0/z, [x0, z0.d, uxtw #1]
 // CHECK-ENCODING: [0x00,0x00,0xa0,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 00 a0 c4 <unknown>
+// CHECK-UNKNOWN: c4a00000 <unknown>
 
 ld1sh   { z0.d }, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-INST: ld1sh   { z0.d }, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-ENCODING: [0x00,0x00,0xe0,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 00 e0 c4 <unknown>
+// CHECK-UNKNOWN: c4e00000 <unknown>
 
 ld1sh   { z31.s }, p7/z, [z31.s, #62]
 // CHECK-INST: ld1sh   { z31.s }, p7/z, [z31.s, #62]
 // CHECK-ENCODING: [0xff,0x9f,0xbf,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 9f bf 84 <unknown>
+// CHECK-UNKNOWN: 84bf9fff <unknown>
 
 ld1sh   { z0.s }, p0/z, [z0.s]
 // CHECK-INST: ld1sh   { z0.s }, p0/z, [z0.s]
 // CHECK-ENCODING: [0x00,0x80,0xa0,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 a0 84 <unknown>
+// CHECK-UNKNOWN: 84a08000 <unknown>
 
 ld1sh   { z31.d }, p7/z, [z31.d, #62]
 // CHECK-INST: ld1sh   { z31.d }, p7/z, [z31.d, #62]
 // CHECK-ENCODING: [0xff,0x9f,0xbf,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 9f bf c4 <unknown>
+// CHECK-UNKNOWN: c4bf9fff <unknown>
 
 ld1sh   { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ld1sh   { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0x80,0xa0,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 a0 c4 <unknown>
+// CHECK-UNKNOWN: c4a08000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1sh.s b/llvm/test/MC/AArch64/SVE/ld1sh.s
index 11ff84bf2d65b..8665f2e5b2110 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sh.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sh.s
@@ -13,64 +13,64 @@ ld1sh   z0.s, p0/z, [x0]
 // CHECK-INST: ld1sh   { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x20,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 20 a5 <unknown>
+// CHECK-UNKNOWN: a520a000 <unknown>
 
 ld1sh   z0.d, p0/z, [x0]
 // CHECK-INST: ld1sh   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x00,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 00 a5 <unknown>
+// CHECK-UNKNOWN: a500a000 <unknown>
 
 ld1sh   { z0.s }, p0/z, [x0]
 // CHECK-INST: ld1sh   { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x20,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 20 a5 <unknown>
+// CHECK-UNKNOWN: a520a000 <unknown>
 
 ld1sh   { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1sh   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x00,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 00 a5 <unknown>
+// CHECK-UNKNOWN: a500a000 <unknown>
 
 ld1sh   { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1sh   { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x2f,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 2f a5 <unknown>
+// CHECK-UNKNOWN: a52fbfff <unknown>
 
 ld1sh   { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1sh   { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x25,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 25 a5 <unknown>
+// CHECK-UNKNOWN: a525b555 <unknown>
 
 ld1sh   { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1sh   { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x0f,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 0f a5 <unknown>
+// CHECK-UNKNOWN: a50fbfff <unknown>
 
 ld1sh   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1sh   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x05,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 05 a5 <unknown>
+// CHECK-UNKNOWN: a505b555 <unknown>
 
 ld1sh    { z21.s }, p5/z, [sp, x21, lsl #1]
 // CHECK-INST: ld1sh    { z21.s }, p5/z, [sp, x21, lsl #1]
 // CHECK-ENCODING: [0xf5,0x57,0x35,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 57 35 a5 <unknown>
+// CHECK-UNKNOWN: a53557f5 <unknown>
 
 ld1sh    { z21.s }, p5/z, [x10, x21, lsl #1]
 // CHECK-INST: ld1sh    { z21.s }, p5/z, [x10, x21, lsl #1]
 // CHECK-ENCODING: [0x55,0x55,0x35,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 55 35 a5 <unknown>
+// CHECK-UNKNOWN: a5355555 <unknown>
 
 ld1sh    { z23.d }, p3/z, [x13, x8, lsl #1]
 // CHECK-INST: ld1sh    { z23.d }, p3/z, [x13, x8, lsl #1]
 // CHECK-ENCODING: [0xb7,0x4d,0x08,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 4d 08 a5 <unknown>
+// CHECK-UNKNOWN: a5084db7 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1sw-sve-only.s b/llvm/test/MC/AArch64/SVE/ld1sw-sve-only.s
index c31d48efecf0c..4063c02008645 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sw-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sw-sve-only.s
@@ -15,46 +15,46 @@ ld1sw   { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ld1sw   { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0x9f,0x5f,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 9f 5f c5 <unknown>
+// CHECK-UNKNOWN: c55f9fff <unknown>
 
 ld1sw   { z23.d }, p3/z, [x13, z8.d, lsl #2]
 // CHECK-INST: ld1sw   { z23.d }, p3/z, [x13, z8.d, lsl #2]
 // CHECK-ENCODING: [0xb7,0x8d,0x68,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: b7 8d 68 c5 <unknown>
+// CHECK-UNKNOWN: c5688db7 <unknown>
 
 ld1sw   { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ld1sw   { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x15,0x15,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 15 15 c5 <unknown>
+// CHECK-UNKNOWN: c5151555 <unknown>
 
 ld1sw   { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ld1sw   { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x15,0x55,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 15 55 c5 <unknown>
+// CHECK-UNKNOWN: c5551555 <unknown>
 
 ld1sw   { z0.d }, p0/z, [x0, z0.d, uxtw #2]
 // CHECK-INST: ld1sw   { z0.d }, p0/z, [x0, z0.d, uxtw #2]
 // CHECK-ENCODING: [0x00,0x00,0x20,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 00 20 c5 <unknown>
+// CHECK-UNKNOWN: c5200000 <unknown>
 
 ld1sw   { z0.d }, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-INST: ld1sw   { z0.d }, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-ENCODING: [0x00,0x00,0x60,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 00 60 c5 <unknown>
+// CHECK-UNKNOWN: c5600000 <unknown>
 
 ld1sw   { z31.d }, p7/z, [z31.d, #124]
 // CHECK-INST: ld1sw   { z31.d }, p7/z, [z31.d, #124]
 // CHECK-ENCODING: [0xff,0x9f,0x3f,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 9f 3f c5 <unknown>
+// CHECK-UNKNOWN: c53f9fff <unknown>
 
 ld1sw   { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ld1sw   { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0x80,0x20,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 20 c5 <unknown>
+// CHECK-UNKNOWN: c5208000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1sw.s b/llvm/test/MC/AArch64/SVE/ld1sw.s
index 0ab44c08ca11a..6cb04bc14ad75 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sw.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sw.s
@@ -13,34 +13,34 @@ ld1sw   z0.d, p0/z, [x0]
 // CHECK-INST: ld1sw   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x80,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 80 a4 <unknown>
+// CHECK-UNKNOWN: a480a000 <unknown>
 
 ld1sw   { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1sw   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x80,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 80 a4 <unknown>
+// CHECK-UNKNOWN: a480a000 <unknown>
 
 ld1sw   { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1sw   { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x8f,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 8f a4 <unknown>
+// CHECK-UNKNOWN: a48fbfff <unknown>
 
 ld1sw   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1sw   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x85,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 85 a4 <unknown>
+// CHECK-UNKNOWN: a485b555 <unknown>
 
 ld1sw    { z23.d }, p3/z, [sp, x8, lsl #2]
 // CHECK-INST: ld1sw    { z23.d }, p3/z, [sp, x8, lsl #2]
 // CHECK-ENCODING: [0xf7,0x4f,0x88,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f7 4f 88 a4 <unknown>
+// CHECK-UNKNOWN: a4884ff7 <unknown>
 
 ld1sw    { z23.d }, p3/z, [x13, x8, lsl #2]
 // CHECK-INST: ld1sw    { z23.d }, p3/z, [x13, x8, lsl #2]
 // CHECK-ENCODING: [0xb7,0x4d,0x88,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 4d 88 a4 <unknown>
+// CHECK-UNKNOWN: a4884db7 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1w-sve-only.s b/llvm/test/MC/AArch64/SVE/ld1w-sve-only.s
index 1d70e01c8b460..848e3d8dbbb30 100644
--- a/llvm/test/MC/AArch64/SVE/ld1w-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/ld1w-sve-only.s
@@ -15,82 +15,82 @@ ld1w    { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-INST: ld1w    { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-ENCODING: [0x00,0x40,0x00,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 00 85 <unknown>
+// CHECK-UNKNOWN: 85004000 <unknown>
 
 ld1w    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ld1w    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x40,0x40,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 40 85 <unknown>
+// CHECK-UNKNOWN: 85404000 <unknown>
 
 ld1w    { z31.s }, p7/z, [sp, z31.s, uxtw #2]
 // CHECK-INST: ld1w    { z31.s }, p7/z, [sp, z31.s, uxtw #2]
 // CHECK-ENCODING: [0xff,0x5f,0x3f,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 5f 3f 85 <unknown>
+// CHECK-UNKNOWN: 853f5fff <unknown>
 
 ld1w    { z31.s }, p7/z, [sp, z31.s, sxtw #2]
 // CHECK-INST: ld1w    { z31.s }, p7/z, [sp, z31.s, sxtw #2]
 // CHECK-ENCODING: [0xff,0x5f,0x7f,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 5f 7f 85 <unknown>
+// CHECK-UNKNOWN: 857f5fff <unknown>
 
 ld1w    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ld1w    { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0x5f,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff df 5f c5 <unknown>
+// CHECK-UNKNOWN: c55fdfff <unknown>
 
 ld1w    { z23.d }, p3/z, [x13, z8.d, lsl #2]
 // CHECK-INST: ld1w    { z23.d }, p3/z, [x13, z8.d, lsl #2]
 // CHECK-ENCODING: [0xb7,0xcd,0x68,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: b7 cd 68 c5 <unknown>
+// CHECK-UNKNOWN: c568cdb7 <unknown>
 
 ld1w    { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ld1w    { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x55,0x15,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 55 15 c5 <unknown>
+// CHECK-UNKNOWN: c5155555 <unknown>
 
 ld1w    { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ld1w    { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x55,0x55,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 55 55 c5 <unknown>
+// CHECK-UNKNOWN: c5555555 <unknown>
 
 ld1w    { z0.d }, p0/z, [x0, z0.d, uxtw #2]
 // CHECK-INST: ld1w    { z0.d }, p0/z, [x0, z0.d, uxtw #2]
 // CHECK-ENCODING: [0x00,0x40,0x20,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 20 c5 <unknown>
+// CHECK-UNKNOWN: c5204000 <unknown>
 
 ld1w    { z0.d }, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-INST: ld1w    { z0.d }, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-ENCODING: [0x00,0x40,0x60,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 60 c5 <unknown>
+// CHECK-UNKNOWN: c5604000 <unknown>
 
 ld1w    { z31.s }, p7/z, [z31.s, #124]
 // CHECK-INST: ld1w    { z31.s }, p7/z, [z31.s, #124]
 // CHECK-ENCODING: [0xff,0xdf,0x3f,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff df 3f 85 <unknown>
+// CHECK-UNKNOWN: 853fdfff <unknown>
 
 ld1w    { z0.s }, p0/z, [z0.s]
 // CHECK-INST: ld1w    { z0.s }, p0/z, [z0.s]
 // CHECK-ENCODING: [0x00,0xc0,0x20,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 20 85 <unknown>
+// CHECK-UNKNOWN: 8520c000 <unknown>
 
 ld1w    { z31.d }, p7/z, [z31.d, #124]
 // CHECK-INST: ld1w    { z31.d }, p7/z, [z31.d, #124]
 // CHECK-ENCODING: [0xff,0xdf,0x3f,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff df 3f c5 <unknown>
+// CHECK-UNKNOWN: c53fdfff <unknown>
 
 ld1w    { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ld1w    { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0xc0,0x20,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 20 c5 <unknown>
+// CHECK-UNKNOWN: c520c000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld1w.s b/llvm/test/MC/AArch64/SVE/ld1w.s
index 7037f40b51792..72baf19987f2a 100644
--- a/llvm/test/MC/AArch64/SVE/ld1w.s
+++ b/llvm/test/MC/AArch64/SVE/ld1w.s
@@ -13,64 +13,64 @@ ld1w     z0.s, p0/z, [x0]
 // CHECK-INST: ld1w     { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x40,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 40 a5 <unknown>
+// CHECK-UNKNOWN: a540a000 <unknown>
 
 ld1w     z0.d, p0/z, [x0]
 // CHECK-INST: ld1w     { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x60,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 60 a5 <unknown>
+// CHECK-UNKNOWN: a560a000 <unknown>
 
 ld1w    { z0.s }, p0/z, [x0]
 // CHECK-INST: ld1w    { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x40,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 40 a5 <unknown>
+// CHECK-UNKNOWN: a540a000 <unknown>
 
 ld1w    { z0.d }, p0/z, [x0]
 // CHECK-INST: ld1w    { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x60,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 60 a5 <unknown>
+// CHECK-UNKNOWN: a560a000 <unknown>
 
 ld1w    { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1w    { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x4f,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 4f a5 <unknown>
+// CHECK-UNKNOWN: a54fbfff <unknown>
 
 ld1w    { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1w    { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x45,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 45 a5 <unknown>
+// CHECK-UNKNOWN: a545b555 <unknown>
 
 ld1w    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ld1w    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x6f,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 6f a5 <unknown>
+// CHECK-UNKNOWN: a56fbfff <unknown>
 
 ld1w    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ld1w    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x65,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 b5 65 a5 <unknown>
+// CHECK-UNKNOWN: a565b555 <unknown>
 
 ld1w    { z21.s }, p5/z, [sp, x21, lsl #2]
 // CHECK-INST: ld1w    { z21.s }, p5/z, [sp, x21, lsl #2]
 // CHECK-ENCODING: [0xf5,0x57,0x55,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 57 55 a5 <unknown>
+// CHECK-UNKNOWN: a55557f5 <unknown>
 
 ld1w    { z21.s }, p5/z, [x10, x21, lsl #2]
 // CHECK-INST: ld1w    { z21.s }, p5/z, [x10, x21, lsl #2]
 // CHECK-ENCODING: [0x55,0x55,0x55,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 55 55 a5 <unknown>
+// CHECK-UNKNOWN: a5555555 <unknown>
 
 ld1w    { z23.d }, p3/z, [x13, x8, lsl #2]
 // CHECK-INST: ld1w    { z23.d }, p3/z, [x13, x8, lsl #2]
 // CHECK-ENCODING: [0xb7,0x4d,0x68,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 4d 68 a5 <unknown>
+// CHECK-UNKNOWN: a5684db7 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld2b.s b/llvm/test/MC/AArch64/SVE/ld2b.s
index a24fe63f5d554..08d93e4eddb51 100644
--- a/llvm/test/MC/AArch64/SVE/ld2b.s
+++ b/llvm/test/MC/AArch64/SVE/ld2b.s
@@ -13,28 +13,28 @@ ld2b    { z0.b, z1.b }, p0/z, [x0, x0]
 // CHECK-INST: ld2b    { z0.b, z1.b }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0xc0,0x20,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 20 a4 <unknown>
+// CHECK-UNKNOWN: a420c000 <unknown>
 
 ld2b    { z5.b, z6.b }, p3/z, [x17, x16]
 // CHECK-INST: ld2b    { z5.b, z6.b }, p3/z, [x17, x16]
 // CHECK-ENCODING: [0x25,0xce,0x30,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 ce 30 a4 <unknown>
+// CHECK-UNKNOWN: a430ce25 <unknown>
 
 ld2b    { z0.b, z1.b }, p0/z, [x0]
 // CHECK-INST: ld2b    { z0.b, z1.b }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x20,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 20 a4 <unknown>
+// CHECK-UNKNOWN: a420e000 <unknown>
 
 ld2b    { z23.b, z24.b }, p3/z, [x13, #-16, mul vl]
 // CHECK-INST: ld2b    { z23.b, z24.b }, p3/z, [x13, #-16, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x28,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 28 a4 <unknown>
+// CHECK-UNKNOWN: a428edb7 <unknown>
 
 ld2b    { z21.b, z22.b }, p5/z, [x10, #10, mul vl]
 // CHECK-INST: ld2b    { z21.b, z22.b }, p5/z, [x10, #10, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x25,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 25 a4 <unknown>
+// CHECK-UNKNOWN: a425f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld2d.s b/llvm/test/MC/AArch64/SVE/ld2d.s
index c6e459436322d..071f94c85df6b 100644
--- a/llvm/test/MC/AArch64/SVE/ld2d.s
+++ b/llvm/test/MC/AArch64/SVE/ld2d.s
@@ -13,28 +13,28 @@ ld2d    { z0.d, z1.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-INST: ld2d    { z0.d, z1.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0xc0,0xa0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 a0 a5 <unknown>
+// CHECK-UNKNOWN: a5a0c000 <unknown>
 
 ld2d    { z5.d, z6.d }, p3/z, [x17, x16, lsl #3]
 // CHECK-INST: ld2d    { z5.d, z6.d }, p3/z, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0xce,0xb0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 ce b0 a5 <unknown>
+// CHECK-UNKNOWN: a5b0ce25 <unknown>
 
 ld2d    { z0.d, z1.d }, p0/z, [x0]
 // CHECK-INST: ld2d    { z0.d, z1.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xa0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 a0 a5 <unknown>
+// CHECK-UNKNOWN: a5a0e000 <unknown>
 
 ld2d    { z23.d, z24.d }, p3/z, [x13, #-16, mul vl]
 // CHECK-INST: ld2d    { z23.d, z24.d }, p3/z, [x13, #-16, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xa8,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed a8 a5 <unknown>
+// CHECK-UNKNOWN: a5a8edb7 <unknown>
 
 ld2d    { z21.d, z22.d }, p5/z, [x10, #10, mul vl]
 // CHECK-INST: ld2d    { z21.d, z22.d }, p5/z, [x10, #10, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xa5,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 a5 a5 <unknown>
+// CHECK-UNKNOWN: a5a5f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld2h.s b/llvm/test/MC/AArch64/SVE/ld2h.s
index 0dc5b324676d9..8e53958eab2e9 100644
--- a/llvm/test/MC/AArch64/SVE/ld2h.s
+++ b/llvm/test/MC/AArch64/SVE/ld2h.s
@@ -13,28 +13,28 @@ ld2h    { z0.h, z1.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ld2h    { z0.h, z1.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0xc0,0xa0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 a0 a4 <unknown>
+// CHECK-UNKNOWN: a4a0c000 <unknown>
 
 ld2h    { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]
 // CHECK-INST: ld2h    { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0xce,0xb0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 ce b0 a4 <unknown>
+// CHECK-UNKNOWN: a4b0ce25 <unknown>
 
 ld2h    { z0.h, z1.h }, p0/z, [x0]
 // CHECK-INST: ld2h    { z0.h, z1.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xa0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 a0 a4 <unknown>
+// CHECK-UNKNOWN: a4a0e000 <unknown>
 
 ld2h    { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]
 // CHECK-INST: ld2h    { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xa8,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed a8 a4 <unknown>
+// CHECK-UNKNOWN: a4a8edb7 <unknown>
 
 ld2h    { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
 // CHECK-INST: ld2h    { z21.h, z22.h }, p5/z, [x10, #10, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xa5,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 a5 a4 <unknown>
+// CHECK-UNKNOWN: a4a5f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld2w.s b/llvm/test/MC/AArch64/SVE/ld2w.s
index 4e609a62acb45..9739355c67b3a 100644
--- a/llvm/test/MC/AArch64/SVE/ld2w.s
+++ b/llvm/test/MC/AArch64/SVE/ld2w.s
@@ -13,28 +13,28 @@ ld2w    { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ld2w    { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0xc0,0x20,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 20 a5 <unknown>
+// CHECK-UNKNOWN: a520c000 <unknown>
 
 ld2w    { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]
 // CHECK-INST: ld2w    { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0xce,0x30,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 ce 30 a5 <unknown>
+// CHECK-UNKNOWN: a530ce25 <unknown>
 
 ld2w    { z0.s, z1.s }, p0/z, [x0]
 // CHECK-INST: ld2w    { z0.s, z1.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x20,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 20 a5 <unknown>
+// CHECK-UNKNOWN: a520e000 <unknown>
 
 ld2w    { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]
 // CHECK-INST: ld2w    { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x28,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 28 a5 <unknown>
+// CHECK-UNKNOWN: a528edb7 <unknown>
 
 ld2w    { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
 // CHECK-INST: ld2w    { z21.s, z22.s }, p5/z, [x10, #10, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x25,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 25 a5 <unknown>
+// CHECK-UNKNOWN: a525f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld3b.s b/llvm/test/MC/AArch64/SVE/ld3b.s
index c7816b940d21f..f5d67870d145f 100644
--- a/llvm/test/MC/AArch64/SVE/ld3b.s
+++ b/llvm/test/MC/AArch64/SVE/ld3b.s
@@ -13,28 +13,28 @@ ld3b    { z0.b, z1.b, z2.b }, p0/z, [x0, x0]
 // CHECK-INST: ld3b    { z0.b, z1.b, z2.b }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0xc0,0x40,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 40 a4 <unknown>
+// CHECK-UNKNOWN: a440c000 <unknown>
 
 ld3b    { z5.b, z6.b, z7.b }, p3/z, [x17, x16]
 // CHECK-INST: ld3b    { z5.b, z6.b, z7.b }, p3/z, [x17, x16]
 // CHECK-ENCODING: [0x25,0xce,0x50,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 ce 50 a4 <unknown>
+// CHECK-UNKNOWN: a450ce25 <unknown>
 
 ld3b    { z0.b, z1.b, z2.b }, p0/z, [x0]
 // CHECK-INST: ld3b    { z0.b, z1.b, z2.b }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x40,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 40 a4 <unknown>
+// CHECK-UNKNOWN: a440e000 <unknown>
 
 ld3b    { z23.b, z24.b, z25.b }, p3/z, [x13, #-24, mul vl]
 // CHECK-INST: ld3b    { z23.b, z24.b, z25.b }, p3/z, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x48,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 48 a4 <unknown>
+// CHECK-UNKNOWN: a448edb7 <unknown>
 
 ld3b    { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
 // CHECK-INST: ld3b    { z21.b, z22.b, z23.b }, p5/z, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x45,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 45 a4 <unknown>
+// CHECK-UNKNOWN: a445f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld3d.s b/llvm/test/MC/AArch64/SVE/ld3d.s
index 9c4d36fed3213..4a82a8a6feb2f 100644
--- a/llvm/test/MC/AArch64/SVE/ld3d.s
+++ b/llvm/test/MC/AArch64/SVE/ld3d.s
@@ -13,28 +13,28 @@ ld3d    { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-INST: ld3d    { z0.d, z1.d, z2.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0xc0,0xc0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 c0 a5 <unknown>
+// CHECK-UNKNOWN: a5c0c000 <unknown>
 
 ld3d    { z5.d, z6.d, z7.d }, p3/z, [x17, x16, lsl #3]
 // CHECK-INST: ld3d    { z5.d, z6.d, z7.d }, p3/z, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0xce,0xd0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 ce d0 a5 <unknown>
+// CHECK-UNKNOWN: a5d0ce25 <unknown>
 
 ld3d    { z0.d, z1.d, z2.d }, p0/z, [x0]
 // CHECK-INST: ld3d    { z0.d, z1.d, z2.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xc0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 c0 a5 <unknown>
+// CHECK-UNKNOWN: a5c0e000 <unknown>
 
 ld3d    { z23.d, z24.d, z25.d }, p3/z, [x13, #-24, mul vl]
 // CHECK-INST: ld3d    { z23.d, z24.d, z25.d }, p3/z, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xc8,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed c8 a5 <unknown>
+// CHECK-UNKNOWN: a5c8edb7 <unknown>
 
 ld3d    { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
 // CHECK-INST: ld3d    { z21.d, z22.d, z23.d }, p5/z, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xc5,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 c5 a5 <unknown>
+// CHECK-UNKNOWN: a5c5f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld3h.s b/llvm/test/MC/AArch64/SVE/ld3h.s
index 4157c22e4d891..e323623f1a4c1 100644
--- a/llvm/test/MC/AArch64/SVE/ld3h.s
+++ b/llvm/test/MC/AArch64/SVE/ld3h.s
@@ -13,28 +13,28 @@ ld3h    { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ld3h    { z0.h, z1.h, z2.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0xc0,0xc0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 c0 a4 <unknown>
+// CHECK-UNKNOWN: a4c0c000 <unknown>
 
 ld3h    { z5.h, z6.h, z7.h }, p3/z, [x17, x16, lsl #1]
 // CHECK-INST: ld3h    { z5.h, z6.h, z7.h }, p3/z, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0xce,0xd0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 ce d0 a4 <unknown>
+// CHECK-UNKNOWN: a4d0ce25 <unknown>
 
 ld3h    { z0.h, z1.h, z2.h }, p0/z, [x0]
 // CHECK-INST: ld3h    { z0.h, z1.h, z2.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xc0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 c0 a4 <unknown>
+// CHECK-UNKNOWN: a4c0e000 <unknown>
 
 ld3h    { z23.h, z24.h, z25.h }, p3/z, [x13, #-24, mul vl]
 // CHECK-INST: ld3h    { z23.h, z24.h, z25.h }, p3/z, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xc8,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed c8 a4 <unknown>
+// CHECK-UNKNOWN: a4c8edb7 <unknown>
 
 ld3h    { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
 // CHECK-INST: ld3h    { z21.h, z22.h, z23.h }, p5/z, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xc5,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 c5 a4 <unknown>
+// CHECK-UNKNOWN: a4c5f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld3w.s b/llvm/test/MC/AArch64/SVE/ld3w.s
index be16cfc2591e2..a7c8debc059ab 100644
--- a/llvm/test/MC/AArch64/SVE/ld3w.s
+++ b/llvm/test/MC/AArch64/SVE/ld3w.s
@@ -13,28 +13,28 @@ ld3w    { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ld3w    { z0.s, z1.s, z2.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0xc0,0x40,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 40 a5 <unknown>
+// CHECK-UNKNOWN: a540c000 <unknown>
 
 ld3w    { z5.s, z6.s, z7.s }, p3/z, [x17, x16, lsl #2]
 // CHECK-INST: ld3w    { z5.s, z6.s, z7.s }, p3/z, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0xce,0x50,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 ce 50 a5 <unknown>
+// CHECK-UNKNOWN: a550ce25 <unknown>
 
 ld3w    { z0.s, z1.s, z2.s }, p0/z, [x0]
 // CHECK-INST: ld3w    { z0.s, z1.s, z2.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x40,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 40 a5 <unknown>
+// CHECK-UNKNOWN: a540e000 <unknown>
 
 ld3w    { z23.s, z24.s, z25.s }, p3/z, [x13, #-24, mul vl]
 // CHECK-INST: ld3w    { z23.s, z24.s, z25.s }, p3/z, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x48,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 48 a5 <unknown>
+// CHECK-UNKNOWN: a548edb7 <unknown>
 
 ld3w    { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
 // CHECK-INST: ld3w    { z21.s, z22.s, z23.s }, p5/z, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x45,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 45 a5 <unknown>
+// CHECK-UNKNOWN: a545f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld4b.s b/llvm/test/MC/AArch64/SVE/ld4b.s
index 763f37da34961..de4a58bbc1320 100644
--- a/llvm/test/MC/AArch64/SVE/ld4b.s
+++ b/llvm/test/MC/AArch64/SVE/ld4b.s
@@ -13,28 +13,28 @@ ld4b    { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0]
 // CHECK-INST: ld4b    { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0xc0,0x60,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 60 a4 <unknown>
+// CHECK-UNKNOWN: a460c000 <unknown>
 
 ld4b    { z5.b, z6.b, z7.b, z8.b }, p3/z, [x17, x16]
 // CHECK-INST: ld4b    { z5.b, z6.b, z7.b, z8.b }, p3/z, [x17, x16]
 // CHECK-ENCODING: [0x25,0xce,0x70,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 ce 70 a4 <unknown>
+// CHECK-UNKNOWN: a470ce25 <unknown>
 
 ld4b    { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0]
 // CHECK-INST: ld4b    { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x60,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 60 a4 <unknown>
+// CHECK-UNKNOWN: a460e000 <unknown>
 
 ld4b    { z23.b, z24.b, z25.b, z26.b }, p3/z, [x13, #-32, mul vl]
 // CHECK-INST: ld4b    { z23.b, z24.b, z25.b, z26.b }, p3/z, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x68,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 68 a4 <unknown>
+// CHECK-UNKNOWN: a468edb7 <unknown>
 
 ld4b    { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl]
 // CHECK-INST: ld4b    { z21.b, z22.b, z23.b, z24.b }, p5/z, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x65,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 65 a4 <unknown>
+// CHECK-UNKNOWN: a465f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld4d.s b/llvm/test/MC/AArch64/SVE/ld4d.s
index 724c3519e738b..034a446de5254 100644
--- a/llvm/test/MC/AArch64/SVE/ld4d.s
+++ b/llvm/test/MC/AArch64/SVE/ld4d.s
@@ -13,28 +13,28 @@ ld4d    { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-INST: ld4d    { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0xc0,0xe0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 e0 a5 <unknown>
+// CHECK-UNKNOWN: a5e0c000 <unknown>
 
 ld4d    { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3]
 // CHECK-INST: ld4d    { z5.d, z6.d, z7.d, z8.d }, p3/z, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0xce,0xf0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 ce f0 a5 <unknown>
+// CHECK-UNKNOWN: a5f0ce25 <unknown>
 
 ld4d    { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
 // CHECK-INST: ld4d    { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xe0,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e0 a5 <unknown>
+// CHECK-UNKNOWN: a5e0e000 <unknown>
 
 ld4d    { z23.d, z24.d, z25.d, z26.d }, p3/z, [x13, #-32, mul vl]
 // CHECK-INST: ld4d    { z23.d, z24.d, z25.d, z26.d }, p3/z, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xe8,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed e8 a5 <unknown>
+// CHECK-UNKNOWN: a5e8edb7 <unknown>
 
 ld4d    { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
 // CHECK-INST: ld4d    { z21.d, z22.d, z23.d, z24.d }, p5/z, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xe5,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 e5 a5 <unknown>
+// CHECK-UNKNOWN: a5e5f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld4h.s b/llvm/test/MC/AArch64/SVE/ld4h.s
index c13c34cc4954b..6b6371b8fe2a6 100644
--- a/llvm/test/MC/AArch64/SVE/ld4h.s
+++ b/llvm/test/MC/AArch64/SVE/ld4h.s
@@ -13,28 +13,28 @@ ld4h    { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ld4h    { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0xc0,0xe0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 e0 a4 <unknown>
+// CHECK-UNKNOWN: a4e0c000 <unknown>
 
 ld4h    { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1]
 // CHECK-INST: ld4h    { z5.h, z6.h, z7.h, z8.h }, p3/z, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0xce,0xf0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 ce f0 a4 <unknown>
+// CHECK-UNKNOWN: a4f0ce25 <unknown>
 
 ld4h    { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
 // CHECK-INST: ld4h    { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xe0,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e0 a4 <unknown>
+// CHECK-UNKNOWN: a4e0e000 <unknown>
 
 ld4h    { z23.h, z24.h, z25.h, z26.h }, p3/z, [x13, #-32, mul vl]
 // CHECK-INST: ld4h    { z23.h, z24.h, z25.h, z26.h }, p3/z, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xe8,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed e8 a4 <unknown>
+// CHECK-UNKNOWN: a4e8edb7 <unknown>
 
 ld4h    { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl]
 // CHECK-INST: ld4h    { z21.h, z22.h, z23.h, z24.h }, p5/z, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xe5,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 e5 a4 <unknown>
+// CHECK-UNKNOWN: a4e5f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ld4w.s b/llvm/test/MC/AArch64/SVE/ld4w.s
index b293c3ccc5ccd..c5cf15b62e469 100644
--- a/llvm/test/MC/AArch64/SVE/ld4w.s
+++ b/llvm/test/MC/AArch64/SVE/ld4w.s
@@ -13,28 +13,28 @@ ld4w    { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ld4w    { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0xc0,0x60,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 60 a5 <unknown>
+// CHECK-UNKNOWN: a560c000 <unknown>
 
 ld4w    { z5.s, z6.s, z7.s, z8.s }, p3/z, [x17, x16, lsl #2]
 // CHECK-INST: ld4w    { z5.s, z6.s, z7.s, z8.s }, p3/z, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0xce,0x70,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 ce 70 a5 <unknown>
+// CHECK-UNKNOWN: a570ce25 <unknown>
 
 ld4w    { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
 // CHECK-INST: ld4w    { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x60,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 60 a5 <unknown>
+// CHECK-UNKNOWN: a560e000 <unknown>
 
 ld4w    { z23.s, z24.s, z25.s, z26.s }, p3/z, [x13, #-32, mul vl]
 // CHECK-INST: ld4w    { z23.s, z24.s, z25.s, z26.s }, p3/z, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x68,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 68 a5 <unknown>
+// CHECK-UNKNOWN: a568edb7 <unknown>
 
 ld4w    { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl]
 // CHECK-INST: ld4w    { z21.s, z22.s, z23.s, z24.s }, p5/z, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x65,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 65 a5 <unknown>
+// CHECK-UNKNOWN: a565f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldff1b.s b/llvm/test/MC/AArch64/SVE/ldff1b.s
index ccd7ed7fa571f..863e791bba669 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1b.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1b.s
@@ -13,118 +13,118 @@ ldff1b  { z31.b }, p7/z, [sp]
 // CHECK-INST: ldff1b  { z31.b }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x1f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 1f a4 <unknown>
+// CHECK-UNKNOWN: a41f7fff <unknown>
 
 ldff1b  { z31.h }, p7/z, [sp]
 // CHECK-INST: ldff1b  { z31.h }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x3f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 3f a4 <unknown>
+// CHECK-UNKNOWN: a43f7fff <unknown>
 
 ldff1b  { z31.s }, p7/z, [sp]
 // CHECK-INST: ldff1b  { z31.s }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x5f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 5f a4 <unknown>
+// CHECK-UNKNOWN: a45f7fff <unknown>
 
 ldff1b  { z31.d }, p7/z, [sp]
 // CHECK-INST: ldff1b  { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x7f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 7f a4 <unknown>
+// CHECK-UNKNOWN: a47f7fff <unknown>
 
 ldff1b  { z31.b }, p7/z, [sp, xzr]
 // CHECK-INST: ldff1b  { z31.b }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x1f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 1f a4 <unknown>
+// CHECK-UNKNOWN: a41f7fff <unknown>
 
 ldff1b  { z31.h }, p7/z, [sp, xzr]
 // CHECK-INST: ldff1b  { z31.h }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x3f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 3f a4 <unknown>
+// CHECK-UNKNOWN: a43f7fff <unknown>
 
 ldff1b  { z31.s }, p7/z, [sp, xzr]
 // CHECK-INST: ldff1b  { z31.s }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x5f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 5f a4 <unknown>
+// CHECK-UNKNOWN: a45f7fff <unknown>
 
 ldff1b  { z31.d }, p7/z, [sp, xzr]
 // CHECK-INST: ldff1b  { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x7f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 7f a4 <unknown>
+// CHECK-UNKNOWN: a47f7fff <unknown>
 
 ldff1b  { z0.h }, p0/z, [x0, x0]
 // CHECK-INST: ldff1b  { z0.h }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0x20,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 20 a4 <unknown>
+// CHECK-UNKNOWN: a4206000 <unknown>
 
 ldff1b  { z0.s }, p0/z, [x0, x0]
 // CHECK-INST: ldff1b  { z0.s }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0x40,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 40 a4 <unknown>
+// CHECK-UNKNOWN: a4406000 <unknown>
 
 ldff1b  { z0.d }, p0/z, [x0, x0]
 // CHECK-INST: ldff1b  { z0.d }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0x60,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 60 a4 <unknown>
+// CHECK-UNKNOWN: a4606000 <unknown>
 
 ldff1b    { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-INST: ldff1b    { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-ENCODING: [0x00,0x60,0x00,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 00 84 <unknown>
+// CHECK-UNKNOWN: 84006000 <unknown>
 
 ldff1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ldff1b    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x60,0x40,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 40 84 <unknown>
+// CHECK-UNKNOWN: 84406000 <unknown>
 
 ldff1b  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ldff1b  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xff,0x5f,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff ff 5f c4 <unknown>
+// CHECK-UNKNOWN: c45fffff <unknown>
 
 ldff1b  { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ldff1b  { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x75,0x15,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 75 15 c4 <unknown>
+// CHECK-UNKNOWN: c4157555 <unknown>
 
 ldff1b  { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ldff1b  { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x75,0x55,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 75 55 c4 <unknown>
+// CHECK-UNKNOWN: c4557555 <unknown>
 
 ldff1b  { z31.s }, p7/z, [z31.s, #31]
 // CHECK-INST: ldff1b  { z31.s }, p7/z, [z31.s, #31]
 // CHECK-ENCODING: [0xff,0xff,0x3f,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff ff 3f 84 <unknown>
+// CHECK-UNKNOWN: 843fffff <unknown>
 
 ldff1b  { z0.s }, p0/z, [z0.s]
 // CHECK-INST: ldff1b  { z0.s }, p0/z, [z0.s]
 // CHECK-ENCODING: [0x00,0xe0,0x20,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 e0 20 84 <unknown>
+// CHECK-UNKNOWN: 8420e000 <unknown>
 
 ldff1b  { z31.d }, p7/z, [z31.d, #31]
 // CHECK-INST: ldff1b  { z31.d }, p7/z, [z31.d, #31]
 // CHECK-ENCODING: [0xff,0xff,0x3f,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff ff 3f c4 <unknown>
+// CHECK-UNKNOWN: c43fffff <unknown>
 
 ldff1b  { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ldff1b  { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0xe0,0x20,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 e0 20 c4 <unknown>
+// CHECK-UNKNOWN: c420e000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldff1d.s b/llvm/test/MC/AArch64/SVE/ldff1d.s
index 0a5c7bab1d89f..9393bc1f7012b 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1d.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1d.s
@@ -13,64 +13,64 @@ ldff1d  { z31.d }, p7/z, [sp]
 // CHECK-INST: ldff1d  { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0xff,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f ff a5 <unknown>
+// CHECK-UNKNOWN: a5ff7fff <unknown>
 
 ldff1d  { z31.d }, p7/z, [sp, xzr, lsl #3]
 // CHECK-INST: ldff1d  { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0xff,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f ff a5 <unknown>
+// CHECK-UNKNOWN: a5ff7fff <unknown>
 
 ldff1d  { z0.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-INST: ldff1d  { z0.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x60,0xe0,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 e0 a5 <unknown>
+// CHECK-UNKNOWN: a5e06000 <unknown>
 
 ldff1d  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ldff1d  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xff,0xdf,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff ff df c5 <unknown>
+// CHECK-UNKNOWN: c5dfffff <unknown>
 
 ldff1d  { z23.d }, p3/z, [x13, z8.d, lsl #3]
 // CHECK-INST: ldff1d  { z23.d }, p3/z, [x13, z8.d, lsl #3]
 // CHECK-ENCODING: [0xb7,0xed,0xe8,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: b7 ed e8 c5 <unknown>
+// CHECK-UNKNOWN: c5e8edb7 <unknown>
 
 ldff1d  { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ldff1d  { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x75,0x95,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 75 95 c5 <unknown>
+// CHECK-UNKNOWN: c5957555 <unknown>
 
 ldff1d  { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ldff1d  { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x75,0xd5,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 75 d5 c5 <unknown>
+// CHECK-UNKNOWN: c5d57555 <unknown>
 
 ldff1d  { z0.d }, p0/z, [x0, z0.d, uxtw #3]
 // CHECK-INST: ldff1d  { z0.d }, p0/z, [x0, z0.d, uxtw #3]
 // CHECK-ENCODING: [0x00,0x60,0xa0,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 a0 c5 <unknown>
+// CHECK-UNKNOWN: c5a06000 <unknown>
 
 ldff1d  { z0.d }, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-INST: ldff1d  { z0.d }, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-ENCODING: [0x00,0x60,0xe0,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 e0 c5 <unknown>
+// CHECK-UNKNOWN: c5e06000 <unknown>
 
 ldff1d  { z31.d }, p7/z, [z31.d, #248]
 // CHECK-INST: ldff1d  { z31.d }, p7/z, [z31.d, #248]
 // CHECK-ENCODING: [0xff,0xff,0xbf,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff ff bf c5 <unknown>
+// CHECK-UNKNOWN: c5bfffff <unknown>
 
 ldff1d  { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ldff1d  { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0xe0,0xa0,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 e0 a0 c5 <unknown>
+// CHECK-UNKNOWN: c5a0e000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldff1h.s b/llvm/test/MC/AArch64/SVE/ldff1h.s
index 0c90aad7efe92..51877b67d80cc 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1h.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1h.s
@@ -13,136 +13,136 @@ ldff1h  { z31.h }, p7/z, [sp]
 // CHECK-INST: ldff1h  { z31.h }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0xbf,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f bf a4 <unknown>
+// CHECK-UNKNOWN: a4bf7fff <unknown>
 
 ldff1h  { z31.s }, p7/z, [sp]
 // CHECK-INST: ldff1h  { z31.s }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0xdf,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f df a4 <unknown>
+// CHECK-UNKNOWN: a4df7fff <unknown>
 
 ldff1h  { z31.d }, p7/z, [sp]
 // CHECK-INST: ldff1h  { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0xff,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f ff a4 <unknown>
+// CHECK-UNKNOWN: a4ff7fff <unknown>
 
 ldff1h  { z31.h }, p7/z, [sp, xzr, lsl #1]
 // CHECK-INST: ldff1h  { z31.h }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0xbf,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f bf a4 <unknown>
+// CHECK-UNKNOWN: a4bf7fff <unknown>
 
 ldff1h  { z31.s }, p7/z, [sp, xzr, lsl #1]
 // CHECK-INST: ldff1h  { z31.s }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0xdf,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f df a4 <unknown>
+// CHECK-UNKNOWN: a4df7fff <unknown>
 
 ldff1h  { z31.d }, p7/z, [sp, xzr, lsl #1]
 // CHECK-INST: ldff1h  { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0xff,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f ff a4 <unknown>
+// CHECK-UNKNOWN: a4ff7fff <unknown>
 
 ldff1h  { z0.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ldff1h  { z0.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x60,0xa0,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 a0 a4 <unknown>
+// CHECK-UNKNOWN: a4a06000 <unknown>
 
 ldff1h  { z0.s }, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ldff1h  { z0.s }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x60,0xc0,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 c0 a4 <unknown>
+// CHECK-UNKNOWN: a4c06000 <unknown>
 
 ldff1h  { z0.d }, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ldff1h  { z0.d }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x60,0xe0,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 e0 a4 <unknown>
+// CHECK-UNKNOWN: a4e06000 <unknown>
 
 ldff1h    { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-INST: ldff1h    { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-ENCODING: [0x00,0x60,0x80,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 80 84 <unknown>
+// CHECK-UNKNOWN: 84806000 <unknown>
 
 ldff1h    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ldff1h    { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x60,0xc0,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 c0 84 <unknown>
+// CHECK-UNKNOWN: 84c06000 <unknown>
 
 ldff1h  { z31.s }, p7/z, [sp, z31.s, uxtw #1]
 // CHECK-INST: ldff1h  { z31.s }, p7/z, [sp, z31.s, uxtw #1]
 // CHECK-ENCODING: [0xff,0x7f,0xbf,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f bf 84 <unknown>
+// CHECK-UNKNOWN: 84bf7fff <unknown>
 
 ldff1h  { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-INST: ldff1h  { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-ENCODING: [0xff,0x7f,0xff,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f ff 84 <unknown>
+// CHECK-UNKNOWN: 84ff7fff <unknown>
 
 ldff1h  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ldff1h  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xff,0xdf,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff ff df c4 <unknown>
+// CHECK-UNKNOWN: c4dfffff <unknown>
 
 ldff1h  { z23.d }, p3/z, [x13, z8.d, lsl #1]
 // CHECK-INST: ldff1h  { z23.d }, p3/z, [x13, z8.d, lsl #1]
 // CHECK-ENCODING: [0xb7,0xed,0xe8,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: b7 ed e8 c4 <unknown>
+// CHECK-UNKNOWN: c4e8edb7 <unknown>
 
 ldff1h  { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ldff1h  { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x75,0x95,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 75 95 c4 <unknown>
+// CHECK-UNKNOWN: c4957555 <unknown>
 
 ldff1h  { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ldff1h  { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x75,0xd5,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 75 d5 c4 <unknown>
+// CHECK-UNKNOWN: c4d57555 <unknown>
 
 ldff1h  { z0.d }, p0/z, [x0, z0.d, uxtw #1]
 // CHECK-INST: ldff1h  { z0.d }, p0/z, [x0, z0.d, uxtw #1]
 // CHECK-ENCODING: [0x00,0x60,0xa0,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 a0 c4 <unknown>
+// CHECK-UNKNOWN: c4a06000 <unknown>
 
 ldff1h  { z0.d }, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-INST: ldff1h  { z0.d }, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-ENCODING: [0x00,0x60,0xe0,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 e0 c4 <unknown>
+// CHECK-UNKNOWN: c4e06000 <unknown>
 
 ldff1h  { z31.s }, p7/z, [z31.s, #62]
 // CHECK-INST: ldff1h  { z31.s }, p7/z, [z31.s, #62]
 // CHECK-ENCODING: [0xff,0xff,0xbf,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff ff bf 84 <unknown>
+// CHECK-UNKNOWN: 84bfffff <unknown>
 
 ldff1h  { z0.s }, p0/z, [z0.s]
 // CHECK-INST: ldff1h  { z0.s }, p0/z, [z0.s]
 // CHECK-ENCODING: [0x00,0xe0,0xa0,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 e0 a0 84 <unknown>
+// CHECK-UNKNOWN: 84a0e000 <unknown>
 
 ldff1h  { z31.d }, p7/z, [z31.d, #62]
 // CHECK-INST: ldff1h  { z31.d }, p7/z, [z31.d, #62]
 // CHECK-ENCODING: [0xff,0xff,0xbf,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff ff bf c4 <unknown>
+// CHECK-UNKNOWN: c4bfffff <unknown>
 
 ldff1h  { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ldff1h  { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0xe0,0xa0,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 e0 a0 c4 <unknown>
+// CHECK-UNKNOWN: c4a0e000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldff1sb.s b/llvm/test/MC/AArch64/SVE/ldff1sb.s
index 201abf26ef2a0..776fa78a13455 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1sb.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sb.s
@@ -13,106 +13,106 @@ ldff1sb { z31.h }, p7/z, [sp]
 // CHECK-INST: ldff1sb { z31.h }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0xdf,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f df a5 <unknown>
+// CHECK-UNKNOWN: a5df7fff <unknown>
 
 ldff1sb { z31.s }, p7/z, [sp]
 // CHECK-INST: ldff1sb { z31.s }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0xbf,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f bf a5 <unknown>
+// CHECK-UNKNOWN: a5bf7fff <unknown>
 
 ldff1sb { z31.d }, p7/z, [sp]
 // CHECK-INST: ldff1sb { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x9f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 9f a5 <unknown>
+// CHECK-UNKNOWN: a59f7fff <unknown>
 
 ldff1sb { z31.h }, p7/z, [sp, xzr]
 // CHECK-INST: ldff1sb { z31.h }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0xdf,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f df a5 <unknown>
+// CHECK-UNKNOWN: a5df7fff <unknown>
 
 ldff1sb { z31.s }, p7/z, [sp, xzr]
 // CHECK-INST: ldff1sb { z31.s }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0xbf,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f bf a5 <unknown>
+// CHECK-UNKNOWN: a5bf7fff <unknown>
 
 ldff1sb { z31.d }, p7/z, [sp, xzr]
 // CHECK-INST: ldff1sb { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x9f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 9f a5 <unknown>
+// CHECK-UNKNOWN: a59f7fff <unknown>
 
 ldff1sb { z0.h }, p0/z, [x0, x0]
 // CHECK-INST: ldff1sb { z0.h }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0xc0,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 c0 a5 <unknown>
+// CHECK-UNKNOWN: a5c06000 <unknown>
 
 ldff1sb { z0.s }, p0/z, [x0, x0]
 // CHECK-INST: ldff1sb { z0.s }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0xa0,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 a0 a5 <unknown>
+// CHECK-UNKNOWN: a5a06000 <unknown>
 
 ldff1sb { z0.d }, p0/z, [x0, x0]
 // CHECK-INST: ldff1sb { z0.d }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0x80,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 80 a5 <unknown>
+// CHECK-UNKNOWN: a5806000 <unknown>
 
 ldff1sb   { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-INST: ldff1sb   { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-ENCODING: [0x00,0x20,0x00,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 20 00 84 <unknown>
+// CHECK-UNKNOWN: 84002000 <unknown>
 
 ldff1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ldff1sb   { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x20,0x40,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 20 40 84 <unknown>
+// CHECK-UNKNOWN: 84402000 <unknown>
 
 ldff1sb { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ldff1sb { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xbf,0x5f,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 5f c4 <unknown>
+// CHECK-UNKNOWN: c45fbfff <unknown>
 
 ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x35,0x15,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 35 15 c4 <unknown>
+// CHECK-UNKNOWN: c4153555 <unknown>
 
 ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x35,0x55,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 35 55 c4 <unknown>
+// CHECK-UNKNOWN: c4553555 <unknown>
 
 ldff1sb { z31.s }, p7/z, [z31.s, #31]
 // CHECK-INST: ldff1sb { z31.s }, p7/z, [z31.s, #31]
 // CHECK-ENCODING: [0xff,0xbf,0x3f,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 3f 84 <unknown>
+// CHECK-UNKNOWN: 843fbfff <unknown>
 
 ldff1sb { z0.s }, p0/z, [z0.s]
 // CHECK-INST: ldff1sb { z0.s }, p0/z, [z0.s]
 // CHECK-ENCODING: [0x00,0xa0,0x20,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 20 84 <unknown>
+// CHECK-UNKNOWN: 8420a000 <unknown>
 
 ldff1sb { z31.d }, p7/z, [z31.d, #31]
 // CHECK-INST: ldff1sb { z31.d }, p7/z, [z31.d, #31]
 // CHECK-ENCODING: [0xff,0xbf,0x3f,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 3f c4 <unknown>
+// CHECK-UNKNOWN: c43fbfff <unknown>
 
 ldff1sb { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ldff1sb { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0xa0,0x20,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 20 c4 <unknown>
+// CHECK-UNKNOWN: c420a000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldff1sh.s b/llvm/test/MC/AArch64/SVE/ldff1sh.s
index 2d8d31232316c..a53e88503430b 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1sh.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sh.s
@@ -13,118 +13,118 @@ ldff1sh { z31.s }, p7/z, [sp]
 // CHECK-INST: ldff1sh { z31.s }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x3f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 3f a5 <unknown>
+// CHECK-UNKNOWN: a53f7fff <unknown>
 
 ldff1sh { z31.d }, p7/z, [sp]
 // CHECK-INST: ldff1sh { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x1f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 1f a5 <unknown>
+// CHECK-UNKNOWN: a51f7fff <unknown>
 
 ldff1sh { z31.s }, p7/z, [sp, xzr, lsl #1]
 // CHECK-INST: ldff1sh { z31.s }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x3f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 3f a5 <unknown>
+// CHECK-UNKNOWN: a53f7fff <unknown>
 
 ldff1sh { z31.d }, p7/z, [sp, xzr, lsl #1]
 // CHECK-INST: ldff1sh { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x1f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 1f a5 <unknown>
+// CHECK-UNKNOWN: a51f7fff <unknown>
 
 ldff1sh { z0.s }, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ldff1sh { z0.s }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x60,0x20,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 20 a5 <unknown>
+// CHECK-UNKNOWN: a5206000 <unknown>
 
 ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x60,0x00,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 00 a5 <unknown>
+// CHECK-UNKNOWN: a5006000 <unknown>
 
 ldff1sh   { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-INST: ldff1sh   { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-ENCODING: [0x00,0x20,0x80,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 20 80 84 <unknown>
+// CHECK-UNKNOWN: 84802000 <unknown>
 
 ldff1sh   { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ldff1sh   { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x20,0xc0,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 20 c0 84 <unknown>
+// CHECK-UNKNOWN: 84c02000 <unknown>
 
 ldff1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
 // CHECK-INST: ldff1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]
 // CHECK-ENCODING: [0xff,0x3f,0xbf,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 3f bf 84 <unknown>
+// CHECK-UNKNOWN: 84bf3fff <unknown>
 
 ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-INST: ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]
 // CHECK-ENCODING: [0xff,0x3f,0xff,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 3f ff 84 <unknown>
+// CHECK-UNKNOWN: 84ff3fff <unknown>
 
 ldff1sh { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ldff1sh { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xbf,0xdf,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf df c4 <unknown>
+// CHECK-UNKNOWN: c4dfbfff <unknown>
 
 ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
 // CHECK-INST: ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]
 // CHECK-ENCODING: [0xb7,0xad,0xe8,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: b7 ad e8 c4 <unknown>
+// CHECK-UNKNOWN: c4e8adb7 <unknown>
 
 ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x35,0x95,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 35 95 c4 <unknown>
+// CHECK-UNKNOWN: c4953555 <unknown>
 
 ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x35,0xd5,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 35 d5 c4 <unknown>
+// CHECK-UNKNOWN: c4d53555 <unknown>
 
 ldff1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
 // CHECK-INST: ldff1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]
 // CHECK-ENCODING: [0x00,0x20,0xa0,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 20 a0 c4 <unknown>
+// CHECK-UNKNOWN: c4a02000 <unknown>
 
 ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-INST: ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-ENCODING: [0x00,0x20,0xe0,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 20 e0 c4 <unknown>
+// CHECK-UNKNOWN: c4e02000 <unknown>
 
 ldff1sh { z31.s }, p7/z, [z31.s, #62]
 // CHECK-INST: ldff1sh { z31.s }, p7/z, [z31.s, #62]
 // CHECK-ENCODING: [0xff,0xbf,0xbf,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf bf 84 <unknown>
+// CHECK-UNKNOWN: 84bfbfff <unknown>
 
 ldff1sh { z0.s }, p0/z, [z0.s]
 // CHECK-INST: ldff1sh { z0.s }, p0/z, [z0.s]
 // CHECK-ENCODING: [0x00,0xa0,0xa0,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 a0 84 <unknown>
+// CHECK-UNKNOWN: 84a0a000 <unknown>
 
 ldff1sh { z31.d }, p7/z, [z31.d, #62]
 // CHECK-INST: ldff1sh { z31.d }, p7/z, [z31.d, #62]
 // CHECK-ENCODING: [0xff,0xbf,0xbf,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf bf c4 <unknown>
+// CHECK-UNKNOWN: c4bfbfff <unknown>
 
 ldff1sh { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ldff1sh { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0xa0,0xa0,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 a0 c4 <unknown>
+// CHECK-UNKNOWN: c4a0a000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldff1sw.s b/llvm/test/MC/AArch64/SVE/ldff1sw.s
index f0e1472ea23c6..c8ef87041e6c0 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1sw.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sw.s
@@ -13,64 +13,64 @@ ldff1sw { z31.d }, p7/z, [sp]
 // CHECK-INST: ldff1sw { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x9f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 9f a4 <unknown>
+// CHECK-UNKNOWN: a49f7fff <unknown>
 
 ldff1sw { z31.d }, p7/z, [sp, xzr, lsl #2]
 // CHECK-INST: ldff1sw { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x9f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 9f a4 <unknown>
+// CHECK-UNKNOWN: a49f7fff <unknown>
 
 ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x60,0x80,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 80 a4 <unknown>
+// CHECK-UNKNOWN: a4806000 <unknown>
 
 ldff1sw { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ldff1sw { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xbf,0x5f,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 5f c5 <unknown>
+// CHECK-UNKNOWN: c55fbfff <unknown>
 
 ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
 // CHECK-INST: ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]
 // CHECK-ENCODING: [0xb7,0xad,0x68,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: b7 ad 68 c5 <unknown>
+// CHECK-UNKNOWN: c568adb7 <unknown>
 
 ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x35,0x15,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 35 15 c5 <unknown>
+// CHECK-UNKNOWN: c5153555 <unknown>
 
 ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x35,0x55,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 35 55 c5 <unknown>
+// CHECK-UNKNOWN: c5553555 <unknown>
 
 ldff1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
 // CHECK-INST: ldff1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]
 // CHECK-ENCODING: [0x00,0x20,0x20,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 20 20 c5 <unknown>
+// CHECK-UNKNOWN: c5202000 <unknown>
 
 ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-INST: ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-ENCODING: [0x00,0x20,0x60,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 20 60 c5 <unknown>
+// CHECK-UNKNOWN: c5602000 <unknown>
 
 ldff1sw { z31.d }, p7/z, [z31.d, #124]
 // CHECK-INST: ldff1sw { z31.d }, p7/z, [z31.d, #124]
 // CHECK-ENCODING: [0xff,0xbf,0x3f,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 3f c5 <unknown>
+// CHECK-UNKNOWN: c53fbfff <unknown>
 
 ldff1sw { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ldff1sw { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0xa0,0x20,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 20 c5 <unknown>
+// CHECK-UNKNOWN: c520a000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldff1w.s b/llvm/test/MC/AArch64/SVE/ldff1w.s
index 71585dc37ef35..b90157e218c71 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1w.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1w.s
@@ -13,118 +13,118 @@ ldff1w  { z31.d }, p7/z, [sp]
 // CHECK-INST: ldff1w  { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x7f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 7f a5 <unknown>
+// CHECK-UNKNOWN: a57f7fff <unknown>
 
 ldff1w  { z31.s }, p7/z, [sp]
 // CHECK-INST: ldff1w  { z31.s }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x5f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 5f a5 <unknown>
+// CHECK-UNKNOWN: a55f7fff <unknown>
 
 ldff1w  { z31.d }, p7/z, [sp, xzr, lsl #2]
 // CHECK-INST: ldff1w  { z31.d }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x7f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 7f a5 <unknown>
+// CHECK-UNKNOWN: a57f7fff <unknown>
 
 ldff1w  { z31.s }, p7/z, [sp, xzr, lsl #2]
 // CHECK-INST: ldff1w  { z31.s }, p7/z, [sp]
 // CHECK-ENCODING: [0xff,0x7f,0x5f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 5f a5 <unknown>
+// CHECK-UNKNOWN: a55f7fff <unknown>
 
 ldff1w  { z0.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ldff1w  { z0.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x60,0x40,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 40 a5 <unknown>
+// CHECK-UNKNOWN: a5406000 <unknown>
 
 ldff1w  { z0.d }, p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ldff1w  { z0.d }, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x60,0x60,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 60 a5 <unknown>
+// CHECK-UNKNOWN: a5606000 <unknown>
 
 ldff1w  { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-INST: ldff1w  { z0.s }, p0/z, [x0, z0.s, uxtw]
 // CHECK-ENCODING: [0x00,0x60,0x00,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 00 85 <unknown>
+// CHECK-UNKNOWN: 85006000 <unknown>
 
 ldff1w  { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-INST: ldff1w  { z0.s }, p0/z, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0x60,0x40,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 40 85 <unknown>
+// CHECK-UNKNOWN: 85406000 <unknown>
 
 ldff1w  { z31.s }, p7/z, [sp, z31.s, uxtw #2]
 // CHECK-INST: ldff1w  { z31.s }, p7/z, [sp, z31.s, uxtw #2]
 // CHECK-ENCODING: [0xff,0x7f,0x3f,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 3f 85 <unknown>
+// CHECK-UNKNOWN: 853f7fff <unknown>
 
 ldff1w  { z31.s }, p7/z, [sp, z31.s, sxtw #2]
 // CHECK-INST: ldff1w  { z31.s }, p7/z, [sp, z31.s, sxtw #2]
 // CHECK-ENCODING: [0xff,0x7f,0x7f,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff 7f 7f 85 <unknown>
+// CHECK-UNKNOWN: 857f7fff <unknown>
 
 ldff1w  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-INST: ldff1w  { z31.d }, p7/z, [sp, z31.d]
 // CHECK-ENCODING: [0xff,0xff,0x5f,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff ff 5f c5 <unknown>
+// CHECK-UNKNOWN: c55fffff <unknown>
 
 ldff1w  { z23.d }, p3/z, [x13, z8.d, lsl #2]
 // CHECK-INST: ldff1w  { z23.d }, p3/z, [x13, z8.d, lsl #2]
 // CHECK-ENCODING: [0xb7,0xed,0x68,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: b7 ed 68 c5 <unknown>
+// CHECK-UNKNOWN: c568edb7 <unknown>
 
 ldff1w  { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-INST: ldff1w  { z21.d }, p5/z, [x10, z21.d, uxtw]
 // CHECK-ENCODING: [0x55,0x75,0x15,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 75 15 c5 <unknown>
+// CHECK-UNKNOWN: c5157555 <unknown>
 
 ldff1w  { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-INST: ldff1w  { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x75,0x55,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 75 55 c5 <unknown>
+// CHECK-UNKNOWN: c5557555 <unknown>
 
 ldff1w  { z0.d }, p0/z, [x0, z0.d, uxtw #2]
 // CHECK-INST: ldff1w  { z0.d }, p0/z, [x0, z0.d, uxtw #2]
 // CHECK-ENCODING: [0x00,0x60,0x20,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 20 c5 <unknown>
+// CHECK-UNKNOWN: c5206000 <unknown>
 
 ldff1w  { z0.d }, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-INST: ldff1w  { z0.d }, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-ENCODING: [0x00,0x60,0x60,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 60 c5 <unknown>
+// CHECK-UNKNOWN: c5606000 <unknown>
 
 ldff1w  { z31.s }, p7/z, [z31.s, #124]
 // CHECK-INST: ldff1w  { z31.s }, p7/z, [z31.s, #124]
 // CHECK-ENCODING: [0xff,0xff,0x3f,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff ff 3f 85 <unknown>
+// CHECK-UNKNOWN: 853fffff <unknown>
 
 ldff1w  { z0.s }, p0/z, [z0.s]
 // CHECK-INST: ldff1w  { z0.s }, p0/z, [z0.s]
 // CHECK-ENCODING: [0x00,0xe0,0x20,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 e0 20 85 <unknown>
+// CHECK-UNKNOWN: 8520e000 <unknown>
 
 ldff1w  { z31.d }, p7/z, [z31.d, #124]
 // CHECK-INST: ldff1w  { z31.d }, p7/z, [z31.d, #124]
 // CHECK-ENCODING: [0xff,0xff,0x3f,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff ff 3f c5 <unknown>
+// CHECK-UNKNOWN: c53fffff <unknown>
 
 ldff1w  { z0.d }, p0/z, [z0.d]
 // CHECK-INST: ldff1w  { z0.d }, p0/z, [z0.d]
 // CHECK-ENCODING: [0x00,0xe0,0x20,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 e0 20 c5 <unknown>
+// CHECK-UNKNOWN: c520e000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldnf1b.s b/llvm/test/MC/AArch64/SVE/ldnf1b.s
index a080fdb595dc8..72d7cdce755f4 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1b.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1b.s
@@ -13,94 +13,94 @@ ldnf1b     z0.b, p0/z, [x0]
 // CHECK-INST: ldnf1b     { z0.b }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x10,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 10 a4 <unknown>
+// CHECK-UNKNOWN: a410a000 <unknown>
 
 ldnf1b     z0.h, p0/z, [x0]
 // CHECK-INST: ldnf1b     { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x30,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 30 a4 <unknown>
+// CHECK-UNKNOWN: a430a000 <unknown>
 
 ldnf1b     z0.s, p0/z, [x0]
 // CHECK-INST: ldnf1b     { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x50,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 50 a4 <unknown>
+// CHECK-UNKNOWN: a450a000 <unknown>
 
 ldnf1b     z0.d, p0/z, [x0]
 // CHECK-INST: ldnf1b     { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x70,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 70 a4 <unknown>
+// CHECK-UNKNOWN: a470a000 <unknown>
 
 ldnf1b    { z0.b }, p0/z, [x0]
 // CHECK-INST: ldnf1b    { z0.b }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x10,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 10 a4 <unknown>
+// CHECK-UNKNOWN: a410a000 <unknown>
 
 ldnf1b    { z0.h }, p0/z, [x0]
 // CHECK-INST: ldnf1b    { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x30,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 30 a4 <unknown>
+// CHECK-UNKNOWN: a430a000 <unknown>
 
 ldnf1b    { z0.s }, p0/z, [x0]
 // CHECK-INST: ldnf1b    { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x50,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 50 a4 <unknown>
+// CHECK-UNKNOWN: a450a000 <unknown>
 
 ldnf1b    { z0.d }, p0/z, [x0]
 // CHECK-INST: ldnf1b    { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x70,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 70 a4 <unknown>
+// CHECK-UNKNOWN: a470a000 <unknown>
 
 ldnf1b    { z31.b }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1b    { z31.b }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x1f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 1f a4 <unknown>
+// CHECK-UNKNOWN: a41fbfff <unknown>
 
 ldnf1b    { z21.b }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1b    { z21.b }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x15,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 15 a4 <unknown>
+// CHECK-UNKNOWN: a415b555 <unknown>
 
 ldnf1b    { z31.h }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1b    { z31.h }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x3f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 3f a4 <unknown>
+// CHECK-UNKNOWN: a43fbfff <unknown>
 
 ldnf1b    { z21.h }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1b    { z21.h }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x35,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 35 a4 <unknown>
+// CHECK-UNKNOWN: a435b555 <unknown>
 
 ldnf1b    { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1b    { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x5f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 5f a4 <unknown>
+// CHECK-UNKNOWN: a45fbfff <unknown>
 
 ldnf1b    { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1b    { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x55,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 55 a4 <unknown>
+// CHECK-UNKNOWN: a455b555 <unknown>
 
 ldnf1b    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1b    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x7f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 7f a4 <unknown>
+// CHECK-UNKNOWN: a47fbfff <unknown>
 
 ldnf1b    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1b    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x75,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 75 a4 <unknown>
+// CHECK-UNKNOWN: a475b555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldnf1d.s b/llvm/test/MC/AArch64/SVE/ldnf1d.s
index 7b08412ed127d..b9a515dcab9d6 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1d.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1d.s
@@ -13,22 +13,22 @@ ldnf1d     z0.d, p0/z, [x0]
 // CHECK-INST: ldnf1d     { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xf0,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 f0 a5 <unknown>
+// CHECK-UNKNOWN: a5f0a000 <unknown>
 
 ldnf1d    { z0.d }, p0/z, [x0]
 // CHECK-INST: ldnf1d    { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xf0,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 f0 a5 <unknown>
+// CHECK-UNKNOWN: a5f0a000 <unknown>
 
 ldnf1d    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1d    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0xff,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf ff a5 <unknown>
+// CHECK-UNKNOWN: a5ffbfff <unknown>
 
 ldnf1d    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1d    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xf5,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 f5 a5 <unknown>
+// CHECK-UNKNOWN: a5f5b555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldnf1h.s b/llvm/test/MC/AArch64/SVE/ldnf1h.s
index 27d0d11b8b282..078817a3ade99 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1h.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1h.s
@@ -13,70 +13,70 @@ ldnf1h     z0.h, p0/z, [x0]
 // CHECK-INST: ldnf1h     { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xb0,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 b0 a4 <unknown>
+// CHECK-UNKNOWN: a4b0a000 <unknown>
 
 ldnf1h     z0.s, p0/z, [x0]
 // CHECK-INST: ldnf1h     { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xd0,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 d0 a4 <unknown>
+// CHECK-UNKNOWN: a4d0a000 <unknown>
 
 ldnf1h     z0.d, p0/z, [x0]
 // CHECK-INST: ldnf1h     { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xf0,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 f0 a4 <unknown>
+// CHECK-UNKNOWN: a4f0a000 <unknown>
 
 ldnf1h    { z0.h }, p0/z, [x0]
 // CHECK-INST: ldnf1h    { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xb0,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 b0 a4 <unknown>
+// CHECK-UNKNOWN: a4b0a000 <unknown>
 
 ldnf1h    { z0.s }, p0/z, [x0]
 // CHECK-INST: ldnf1h    { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xd0,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 d0 a4 <unknown>
+// CHECK-UNKNOWN: a4d0a000 <unknown>
 
 ldnf1h    { z0.d }, p0/z, [x0]
 // CHECK-INST: ldnf1h    { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xf0,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 f0 a4 <unknown>
+// CHECK-UNKNOWN: a4f0a000 <unknown>
 
 ldnf1h    { z31.h }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1h    { z31.h }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0xbf,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf bf a4 <unknown>
+// CHECK-UNKNOWN: a4bfbfff <unknown>
 
 ldnf1h    { z21.h }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1h    { z21.h }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xb5,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 b5 a4 <unknown>
+// CHECK-UNKNOWN: a4b5b555 <unknown>
 
 ldnf1h    { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1h    { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0xdf,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf df a4 <unknown>
+// CHECK-UNKNOWN: a4dfbfff <unknown>
 
 ldnf1h    { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1h    { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xd5,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 d5 a4 <unknown>
+// CHECK-UNKNOWN: a4d5b555 <unknown>
 
 ldnf1h    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1h    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0xff,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf ff a4 <unknown>
+// CHECK-UNKNOWN: a4ffbfff <unknown>
 
 ldnf1h    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1h    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xf5,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 f5 a4 <unknown>
+// CHECK-UNKNOWN: a4f5b555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldnf1sb.s b/llvm/test/MC/AArch64/SVE/ldnf1sb.s
index 899c14fe8ac94..0c98cd54abda8 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1sb.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1sb.s
@@ -13,70 +13,70 @@ ldnf1sb   z0.h, p0/z, [x0]
 // CHECK-INST: ldnf1sb   { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xd0,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 d0 a5 <unknown>
+// CHECK-UNKNOWN: a5d0a000 <unknown>
 
 ldnf1sb   z0.s, p0/z, [x0]
 // CHECK-INST: ldnf1sb   { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xb0,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 b0 a5 <unknown>
+// CHECK-UNKNOWN: a5b0a000 <unknown>
 
 ldnf1sb   z0.d, p0/z, [x0]
 // CHECK-INST: ldnf1sb   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x90,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 90 a5 <unknown>
+// CHECK-UNKNOWN: a590a000 <unknown>
 
 ldnf1sb   { z0.h }, p0/z, [x0]
 // CHECK-INST: ldnf1sb   { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xd0,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 d0 a5 <unknown>
+// CHECK-UNKNOWN: a5d0a000 <unknown>
 
 ldnf1sb   { z0.s }, p0/z, [x0]
 // CHECK-INST: ldnf1sb   { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0xb0,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 b0 a5 <unknown>
+// CHECK-UNKNOWN: a5b0a000 <unknown>
 
 ldnf1sb   { z0.d }, p0/z, [x0]
 // CHECK-INST: ldnf1sb   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x90,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 90 a5 <unknown>
+// CHECK-UNKNOWN: a590a000 <unknown>
 
 ldnf1sb   { z31.h }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1sb   { z31.h }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0xdf,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf df a5 <unknown>
+// CHECK-UNKNOWN: a5dfbfff <unknown>
 
 ldnf1sb   { z21.h }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1sb   { z21.h }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xd5,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 d5 a5 <unknown>
+// CHECK-UNKNOWN: a5d5b555 <unknown>
 
 ldnf1sb   { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1sb   { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0xbf,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf bf a5 <unknown>
+// CHECK-UNKNOWN: a5bfbfff <unknown>
 
 ldnf1sb   { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1sb   { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0xb5,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 b5 a5 <unknown>
+// CHECK-UNKNOWN: a5b5b555 <unknown>
 
 ldnf1sb   { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1sb   { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x9f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 9f a5 <unknown>
+// CHECK-UNKNOWN: a59fbfff <unknown>
 
 ldnf1sb   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1sb   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x95,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 95 a5 <unknown>
+// CHECK-UNKNOWN: a595b555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldnf1sh.s b/llvm/test/MC/AArch64/SVE/ldnf1sh.s
index c32ca98f0fae7..c7d251b76c477 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1sh.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1sh.s
@@ -13,46 +13,46 @@ ldnf1sh   z0.s, p0/z, [x0]
 // CHECK-INST: ldnf1sh   { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x30,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 30 a5 <unknown>
+// CHECK-UNKNOWN: a530a000 <unknown>
 
 ldnf1sh   z0.d, p0/z, [x0]
 // CHECK-INST: ldnf1sh   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x10,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 10 a5 <unknown>
+// CHECK-UNKNOWN: a510a000 <unknown>
 
 ldnf1sh   { z0.s }, p0/z, [x0]
 // CHECK-INST: ldnf1sh   { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x30,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 30 a5 <unknown>
+// CHECK-UNKNOWN: a530a000 <unknown>
 
 ldnf1sh   { z0.d }, p0/z, [x0]
 // CHECK-INST: ldnf1sh   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x10,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 10 a5 <unknown>
+// CHECK-UNKNOWN: a510a000 <unknown>
 
 ldnf1sh   { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1sh   { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x3f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 3f a5 <unknown>
+// CHECK-UNKNOWN: a53fbfff <unknown>
 
 ldnf1sh   { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1sh   { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x35,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 35 a5 <unknown>
+// CHECK-UNKNOWN: a535b555 <unknown>
 
 ldnf1sh   { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1sh   { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x1f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 1f a5 <unknown>
+// CHECK-UNKNOWN: a51fbfff <unknown>
 
 ldnf1sh   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1sh   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x15,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 15 a5 <unknown>
+// CHECK-UNKNOWN: a515b555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldnf1sw.s b/llvm/test/MC/AArch64/SVE/ldnf1sw.s
index 29625b1f200e7..7a0fe02e64f7f 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1sw.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1sw.s
@@ -13,22 +13,22 @@ ldnf1sw   z0.d, p0/z, [x0]
 // CHECK-INST: ldnf1sw   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x90,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 90 a4 <unknown>
+// CHECK-UNKNOWN: a490a000 <unknown>
 
 ldnf1sw   { z0.d }, p0/z, [x0]
 // CHECK-INST: ldnf1sw   { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x90,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 90 a4 <unknown>
+// CHECK-UNKNOWN: a490a000 <unknown>
 
 ldnf1sw   { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1sw   { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x9f,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 9f a4 <unknown>
+// CHECK-UNKNOWN: a49fbfff <unknown>
 
 ldnf1sw   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1sw   { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x95,0xa4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 95 a4 <unknown>
+// CHECK-UNKNOWN: a495b555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldnf1w.s b/llvm/test/MC/AArch64/SVE/ldnf1w.s
index 8c1236e7606ff..235a99dacaa5e 100644
--- a/llvm/test/MC/AArch64/SVE/ldnf1w.s
+++ b/llvm/test/MC/AArch64/SVE/ldnf1w.s
@@ -13,46 +13,46 @@ ldnf1w     z0.s, p0/z, [x0]
 // CHECK-INST: ldnf1w     { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x50,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 50 a5 <unknown>
+// CHECK-UNKNOWN: a550a000 <unknown>
 
 ldnf1w     z0.d, p0/z, [x0]
 // CHECK-INST: ldnf1w     { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x70,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 70 a5 <unknown>
+// CHECK-UNKNOWN: a570a000 <unknown>
 
 ldnf1w    { z0.s }, p0/z, [x0]
 // CHECK-INST: ldnf1w    { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x50,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 50 a5 <unknown>
+// CHECK-UNKNOWN: a550a000 <unknown>
 
 ldnf1w    { z0.d }, p0/z, [x0]
 // CHECK-INST: ldnf1w    { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xa0,0x70,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 70 a5 <unknown>
+// CHECK-UNKNOWN: a570a000 <unknown>
 
 ldnf1w    { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1w    { z31.s }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x5f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 5f a5 <unknown>
+// CHECK-UNKNOWN: a55fbfff <unknown>
 
 ldnf1w    { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1w    { z21.s }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x55,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 55 a5 <unknown>
+// CHECK-UNKNOWN: a555b555 <unknown>
 
 ldnf1w    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-INST: ldnf1w    { z31.d }, p7/z, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xbf,0x7f,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 7f a5 <unknown>
+// CHECK-UNKNOWN: a57fbfff <unknown>
 
 ldnf1w    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-INST: ldnf1w    { z21.d }, p5/z, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xb5,0x75,0xa5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 55 b5 75 a5 <unknown>
+// CHECK-UNKNOWN: a575b555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldnt1b.s b/llvm/test/MC/AArch64/SVE/ldnt1b.s
index 44189162abf3f..e25da25817798 100644
--- a/llvm/test/MC/AArch64/SVE/ldnt1b.s
+++ b/llvm/test/MC/AArch64/SVE/ldnt1b.s
@@ -13,28 +13,28 @@ ldnt1b  z0.b, p0/z, [x0]
 // CHECK-INST: ldnt1b  { z0.b }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x00,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 00 a4 <unknown>
+// CHECK-UNKNOWN: a400e000 <unknown>
 
 ldnt1b  { z0.b }, p0/z, [x0]
 // CHECK-INST: ldnt1b  { z0.b }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x00,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 00 a4 <unknown>
+// CHECK-UNKNOWN: a400e000 <unknown>
 
 ldnt1b  { z23.b }, p3/z, [x13, #-8, mul vl]
 // CHECK-INST: ldnt1b  { z23.b }, p3/z, [x13, #-8, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x08,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 08 a4 <unknown>
+// CHECK-UNKNOWN: a408edb7 <unknown>
 
 ldnt1b  { z21.b }, p5/z, [x10, #7, mul vl]
 // CHECK-INST: ldnt1b  { z21.b }, p5/z, [x10, #7, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x07,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 07 a4 <unknown>
+// CHECK-UNKNOWN: a407f555 <unknown>
 
 ldnt1b  { z0.b }, p0/z, [x0, x0]
 // CHECK-INST: ldnt1b  { z0.b }, p0/z, [x0, x0]
 // CHECK-ENCODING: [0x00,0xc0,0x00,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 00 a4 <unknown>
+// CHECK-UNKNOWN: a400c000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldnt1d.s b/llvm/test/MC/AArch64/SVE/ldnt1d.s
index b028bd82bbc57..b035c3cb4e163 100644
--- a/llvm/test/MC/AArch64/SVE/ldnt1d.s
+++ b/llvm/test/MC/AArch64/SVE/ldnt1d.s
@@ -13,28 +13,28 @@ ldnt1d  z0.d, p0/z, [x0]
 // CHECK-INST: ldnt1d  { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x80,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 80 a5 <unknown>
+// CHECK-UNKNOWN: a580e000 <unknown>
 
 ldnt1d  { z0.d }, p0/z, [x0]
 // CHECK-INST: ldnt1d  { z0.d }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x80,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 80 a5 <unknown>
+// CHECK-UNKNOWN: a580e000 <unknown>
 
 ldnt1d  { z23.d }, p3/z, [x13, #-8, mul vl]
 // CHECK-INST: ldnt1d  { z23.d }, p3/z, [x13, #-8, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x88,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 88 a5 <unknown>
+// CHECK-UNKNOWN: a588edb7 <unknown>
 
 ldnt1d  { z21.d }, p5/z, [x10, #7, mul vl]
 // CHECK-INST: ldnt1d  { z21.d }, p5/z, [x10, #7, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x87,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 87 a5 <unknown>
+// CHECK-UNKNOWN: a587f555 <unknown>
 
 ldnt1d  { z0.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-INST: ldnt1d  { z0.d }, p0/z, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0xc0,0x80,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 80 a5 <unknown>
+// CHECK-UNKNOWN: a580c000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldnt1h.s b/llvm/test/MC/AArch64/SVE/ldnt1h.s
index 36b17a531797b..0cdd2d72c134b 100644
--- a/llvm/test/MC/AArch64/SVE/ldnt1h.s
+++ b/llvm/test/MC/AArch64/SVE/ldnt1h.s
@@ -13,28 +13,28 @@ ldnt1h  z0.h, p0/z, [x0]
 // CHECK-INST: ldnt1h  { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x80,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 80 a4 <unknown>
+// CHECK-UNKNOWN: a480e000 <unknown>
 
 ldnt1h  { z0.h }, p0/z, [x0]
 // CHECK-INST: ldnt1h  { z0.h }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x80,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 80 a4 <unknown>
+// CHECK-UNKNOWN: a480e000 <unknown>
 
 ldnt1h  { z23.h }, p3/z, [x13, #-8, mul vl]
 // CHECK-INST: ldnt1h  { z23.h }, p3/z, [x13, #-8, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x88,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 88 a4 <unknown>
+// CHECK-UNKNOWN: a488edb7 <unknown>
 
 ldnt1h  { z21.h }, p5/z, [x10, #7, mul vl]
 // CHECK-INST: ldnt1h  { z21.h }, p5/z, [x10, #7, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x87,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 87 a4 <unknown>
+// CHECK-UNKNOWN: a487f555 <unknown>
 
 ldnt1h  { z0.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-INST: ldnt1h  { z0.h }, p0/z, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0xc0,0x80,0xa4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 80 a4 <unknown>
+// CHECK-UNKNOWN: a480c000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldnt1w.s b/llvm/test/MC/AArch64/SVE/ldnt1w.s
index 41ba92136df1e..bc7a2047bffdc 100644
--- a/llvm/test/MC/AArch64/SVE/ldnt1w.s
+++ b/llvm/test/MC/AArch64/SVE/ldnt1w.s
@@ -13,28 +13,28 @@ ldnt1w  z0.s, p0/z, [x0]
 // CHECK-INST: ldnt1w  { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x00,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 00 a5 <unknown>
+// CHECK-UNKNOWN: a500e000 <unknown>
 
 ldnt1w  { z0.s }, p0/z, [x0]
 // CHECK-INST: ldnt1w  { z0.s }, p0/z, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x00,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 00 a5 <unknown>
+// CHECK-UNKNOWN: a500e000 <unknown>
 
 ldnt1w  { z23.s }, p3/z, [x13, #-8, mul vl]
 // CHECK-INST: ldnt1w  { z23.s }, p3/z, [x13, #-8, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x08,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 08 a5 <unknown>
+// CHECK-UNKNOWN: a508edb7 <unknown>
 
 ldnt1w  { z21.s }, p5/z, [x10, #7, mul vl]
 // CHECK-INST: ldnt1w  { z21.s }, p5/z, [x10, #7, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x07,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 07 a5 <unknown>
+// CHECK-UNKNOWN: a507f555 <unknown>
 
 ldnt1w  { z0.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-INST: ldnt1w  { z0.s }, p0/z, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0xc0,0x00,0xa5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 00 a5 <unknown>
+// CHECK-UNKNOWN: a500c000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ldr.s b/llvm/test/MC/AArch64/SVE/ldr.s
index d33392ce0354d..476ab944f9634 100644
--- a/llvm/test/MC/AArch64/SVE/ldr.s
+++ b/llvm/test/MC/AArch64/SVE/ldr.s
@@ -13,34 +13,34 @@ ldr     z0, [x0]
 // CHECK-INST: ldr     z0, [x0]
 // CHECK-ENCODING: [0x00,0x40,0x80,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 80 85 <unknown>
+// CHECK-UNKNOWN: 85804000 <unknown>
 
 ldr     z31, [sp, #-256, mul vl]
 // CHECK-INST: ldr     z31, [sp, #-256, mul vl]
 // CHECK-ENCODING: [0xff,0x43,0xa0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 43 a0 85 <unknown>
+// CHECK-UNKNOWN: 85a043ff <unknown>
 
 ldr     z23, [x13, #255, mul vl]
 // CHECK-INST: ldr     z23, [x13, #255, mul vl]
 // CHECK-ENCODING: [0xb7,0x5d,0x9f,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 5d 9f 85 <unknown>
+// CHECK-UNKNOWN: 859f5db7 <unknown>
 
 ldr     p0, [x0]
 // CHECK-INST: ldr     p0, [x0]
 // CHECK-ENCODING: [0x00,0x00,0x80,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 80 85 <unknown>
+// CHECK-UNKNOWN: 85800000 <unknown>
 
 ldr     p7, [x13, #-256, mul vl]
 // CHECK-INST: ldr     p7, [x13, #-256, mul vl]
 // CHECK-ENCODING: [0xa7,0x01,0xa0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a7 01 a0 85 <unknown>
+// CHECK-UNKNOWN: 85a001a7 <unknown>
 
 ldr     p5, [x10, #255, mul vl]
 // CHECK-INST: ldr     p5, [x10, #255, mul vl]
 // CHECK-ENCODING: [0x45,0x1d,0x9f,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 45 1d 9f 85 <unknown>
+// CHECK-UNKNOWN: 859f1d45 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/lsl.s b/llvm/test/MC/AArch64/SVE/lsl.s
index 6b2fad9263266..27abaf2b6fcac 100644
--- a/llvm/test/MC/AArch64/SVE/lsl.s
+++ b/llvm/test/MC/AArch64/SVE/lsl.s
@@ -13,157 +13,157 @@ lsl     z0.b, z0.b, #0
 // CHECK-INST: lsl	z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0x9c,0x28,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 9c 28 04 <unknown>
+// CHECK-UNKNOWN: 04289c00 <unknown>
 
 lsl     z31.b, z31.b, #7
 // CHECK-INST: lsl	z31.b, z31.b, #7
 // CHECK-ENCODING: [0xff,0x9f,0x2f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f 2f 04 <unknown>
+// CHECK-UNKNOWN: 042f9fff <unknown>
 
 lsl     z0.h, z0.h, #0
 // CHECK-INST: lsl	z0.h, z0.h, #0
 // CHECK-ENCODING: [0x00,0x9c,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 9c 30 04 <unknown>
+// CHECK-UNKNOWN: 04309c00 <unknown>
 
 lsl     z31.h, z31.h, #15
 // CHECK-INST: lsl	z31.h, z31.h, #15
 // CHECK-ENCODING: [0xff,0x9f,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f 3f 04 <unknown>
+// CHECK-UNKNOWN: 043f9fff <unknown>
 
 lsl     z0.s, z0.s, #0
 // CHECK-INST: lsl	z0.s, z0.s, #0
 // CHECK-ENCODING: [0x00,0x9c,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 9c 60 04 <unknown>
+// CHECK-UNKNOWN: 04609c00 <unknown>
 
 lsl     z31.s, z31.s, #31
 // CHECK-INST: lsl	z31.s, z31.s, #31
 // CHECK-ENCODING: [0xff,0x9f,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f 7f 04 <unknown>
+// CHECK-UNKNOWN: 047f9fff <unknown>
 
 lsl     z0.d, z0.d, #0
 // CHECK-INST: lsl	z0.d, z0.d, #0
 // CHECK-ENCODING: [0x00,0x9c,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 9c a0 04 <unknown>
+// CHECK-UNKNOWN: 04a09c00 <unknown>
 
 lsl     z31.d, z31.d, #63
 // CHECK-INST: lsl	z31.d, z31.d, #63
 // CHECK-ENCODING: [0xff,0x9f,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff9fff <unknown>
 
 lsl     z0.b, p0/m, z0.b, #0
 // CHECK-INST: lsl	z0.b, p0/m, z0.b, #0
 // CHECK-ENCODING: [0x00,0x81,0x03,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 81 03 04 <unknown>
+// CHECK-UNKNOWN: 04038100 <unknown>
 
 lsl     z31.b, p0/m, z31.b, #7
 // CHECK-INST: lsl	z31.b, p0/m, z31.b, #7
 // CHECK-ENCODING: [0xff,0x81,0x03,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 81 03 04 <unknown>
+// CHECK-UNKNOWN: 040381ff <unknown>
 
 lsl     z0.h, p0/m, z0.h, #0
 // CHECK-INST: lsl	z0.h, p0/m, z0.h, #0
 // CHECK-ENCODING: [0x00,0x82,0x03,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 82 03 04 <unknown>
+// CHECK-UNKNOWN: 04038200 <unknown>
 
 lsl     z31.h, p0/m, z31.h, #15
 // CHECK-INST: lsl	z31.h, p0/m, z31.h, #15
 // CHECK-ENCODING: [0xff,0x83,0x03,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 83 03 04 <unknown>
+// CHECK-UNKNOWN: 040383ff <unknown>
 
 lsl     z0.s, p0/m, z0.s, #0
 // CHECK-INST: lsl	z0.s, p0/m, z0.s, #0
 // CHECK-ENCODING: [0x00,0x80,0x43,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 43 04 <unknown>
+// CHECK-UNKNOWN: 04438000 <unknown>
 
 lsl     z31.s, p0/m, z31.s, #31
 // CHECK-INST: lsl	z31.s, p0/m, z31.s, #31
 // CHECK-ENCODING: [0xff,0x83,0x43,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 83 43 04 <unknown>
+// CHECK-UNKNOWN: 044383ff <unknown>
 
 lsl     z0.d, p0/m, z0.d, #0
 // CHECK-INST: lsl	z0.d, p0/m, z0.d, #0
 // CHECK-ENCODING: [0x00,0x80,0x83,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 83 04 <unknown>
+// CHECK-UNKNOWN: 04838000 <unknown>
 
 lsl     z31.d, p0/m, z31.d, #63
 // CHECK-INST: lsl	z31.d, p0/m, z31.d, #63
 // CHECK-ENCODING: [0xff,0x83,0xc3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 83 c3 04 <unknown>
+// CHECK-UNKNOWN: 04c383ff <unknown>
 
 lsl     z0.b, p0/m, z0.b, z0.b
 // CHECK-INST: lsl	z0.b, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x80,0x13,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 13 04 <unknown>
+// CHECK-UNKNOWN: 04138000 <unknown>
 
 lsl     z0.h, p0/m, z0.h, z0.h
 // CHECK-INST: lsl	z0.h, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x80,0x53,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 53 04 <unknown>
+// CHECK-UNKNOWN: 04538000 <unknown>
 
 lsl     z0.s, p0/m, z0.s, z0.s
 // CHECK-INST: lsl	z0.s, p0/m, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x80,0x93,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 93 04 <unknown>
+// CHECK-UNKNOWN: 04938000 <unknown>
 
 lsl     z0.d, p0/m, z0.d, z0.d
 // CHECK-INST: lsl	z0.d, p0/m, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x80,0xd3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 d3 04 <unknown>
+// CHECK-UNKNOWN: 04d38000 <unknown>
 
 lsl     z0.b, p0/m, z0.b, z1.d
 // CHECK-INST: lsl	z0.b, p0/m, z0.b, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x1b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 1b 04 <unknown>
+// CHECK-UNKNOWN: 041b8020 <unknown>
 
 lsl     z0.h, p0/m, z0.h, z1.d
 // CHECK-INST: lsl	z0.h, p0/m, z0.h, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x5b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 5b 04 <unknown>
+// CHECK-UNKNOWN: 045b8020 <unknown>
 
 lsl     z0.s, p0/m, z0.s, z1.d
 // CHECK-INST: lsl	z0.s, p0/m, z0.s, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x9b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 9b 04 <unknown>
+// CHECK-UNKNOWN: 049b8020 <unknown>
 
 lsl     z0.b, z1.b, z2.d
 // CHECK-INST: lsl	z0.b, z1.b, z2.d
 // CHECK-ENCODING: [0x20,0x8c,0x22,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 8c 22 04 <unknown>
+// CHECK-UNKNOWN: 04228c20 <unknown>
 
 lsl     z0.h, z1.h, z2.d
 // CHECK-INST: lsl	z0.h, z1.h, z2.d
 // CHECK-ENCODING: [0x20,0x8c,0x62,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 8c 62 04 <unknown>
+// CHECK-UNKNOWN: 04628c20 <unknown>
 
 lsl     z0.s, z1.s, z2.d
 // CHECK-INST: lsl	z0.s, z1.s, z2.d
 // CHECK-ENCODING: [0x20,0x8c,0xa2,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 8c a2 04 <unknown>
+// CHECK-UNKNOWN: 04a28c20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -173,46 +173,46 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx	z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 lsl     z31.d, p0/m, z31.d, #63
 // CHECK-INST: lsl	z31.d, p0/m, z31.d, #63
 // CHECK-ENCODING: [0xff,0x83,0xc3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 83 c3 04 <unknown>
+// CHECK-UNKNOWN: 04c383ff <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 lsl     z31.d, p0/m, z31.d, #63
 // CHECK-INST: lsl	z31.d, p0/m, z31.d, #63
 // CHECK-ENCODING: [0xff,0x83,0xc3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 83 c3 04 <unknown>
+// CHECK-UNKNOWN: 04c383ff <unknown>
 
 movprfx z0.s, p0/z, z7.s
 // CHECK-INST: movprfx	z0.s, p0/z, z7.s
 // CHECK-ENCODING: [0xe0,0x20,0x90,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 20 90 04 <unknown>
+// CHECK-UNKNOWN: 049020e0 <unknown>
 
 lsl     z0.s, p0/m, z0.s, z1.d
 // CHECK-INST: lsl	z0.s, p0/m, z0.s, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x9b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 9b 04 <unknown>
+// CHECK-UNKNOWN: 049b8020 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 lsl     z0.s, p0/m, z0.s, z1.d
 // CHECK-INST: lsl	z0.s, p0/m, z0.s, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x9b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 9b 04 <unknown>
+// CHECK-UNKNOWN: 049b8020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/lslr.s b/llvm/test/MC/AArch64/SVE/lslr.s
index 34d562013b1f4..753f65ae0c449 100644
--- a/llvm/test/MC/AArch64/SVE/lslr.s
+++ b/llvm/test/MC/AArch64/SVE/lslr.s
@@ -13,25 +13,25 @@ lslr    z0.b, p0/m, z0.b, z0.b
 // CHECK-INST: lslr	z0.b, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x80,0x17,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 17 04 <unknown>
+// CHECK-UNKNOWN: 04178000 <unknown>
 
 lslr    z0.h, p0/m, z0.h, z0.h
 // CHECK-INST: lslr	z0.h, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x80,0x57,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 57 04 <unknown>
+// CHECK-UNKNOWN: 04578000 <unknown>
 
 lslr    z0.s, p0/m, z0.s, z0.s
 // CHECK-INST: lslr	z0.s, p0/m, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x80,0x97,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 97 04 <unknown>
+// CHECK-UNKNOWN: 04978000 <unknown>
 
 lslr    z0.d, p0/m, z0.d, z0.d
 // CHECK-INST: lslr	z0.d, p0/m, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x80,0xd7,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 d7 04 <unknown>
+// CHECK-UNKNOWN: 04d78000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z5.d, p0/z, z7.d
 // CHECK-INST: movprfx	z5.d, p0/z, z7.d
 // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020e5 <unknown>
 
 lslr    z5.d, p0/m, z5.d, z0.d
 // CHECK-INST: lslr	z5.d, p0/m, z5.d, z0.d
 // CHECK-ENCODING: [0x05,0x80,0xd7,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 80 d7 04 <unknown>
+// CHECK-UNKNOWN: 04d78005 <unknown>
 
 movprfx z5, z7
 // CHECK-INST: movprfx	z5, z7
 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce5 <unknown>
 
 lslr    z5.d, p0/m, z5.d, z0.d
 // CHECK-INST: lslr	z5.d, p0/m, z5.d, z0.d
 // CHECK-ENCODING: [0x05,0x80,0xd7,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 80 d7 04 <unknown>
+// CHECK-UNKNOWN: 04d78005 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/lsr.s b/llvm/test/MC/AArch64/SVE/lsr.s
index 046f725c2d5b0..9178323bfc789 100644
--- a/llvm/test/MC/AArch64/SVE/lsr.s
+++ b/llvm/test/MC/AArch64/SVE/lsr.s
@@ -13,157 +13,157 @@ lsr     z0.b, z0.b, #1
 // CHECK-INST: lsr	z0.b, z0.b, #1
 // CHECK-ENCODING: [0x00,0x94,0x2f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 94 2f 04 <unknown>
+// CHECK-UNKNOWN: 042f9400 <unknown>
 
 lsr     z31.b, z31.b, #8
 // CHECK-INST: lsr	z31.b, z31.b, #8
 // CHECK-ENCODING: [0xff,0x97,0x28,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 97 28 04 <unknown>
+// CHECK-UNKNOWN: 042897ff <unknown>
 
 lsr     z0.h, z0.h, #1
 // CHECK-INST: lsr	z0.h, z0.h, #1
 // CHECK-ENCODING: [0x00,0x94,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 94 3f 04 <unknown>
+// CHECK-UNKNOWN: 043f9400 <unknown>
 
 lsr     z31.h, z31.h, #16
 // CHECK-INST: lsr	z31.h, z31.h, #16
 // CHECK-ENCODING: [0xff,0x97,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 97 30 04 <unknown>
+// CHECK-UNKNOWN: 043097ff <unknown>
 
 lsr     z0.s, z0.s, #1
 // CHECK-INST: lsr	z0.s, z0.s, #1
 // CHECK-ENCODING: [0x00,0x94,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 94 7f 04 <unknown>
+// CHECK-UNKNOWN: 047f9400 <unknown>
 
 lsr     z31.s, z31.s, #32
 // CHECK-INST: lsr	z31.s, z31.s, #32
 // CHECK-ENCODING: [0xff,0x97,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 97 60 04 <unknown>
+// CHECK-UNKNOWN: 046097ff <unknown>
 
 lsr     z0.d, z0.d, #1
 // CHECK-INST: lsr	z0.d, z0.d, #1
 // CHECK-ENCODING: [0x00,0x94,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 94 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff9400 <unknown>
 
 lsr     z31.d, z31.d, #64
 // CHECK-INST: lsr	z31.d, z31.d, #64
 // CHECK-ENCODING: [0xff,0x97,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 97 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a097ff <unknown>
 
 lsr     z0.b, p0/m, z0.b, #1
 // CHECK-INST: lsr	z0.b, p0/m, z0.b, #1
 // CHECK-ENCODING: [0xe0,0x81,0x01,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 81 01 04 <unknown>
+// CHECK-UNKNOWN: 040181e0 <unknown>
 
 lsr     z31.b, p0/m, z31.b, #8
 // CHECK-INST: lsr	z31.b, p0/m, z31.b, #8
 // CHECK-ENCODING: [0x1f,0x81,0x01,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 81 01 04 <unknown>
+// CHECK-UNKNOWN: 0401811f <unknown>
 
 lsr     z0.h, p0/m, z0.h, #1
 // CHECK-INST: lsr	z0.h, p0/m, z0.h, #1
 // CHECK-ENCODING: [0xe0,0x83,0x01,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 83 01 04 <unknown>
+// CHECK-UNKNOWN: 040183e0 <unknown>
 
 lsr     z31.h, p0/m, z31.h, #16
 // CHECK-INST: lsr	z31.h, p0/m, z31.h, #16
 // CHECK-ENCODING: [0x1f,0x82,0x01,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 82 01 04 <unknown>
+// CHECK-UNKNOWN: 0401821f <unknown>
 
 lsr     z0.s, p0/m, z0.s, #1
 // CHECK-INST: lsr	z0.s, p0/m, z0.s, #1
 // CHECK-ENCODING: [0xe0,0x83,0x41,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 83 41 04 <unknown>
+// CHECK-UNKNOWN: 044183e0 <unknown>
 
 lsr     z31.s, p0/m, z31.s, #32
 // CHECK-INST: lsr	z31.s, p0/m, z31.s, #32
 // CHECK-ENCODING: [0x1f,0x80,0x41,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 80 41 04 <unknown>
+// CHECK-UNKNOWN: 0441801f <unknown>
 
 lsr     z0.d, p0/m, z0.d, #1
 // CHECK-INST: lsr	z0.d, p0/m, z0.d, #1
 // CHECK-ENCODING: [0xe0,0x83,0xc1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 83 c1 04 <unknown>
+// CHECK-UNKNOWN: 04c183e0 <unknown>
 
 lsr     z31.d, p0/m, z31.d, #64
 // CHECK-INST: lsr	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x81,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 80 81 04 <unknown>
+// CHECK-UNKNOWN: 0481801f <unknown>
 
 lsr     z0.b, p0/m, z0.b, z0.b
 // CHECK-INST: lsr	z0.b, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x80,0x11,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 11 04 <unknown>
+// CHECK-UNKNOWN: 04118000 <unknown>
 
 lsr     z0.h, p0/m, z0.h, z0.h
 // CHECK-INST: lsr	z0.h, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x80,0x51,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 51 04 <unknown>
+// CHECK-UNKNOWN: 04518000 <unknown>
 
 lsr     z0.s, p0/m, z0.s, z0.s
 // CHECK-INST: lsr	z0.s, p0/m, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x80,0x91,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 91 04 <unknown>
+// CHECK-UNKNOWN: 04918000 <unknown>
 
 lsr     z0.d, p0/m, z0.d, z0.d
 // CHECK-INST: lsr	z0.d, p0/m, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x80,0xd1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 d1 04 <unknown>
+// CHECK-UNKNOWN: 04d18000 <unknown>
 
 lsr     z0.b, p0/m, z0.b, z1.d
 // CHECK-INST: lsr	z0.b, p0/m, z0.b, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x19,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 19 04 <unknown>
+// CHECK-UNKNOWN: 04198020 <unknown>
 
 lsr     z0.h, p0/m, z0.h, z1.d
 // CHECK-INST: lsr	z0.h, p0/m, z0.h, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x59,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 59 04 <unknown>
+// CHECK-UNKNOWN: 04598020 <unknown>
 
 lsr     z0.s, p0/m, z0.s, z1.d
 // CHECK-INST: lsr	z0.s, p0/m, z0.s, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x99,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 99 04 <unknown>
+// CHECK-UNKNOWN: 04998020 <unknown>
 
 lsr     z0.b, z1.b, z2.d
 // CHECK-INST: lsr	z0.b, z1.b, z2.d
 // CHECK-ENCODING: [0x20,0x84,0x22,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 84 22 04 <unknown>
+// CHECK-UNKNOWN: 04228420 <unknown>
 
 lsr     z0.h, z1.h, z2.d
 // CHECK-INST: lsr	z0.h, z1.h, z2.d
 // CHECK-ENCODING: [0x20,0x84,0x62,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 84 62 04 <unknown>
+// CHECK-UNKNOWN: 04628420 <unknown>
 
 lsr     z0.s, z1.s, z2.d
 // CHECK-INST: lsr	z0.s, z1.s, z2.d
 // CHECK-ENCODING: [0x20,0x84,0xa2,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 84 a2 04 <unknown>
+// CHECK-UNKNOWN: 04a28420 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -173,46 +173,46 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx	z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 lsr     z31.d, p0/m, z31.d, #64
 // CHECK-INST: lsr	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x81,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 80 81 04 <unknown>
+// CHECK-UNKNOWN: 0481801f <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 lsr     z31.d, p0/m, z31.d, #64
 // CHECK-INST: lsr	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x81,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 80 81 04 <unknown>
+// CHECK-UNKNOWN: 0481801f <unknown>
 
 movprfx z0.s, p0/z, z7.s
 // CHECK-INST: movprfx	z0.s, p0/z, z7.s
 // CHECK-ENCODING: [0xe0,0x20,0x90,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 20 90 04 <unknown>
+// CHECK-UNKNOWN: 049020e0 <unknown>
 
 lsr     z0.s, p0/m, z0.s, z1.d
 // CHECK-INST: lsr	z0.s, p0/m, z0.s, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x99,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 99 04 <unknown>
+// CHECK-UNKNOWN: 04998020 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 lsr     z0.s, p0/m, z0.s, z1.d
 // CHECK-INST: lsr	z0.s, p0/m, z0.s, z1.d
 // CHECK-ENCODING: [0x20,0x80,0x99,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 80 99 04 <unknown>
+// CHECK-UNKNOWN: 04998020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/lsrr.s b/llvm/test/MC/AArch64/SVE/lsrr.s
index f8ea9ad0d6fdb..1074a501ef78a 100644
--- a/llvm/test/MC/AArch64/SVE/lsrr.s
+++ b/llvm/test/MC/AArch64/SVE/lsrr.s
@@ -13,25 +13,25 @@ lsrr    z0.b, p0/m, z0.b, z0.b
 // CHECK-INST: lsrr	z0.b, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x80,0x15,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 15 04 <unknown>
+// CHECK-UNKNOWN: 04158000 <unknown>
 
 lsrr    z0.h, p0/m, z0.h, z0.h
 // CHECK-INST: lsrr	z0.h, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x80,0x55,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 55 04 <unknown>
+// CHECK-UNKNOWN: 04558000 <unknown>
 
 lsrr    z0.s, p0/m, z0.s, z0.s
 // CHECK-INST: lsrr	z0.s, p0/m, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x80,0x95,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 95 04 <unknown>
+// CHECK-UNKNOWN: 04958000 <unknown>
 
 lsrr    z0.d, p0/m, z0.d, z0.d
 // CHECK-INST: lsrr	z0.d, p0/m, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x80,0xd5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 d5 04 <unknown>
+// CHECK-UNKNOWN: 04d58000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z5.d, p0/z, z7.d
 // CHECK-INST: movprfx	z5.d, p0/z, z7.d
 // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020e5 <unknown>
 
 lsrr    z5.d, p0/m, z5.d, z0.d
 // CHECK-INST: lsrr	z5.d, p0/m, z5.d, z0.d
 // CHECK-ENCODING: [0x05,0x80,0xd5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 80 d5 04 <unknown>
+// CHECK-UNKNOWN: 04d58005 <unknown>
 
 movprfx z5, z7
 // CHECK-INST: movprfx	z5, z7
 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce5 <unknown>
 
 lsrr    z5.d, p0/m, z5.d, z0.d
 // CHECK-INST: lsrr	z5.d, p0/m, z5.d, z0.d
 // CHECK-ENCODING: [0x05,0x80,0xd5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 80 d5 04 <unknown>
+// CHECK-UNKNOWN: 04d58005 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/mad.s b/llvm/test/MC/AArch64/SVE/mad.s
index 50e001f838240..5940beda32077 100644
--- a/llvm/test/MC/AArch64/SVE/mad.s
+++ b/llvm/test/MC/AArch64/SVE/mad.s
@@ -13,25 +13,25 @@ mad z0.b, p7/m, z1.b, z31.b
 // CHECK-INST: mad	z0.b, p7/m, z1.b, z31.b
 // CHECK-ENCODING: [0xe0,0xdf,0x01,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 df 01 04 <unknown>
+// CHECK-UNKNOWN: 0401dfe0 <unknown>
 
 mad z0.h, p7/m, z1.h, z31.h
 // CHECK-INST: mad	z0.h, p7/m, z1.h, z31.h
 // CHECK-ENCODING: [0xe0,0xdf,0x41,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 df 41 04 <unknown>
+// CHECK-UNKNOWN: 0441dfe0 <unknown>
 
 mad z0.s, p7/m, z1.s, z31.s
 // CHECK-INST: mad	z0.s, p7/m, z1.s, z31.s
 // CHECK-ENCODING: [0xe0,0xdf,0x81,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 df 81 04 <unknown>
+// CHECK-UNKNOWN: 0481dfe0 <unknown>
 
 mad z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: mad	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 df c1 04 <unknown>
+// CHECK-UNKNOWN: 04c1dfe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 mad z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: mad	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 df c1 04 <unknown>
+// CHECK-UNKNOWN: 04c1dfe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 mad z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: mad	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0xe0,0xdf,0xc1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 df c1 04 <unknown>
+// CHECK-UNKNOWN: 04c1dfe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/matrix-multiply-fp32.s b/llvm/test/MC/AArch64/SVE/matrix-multiply-fp32.s
index b68cc3fcf3a39..2fed2bc3b8b18 100644
--- a/llvm/test/MC/AArch64/SVE/matrix-multiply-fp32.s
+++ b/llvm/test/MC/AArch64/SVE/matrix-multiply-fp32.s
@@ -16,4 +16,4 @@ fmmla z0.s, z1.s, z2.s
 // CHECK-INST: fmmla z0.s, z1.s, z2.s
 // CHECK-ENCODING: [0x20,0xe4,0xa2,0x64]
 // CHECK-ERROR: instruction requires: f32mm sve
-// CHECK-UNKNOWN: 20 e4 a2 64 <unknown>
+// CHECK-UNKNOWN: 64a2e420 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/matrix-multiply-fp64.s b/llvm/test/MC/AArch64/SVE/matrix-multiply-fp64.s
index 924089ef1017d..3c5c94d6fea20 100644
--- a/llvm/test/MC/AArch64/SVE/matrix-multiply-fp64.s
+++ b/llvm/test/MC/AArch64/SVE/matrix-multiply-fp64.s
@@ -14,7 +14,7 @@ fmmla z0.d, z1.d, z2.d
 // CHECK-INST: fmmla z0.d, z1.d, z2.d
 // CHECK-ENCODING: [0x20,0xe4,0xe2,0x64]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 20 e4 e2 64 <unknown>
+// CHECK-UNKNOWN: 64e2e420 <unknown>
 
 // --------------------------------------------------------------------------//
 // LD1RO (SVE, scalar plus immediate)
@@ -25,25 +25,25 @@ ld1rob { z0.b }, p1/z, [x2, #224]
 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2, #224]
 // CHECK-ENCODING: [0x40,0x24,0x27,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 27 a4 <unknown>
+// CHECK-UNKNOWN: a4272440 <unknown>
 
 ld1roh { z0.h }, p1/z, [x2, #224]
 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2, #224]
 // CHECK-ENCODING: [0x40,0x24,0xa7,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 a7 a4 <unknown>
+// CHECK-UNKNOWN: a4a72440 <unknown>
 
 ld1row { z0.s }, p1/z, [x2, #224]
 // CHECK-INST: ld1row { z0.s }, p1/z, [x2, #224]
 // CHECK-ENCODING: [0x40,0x24,0x27,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 27 a5 <unknown>
+// CHECK-UNKNOWN: a5272440 <unknown>
 
 ld1rod { z0.d }, p1/z, [x2, #224]
 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2, #224]
 // CHECK-ENCODING: [0x40,0x24,0xa7,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 a7 a5 <unknown>
+// CHECK-UNKNOWN: a5a72440 <unknown>
 
 // With minimum immediate (-256)
 
@@ -51,25 +51,25 @@ ld1rob { z0.b }, p1/z, [x2, #-256]
 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2, #-256]
 // CHECK-ENCODING: [0x40,0x24,0x28,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 28 a4 <unknown>
+// CHECK-UNKNOWN: a4282440 <unknown>
 
 ld1roh { z0.h }, p1/z, [x2, #-256]
 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2, #-256]
 // CHECK-ENCODING: [0x40,0x24,0xa8,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 a8 a4 <unknown>
+// CHECK-UNKNOWN: a4a82440 <unknown>
 
 ld1row { z0.s }, p1/z, [x2, #-256]
 // CHECK-INST: ld1row { z0.s }, p1/z, [x2, #-256]
 // CHECK-ENCODING: [0x40,0x24,0x28,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 28 a5 <unknown>
+// CHECK-UNKNOWN: a5282440 <unknown>
 
 ld1rod { z0.d }, p1/z, [x2, #-256]
 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2, #-256]
 // CHECK-ENCODING: [0x40,0x24,0xa8,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 a8 a5 <unknown>
+// CHECK-UNKNOWN: a5a82440 <unknown>
 
 // Aliases with a vector first operand, and omitted offset.
 
@@ -77,25 +77,25 @@ ld1rob { z0.b }, p1/z, [x2]
 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2]
 // CHECK-ENCODING: [0x40,0x24,0x20,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 20 a4 <unknown>
+// CHECK-UNKNOWN: a4202440 <unknown>
 
 ld1roh { z0.h }, p1/z, [x2]
 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2]
 // CHECK-ENCODING: [0x40,0x24,0xa0,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 a0 a4 <unknown>
+// CHECK-UNKNOWN: a4a02440 <unknown>
 
 ld1row { z0.s }, p1/z, [x2]
 // CHECK-INST: ld1row { z0.s }, p1/z, [x2]
 // CHECK-ENCODING: [0x40,0x24,0x20,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 20 a5 <unknown>
+// CHECK-UNKNOWN: a5202440 <unknown>
 
 ld1rod { z0.d }, p1/z, [x2]
 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2]
 // CHECK-ENCODING: [0x40,0x24,0xa0,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 a0 a5 <unknown>
+// CHECK-UNKNOWN: a5a02440 <unknown>
 
 // Aliases with a plain (non-list) first operand, and omitted offset.
 
@@ -103,25 +103,25 @@ ld1rob z0.b, p1/z, [x2]
 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2]
 // CHECK-ENCODING: [0x40,0x24,0x20,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 20 a4 <unknown>
+// CHECK-UNKNOWN: a4202440 <unknown>
 
 ld1roh z0.h, p1/z, [x2]
 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2]
 // CHECK-ENCODING: [0x40,0x24,0xa0,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 a0 a4 <unknown>
+// CHECK-UNKNOWN: a4a02440 <unknown>
 
 ld1row z0.s, p1/z, [x2]
 // CHECK-INST: ld1row { z0.s }, p1/z, [x2]
 // CHECK-ENCODING: [0x40,0x24,0x20,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 20 a5 <unknown>
+// CHECK-UNKNOWN: a5202440 <unknown>
 
 ld1rod z0.d, p1/z, [x2]
 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2]
 // CHECK-ENCODING: [0x40,0x24,0xa0,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 a0 a5 <unknown>
+// CHECK-UNKNOWN: a5a02440 <unknown>
 
 // Aliases with a plain (non-list) first operand, plus offset.
 
@@ -131,25 +131,25 @@ ld1rob z0.b, p1/z, [x2, #224]
 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2, #224]
 // CHECK-ENCODING: [0x40,0x24,0x27,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 27 a4 <unknown>
+// CHECK-UNKNOWN: a4272440 <unknown>
 
 ld1roh z0.h, p1/z, [x2, #224]
 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2, #224]
 // CHECK-ENCODING: [0x40,0x24,0xa7,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 a7 a4 <unknown>
+// CHECK-UNKNOWN: a4a72440 <unknown>
 
 ld1row z0.s, p1/z, [x2, #224]
 // CHECK-INST: ld1row { z0.s }, p1/z, [x2, #224]
 // CHECK-ENCODING: [0x40,0x24,0x27,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 27 a5 <unknown>
+// CHECK-UNKNOWN: a5272440 <unknown>
 
 ld1rod z0.d, p1/z, [x2, #224]
 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2, #224]
 // CHECK-ENCODING: [0x40,0x24,0xa7,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 a7 a5 <unknown>
+// CHECK-UNKNOWN: a5a72440 <unknown>
 
 // With minimum immediate (-256)
 
@@ -157,25 +157,25 @@ ld1rob z0.b, p1/z, [x2, #-256]
 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2, #-256]
 // CHECK-ENCODING: [0x40,0x24,0x28,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 28 a4 <unknown>
+// CHECK-UNKNOWN: a4282440 <unknown>
 
 ld1roh z0.h, p1/z, [x2, #-256]
 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2, #-256]
 // CHECK-ENCODING: [0x40,0x24,0xa8,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 a8 a4 <unknown>
+// CHECK-UNKNOWN: a4a82440 <unknown>
 
 ld1row z0.s, p1/z, [x2, #-256]
 // CHECK-INST: ld1row { z0.s }, p1/z, [x2, #-256]
 // CHECK-ENCODING: [0x40,0x24,0x28,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 28 a5 <unknown>
+// CHECK-UNKNOWN: a5282440 <unknown>
 
 ld1rod z0.d, p1/z, [x2, #-256]
 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2, #-256]
 // CHECK-ENCODING: [0x40,0x24,0xa8,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 24 a8 a5 <unknown>
+// CHECK-UNKNOWN: a5a82440 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -185,25 +185,25 @@ ld1rob { z0.b }, p1/z, [x2, x3, lsl #0]
 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2, x3]
 // CHECK-ENCODING: [0x40,0x04,0x23,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 04 23 a4 <unknown>
+// CHECK-UNKNOWN: a4230440 <unknown>
 
 ld1roh { z0.h }, p1/z, [x2, x3, lsl #1]
 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2, x3, lsl #1]
 // CHECK-ENCODING: [0x40,0x04,0xa3,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 04 a3 a4 <unknown>
+// CHECK-UNKNOWN: a4a30440 <unknown>
 
 ld1row { z0.s }, p1/z, [x2, x3, lsl #2]
 // CHECK-INST: ld1row { z0.s }, p1/z, [x2, x3, lsl #2]
 // CHECK-ENCODING: [0x40,0x04,0x23,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 04 23 a5 <unknown>
+// CHECK-UNKNOWN: a5230440 <unknown>
 
 ld1rod { z0.d }, p1/z, [x2, x3, lsl #3]
 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2, x3, lsl #3]
 // CHECK-ENCODING: [0x40,0x04,0xa3,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 04 a3 a5 <unknown>
+// CHECK-UNKNOWN: a5a30440 <unknown>
 
 // Aliases with a plain (non-list) first operand, and omitted shift for the
 // byte variant.
@@ -212,25 +212,25 @@ ld1rob z0.b, p1/z, [x2, x3]
 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2, x3]
 // CHECK-ENCODING: [0x40,0x04,0x23,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 04 23 a4 <unknown>
+// CHECK-UNKNOWN: a4230440 <unknown>
 
 ld1roh z0.h, p1/z, [x2, x3, lsl #1]
 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2, x3, lsl #1]
 // CHECK-ENCODING: [0x40,0x04,0xa3,0xa4]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 04 a3 a4 <unknown>
+// CHECK-UNKNOWN: a4a30440 <unknown>
 
 ld1row z0.s, p1/z, [x2, x3, lsl #2]
 // CHECK-INST: ld1row { z0.s }, p1/z, [x2, x3, lsl #2]
 // CHECK-ENCODING: [0x40,0x04,0x23,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 04 23 a5 <unknown>
+// CHECK-UNKNOWN: a5230440 <unknown>
 
 ld1rod z0.d, p1/z, [x2, x3, lsl #3]
 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2, x3, lsl #3]
 // CHECK-ENCODING: [0x40,0x04,0xa3,0xa5]
 // CHECK-ERROR: instruction requires: f64mm sve
-// CHECK-UNKNOWN: 40 04 a3 a5 <unknown>
+// CHECK-UNKNOWN: a5a30440 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -240,13 +240,13 @@ zip1 z0.q, z1.q, z2.q
 // CHECK-INST: zip1 z0.q, z1.q, z2.q
 // CHECK-ENCODING: [0x20,0x00,0xa2,0x05]
 // CHECK-ERROR: instruction requires: f64mm sve or sme
-// CHECK-UNKNOWN: 20 00 a2 05 <unknown>
+// CHECK-UNKNOWN: 05a20020 <unknown>
 
 zip2 z0.q, z1.q, z2.q
 // CHECK-INST: zip2 z0.q, z1.q, z2.q
 // CHECK-ENCODING: [0x20,0x04,0xa2,0x05]
 // CHECK-ERROR: instruction requires: f64mm sve or sme
-// CHECK-UNKNOWN: 20 04 a2 05 <unknown>
+// CHECK-UNKNOWN: 05a20420 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -256,13 +256,13 @@ uzp1 z0.q, z1.q, z2.q
 // CHECK-INST: uzp1 z0.q, z1.q, z2.q
 // CHECK-ENCODING: [0x20,0x08,0xa2,0x05]
 // CHECK-ERROR: instruction requires: f64mm sve or sme
-// CHECK-UNKNOWN: 20 08 a2 05 <unknown>
+// CHECK-UNKNOWN: 05a20820 <unknown>
 
 uzp2 z0.q, z1.q, z2.q
 // CHECK-INST: uzp2 z0.q, z1.q, z2.q
 // CHECK-ENCODING: [0x20,0x0c,0xa2,0x05]
 // CHECK-ERROR: instruction requires: f64mm sve or sme
-// CHECK-UNKNOWN: 20 0c a2 05 <unknown>
+// CHECK-UNKNOWN: 05a20c20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -272,10 +272,10 @@ trn1 z0.q, z1.q, z2.q
 // CHECK-INST: trn1 z0.q, z1.q, z2.q
 // CHECK-ENCODING: [0x20,0x18,0xa2,0x05]
 // CHECK-ERROR: instruction requires: f64mm sve or sme
-// CHECK-UNKNOWN: 20 18 a2 05 <unknown>
+// CHECK-UNKNOWN: 05a21820 <unknown>
 
 trn2 z0.q, z1.q, z2.q
 // CHECK-INST: trn2 z0.q, z1.q, z2.q
 // CHECK-ENCODING: [0x20,0x1c,0xa2,0x05]
 // CHECK-ERROR: instruction requires: f64mm sve or sme
-// CHECK-UNKNOWN: 20 1c a2 05 <unknown>
+// CHECK-UNKNOWN: 05a21c20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/matrix-multiply-int8.s b/llvm/test/MC/AArch64/SVE/matrix-multiply-int8.s
index d7f6668866e22..da22a2305806f 100644
--- a/llvm/test/MC/AArch64/SVE/matrix-multiply-int8.s
+++ b/llvm/test/MC/AArch64/SVE/matrix-multiply-int8.s
@@ -15,19 +15,19 @@ ummla z0.s, z1.b, z2.b
 // CHECK-INST: ummla z0.s, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x98,0xc2,0x45]
 // CHECK-ERROR: instruction requires: i8mm sve
-// CHECK-UNKNOWN: 20 98 c2 45 <unknown>
+// CHECK-UNKNOWN: 45c29820 <unknown>
 
 smmla z0.s, z1.b, z2.b
 // CHECK-INST: smmla z0.s, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x98,0x02,0x45]
 // CHECK-ERROR: instruction requires: i8mm sve
-// CHECK-UNKNOWN: 20 98 02 45 <unknown>
+// CHECK-UNKNOWN: 45029820 <unknown>
 
 usmmla z0.s, z1.b, z2.b
 // CHECK-INST: usmmla z0.s, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x98,0x82,0x45]
 // CHECK-ERROR: instruction requires: i8mm sve
-// CHECK-UNKNOWN: 20 98 82 45 <unknown>
+// CHECK-UNKNOWN: 45829820 <unknown>
 
 
 // Test compatibility with MOVPRFX instruction.
@@ -35,35 +35,35 @@ usmmla z0.s, z1.b, z2.b
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 ummla z0.s, z1.b, z2.b
 // CHECK-INST: ummla z0.s, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x98,0xc2,0x45]
 // CHECK-ERROR: instruction requires: i8mm sve
-// CHECK-UNKNOWN: 20 98 c2 45 <unknown>
+// CHECK-UNKNOWN: 45c29820 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 smmla z0.s, z1.b, z2.b
 // CHECK-INST: smmla z0.s, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x98,0x02,0x45]
 // CHECK-ERROR: instruction requires: i8mm sve
-// CHECK-UNKNOWN: 20 98 02 45 <unknown>
+// CHECK-UNKNOWN: 45029820 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 usmmla z0.s, z1.b, z2.b
 // CHECK-INST: usmmla z0.s, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x98,0x82,0x45]
 // CHECK-ERROR: instruction requires: i8mm sve
-// CHECK-UNKNOWN: 20 98 82 45 <unknown>
+// CHECK-UNKNOWN: 45829820 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -73,20 +73,20 @@ usdot z0.s, z1.b, z2.b
 // CHECK-INST: usdot z0.s, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x78,0x82,0x44]
 // CHECK-ERROR: instruction requires: i8mm sve or sme
-// CHECK-UNKNOWN: 20 78 82 44 <unknown>
+// CHECK-UNKNOWN: 44827820 <unknown>
 
 // Test compatibility with MOVPRFX instruction.
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 usdot z0.s, z1.b, z2.b
 // CHECK-INST: usdot z0.s, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x78,0x82,0x44]
 // CHECK-ERROR: instruction requires: i8mm sve or sme
-// CHECK-UNKNOWN: 20 78 82 44 <unknown>
+// CHECK-UNKNOWN: 44827820 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -96,34 +96,34 @@ usdot z0.s, z1.b, z2.b[0]
 // CHECK-INST: usdot z0.s, z1.b, z2.b[0]
 // CHECK-ENCODING: [0x20,0x18,0xa2,0x44]
 // CHECK-ERROR: instruction requires: i8mm sve or sme
-// CHECK-UNKNOWN: 20 18 a2 44 <unknown>
+// CHECK-UNKNOWN: 44a21820 <unknown>
 
 sudot z0.s, z1.b, z2.b[3]
 // CHECK-INST: sudot z0.s, z1.b, z2.b[3]
 // CHECK-ENCODING: [0x20,0x1c,0xba,0x44]
 // CHECK-ERROR: instruction requires: i8mm sve or sme
-// CHECK-UNKNOWN: 20 1c ba 44 <unknown>
+// CHECK-UNKNOWN: 44ba1c20 <unknown>
 
 // Test compatibility with MOVPRFX instruction.
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 usdot z0.s, z1.b, z2.b[0]
 // CHECK-INST: usdot z0.s, z1.b, z2.b[0]
 // CHECK-ENCODING: [0x20,0x18,0xa2,0x44]
 // CHECK-ERROR: instruction requires: i8mm sve or sme
-// CHECK-UNKNOWN: 20 18 a2 44 <unknown>
+// CHECK-UNKNOWN: 44a21820 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sudot z0.s, z1.b, z2.b[0]
 // CHECK-INST: sudot z0.s, z1.b, z2.b[0]
 // CHECK-ENCODING: [0x20,0x1c,0xa2,0x44]
 // CHECK-ERROR: instruction requires: i8mm sve or sme
-// CHECK-UNKNOWN: 20 1c a2 44 <unknown>
+// CHECK-UNKNOWN: 44a21c20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/mla.s b/llvm/test/MC/AArch64/SVE/mla.s
index 57a0db78cb42c..8087a2058c67e 100644
--- a/llvm/test/MC/AArch64/SVE/mla.s
+++ b/llvm/test/MC/AArch64/SVE/mla.s
@@ -13,25 +13,25 @@ mla z0.b, p7/m, z1.b, z31.b
 // CHECK-INST: mla	z0.b, p7/m, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x5c,0x1f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 5c 1f 04 <unknown>
+// CHECK-UNKNOWN: 041f5c20 <unknown>
 
 mla z0.h, p7/m, z1.h, z31.h
 // CHECK-INST: mla	z0.h, p7/m, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x5c,0x5f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 5c 5f 04 <unknown>
+// CHECK-UNKNOWN: 045f5c20 <unknown>
 
 mla z0.s, p7/m, z1.s, z31.s
 // CHECK-INST: mla	z0.s, p7/m, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x5c,0x9f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 5c 9f 04 <unknown>
+// CHECK-UNKNOWN: 049f5c20 <unknown>
 
 mla z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: mla	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x5c,0xdf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 5c df 04 <unknown>
+// CHECK-UNKNOWN: 04df5c20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 mla z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: mla	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x5c,0xdf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 5c df 04 <unknown>
+// CHECK-UNKNOWN: 04df5c20 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 mla z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: mla	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x5c,0xdf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 5c df 04 <unknown>
+// CHECK-UNKNOWN: 04df5c20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/mls.s b/llvm/test/MC/AArch64/SVE/mls.s
index bc14ae637de61..6f5646d80db77 100644
--- a/llvm/test/MC/AArch64/SVE/mls.s
+++ b/llvm/test/MC/AArch64/SVE/mls.s
@@ -13,25 +13,25 @@ mls z0.b, p7/m, z1.b, z31.b
 // CHECK-INST: mls	z0.b, p7/m, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x7c,0x1f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 7c 1f 04 <unknown>
+// CHECK-UNKNOWN: 041f7c20 <unknown>
 
 mls z0.h, p7/m, z1.h, z31.h
 // CHECK-INST: mls	z0.h, p7/m, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x7c,0x5f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 7c 5f 04 <unknown>
+// CHECK-UNKNOWN: 045f7c20 <unknown>
 
 mls z0.s, p7/m, z1.s, z31.s
 // CHECK-INST: mls	z0.s, p7/m, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x7c,0x9f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 7c 9f 04 <unknown>
+// CHECK-UNKNOWN: 049f7c20 <unknown>
 
 mls z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: mls	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x7c,0xdf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 7c df 04 <unknown>
+// CHECK-UNKNOWN: 04df7c20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 mls z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: mls	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x7c,0xdf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 7c df 04 <unknown>
+// CHECK-UNKNOWN: 04df7c20 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 mls z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: mls	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x7c,0xdf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 7c df 04 <unknown>
+// CHECK-UNKNOWN: 04df7c20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/mov.s b/llvm/test/MC/AArch64/SVE/mov.s
index 95564b4a33b40..125e349c866fd 100644
--- a/llvm/test/MC/AArch64/SVE/mov.s
+++ b/llvm/test/MC/AArch64/SVE/mov.s
@@ -13,367 +13,367 @@ mov     z0.b, w0
 // CHECK-INST: mov     z0.b, w0
 // CHECK-ENCODING: [0x00,0x38,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 38 20 05 <unknown>
+// CHECK-UNKNOWN: 05203800 <unknown>
 
 mov     z0.h, w0
 // CHECK-INST: mov     z0.h, w0
 // CHECK-ENCODING: [0x00,0x38,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 38 60 05 <unknown>
+// CHECK-UNKNOWN: 05603800 <unknown>
 
 mov     z0.s, w0
 // CHECK-INST: mov     z0.s, w0
 // CHECK-ENCODING: [0x00,0x38,0xa0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 38 a0 05 <unknown>
+// CHECK-UNKNOWN: 05a03800 <unknown>
 
 mov     z0.d, x0
 // CHECK-INST: mov     z0.d, x0
 // CHECK-ENCODING: [0x00,0x38,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 38 e0 05 <unknown>
+// CHECK-UNKNOWN: 05e03800 <unknown>
 
 mov     z31.h, wsp
 // CHECK-INST: mov     z31.h, wsp
 // CHECK-ENCODING: [0xff,0x3b,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b 60 05 <unknown>
+// CHECK-UNKNOWN: 05603bff <unknown>
 
 mov     z31.s, wsp
 // CHECK-INST: mov     z31.s, wsp
 // CHECK-ENCODING: [0xff,0x3b,0xa0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b a0 05 <unknown>
+// CHECK-UNKNOWN: 05a03bff <unknown>
 
 mov     z31.d, sp
 // CHECK-INST: mov     z31.d, sp
 // CHECK-ENCODING: [0xff,0x3b,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b e0 05 <unknown>
+// CHECK-UNKNOWN: 05e03bff <unknown>
 
 mov     z31.b, wsp
 // CHECK-INST: mov     z31.b, wsp
 // CHECK-ENCODING: [0xff,0x3b,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b 20 05 <unknown>
+// CHECK-UNKNOWN: 05203bff <unknown>
 
 mov     z0.d, z0.d
 // CHECK-INST: mov     z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+// CHECK-UNKNOWN: 04603000 <unknown>
 
 mov     z31.d, z0.d
 // CHECK-INST: mov     z31.d, z0.d
 // CHECK-ENCODING: [0x1f,0x30,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 30 60 04 <unknown>
+// CHECK-UNKNOWN: 0460301f <unknown>
 
 mov     z5.b, #-128
 // CHECK-INST: mov     z5.b, #-128
 // CHECK-ENCODING: [0x05,0xd0,0x38,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 d0 38 25 <unknown>
+// CHECK-UNKNOWN: 2538d005 <unknown>
 
 mov     z5.b, #127
 // CHECK-INST: mov     z5.b, #127
 // CHECK-ENCODING: [0xe5,0xcf,0x38,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 cf 38 25 <unknown>
+// CHECK-UNKNOWN: 2538cfe5 <unknown>
 
 mov     z5.b, #255
 // CHECK-INST: mov     z5.b, #-1
 // CHECK-ENCODING: [0xe5,0xdf,0x38,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 df 38 25 <unknown>
+// CHECK-UNKNOWN: 2538dfe5 <unknown>
 
 mov     z21.h, #-128
 // CHECK-INST: mov     z21.h, #-128
 // CHECK-ENCODING: [0x15,0xd0,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 d0 78 25 <unknown>
+// CHECK-UNKNOWN: 2578d015 <unknown>
 
 mov     z21.h, #-128, lsl #8
 // CHECK-INST: mov     z21.h, #-32768
 // CHECK-ENCODING: [0x15,0xf0,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 f0 78 25 <unknown>
+// CHECK-UNKNOWN: 2578f015 <unknown>
 
 mov     z21.h, #-32768
 // CHECK-INST: mov     z21.h, #-32768
 // CHECK-ENCODING: [0x15,0xf0,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 f0 78 25 <unknown>
+// CHECK-UNKNOWN: 2578f015 <unknown>
 
 mov     z21.h, #127
 // CHECK-INST: mov     z21.h, #127
 // CHECK-ENCODING: [0xf5,0xcf,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 cf 78 25 <unknown>
+// CHECK-UNKNOWN: 2578cff5 <unknown>
 
 mov     z21.h, #127, lsl #8
 // CHECK-INST: mov     z21.h, #32512
 // CHECK-ENCODING: [0xf5,0xef,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 ef 78 25 <unknown>
+// CHECK-UNKNOWN: 2578eff5 <unknown>
 
 mov     z21.h, #32512
 // CHECK-INST: mov     z21.h, #32512
 // CHECK-ENCODING: [0xf5,0xef,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 ef 78 25 <unknown>
+// CHECK-UNKNOWN: 2578eff5 <unknown>
 
 mov     z21.s, #-128
 // CHECK-INST: mov     z21.s, #-128
 // CHECK-ENCODING: [0x15,0xd0,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 d0 b8 25 <unknown>
+// CHECK-UNKNOWN: 25b8d015 <unknown>
 
 mov     z21.s, #-128, lsl #8
 // CHECK-INST: mov     z21.s, #-32768
 // CHECK-ENCODING: [0x15,0xf0,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 f0 b8 25 <unknown>
+// CHECK-UNKNOWN: 25b8f015 <unknown>
 
 mov     z21.s, #-32768
 // CHECK-INST: mov     z21.s, #-32768
 // CHECK-ENCODING: [0x15,0xf0,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 f0 b8 25 <unknown>
+// CHECK-UNKNOWN: 25b8f015 <unknown>
 
 mov     z21.s, #127
 // CHECK-INST: mov     z21.s, #127
 // CHECK-ENCODING: [0xf5,0xcf,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 cf b8 25 <unknown>
+// CHECK-UNKNOWN: 25b8cff5 <unknown>
 
 mov     z21.s, #127, lsl #8
 // CHECK-INST: mov     z21.s, #32512
 // CHECK-ENCODING: [0xf5,0xef,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 ef b8 25 <unknown>
+// CHECK-UNKNOWN: 25b8eff5 <unknown>
 
 mov     z21.s, #32512
 // CHECK-INST: mov     z21.s, #32512
 // CHECK-ENCODING: [0xf5,0xef,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 ef b8 25 <unknown>
+// CHECK-UNKNOWN: 25b8eff5 <unknown>
 
 mov     z21.d, #-128
 // CHECK-INST: mov     z21.d, #-128
 // CHECK-ENCODING: [0x15,0xd0,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 d0 f8 25 <unknown>
+// CHECK-UNKNOWN: 25f8d015 <unknown>
 
 mov     z21.d, #-128, lsl #8
 // CHECK-INST: mov     z21.d, #-32768
 // CHECK-ENCODING: [0x15,0xf0,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 f0 f8 25 <unknown>
+// CHECK-UNKNOWN: 25f8f015 <unknown>
 
 mov     z21.d, #-32768
 // CHECK-INST: mov     z21.d, #-32768
 // CHECK-ENCODING: [0x15,0xf0,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 f0 f8 25 <unknown>
+// CHECK-UNKNOWN: 25f8f015 <unknown>
 
 mov     z21.d, #127
 // CHECK-INST: mov     z21.d, #127
 // CHECK-ENCODING: [0xf5,0xcf,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 cf f8 25 <unknown>
+// CHECK-UNKNOWN: 25f8cff5 <unknown>
 
 mov     z21.d, #127, lsl #8
 // CHECK-INST: mov     z21.d, #32512
 // CHECK-ENCODING: [0xf5,0xef,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 ef f8 25 <unknown>
+// CHECK-UNKNOWN: 25f8eff5 <unknown>
 
 mov     z21.d, #32512
 // CHECK-INST: mov     z21.d, #32512
 // CHECK-ENCODING: [0xf5,0xef,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 ef f8 25 <unknown>
+// CHECK-UNKNOWN: 25f8eff5 <unknown>
 
 mov     z0.h, #32768
 // CHECK-INST: mov    z0.h, #-32768
 // CHECK-ENCODING: [0x00,0xf0,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f0 78 25 <unknown>
+// CHECK-UNKNOWN: 2578f000 <unknown>
 
 mov     z0.h, #65280
 // CHECK-INST: mov    z0.h, #-256
 // CHECK-ENCODING: [0xe0,0xff,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 78 25 <unknown>
+// CHECK-UNKNOWN: 2578ffe0 <unknown>
 
 mov     z0.h, #-33024
 // CHECK-INST: mov z0.h, #32512
 // CHECK-ENCODING: [0xe0,0xef,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ef 78 25 <unknown>
+// CHECK-UNKNOWN: 2578efe0 <unknown>
 
 mov     z0.h, #-32769
 // CHECK-INST: mov z0.h, #32767
 // CHECK-ENCODING: [0xc0,0x05,0xc0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 05 c0 05 <unknown>
+// CHECK-UNKNOWN: 05c005c0 <unknown>
 
 mov     z0.s, #-32769
 // CHECK-INST: mov     z0.s, #0xffff7fff
 // CHECK-ENCODING: [0xc0,0x83,0xc0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 83 c0 05 <unknown>
+// CHECK-UNKNOWN: 05c083c0 <unknown>
 
 mov     z0.s, #32768
 // CHECK-INST: mov     z0.s, #32768
 // CHECK-ENCODING: [0x00,0x88,0xc0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 88 c0 05 <unknown>
+// CHECK-UNKNOWN: 05c08800 <unknown>
 
 mov     z0.d, #-32769
 // CHECK-INST: mov     z0.d, #0xffffffffffff7fff
 // CHECK-ENCODING: [0xc0,0x87,0xc3,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 87 c3 05 <unknown>
+// CHECK-UNKNOWN: 05c387c0 <unknown>
 
 mov     z0.d, #32768
 // CHECK-INST: mov     z0.d, #32768
 // CHECK-ENCODING: [0x00,0x88,0xc3,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 88 c3 05 <unknown>
+// CHECK-UNKNOWN: 05c38800 <unknown>
 
 mov     z0.d, #0xe0000000000003ff
 // CHECK-INST: mov     z0.d, #0xe0000000000003ff
 // CHECK-ENCODING: [0x80,0x19,0xc2,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 19 c2 05 <unknown>
+// CHECK-UNKNOWN: 05c21980 <unknown>
 
 mov     z5.b, p0/z, #-128
 // CHECK-INST: mov     z5.b, p0/z, #-128
 // CHECK-ENCODING: [0x05,0x10,0x10,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 10 10 05  <unknown>
+// CHECK-UNKNOWN: 05101005  <unknown>
 
 mov     z5.b, p0/z, #127
 // CHECK-INST: mov     z5.b, p0/z, #127
 // CHECK-ENCODING: [0xe5,0x0f,0x10,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 0f 10 05  <unknown>
+// CHECK-UNKNOWN: 05100fe5  <unknown>
 
 mov     z5.b, p0/z, #255
 // CHECK-INST: mov     z5.b, p0/z, #-1
 // CHECK-ENCODING: [0xe5,0x1f,0x10,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 1f 10 05  <unknown>
+// CHECK-UNKNOWN: 05101fe5  <unknown>
 
 mov     z21.h, p0/z, #-128
 // CHECK-INST: mov     z21.h, p0/z, #-128
 // CHECK-ENCODING: [0x15,0x10,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 10 50 05  <unknown>
+// CHECK-UNKNOWN: 05501015  <unknown>
 
 mov     z21.h, p0/z, #-128, lsl #8
 // CHECK-INST: mov     z21.h, p0/z, #-32768
 // CHECK-ENCODING: [0x15,0x30,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 30 50 05  <unknown>
+// CHECK-UNKNOWN: 05503015  <unknown>
 
 mov     z21.h, p0/z, #-32768
 // CHECK-INST: mov     z21.h, p0/z, #-32768
 // CHECK-ENCODING: [0x15,0x30,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 30 50 05  <unknown>
+// CHECK-UNKNOWN: 05503015  <unknown>
 
 mov     z21.h, p0/z, #127
 // CHECK-INST: mov     z21.h, p0/z, #127
 // CHECK-ENCODING: [0xf5,0x0f,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 0f 50 05  <unknown>
+// CHECK-UNKNOWN: 05500ff5  <unknown>
 
 mov     z21.h, p0/z, #127, lsl #8
 // CHECK-INST: mov     z21.h, p0/z, #32512
 // CHECK-ENCODING: [0xf5,0x2f,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 2f 50 05  <unknown>
+// CHECK-UNKNOWN: 05502ff5  <unknown>
 
 mov     z21.h, p0/z, #32512
 // CHECK-INST: mov     z21.h, p0/z, #32512
 // CHECK-ENCODING: [0xf5,0x2f,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 2f 50 05  <unknown>
+// CHECK-UNKNOWN: 05502ff5  <unknown>
 
 mov     z21.s, p0/z, #-128
 // CHECK-INST: mov     z21.s, p0/z, #-128
 // CHECK-ENCODING: [0x15,0x10,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 10 90 05  <unknown>
+// CHECK-UNKNOWN: 05901015  <unknown>
 
 mov     z21.s, p0/z, #-128, lsl #8
 // CHECK-INST: mov     z21.s, p0/z, #-32768
 // CHECK-ENCODING: [0x15,0x30,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 30 90 05  <unknown>
+// CHECK-UNKNOWN: 05903015  <unknown>
 
 mov     z21.s, p0/z, #-32768
 // CHECK-INST: mov     z21.s, p0/z, #-32768
 // CHECK-ENCODING: [0x15,0x30,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 30 90 05  <unknown>
+// CHECK-UNKNOWN: 05903015  <unknown>
 
 mov     z21.s, p0/z, #127
 // CHECK-INST: mov     z21.s, p0/z, #127
 // CHECK-ENCODING: [0xf5,0x0f,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 0f 90 05  <unknown>
+// CHECK-UNKNOWN: 05900ff5  <unknown>
 
 mov     z21.s, p0/z, #127, lsl #8
 // CHECK-INST: mov     z21.s, p0/z, #32512
 // CHECK-ENCODING: [0xf5,0x2f,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 2f 90 05  <unknown>
+// CHECK-UNKNOWN: 05902ff5  <unknown>
 
 mov     z21.s, p0/z, #32512
 // CHECK-INST: mov     z21.s, p0/z, #32512
 // CHECK-ENCODING: [0xf5,0x2f,0x90,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 2f 90 05  <unknown>
+// CHECK-UNKNOWN: 05902ff5  <unknown>
 
 mov     z21.d, p0/z, #-128
 // CHECK-INST: mov     z21.d, p0/z, #-128
 // CHECK-ENCODING: [0x15,0x10,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 10 d0 05  <unknown>
+// CHECK-UNKNOWN: 05d01015  <unknown>
 
 mov     z21.d, p0/z, #-128, lsl #8
 // CHECK-INST: mov     z21.d, p0/z, #-32768
 // CHECK-ENCODING: [0x15,0x30,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 30 d0 05  <unknown>
+// CHECK-UNKNOWN: 05d03015  <unknown>
 
 mov     z21.d, p0/z, #-32768
 // CHECK-INST: mov     z21.d, p0/z, #-32768
 // CHECK-ENCODING: [0x15,0x30,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 30 d0 05  <unknown>
+// CHECK-UNKNOWN: 05d03015  <unknown>
 
 mov     z21.d, p0/z, #127
 // CHECK-INST: mov     z21.d, p0/z, #127
 // CHECK-ENCODING: [0xf5,0x0f,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 0f d0 05  <unknown>
+// CHECK-UNKNOWN: 05d00ff5  <unknown>
 
 mov     z21.d, p0/z, #127, lsl #8
 // CHECK-INST: mov     z21.d, p0/z, #32512
 // CHECK-ENCODING: [0xf5,0x2f,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 2f d0 05  <unknown>
+// CHECK-UNKNOWN: 05d02ff5  <unknown>
 
 mov     z21.d, p0/z, #32512
 // CHECK-INST: mov     z21.d, p0/z, #32512
 // CHECK-ENCODING: [0xf5,0x2f,0xd0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f5 2f d0 05  <unknown>
+// CHECK-UNKNOWN: 05d02ff5  <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -384,49 +384,49 @@ mov     z0.b, #-129
 // CHECK-INST: mov     z0.b, #127
 // CHECK-ENCODING: [0xe0,0xcf,0x38,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf 38 25 <unknown>
+// CHECK-UNKNOWN: 2538cfe0 <unknown>
 
 mov     z0.h, #-129, lsl #8
 // CHECK-INST: mov     z0.h, #32512
 // CHECK-ENCODING: [0xe0,0xef,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ef 78 25 <unknown>
+// CHECK-UNKNOWN: 2578efe0 <unknown>
 
 mov     z5.h, #0xfffa
 // CHECK-INST: mov     z5.h, #-6
 // CHECK-ENCODING: [0x45,0xdf,0x78,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 45 df 78 25 <unknown>
+// CHECK-UNKNOWN: 2578df45 <unknown>
 
 mov     z5.s, #0xfffffffa
 // CHECK-INST: mov     z5.s, #-6
 // CHECK-ENCODING: [0x45,0xdf,0xb8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 45 df b8 25 <unknown>
+// CHECK-UNKNOWN: 25b8df45 <unknown>
 
 mov     z5.d, #0xfffffffffffffffa
 // CHECK-INST: mov     z5.d, #-6
 // CHECK-ENCODING: [0x45,0xdf,0xf8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 45 df f8 25 <unknown>
+// CHECK-UNKNOWN: 25f8df45 <unknown>
 
 mov     z0.b, p0/z, #-129
 // CHECK-INST: mov     z0.b, p0/z, #127
 // CHECK-ENCODING: [0xe0,0x0f,0x10,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 0f 10 05 <unknown>
+// CHECK-UNKNOWN: 05100fe0 <unknown>
 
 mov     z0.h, p0/z, #-33024
 // CHECK-INST: mov     z0.h, p0/z, #32512
 // CHECK-ENCODING: [0xe0,0x2f,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 2f 50 05 <unknown>
+// CHECK-UNKNOWN: 05502fe0 <unknown>
 
 mov     z0.h, p0/z, #-129, lsl #8
 // CHECK-INST: mov     z0.h, p0/z, #32512
 // CHECK-ENCODING: [0xe0,0x2f,0x50,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 2f 50 05 <unknown>
+// CHECK-UNKNOWN: 05502fe0 <unknown>
 
 // --------------------------------------------------------------------------//
 // Tests for merging variant (/m) and testing the range of predicate (> 7)
@@ -436,43 +436,43 @@ mov     z5.b, p15/m, #-128
 // CHECK-INST: mov     z5.b, p15/m, #-128
 // CHECK-ENCODING: [0x05,0x50,0x1f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 50 1f 05  <unknown>
+// CHECK-UNKNOWN: 051f5005  <unknown>
 
 mov     z21.h, p15/m, #-128
 // CHECK-INST: mov     z21.h, p15/m, #-128
 // CHECK-ENCODING: [0x15,0x50,0x5f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 50 5f 05  <unknown>
+// CHECK-UNKNOWN: 055f5015  <unknown>
 
 mov     z21.h, p15/m, #-128, lsl #8
 // CHECK-INST: mov     z21.h, p15/m, #-32768
 // CHECK-ENCODING: [0x15,0x70,0x5f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 70 5f 05  <unknown>
+// CHECK-UNKNOWN: 055f7015  <unknown>
 
 mov     z21.s, p15/m, #-128
 // CHECK-INST: mov     z21.s, p15/m, #-128
 // CHECK-ENCODING: [0x15,0x50,0x9f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 50 9f 05  <unknown>
+// CHECK-UNKNOWN: 059f5015  <unknown>
 
 mov     z21.s, p15/m, #-128, lsl #8
 // CHECK-INST: mov     z21.s, p15/m, #-32768
 // CHECK-ENCODING: [0x15,0x70,0x9f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 70 9f 05  <unknown>
+// CHECK-UNKNOWN: 059f7015  <unknown>
 
 mov     z21.d, p15/m, #-128
 // CHECK-INST: mov     z21.d, p15/m, #-128
 // CHECK-ENCODING: [0x15,0x50,0xdf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 50 df 05  <unknown>
+// CHECK-UNKNOWN: 05df5015  <unknown>
 
 mov     z21.d, p15/m, #-128, lsl #8
 // CHECK-INST: mov     z21.d, p15/m, #-32768
 // CHECK-ENCODING: [0x15,0x70,0xdf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 70 df 05  <unknown>
+// CHECK-UNKNOWN: 05df7015  <unknown>
 
 // --------------------------------------------------------------------------//
 // Tests for indexed variant
@@ -481,91 +481,91 @@ mov     z0.b, z0.b[0]
 // CHECK-INST: mov     z0.b, b0
 // CHECK-ENCODING: [0x00,0x20,0x21,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 21 05 <unknown>
+// CHECK-UNKNOWN: 05212000 <unknown>
 
 mov     z0.h, z0.h[0]
 // CHECK-INST: mov     z0.h, h0
 // CHECK-ENCODING: [0x00,0x20,0x22,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 22 05 <unknown>
+// CHECK-UNKNOWN: 05222000 <unknown>
 
 mov     z0.s, z0.s[0]
 // CHECK-INST: mov     z0.s, s0
 // CHECK-ENCODING: [0x00,0x20,0x24,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 24 05 <unknown>
+// CHECK-UNKNOWN: 05242000 <unknown>
 
 mov     z0.d, z0.d[0]
 // CHECK-INST: mov     z0.d, d0
 // CHECK-ENCODING: [0x00,0x20,0x28,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 28 05 <unknown>
+// CHECK-UNKNOWN: 05282000 <unknown>
 
 mov     z0.q, z0.q[0]
 // CHECK-INST: mov     z0.q, q0
 // CHECK-ENCODING: [0x00,0x20,0x30,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 30 05 <unknown>
+// CHECK-UNKNOWN: 05302000 <unknown>
 
 mov     z0.b, b0
 // CHECK-INST: mov     z0.b, b0
 // CHECK-ENCODING: [0x00,0x20,0x21,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 21 05 <unknown>
+// CHECK-UNKNOWN: 05212000 <unknown>
 
 mov     z0.h, h0
 // CHECK-INST: mov     z0.h, h0
 // CHECK-ENCODING: [0x00,0x20,0x22,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 22 05 <unknown>
+// CHECK-UNKNOWN: 05222000 <unknown>
 
 mov     z0.s, s0
 // CHECK-INST: mov     z0.s, s0
 // CHECK-ENCODING: [0x00,0x20,0x24,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 24 05 <unknown>
+// CHECK-UNKNOWN: 05242000 <unknown>
 
 mov     z0.d, d0
 // CHECK-INST: mov     z0.d, d0
 // CHECK-ENCODING: [0x00,0x20,0x28,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 28 05 <unknown>
+// CHECK-UNKNOWN: 05282000 <unknown>
 
 mov     z0.q, q0
 // CHECK-INST: mov     z0.q, q0
 // CHECK-ENCODING: [0x00,0x20,0x30,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 30 05 <unknown>
+// CHECK-UNKNOWN: 05302000 <unknown>
 
 mov     z31.b, z31.b[63]
 // CHECK-INST: mov     z31.b, z31.b[63]
 // CHECK-ENCODING: [0xff,0x23,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 23 ff 05 <unknown>
+// CHECK-UNKNOWN: 05ff23ff <unknown>
 
 mov     z31.h, z31.h[31]
 // CHECK-INST: mov     z31.h, z31.h[31]
 // CHECK-ENCODING: [0xff,0x23,0xfe,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 23 fe 05 <unknown>
+// CHECK-UNKNOWN: 05fe23ff <unknown>
 
 mov     z31.s, z31.s[15]
 // CHECK-INST: mov     z31.s, z31.s[15]
 // CHECK-ENCODING: [0xff,0x23,0xfc,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 23 fc 05 <unknown>
+// CHECK-UNKNOWN: 05fc23ff <unknown>
 
 mov     z31.d, z31.d[7]
 // CHECK-INST: mov     z31.d, z31.d[7]
 // CHECK-ENCODING: [0xff,0x23,0xf8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 23 f8 05 <unknown>
+// CHECK-UNKNOWN: 05f823ff <unknown>
 
 mov     z5.q, z17.q[3]
 // CHECK-INST: mov     z5.q, z17.q[3]
 // CHECK-ENCODING: [0x25,0x22,0xf0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 22 f0 05 <unknown>
+// CHECK-UNKNOWN: 05f02225 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -575,157 +575,157 @@ mov     z0.b, p0/m, w0
 // CHECK-INST: mov     z0.b, p0/m, w0
 // CHECK-ENCODING: [0x00,0xa0,0x28,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 28 05 <unknown>
+// CHECK-UNKNOWN: 0528a000 <unknown>
 
 mov     z0.h, p0/m, w0
 // CHECK-INST: mov     z0.h, p0/m, w0
 // CHECK-ENCODING: [0x00,0xa0,0x68,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 68 05 <unknown>
+// CHECK-UNKNOWN: 0568a000 <unknown>
 
 mov     z0.s, p0/m, w0
 // CHECK-INST: mov     z0.s, p0/m, w0
 // CHECK-ENCODING: [0x00,0xa0,0xa8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 a8 05 <unknown>
+// CHECK-UNKNOWN: 05a8a000 <unknown>
 
 mov     z0.d, p0/m, x0
 // CHECK-INST: mov     z0.d, p0/m, x0
 // CHECK-ENCODING: [0x00,0xa0,0xe8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 e8 05 <unknown>
+// CHECK-UNKNOWN: 05e8a000 <unknown>
 
 mov     z31.b, p7/m, wsp
 // CHECK-INST: mov     z31.b, p7/m, wsp
 // CHECK-ENCODING: [0xff,0xbf,0x28,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 28 05 <unknown>
+// CHECK-UNKNOWN: 0528bfff <unknown>
 
 mov     z31.h, p7/m, wsp
 // CHECK-INST: mov     z31.h, p7/m, wsp
 // CHECK-ENCODING: [0xff,0xbf,0x68,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 68 05 <unknown>
+// CHECK-UNKNOWN: 0568bfff <unknown>
 
 mov     z31.s, p7/m, wsp
 // CHECK-INST: mov     z31.s, p7/m, wsp
 // CHECK-ENCODING: [0xff,0xbf,0xa8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf a8 05 <unknown>
+// CHECK-UNKNOWN: 05a8bfff <unknown>
 
 mov     z31.d, p7/m, sp
 // CHECK-INST: mov     z31.d, p7/m, sp
 // CHECK-ENCODING: [0xff,0xbf,0xe8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf e8 05 <unknown>
+// CHECK-UNKNOWN: 05e8bfff <unknown>
 
 mov     z0.b, p0/m, b0
 // CHECK-INST: mov     z0.b, p0/m, b0
 // CHECK-ENCODING: [0x00,0x80,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 20 05 <unknown>
+// CHECK-UNKNOWN: 05208000 <unknown>
 
 mov     z31.b, p7/m, b31
 // CHECK-INST: mov     z31.b, p7/m, b31
 // CHECK-ENCODING: [0xff,0x9f,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f 20 05 <unknown>
+// CHECK-UNKNOWN: 05209fff <unknown>
 
 mov     z0.h, p0/m, h0
 // CHECK-INST: mov     z0.h, p0/m, h0
 // CHECK-ENCODING: [0x00,0x80,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 60 05 <unknown>
+// CHECK-UNKNOWN: 05608000 <unknown>
 
 mov     z31.h, p7/m, h31
 // CHECK-INST: mov     z31.h, p7/m, h31
 // CHECK-ENCODING: [0xff,0x9f,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f 60 05 <unknown>
+// CHECK-UNKNOWN: 05609fff <unknown>
 
 mov     z0.s, p0/m, s0
 // CHECK-INST: mov     z0.s, p0/m, s0
 // CHECK-ENCODING: [0x00,0x80,0xa0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 a0 05 <unknown>
+// CHECK-UNKNOWN: 05a08000 <unknown>
 
 mov     z31.s, p7/m, s31
 // CHECK-INST: mov     z31.s, p7/m, s31
 // CHECK-ENCODING: [0xff,0x9f,0xa0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f a0 05 <unknown>
+// CHECK-UNKNOWN: 05a09fff <unknown>
 
 mov     z0.d, p0/m, d0
 // CHECK-INST: mov     z0.d, p0/m, d0
 // CHECK-ENCODING: [0x00,0x80,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 e0 05 <unknown>
+// CHECK-UNKNOWN: 05e08000 <unknown>
 
 mov     z31.d, p7/m, d31
 // CHECK-INST: mov     z31.d, p7/m, d31
 // CHECK-ENCODING: [0xff,0x9f,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f e0 05 <unknown>
+// CHECK-UNKNOWN: 05e09fff <unknown>
 
 mov     p0.b, p0/m, p0.b
 // CHECK-INST: mov     p0.b, p0/m, p0.b
 // CHECK-ENCODING: [0x10,0x42,0x00,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 42 00 25 <unknown>
+// CHECK-UNKNOWN: 25004210 <unknown>
 
 mov     p15.b, p15/m, p15.b
 // CHECK-INST: mov     p15.b, p15/m, p15.b
 // CHECK-ENCODING: [0xff,0x7f,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 7f 0f 25 <unknown>
+// CHECK-UNKNOWN: 250f7fff <unknown>
 
 mov     z31.b, p15/m, z31.b
 // CHECK-INST: mov     z31.b, p15/m, z31.b
 // CHECK-ENCODING: [0xff,0xff,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 3f 05 <unknown>
+// CHECK-UNKNOWN: 053fffff <unknown>
 
 mov     z31.h, p15/m, z31.h
 // CHECK-INST: mov     z31.h, p15/m, z31.h
 // CHECK-ENCODING: [0xff,0xff,0x7f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 7f 05 <unknown>
+// CHECK-UNKNOWN: 057fffff <unknown>
 
 mov     z31.s, p15/m, z31.s
 // CHECK-INST: mov     z31.s, p15/m, z31.s
 // CHECK-ENCODING: [0xff,0xff,0xbf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff bf 05 <unknown>
+// CHECK-UNKNOWN: 05bfffff <unknown>
 
 mov     z31.d, p15/m, z31.d
 // CHECK-INST: mov     z31.d, p15/m, z31.d
 // CHECK-ENCODING: [0xff,0xff,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff ff 05 <unknown>
+// CHECK-UNKNOWN: 05ffffff <unknown>
 
 mov     p0.b, p0.b
 // CHECK-INST: mov     p0.b, p0.b
 // CHECK-ENCODING: [0x00,0x40,0x80,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 80 25 <unknown>
+// CHECK-UNKNOWN: 25804000 <unknown>
 
 mov     p15.b, p15.b
 // CHECK-INST: mov     p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x7d,0x8f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7d 8f 25 <unknown>
+// CHECK-UNKNOWN: 258f7def <unknown>
 
 mov     p0.b, p0/z, p0.b
 // CHECK-INST: mov     p0.b, p0/z, p0.b
 // CHECK-ENCODING: [0x00,0x40,0x00,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 00 25 <unknown>
+// CHECK-UNKNOWN: 25004000 <unknown>
 
 mov     p15.b, p15/z, p15.b
 // CHECK-INST: mov     p15.b, p15/z, p15.b
 // CHECK-ENCODING: [0xef,0x7d,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7d 0f 25 <unknown>
+// CHECK-UNKNOWN: 250f7def <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -735,70 +735,70 @@ movprfx z31.d, p7/z, z6.d
 // CHECK-INST: movprfx	z31.d, p7/z, z6.d
 // CHECK-ENCODING: [0xdf,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cdf <unknown>
 
 mov     z31.d, p7/m, sp
 // CHECK-INST: mov	z31.d, p7/m, sp
 // CHECK-ENCODING: [0xff,0xbf,0xe8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf e8 05 <unknown>
+// CHECK-UNKNOWN: 05e8bfff <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 mov     z31.d, p7/m, sp
 // CHECK-INST: mov	z31.d, p7/m, sp
 // CHECK-ENCODING: [0xff,0xbf,0xe8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf e8 05 <unknown>
+// CHECK-UNKNOWN: 05e8bfff <unknown>
 
 movprfx z21.d, p7/z, z28.d
 // CHECK-INST: movprfx	z21.d, p7/z, z28.d
 // CHECK-ENCODING: [0x95,0x3f,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 3f d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03f95 <unknown>
 
 mov     z21.d, p7/m, #-128, lsl #8
 // CHECK-INST: mov	z21.d, p7/m, #-32768
 // CHECK-ENCODING: [0x15,0x70,0xd7,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 70 d7 05 <unknown>
+// CHECK-UNKNOWN: 05d77015 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 mov     z21.d, p15/m, #-128, lsl #8
 // CHECK-INST: mov	z21.d, p15/m, #-32768
 // CHECK-ENCODING: [0x15,0x70,0xdf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 70 df 05 <unknown>
+// CHECK-UNKNOWN: 05df7015 <unknown>
 
 movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 mov     z4.d, p7/m, d31
 // CHECK-INST: mov	z4.d, p7/m, d31
 // CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 9f e0 05 <unknown>
+// CHECK-UNKNOWN: 05e09fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 mov     z4.d, p7/m, d31
 // CHECK-INST: mov	z4.d, p7/m, d31
 // CHECK-ENCODING: [0xe4,0x9f,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 9f e0 05 <unknown>
+// CHECK-UNKNOWN: 05e09fe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/movprfx.s b/llvm/test/MC/AArch64/SVE/movprfx.s
index 2e76d7d094af4..58de89e54c45a 100644
--- a/llvm/test/MC/AArch64/SVE/movprfx.s
+++ b/llvm/test/MC/AArch64/SVE/movprfx.s
@@ -41,7 +41,7 @@ movprfx z0, z1
 // CHECK-INST: movprfx  z0, z1
 // CHECK-ENCODING: [0x20,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bc20 <unknown>
 
 hlt #1
 // CHECK-INST: hlt      #0x1
@@ -51,7 +51,7 @@ movprfx z0.d, p0/z, z1.d
 // CHECK-INST: movprfx  z0.d, p0/z, z1.d
 // CHECK-ENCODING: [0x20,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d02020 <unknown>
 
 hlt #1
 // CHECK-INST: hlt      #0x1
@@ -61,7 +61,7 @@ movprfx z0, z1
 // CHECK-INST: movprfx  z0, z1
 // CHECK-ENCODING: [0x20,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bc20 <unknown>
 
 brk #1
 // CHECK-INST: brk      #0x1
@@ -71,7 +71,7 @@ movprfx z0.d, p0/z, z1.d
 // CHECK-INST: movprfx  z0.d, p0/z, z1.d
 // CHECK-ENCODING: [0x20,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d02020 <unknown>
 
 brk #1
 // CHECK-INST: brk      #0x1
@@ -84,16 +84,16 @@ movprfx z0, z1
 // CHECK-INST: movprfx  z0, z1
 // CHECK-ENCODING: [0x20,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bc20 <unknown>
 
 add z0.d, p0/m, z0.d, z1.d
 // CHECK-INST: add      z0.d, p0/m, z0.d, z1.d
 // CHECK-ENCODING: [0x20,0x00,0xc0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 c0 04 <unknown>
+// CHECK-UNKNOWN: 04c00020 <unknown>
 
 add z0.d, p0/m, z0.d, z1.d
 // CHECK-INST: add      z0.d, p0/m, z0.d, z1.d
 // CHECK-ENCODING: [0x20,0x00,0xc0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 c0 04 <unknown>
+// CHECK-UNKNOWN: 04c00020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/movs.s b/llvm/test/MC/AArch64/SVE/movs.s
index 7f2130b483316..7124db150202a 100644
--- a/llvm/test/MC/AArch64/SVE/movs.s
+++ b/llvm/test/MC/AArch64/SVE/movs.s
@@ -13,22 +13,22 @@ movs    p0.b, p0.b
 // CHECK-INST: movs    p0.b, p0.b
 // CHECK-ENCODING: [0x00,0x40,0xc0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 c0 25 <unknown>
+// CHECK-UNKNOWN: 25c04000 <unknown>
 
 movs    p15.b, p15.b
 // CHECK-INST: movs    p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x7d,0xcf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7d cf 25 <unknown>
+// CHECK-UNKNOWN: 25cf7def <unknown>
 
 movs    p0.b, p0/z, p0.b
 // CHECK-INST: movs    p0.b, p0/z, p0.b
 // CHECK-ENCODING: [0x00,0x40,0x40,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 40 25 <unknown>
+// CHECK-UNKNOWN: 25404000 <unknown>
 
 movs    p15.b, p15/z, p15.b
 // CHECK-INST: movs    p15.b, p15/z, p15.b
 // CHECK-ENCODING: [0xef,0x7d,0x4f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7d 4f 25 <unknown>
+// CHECK-UNKNOWN: 254f7def <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/msb.s b/llvm/test/MC/AArch64/SVE/msb.s
index dad01e102a04b..a45ae252e9054 100644
--- a/llvm/test/MC/AArch64/SVE/msb.s
+++ b/llvm/test/MC/AArch64/SVE/msb.s
@@ -13,25 +13,25 @@ msb z0.b, p7/m, z1.b, z31.b
 // CHECK-INST: msb	z0.b, p7/m, z1.b, z31.b
 // CHECK-ENCODING: [0xe0,0xff,0x01,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 01 04 <unknown>
+// CHECK-UNKNOWN: 0401ffe0 <unknown>
 
 msb z0.h, p7/m, z1.h, z31.h
 // CHECK-INST: msb	z0.h, p7/m, z1.h, z31.h
 // CHECK-ENCODING: [0xe0,0xff,0x41,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 41 04 <unknown>
+// CHECK-UNKNOWN: 0441ffe0 <unknown>
 
 msb z0.s, p7/m, z1.s, z31.s
 // CHECK-INST: msb	z0.s, p7/m, z1.s, z31.s
 // CHECK-ENCODING: [0xe0,0xff,0x81,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 81 04 <unknown>
+// CHECK-UNKNOWN: 0481ffe0 <unknown>
 
 msb z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: msb	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0xe0,0xff,0xc1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff c1 04 <unknown>
+// CHECK-UNKNOWN: 04c1ffe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 msb z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: msb	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0xe0,0xff,0xc1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff c1 04 <unknown>
+// CHECK-UNKNOWN: 04c1ffe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 msb z0.d, p7/m, z1.d, z31.d
 // CHECK-INST: msb	z0.d, p7/m, z1.d, z31.d
 // CHECK-ENCODING: [0xe0,0xff,0xc1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff c1 04 <unknown>
+// CHECK-UNKNOWN: 04c1ffe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/mul.s b/llvm/test/MC/AArch64/SVE/mul.s
index 20ce6caa8081e..36a714a7af9e7 100644
--- a/llvm/test/MC/AArch64/SVE/mul.s
+++ b/llvm/test/MC/AArch64/SVE/mul.s
@@ -13,73 +13,73 @@ mul z0.b, p7/m, z0.b, z31.b
 // CHECK-INST: mul	z0.b, p7/m, z0.b, z31.b
 // CHECK-ENCODING: [0xe0,0x1f,0x10,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f 10 04 <unknown>
+// CHECK-UNKNOWN: 04101fe0 <unknown>
 
 mul z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: mul	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x1f,0x50,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f 50 04 <unknown>
+// CHECK-UNKNOWN: 04501fe0 <unknown>
 
 mul z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: mul	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x1f,0x90,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f 90 04 <unknown>
+// CHECK-UNKNOWN: 04901fe0 <unknown>
 
 mul z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: mul	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d0 04 <unknown>
+// CHECK-UNKNOWN: 04d01fe0 <unknown>
 
 mul z31.b, z31.b, #-128
 // CHECK-INST: mul	z31.b, z31.b, #-128
 // CHECK-ENCODING: [0x1f,0xd0,0x30,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f d0 30 25 <unknown>
+// CHECK-UNKNOWN: 2530d01f <unknown>
 
 mul z31.b, z31.b, #127
 // CHECK-INST: mul	z31.b, z31.b, #127
 // CHECK-ENCODING: [0xff,0xcf,0x30,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf 30 25 <unknown>
+// CHECK-UNKNOWN: 2530cfff <unknown>
 
 mul z31.h, z31.h, #-128
 // CHECK-INST: mul	z31.h, z31.h, #-128
 // CHECK-ENCODING: [0x1f,0xd0,0x70,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f d0 70 25 <unknown>
+// CHECK-UNKNOWN: 2570d01f <unknown>
 
 mul z31.h, z31.h, #127
 // CHECK-INST: mul	z31.h, z31.h, #127
 // CHECK-ENCODING: [0xff,0xcf,0x70,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf 70 25 <unknown>
+// CHECK-UNKNOWN: 2570cfff <unknown>
 
 mul z31.s, z31.s, #-128
 // CHECK-INST: mul	z31.s, z31.s, #-128
 // CHECK-ENCODING: [0x1f,0xd0,0xb0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f d0 b0 25 <unknown>
+// CHECK-UNKNOWN: 25b0d01f <unknown>
 
 mul z31.s, z31.s, #127
 // CHECK-INST: mul	z31.s, z31.s, #127
 // CHECK-ENCODING: [0xff,0xcf,0xb0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf b0 25 <unknown>
+// CHECK-UNKNOWN: 25b0cfff <unknown>
 
 mul z31.d, z31.d, #-128
 // CHECK-INST: mul	z31.d, z31.d, #-128
 // CHECK-ENCODING: [0x1f,0xd0,0xf0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f d0 f0 25 <unknown>
+// CHECK-UNKNOWN: 25f0d01f <unknown>
 
 mul z31.d, z31.d, #127
 // CHECK-INST: mul	z31.d, z31.d, #127
 // CHECK-ENCODING: [0xff,0xcf,0xf0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf f0 25 <unknown>
+// CHECK-UNKNOWN: 25f0cfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -89,34 +89,34 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 mul z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: mul	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d0 04 <unknown>
+// CHECK-UNKNOWN: 04d01fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 mul z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: mul	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d0 04 <unknown>
+// CHECK-UNKNOWN: 04d01fe0 <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 mul z31.d, z31.d, #127
 // CHECK-INST: mul	z31.d, z31.d, #127
 // CHECK-ENCODING: [0xff,0xcf,0xf0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf f0 25 <unknown>
+// CHECK-UNKNOWN: 25f0cfff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/nand.s b/llvm/test/MC/AArch64/SVE/nand.s
index b6edfa7c05354..54a77f7c81a3c 100644
--- a/llvm/test/MC/AArch64/SVE/nand.s
+++ b/llvm/test/MC/AArch64/SVE/nand.s
@@ -13,10 +13,10 @@ nand    p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: nand    p0.b, p0/z, p0.b, p0.b
 // CHECK-ENCODING: [0x10,0x42,0x80,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 42 80 25 <unknown>
+// CHECK-UNKNOWN: 25804210 <unknown>
 
 nand    p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: nand    p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xff,0x7f,0x8f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 7f 8f 25 <unknown>
+// CHECK-UNKNOWN: 258f7fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/nands.s b/llvm/test/MC/AArch64/SVE/nands.s
index 69e896f1401b4..2c233e3059538 100644
--- a/llvm/test/MC/AArch64/SVE/nands.s
+++ b/llvm/test/MC/AArch64/SVE/nands.s
@@ -13,10 +13,10 @@ nands   p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: nands   p0.b, p0/z, p0.b, p0.b
 // CHECK-ENCODING: [0x10,0x42,0xc0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 42 c0 25 <unknown>
+// CHECK-UNKNOWN: 25c04210 <unknown>
 
 nands   p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: nands   p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xff,0x7f,0xcf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 7f cf 25 <unknown>
+// CHECK-UNKNOWN: 25cf7fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/neg.s b/llvm/test/MC/AArch64/SVE/neg.s
index f848f76e805d0..8190004a0db5d 100644
--- a/llvm/test/MC/AArch64/SVE/neg.s
+++ b/llvm/test/MC/AArch64/SVE/neg.s
@@ -13,49 +13,49 @@ neg     z0.b, p0/m, z0.b
 // CHECK-INST: neg     z0.b, p0/m, z0.b
 // CHECK-ENCODING: [0x00,0xa0,0x17,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 17 04 <unknown>
+// CHECK-UNKNOWN: 0417a000 <unknown>
 
 neg     z0.h, p0/m, z0.h
 // CHECK-INST: neg     z0.h, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x57,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 57 04 <unknown>
+// CHECK-UNKNOWN: 0457a000 <unknown>
 
 neg     z0.s, p0/m, z0.s
 // CHECK-INST: neg     z0.s, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x97,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 97 04 <unknown>
+// CHECK-UNKNOWN: 0497a000 <unknown>
 
 neg     z0.d, p0/m, z0.d
 // CHECK-INST: neg     z0.d, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd7,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d7 04 <unknown>
+// CHECK-UNKNOWN: 04d7a000 <unknown>
 
 neg     z31.b, p7/m, z31.b
 // CHECK-INST: neg     z31.b, p7/m, z31.b
 // CHECK-ENCODING: [0xff,0xbf,0x17,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 17 04 <unknown>
+// CHECK-UNKNOWN: 0417bfff <unknown>
 
 neg     z31.h, p7/m, z31.h
 // CHECK-INST: neg     z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x57,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 57 04 <unknown>
+// CHECK-UNKNOWN: 0457bfff <unknown>
 
 neg     z31.s, p7/m, z31.s
 // CHECK-INST: neg     z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x97,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 97 04 <unknown>
+// CHECK-UNKNOWN: 0497bfff <unknown>
 
 neg     z31.d, p7/m, z31.d
 // CHECK-INST: neg     z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xd7,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf d7 04 <unknown>
+// CHECK-UNKNOWN: 04d7bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -65,22 +65,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 neg     z4.d, p7/m, z31.d
 // CHECK-INST: neg	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd7,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d7 04 <unknown>
+// CHECK-UNKNOWN: 04d7bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 neg     z4.d, p7/m, z31.d
 // CHECK-INST: neg	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd7,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d7 04 <unknown>
+// CHECK-UNKNOWN: 04d7bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/nor.s b/llvm/test/MC/AArch64/SVE/nor.s
index d628aebdc45b1..f17dc2b5a6030 100644
--- a/llvm/test/MC/AArch64/SVE/nor.s
+++ b/llvm/test/MC/AArch64/SVE/nor.s
@@ -13,10 +13,10 @@ nor     p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: nor     p0.b, p0/z, p0.b, p0.b
 // CHECK-ENCODING: [0x00,0x42,0x80,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 42 80 25 <unknown>
+// CHECK-UNKNOWN: 25804200 <unknown>
 
 nor     p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: nor     p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x7f,0x8f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7f 8f 25 <unknown>
+// CHECK-UNKNOWN: 258f7fef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/nors.s b/llvm/test/MC/AArch64/SVE/nors.s
index ac71afbd704ec..8919cc09b5b39 100644
--- a/llvm/test/MC/AArch64/SVE/nors.s
+++ b/llvm/test/MC/AArch64/SVE/nors.s
@@ -13,10 +13,10 @@ nors    p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: nors    p0.b, p0/z, p0.b, p0.b
 // CHECK-ENCODING: [0x00,0x42,0xc0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 42 c0 25 <unknown>
+// CHECK-UNKNOWN: 25c04200 <unknown>
 
 nors    p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: nors    p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x7f,0xcf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7f cf 25 <unknown>
+// CHECK-UNKNOWN: 25cf7fef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/not.s b/llvm/test/MC/AArch64/SVE/not.s
index 4b9a5c19241b8..699d7410c74c6 100644
--- a/llvm/test/MC/AArch64/SVE/not.s
+++ b/llvm/test/MC/AArch64/SVE/not.s
@@ -13,37 +13,37 @@ not     z31.b, p7/m, z31.b
 // CHECK-INST: not	z31.b, p7/m, z31.b
 // CHECK-ENCODING: [0xff,0xbf,0x1e,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 1e 04 <unknown>
+// CHECK-UNKNOWN: 041ebfff <unknown>
 
 not     z31.h, p7/m, z31.h
 // CHECK-INST: not	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x5e,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 5e 04 <unknown>
+// CHECK-UNKNOWN: 045ebfff <unknown>
 
 not     z31.s, p7/m, z31.s
 // CHECK-INST: not	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x9e,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 9e 04 <unknown>
+// CHECK-UNKNOWN: 049ebfff <unknown>
 
 not     z31.d, p7/m, z31.d
 // CHECK-INST: not	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xde,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf de 04 <unknown>
+// CHECK-UNKNOWN: 04debfff <unknown>
 
 not     p0.b, p0/z, p0.b
 // CHECK-INST: not     p0.b, p0/z, p0.b
 // CHECK-ENCODING: [0x00,0x42,0x00,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 42 00 25 <unknown>
+// CHECK-UNKNOWN: 25004200 <unknown>
 
 not     p15.b, p15/z, p15.b
 // CHECK-INST: not     p15.b, p15/z, p15.b
 // CHECK-ENCODING: [0xef,0x7f,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7f 0f 25 <unknown>
+// CHECK-UNKNOWN: 250f7fef <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -53,22 +53,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 not     z4.d, p7/m, z31.d
 // CHECK-INST: not	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xde,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf de 04 <unknown>
+// CHECK-UNKNOWN: 04debfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 not     z4.d, p7/m, z31.d
 // CHECK-INST: not	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xde,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf de 04 <unknown>
+// CHECK-UNKNOWN: 04debfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/nots.s b/llvm/test/MC/AArch64/SVE/nots.s
index 5ba7359a5f4c0..072de20a8cc9c 100644
--- a/llvm/test/MC/AArch64/SVE/nots.s
+++ b/llvm/test/MC/AArch64/SVE/nots.s
@@ -13,10 +13,10 @@ nots    p0.b, p0/z, p0.b
 // CHECK-INST: nots    p0.b, p0/z, p0.b
 // CHECK-ENCODING: [0x00,0x42,0x40,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 42 40 25 <unknown>
+// CHECK-UNKNOWN: 25404200 <unknown>
 
 nots    p15.b, p15/z, p15.b
 // CHECK-INST: nots    p15.b, p15/z, p15.b
 // CHECK-ENCODING: [0xef,0x7f,0x4f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7f 4f 25 <unknown>
+// CHECK-UNKNOWN: 254f7fef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/orn.s b/llvm/test/MC/AArch64/SVE/orn.s
index be7b48e7d83f3..f2e42091133c6 100644
--- a/llvm/test/MC/AArch64/SVE/orn.s
+++ b/llvm/test/MC/AArch64/SVE/orn.s
@@ -13,61 +13,61 @@ orn     z5.b, z5.b, #0xf9
 // CHECK-INST: orr     z5.b, z5.b, #0x6
 // CHECK-ENCODING: [0x25,0x3e,0x00,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 3e 00 05 <unknown>
+// CHECK-UNKNOWN: 05003e25 <unknown>
 
 orn     z23.h, z23.h, #0xfff9
 // CHECK-INST: orr     z23.h, z23.h, #0x6
 // CHECK-ENCODING: [0x37,0x7c,0x00,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 37 7c 00 05 <unknown>
+// CHECK-UNKNOWN: 05007c37 <unknown>
 
 orn     z0.s, z0.s, #0xfffffff9
 // CHECK-INST: orr     z0.s, z0.s, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x00,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 00 05 <unknown>
+// CHECK-UNKNOWN: 0500f820 <unknown>
 
 orn     z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-INST: orr     z0.d, z0.d, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x03,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 03 05 <unknown>
+// CHECK-UNKNOWN: 0503f820 <unknown>
 
 orn     z5.b, z5.b, #0x6
 // CHECK-INST: orr     z5.b, z5.b, #0xf9
 // CHECK-ENCODING: [0xa5,0x2e,0x00,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a5 2e 00 05 <unknown>
+// CHECK-UNKNOWN: 05002ea5 <unknown>
 
 orn     z23.h, z23.h, #0x6
 // CHECK-INST: orr     z23.h, z23.h, #0xfff9
 // CHECK-ENCODING: [0xb7,0x6d,0x00,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 6d 00 05 <unknown>
+// CHECK-UNKNOWN: 05006db7 <unknown>
 
 orn     z0.s, z0.s, #0x6
 // CHECK-INST: orr     z0.s, z0.s, #0xfffffff9
 // CHECK-ENCODING: [0xa0,0xeb,0x00,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 eb 00 05 <unknown>
+// CHECK-UNKNOWN: 0500eba0 <unknown>
 
 orn     z0.d, z0.d, #0x6
 // CHECK-INST: orr     z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-ENCODING: [0xa0,0xef,0x03,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ef 03 05 <unknown>
+// CHECK-UNKNOWN: 0503efa0 <unknown>
 
 orn     p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: orn     p0.b, p0/z, p0.b, p0.b
 // CHECK-ENCODING: [0x10,0x40,0x80,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 40 80 25 <unknown>
+// CHECK-UNKNOWN: 25804010 <unknown>
 
 orn     p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: orn     p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xff,0x7d,0x8f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 7d 8f 25 <unknown>
+// CHECK-UNKNOWN: 258f7dff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -77,10 +77,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 orn     z0.d, z0.d, #0x6
 // CHECK-INST: orr	z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-ENCODING: [0xa0,0xef,0x03,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ef 03 05 <unknown>
+// CHECK-UNKNOWN: 0503efa0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/orns.s b/llvm/test/MC/AArch64/SVE/orns.s
index 4f7f2f2bc28c0..036da79fc0a39 100644
--- a/llvm/test/MC/AArch64/SVE/orns.s
+++ b/llvm/test/MC/AArch64/SVE/orns.s
@@ -13,10 +13,10 @@ orns    p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: orns    p0.b, p0/z, p0.b, p0.b
 // CHECK-ENCODING: [0x10,0x40,0xc0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 40 c0 25 <unknown>
+// CHECK-UNKNOWN: 25c04010 <unknown>
 
 orns    p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: orns    p15.b, p15/z, p15.b, p15.b
 // CHECK-ENCODING: [0xff,0x7d,0xcf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 7d cf 25 <unknown>
+// CHECK-UNKNOWN: 25cf7dff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/orr.s b/llvm/test/MC/AArch64/SVE/orr.s
index 8992573f4c0dc..3ccb96e29e7ca 100644
--- a/llvm/test/MC/AArch64/SVE/orr.s
+++ b/llvm/test/MC/AArch64/SVE/orr.s
@@ -15,103 +15,103 @@ orr     z5.b, z5.b, #0xf9
 // CHECK-INST: orr     z5.b, z5.b, #0xf9
 // CHECK-ENCODING: [0xa5,0x2e,0x00,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a5 2e 00 05 <unknown>
+// CHECK-UNKNOWN: 05002ea5 <unknown>
 
 orr     z23.h, z23.h, #0xfff9
 // CHECK-INST: orr     z23.h, z23.h, #0xfff9
 // CHECK-ENCODING: [0xb7,0x6d,0x00,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 6d 00 05 <unknown>
+// CHECK-UNKNOWN: 05006db7 <unknown>
 
 orr     z0.s, z0.s, #0xfffffff9
 // CHECK-INST: orr     z0.s, z0.s, #0xfffffff9
 // CHECK-ENCODING: [0xa0,0xeb,0x00,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 eb 00 05 <unknown>
+// CHECK-UNKNOWN: 0500eba0 <unknown>
 
 orr     z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-INST: orr     z0.d, z0.d, #0xfffffffffffffff9
 // CHECK-ENCODING: [0xa0,0xef,0x03,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 ef 03 05 <unknown>
+// CHECK-UNKNOWN: 0503efa0 <unknown>
 
 orr     z5.b, z5.b, #0x6
 // CHECK-INST: orr     z5.b, z5.b, #0x6
 // CHECK-ENCODING: [0x25,0x3e,0x00,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 3e 00 05 <unknown>
+// CHECK-UNKNOWN: 05003e25 <unknown>
 
 orr     z23.h, z23.h, #0x6
 // CHECK-INST: orr     z23.h, z23.h, #0x6
 // CHECK-ENCODING: [0x37,0x7c,0x00,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 37 7c 00 05 <unknown>
+// CHECK-UNKNOWN: 05007c37 <unknown>
 
 orr     z0.s, z0.s, #0x6
 // CHECK-INST: orr     z0.s, z0.s, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x00,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 00 05 <unknown>
+// CHECK-UNKNOWN: 0500f820 <unknown>
 
 orr     z0.d, z0.d, #0x6
 // CHECK-INST: orr     z0.d, z0.d, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x03,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 03 05 <unknown>
+// CHECK-UNKNOWN: 0503f820 <unknown>
 
 orr     z0.d, z0.d, z0.d    // should use mov-alias
 // CHECK-INST: mov     z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+// CHECK-UNKNOWN: 04603000 <unknown>
 
 orr     z23.d, z13.d, z8.d  // should not use mov-alias
 // CHECK-INST: orr     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+// CHECK-UNKNOWN: 046831b7 <unknown>
 
 orr     z31.b, p7/m, z31.b, z31.b
 // CHECK-INST: orr     z31.b, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x1f,0x18,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 18 04 <unknown>
+// CHECK-UNKNOWN: 04181fff <unknown>
 
 orr     z31.h, p7/m, z31.h, z31.h
 // CHECK-INST: orr     z31.h, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x1f,0x58,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 58 04 <unknown>
+// CHECK-UNKNOWN: 04581fff <unknown>
 
 orr     z31.s, p7/m, z31.s, z31.s
 // CHECK-INST: orr     z31.s, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1f,0x98,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 98 04 <unknown>
+// CHECK-UNKNOWN: 04981fff <unknown>
 
 orr     z31.d, p7/m, z31.d, z31.d
 // CHECK-INST: orr     z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xd8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f d8 04 <unknown>
+// CHECK-UNKNOWN: 04d81fff <unknown>
 
 orr     p0.b, p0/z, p0.b, p1.b
 // CHECK-INST: orr     p0.b, p0/z, p0.b, p1.b
 // CHECK-ENCODING: [0x00,0x40,0x81,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 81 25 <unknown>
+// CHECK-UNKNOWN: 25814000 <unknown>
 
 orr     p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: mov     p0.b, p0.b
 // CHECK-ENCODING: [0x00,0x40,0x80,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 80 25 <unknown>
+// CHECK-UNKNOWN: 25804000 <unknown>
 
 orr     p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: mov     p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x7d,0x8f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7d 8f 25 <unknown>
+// CHECK-UNKNOWN: 258f7def <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -121,37 +121,37 @@ orr     z0.s, z0.s, z0.s
 // CHECK-INST: mov     z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+// CHECK-UNKNOWN: 04603000 <unknown>
 
 orr     z0.h, z0.h, z0.h
 // CHECK-INST: mov     z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+// CHECK-UNKNOWN: 04603000 <unknown>
 
 orr     z0.b, z0.b, z0.b
 // CHECK-INST: mov     z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x30,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+// CHECK-UNKNOWN: 04603000 <unknown>
 
 orr     z23.s, z13.s, z8.s  // should not use mov-alias
 // CHECK-INST: orr     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+// CHECK-UNKNOWN: 046831b7 <unknown>
 
 orr     z23.h, z13.h, z8.h  // should not use mov-alias
 // CHECK-INST: orr     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+// CHECK-UNKNOWN: 046831b7 <unknown>
 
 orr     z23.b, z13.b, z8.b  // should not use mov-alias
 // CHECK-INST: orr     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+// CHECK-UNKNOWN: 046831b7 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -161,34 +161,34 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 orr     z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: orr	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xd8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f d8 04 <unknown>
+// CHECK-UNKNOWN: 04d81fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 orr     z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: orr	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xd8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f d8 04 <unknown>
+// CHECK-UNKNOWN: 04d81fe4 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 orr     z0.d, z0.d, #0x6
 // CHECK-INST: orr	z0.d, z0.d, #0x6
 // CHECK-ENCODING: [0x20,0xf8,0x03,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 03 05 <unknown>
+// CHECK-UNKNOWN: 0503f820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/orrs.s b/llvm/test/MC/AArch64/SVE/orrs.s
index 5b2d11cb77d32..a89636b308cae 100644
--- a/llvm/test/MC/AArch64/SVE/orrs.s
+++ b/llvm/test/MC/AArch64/SVE/orrs.s
@@ -13,16 +13,16 @@ orrs    p0.b, p0/z, p0.b, p1.b
 // CHECK-INST: orrs    p0.b, p0/z, p0.b, p1.b
 // CHECK-ENCODING: [0x00,0x40,0xc1,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 c1 25 <unknown>
+// CHECK-UNKNOWN: 25c14000 <unknown>
 
 orrs    p0.b, p0/z, p0.b, p0.b
 // CHECK-INST: movs    p0.b, p0.b
 // CHECK-ENCODING: [0x00,0x40,0xc0,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 c0 25 <unknown>
+// CHECK-UNKNOWN: 25c04000 <unknown>
 
 orrs    p15.b, p15/z, p15.b, p15.b
 // CHECK-INST: movs    p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x7d,0xcf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 7d cf 25 <unknown>
+// CHECK-UNKNOWN: 25cf7def <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/orv.s b/llvm/test/MC/AArch64/SVE/orv.s
index e37068ab62db6..3d68d5f6acffe 100644
--- a/llvm/test/MC/AArch64/SVE/orv.s
+++ b/llvm/test/MC/AArch64/SVE/orv.s
@@ -13,22 +13,22 @@ orv b0, p7, z31.b
 // CHECK-INST: orv	b0, p7, z31.b
 // CHECK-ENCODING: [0xe0,0x3f,0x18,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 18 04 <unknown>
+// CHECK-UNKNOWN: 04183fe0 <unknown>
 
 orv h0, p7, z31.h
 // CHECK-INST: orv	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x58,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 58 04 <unknown>
+// CHECK-UNKNOWN: 04583fe0 <unknown>
 
 orv s0, p7, z31.s
 // CHECK-INST: orv	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x98,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 98 04 <unknown>
+// CHECK-UNKNOWN: 04983fe0 <unknown>
 
 orv d0, p7, z31.d
 // CHECK-INST: orv	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xd8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f d8 04 <unknown>
+// CHECK-UNKNOWN: 04d83fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/pfalse.s b/llvm/test/MC/AArch64/SVE/pfalse.s
index d4f1ba5b50567..4124da8ac92a0 100644
--- a/llvm/test/MC/AArch64/SVE/pfalse.s
+++ b/llvm/test/MC/AArch64/SVE/pfalse.s
@@ -13,4 +13,4 @@ pfalse p15.b
 // CHECK-INST: pfalse	p15.b
 // CHECK-ENCODING: [0x0f,0xe4,0x18,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f e4 18 25 <unknown>
+// CHECK-UNKNOWN: 2518e40f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/pfirst.s b/llvm/test/MC/AArch64/SVE/pfirst.s
index 7518b9805d050..9e4561ac56486 100644
--- a/llvm/test/MC/AArch64/SVE/pfirst.s
+++ b/llvm/test/MC/AArch64/SVE/pfirst.s
@@ -13,10 +13,10 @@ pfirst p0.b, p15, p0.b
 // CHECK-INST: pfirst	p0.b, p15, p0.b
 // CHECK-ENCODING: [0xe0,0xc1,0x58,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c1 58 25 <unknown>
+// CHECK-UNKNOWN: 2558c1e0 <unknown>
 
 pfirst p15.b, p15, p15.b
 // CHECK-INST: pfirst	p15.b, p15, p15.b
 // CHECK-ENCODING: [0xef,0xc1,0x58,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef c1 58 25 <unknown>
+// CHECK-UNKNOWN: 2558c1ef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/pnext.s b/llvm/test/MC/AArch64/SVE/pnext.s
index 7fbd2bd93e908..007885f4bf758 100644
--- a/llvm/test/MC/AArch64/SVE/pnext.s
+++ b/llvm/test/MC/AArch64/SVE/pnext.s
@@ -13,28 +13,28 @@ pnext p15.b, p15, p15.b
 // CHECK-INST: pnext	p15.b, p15, p15.b
 // CHECK-ENCODING: [0xef,0xc5,0x19,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef c5 19 25 <unknown>
+// CHECK-UNKNOWN: 2519c5ef <unknown>
 
 pnext p0.b, p15, p0.b
 // CHECK-INST: pnext	p0.b, p15, p0.b
 // CHECK-ENCODING: [0xe0,0xc5,0x19,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c5 19 25 <unknown>
+// CHECK-UNKNOWN: 2519c5e0 <unknown>
 
 pnext p0.h, p15, p0.h
 // CHECK-INST: pnext	p0.h, p15, p0.h
 // CHECK-ENCODING: [0xe0,0xc5,0x59,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c5 59 25 <unknown>
+// CHECK-UNKNOWN: 2559c5e0 <unknown>
 
 pnext p0.s, p15, p0.s
 // CHECK-INST: pnext	p0.s, p15, p0.s
 // CHECK-ENCODING: [0xe0,0xc5,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c5 99 25 <unknown>
+// CHECK-UNKNOWN: 2599c5e0 <unknown>
 
 pnext p0.d, p15, p0.d
 // CHECK-INST: pnext	p0.d, p15, p0.d
 // CHECK-ENCODING: [0xe0,0xc5,0xd9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c5 d9 25 <unknown>
+// CHECK-UNKNOWN: 25d9c5e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/prfb-sve-only.s b/llvm/test/MC/AArch64/SVE/prfb-sve-only.s
index 2dd080a73e97c..51d56e68d7d90 100644
--- a/llvm/test/MC/AArch64/SVE/prfb-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/prfb-sve-only.s
@@ -18,52 +18,52 @@ prfb    pldl1keep, p0, [x0, z0.s, uxtw]
 // CHECK-INST: prfb    pldl1keep, p0, [x0, z0.s, uxtw]
 // CHECK-ENCODING: [0x00,0x00,0x20,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 00 20 84 <unknown>
+// CHECK-UNKNOWN: 84200000 <unknown>
 
 prfb    pldl3strm, p5, [x10, z21.s, uxtw]
 // CHECK-INST: prfb    pldl3strm, p5, [x10, z21.s, uxtw]
 // CHECK-ENCODING: [0x45,0x15,0x35,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 45 15 35 84 <unknown>
+// CHECK-UNKNOWN: 84351545 <unknown>
 
 prfb    pldl1keep, p0, [x0, z0.d, uxtw]
 // CHECK-INST: prfb    pldl1keep, p0, [x0, z0.d, uxtw]
 // CHECK-ENCODING: [0x00,0x00,0x20,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 00 20 c4 <unknown>
+// CHECK-UNKNOWN: c4200000 <unknown>
 
 prfb    pldl3strm, p5, [x10, z21.d, sxtw]
 // CHECK-INST: prfb    pldl3strm, p5, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x45,0x15,0x75,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 45 15 75 c4 <unknown>
+// CHECK-UNKNOWN: c4751545 <unknown>
 
 prfb    pldl1keep, p0, [x0, z0.d]
 // CHECK-INST: prfb    pldl1keep, p0, [x0, z0.d]
 // CHECK-ENCODING: [0x00,0x80,0x60,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 60 c4 <unknown>
+// CHECK-UNKNOWN: c4608000 <unknown>
 
 prfb    #7, p3, [z13.s, #0]
 // CHECK-INST: prfb    #7, p3, [z13.s]
 // CHECK-ENCODING: [0xa7,0xed,0x00,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: a7 ed 00 84 <unknown>
+// CHECK-UNKNOWN: 8400eda7 <unknown>
 
 prfb    #7, p3, [z13.s, #31]
 // CHECK-INST: prfb    #7, p3, [z13.s, #31]
 // CHECK-ENCODING: [0xa7,0xed,0x1f,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: a7 ed 1f 84 <unknown>
+// CHECK-UNKNOWN: 841feda7 <unknown>
 
 prfb    pldl3strm, p5, [z10.d, #0]
 // CHECK-INST: prfb    pldl3strm, p5, [z10.d]
 // CHECK-ENCODING: [0x45,0xf5,0x00,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 45 f5 00 c4 <unknown>
+// CHECK-UNKNOWN: c400f545 <unknown>
 
 prfb    pldl3strm, p5, [z10.d, #31]
 // CHECK-INST: prfb    pldl3strm, p5, [z10.d, #31]
 // CHECK-ENCODING: [0x45,0xf5,0x1f,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 45 f5 1f c4 <unknown>
+// CHECK-UNKNOWN: c41ff545 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/prfb.s b/llvm/test/MC/AArch64/SVE/prfb.s
index bedbe6c2e53d6..eb82d8f643f57 100644
--- a/llvm/test/MC/AArch64/SVE/prfb.s
+++ b/llvm/test/MC/AArch64/SVE/prfb.s
@@ -16,169 +16,169 @@ prfb    #0, p0, [x0]
 // CHECK-INST: prfb	pldl1keep, p0, [x0]
 // CHECK-ENCODING: [0x00,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00000 <unknown>
 
 prfb	pldl1keep, p0, [x0]
 // CHECK-INST: prfb	pldl1keep, p0, [x0]
 // CHECK-ENCODING: [0x00,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00000 <unknown>
 
 prfb    #1, p0, [x0]
 // CHECK-INST: prfb	pldl1strm, p0, [x0]
 // CHECK-ENCODING: [0x01,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00001 <unknown>
 
 prfb	pldl1strm, p0, [x0]
 // CHECK-INST: prfb	pldl1strm, p0, [x0]
 // CHECK-ENCODING: [0x01,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00001 <unknown>
 
 prfb    #2, p0, [x0]
 // CHECK-INST: prfb	pldl2keep, p0, [x0]
 // CHECK-ENCODING: [0x02,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 02 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00002 <unknown>
 
 prfb	pldl2keep, p0, [x0]
 // CHECK-INST: prfb	pldl2keep, p0, [x0]
 // CHECK-ENCODING: [0x02,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 02 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00002 <unknown>
 
 prfb    #3, p0, [x0]
 // CHECK-INST: prfb	pldl2strm, p0, [x0]
 // CHECK-ENCODING: [0x03,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 03 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00003 <unknown>
 
 prfb	pldl2strm, p0, [x0]
 // CHECK-INST: prfb	pldl2strm, p0, [x0]
 // CHECK-ENCODING: [0x03,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 03 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00003 <unknown>
 
 prfb    #4, p0, [x0]
 // CHECK-INST: prfb	pldl3keep, p0, [x0]
 // CHECK-ENCODING: [0x04,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 04 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00004 <unknown>
 
 prfb	pldl3keep, p0, [x0]
 // CHECK-INST: prfb	pldl3keep, p0, [x0]
 // CHECK-ENCODING: [0x04,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 04 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00004 <unknown>
 
 prfb    #5, p0, [x0]
 // CHECK-INST: prfb	pldl3strm, p0, [x0]
 // CHECK-ENCODING: [0x05,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00005 <unknown>
 
 prfb	pldl3strm, p0, [x0]
 // CHECK-INST: prfb	pldl3strm, p0, [x0]
 // CHECK-ENCODING: [0x05,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00005 <unknown>
 
 prfb    #6, p0, [x0]
 // CHECK-INST: prfb	#6, p0, [x0]
 // CHECK-ENCODING: [0x06,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 06 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00006 <unknown>
 
 prfb    #7, p0, [x0]
 // CHECK-INST: prfb	#7, p0, [x0]
 // CHECK-ENCODING: [0x07,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 07 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00007 <unknown>
 
 prfb    #8, p0, [x0]
 // CHECK-INST: prfb	pstl1keep, p0, [x0]
 // CHECK-ENCODING: [0x08,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 08 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00008 <unknown>
 
 prfb	pstl1keep, p0, [x0]
 // CHECK-INST: prfb	pstl1keep, p0, [x0]
 // CHECK-ENCODING: [0x08,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 08 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00008 <unknown>
 
 prfb    #9, p0, [x0]
 // CHECK-INST: prfb	pstl1strm, p0, [x0]
 // CHECK-ENCODING: [0x09,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 09 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00009 <unknown>
 
 prfb	pstl1strm, p0, [x0]
 // CHECK-INST: prfb	pstl1strm, p0, [x0]
 // CHECK-ENCODING: [0x09,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 09 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c00009 <unknown>
 
 prfb    #10, p0, [x0]
 // CHECK-INST: prfb	pstl2keep, p0, [x0]
 // CHECK-ENCODING: [0x0a,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0a 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0000a <unknown>
 
 prfb	pstl2keep, p0, [x0]
 // CHECK-INST: prfb	pstl2keep, p0, [x0]
 // CHECK-ENCODING: [0x0a,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0a 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0000a <unknown>
 
 prfb    #11, p0, [x0]
 // CHECK-INST: prfb	pstl2strm, p0, [x0]
 // CHECK-ENCODING: [0x0b,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0b 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0000b <unknown>
 
 prfb	pstl2strm, p0, [x0]
 // CHECK-INST: prfb	pstl2strm, p0, [x0]
 // CHECK-ENCODING: [0x0b,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0b 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0000b <unknown>
 
 prfb    #12, p0, [x0]
 // CHECK-INST: prfb	pstl3keep, p0, [x0]
 // CHECK-ENCODING: [0x0c,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0c 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0000c <unknown>
 
 prfb	pstl3keep, p0, [x0]
 // CHECK-INST: prfb	pstl3keep, p0, [x0]
 // CHECK-ENCODING: [0x0c,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0c 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0000c <unknown>
 
 prfb    #13, p0, [x0]
 // CHECK-INST: prfb	pstl3strm, p0, [x0]
 // CHECK-ENCODING: [0x0d,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0d 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0000d <unknown>
 
 prfb	pstl3strm, p0, [x0]
 // CHECK-INST: prfb	pstl3strm, p0, [x0]
 // CHECK-ENCODING: [0x0d,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0d 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0000d <unknown>
 
 prfb    #14, p0, [x0]
 // CHECK-INST: prfb	#14, p0, [x0]
 // CHECK-ENCODING: [0x0e,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0e 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0000e <unknown>
 
 prfb    #15, p0, [x0]
 // CHECK-INST: prfb	#15, p0, [x0]
 // CHECK-ENCODING: [0x0f,0x00,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 00 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0000f <unknown>
 
 // --------------------------------------------------------------------------//
 // Test addressing modes
@@ -187,10 +187,10 @@ prfb    #1, p0, [x0, #-32, mul vl]
 // CHECK-INST: prfb pldl1strm, p0, [x0, #-32, mul vl]
 // CHECK-ENCODING: [0x01,0x00,0xe0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 00 e0 85 <unknown>
+// CHECK-UNKNOWN: 85e00001 <unknown>
 
 prfb    #1, p0, [x0, #31, mul vl]
 // CHECK-INST: prfb pldl1strm, p0, [x0, #31, mul vl]
 // CHECK-ENCODING: [0x01,0x00,0xdf,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 00 df 85 <unknown>
+// CHECK-UNKNOWN: 85df0001 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/prfd-sve-only.s b/llvm/test/MC/AArch64/SVE/prfd-sve-only.s
index 31d1e388d8447..0db549754666a 100644
--- a/llvm/test/MC/AArch64/SVE/prfd-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/prfd-sve-only.s
@@ -18,52 +18,52 @@ prfd    pldl1keep, p0, [x0, z0.s, uxtw #3]
 // CHECK-INST: prfd    pldl1keep, p0, [x0, z0.s, uxtw #3]
 // CHECK-ENCODING: [0x00,0x60,0x20,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 20 84 <unknown>
+// CHECK-UNKNOWN: 84206000 <unknown>
 
 prfd    pldl1keep, p0, [x0, z0.s, sxtw #3]
 // CHECK-INST: prfd    pldl1keep, p0, [x0, z0.s, sxtw #3]
 // CHECK-ENCODING: [0x00,0x60,0x60,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 60 84 <unknown>
+// CHECK-UNKNOWN: 84606000 <unknown>
 
 prfd    pldl1keep, p0, [x0, z0.d, uxtw #3]
 // CHECK-INST: prfd    pldl1keep, p0, [x0, z0.d, uxtw #3]
 // CHECK-ENCODING: [0x00,0x60,0x20,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 20 c4 <unknown>
+// CHECK-UNKNOWN: c4206000 <unknown>
 
 prfd    pldl1keep, p0, [x0, z0.d, sxtw #3]
 // CHECK-INST: prfd    pldl1keep, p0, [x0, z0.d, sxtw #3]
 // CHECK-ENCODING: [0x00,0x60,0x60,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 60 60 c4 <unknown>
+// CHECK-UNKNOWN: c4606000 <unknown>
 
 prfd    pldl1keep, p0, [x0, z0.d, lsl #3]
 // CHECK-INST: prfd    pldl1keep, p0, [x0, z0.d, lsl #3]
 // CHECK-ENCODING: [0x00,0xe0,0x60,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 e0 60 c4 <unknown>
+// CHECK-UNKNOWN: c460e000 <unknown>
 
 prfd    #15, p7, [z31.s, #0]
 // CHECK-INST: prfd    #15, p7, [z31.s]
 // CHECK-ENCODING: [0xef,0xff,0x80,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef ff 80 85 <unknown>
+// CHECK-UNKNOWN: 8580ffef <unknown>
 
 prfd    #15, p7, [z31.s, #248]
 // CHECK-INST: prfd    #15, p7, [z31.s, #248]
 // CHECK-ENCODING: [0xef,0xff,0x9f,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef ff 9f 85 <unknown>
+// CHECK-UNKNOWN: 859fffef <unknown>
 
 prfd    #15, p7, [z31.d, #0]
 // CHECK-INST: prfd    #15, p7, [z31.d]
 // CHECK-ENCODING: [0xef,0xff,0x80,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef ff 80 c5 <unknown>
+// CHECK-UNKNOWN: c580ffef <unknown>
 
 prfd    #15, p7, [z31.d, #248]
 // CHECK-INST: prfd    #15, p7, [z31.d, #248]
 // CHECK-ENCODING: [0xef,0xff,0x9f,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef ff 9f c5 <unknown>
+// CHECK-UNKNOWN: c59fffef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/prfd.s b/llvm/test/MC/AArch64/SVE/prfd.s
index 2ee5e23b81c3d..07a2e86a798e2 100644
--- a/llvm/test/MC/AArch64/SVE/prfd.s
+++ b/llvm/test/MC/AArch64/SVE/prfd.s
@@ -16,169 +16,169 @@ prfd    #0, p0, [x0]
 // CHECK-INST: prfd	pldl1keep, p0, [x0]
 // CHECK-ENCODING: [0x00,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06000 <unknown>
 
 prfd	pldl1keep, p0, [x0]
 // CHECK-INST: prfd	pldl1keep, p0, [x0]
 // CHECK-ENCODING: [0x00,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06000 <unknown>
 
 prfd    #1, p0, [x0]
 // CHECK-INST: prfd	pldl1strm, p0, [x0]
 // CHECK-ENCODING: [0x01,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06001 <unknown>
 
 prfd	pldl1strm, p0, [x0]
 // CHECK-INST: prfd	pldl1strm, p0, [x0]
 // CHECK-ENCODING: [0x01,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06001 <unknown>
 
 prfd    #2, p0, [x0]
 // CHECK-INST: prfd	pldl2keep, p0, [x0]
 // CHECK-ENCODING: [0x02,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 02 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06002 <unknown>
 
 prfd	pldl2keep, p0, [x0]
 // CHECK-INST: prfd	pldl2keep, p0, [x0]
 // CHECK-ENCODING: [0x02,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 02 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06002 <unknown>
 
 prfd    #3, p0, [x0]
 // CHECK-INST: prfd	pldl2strm, p0, [x0]
 // CHECK-ENCODING: [0x03,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 03 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06003 <unknown>
 
 prfd	pldl2strm, p0, [x0]
 // CHECK-INST: prfd	pldl2strm, p0, [x0]
 // CHECK-ENCODING: [0x03,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 03 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06003 <unknown>
 
 prfd    #4, p0, [x0]
 // CHECK-INST: prfd	pldl3keep, p0, [x0]
 // CHECK-ENCODING: [0x04,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 04 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06004 <unknown>
 
 prfd	pldl3keep, p0, [x0]
 // CHECK-INST: prfd	pldl3keep, p0, [x0]
 // CHECK-ENCODING: [0x04,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 04 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06004 <unknown>
 
 prfd    #5, p0, [x0]
 // CHECK-INST: prfd	pldl3strm, p0, [x0]
 // CHECK-ENCODING: [0x05,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06005 <unknown>
 
 prfd	pldl3strm, p0, [x0]
 // CHECK-INST: prfd	pldl3strm, p0, [x0]
 // CHECK-ENCODING: [0x05,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06005 <unknown>
 
 prfd    #6, p0, [x0]
 // CHECK-INST: prfd	#6, p0, [x0]
 // CHECK-ENCODING: [0x06,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 06 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06006 <unknown>
 
 prfd    #7, p0, [x0]
 // CHECK-INST: prfd	#7, p0, [x0]
 // CHECK-ENCODING: [0x07,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 07 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06007 <unknown>
 
 prfd    #8, p0, [x0]
 // CHECK-INST: prfd	pstl1keep, p0, [x0]
 // CHECK-ENCODING: [0x08,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 08 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06008 <unknown>
 
 prfd	pstl1keep, p0, [x0]
 // CHECK-INST: prfd	pstl1keep, p0, [x0]
 // CHECK-ENCODING: [0x08,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 08 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06008 <unknown>
 
 prfd    #9, p0, [x0]
 // CHECK-INST: prfd	pstl1strm, p0, [x0]
 // CHECK-ENCODING: [0x09,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 09 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06009 <unknown>
 
 prfd	pstl1strm, p0, [x0]
 // CHECK-INST: prfd	pstl1strm, p0, [x0]
 // CHECK-ENCODING: [0x09,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 09 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c06009 <unknown>
 
 prfd    #10, p0, [x0]
 // CHECK-INST: prfd	pstl2keep, p0, [x0]
 // CHECK-ENCODING: [0x0a,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0a 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0600a <unknown>
 
 prfd	pstl2keep, p0, [x0]
 // CHECK-INST: prfd	pstl2keep, p0, [x0]
 // CHECK-ENCODING: [0x0a,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0a 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0600a <unknown>
 
 prfd    #11, p0, [x0]
 // CHECK-INST: prfd	pstl2strm, p0, [x0]
 // CHECK-ENCODING: [0x0b,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0b 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0600b <unknown>
 
 prfd	pstl2strm, p0, [x0]
 // CHECK-INST: prfd	pstl2strm, p0, [x0]
 // CHECK-ENCODING: [0x0b,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0b 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0600b <unknown>
 
 prfd    #12, p0, [x0]
 // CHECK-INST: prfd	pstl3keep, p0, [x0]
 // CHECK-ENCODING: [0x0c,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0c 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0600c <unknown>
 
 prfd	pstl3keep, p0, [x0]
 // CHECK-INST: prfd	pstl3keep, p0, [x0]
 // CHECK-ENCODING: [0x0c,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0c 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0600c <unknown>
 
 prfd    #13, p0, [x0]
 // CHECK-INST: prfd	pstl3strm, p0, [x0]
 // CHECK-ENCODING: [0x0d,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0d 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0600d <unknown>
 
 prfd	pstl3strm, p0, [x0]
 // CHECK-INST: prfd	pstl3strm, p0, [x0]
 // CHECK-ENCODING: [0x0d,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0d 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0600d <unknown>
 
 prfd    #14, p0, [x0]
 // CHECK-INST: prfd	#14, p0, [x0]
 // CHECK-ENCODING: [0x0e,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0e 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0600e <unknown>
 
 prfd    #15, p0, [x0]
 // CHECK-INST: prfd	#15, p0, [x0]
 // CHECK-ENCODING: [0x0f,0x60,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 60 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0600f <unknown>
 
 // --------------------------------------------------------------------------//
 // Test addressing modes
@@ -187,10 +187,10 @@ prfd    pldl1strm, p0, [x0, #-32, mul vl]
 // CHECK-INST: prfd     pldl1strm, p0, [x0, #-32, mul vl]
 // CHECK-ENCODING: [0x01,0x60,0xe0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 60 e0 85
+// CHECK-UNKNOWN: 85e06001
 
 prfd    pldl1strm, p0, [x0, #31, mul vl]
 // CHECK-INST: prfd     pldl1strm, p0, [x0, #31, mul vl]
 // CHECK-ENCODING: [0x01,0x60,0xdf,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 60 df 85
+// CHECK-UNKNOWN: 85df6001

diff  --git a/llvm/test/MC/AArch64/SVE/prfh-sve-only.s b/llvm/test/MC/AArch64/SVE/prfh-sve-only.s
index a0fc22ae1d216..90543ba024d9e 100644
--- a/llvm/test/MC/AArch64/SVE/prfh-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/prfh-sve-only.s
@@ -18,52 +18,52 @@ prfh    pldl3strm, p5, [x10, z21.s, uxtw #1]
 // CHECK-INST: prfh    pldl3strm, p5, [x10, z21.s, uxtw #1]
 // CHECK-ENCODING: [0x45,0x35,0x35,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 45 35 35 84 <unknown>
+// CHECK-UNKNOWN: 84353545 <unknown>
 
 prfh    pldl3strm, p5, [x10, z21.s, sxtw #1]
 // CHECK-INST: prfh    pldl3strm, p5, [x10, z21.s, sxtw #1]
 // CHECK-ENCODING: [0x45,0x35,0x75,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 45 35 75 84 <unknown>
+// CHECK-UNKNOWN: 84753545 <unknown>
 
 prfh    pldl3strm, p5, [x10, z21.d, uxtw #1]
 // CHECK-INST: prfh    pldl3strm, p5, [x10, z21.d, uxtw #1]
 // CHECK-ENCODING: [0x45,0x35,0x35,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 45 35 35 c4 <unknown>
+// CHECK-UNKNOWN: c4353545 <unknown>
 
 prfh    pldl3strm, p5, [x10, z21.d, sxtw #1]
 // CHECK-INST: prfh    pldl3strm, p5, [x10, z21.d, sxtw #1]
 // CHECK-ENCODING: [0x45,0x35,0x75,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 45 35 75 c4 <unknown>
+// CHECK-UNKNOWN: c4753545 <unknown>
 
 prfh    pldl1keep, p0, [x0, z0.d, lsl #1]
 // CHECK-INST: prfh    pldl1keep, p0, [x0, z0.d, lsl #1]
 // CHECK-ENCODING: [0x00,0xa0,0x60,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 60 c4 <unknown>
+// CHECK-UNKNOWN: c460a000 <unknown>
 
 prfh    #15, p7, [z31.s, #0]
 // CHECK-INST: prfh    #15, p7, [z31.s]
 // CHECK-ENCODING: [0xef,0xff,0x80,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef ff 80 84 <unknown>
+// CHECK-UNKNOWN: 8480ffef <unknown>
 
 prfh    #15, p7, [z31.s, #62]
 // CHECK-INST: prfh    #15, p7, [z31.s, #62]
 // CHECK-ENCODING: [0xef,0xff,0x9f,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef ff 9f 84 <unknown>
+// CHECK-UNKNOWN: 849fffef <unknown>
 
 prfh    #15, p7, [z31.d, #0]
 // CHECK-INST: prfh    #15, p7, [z31.d]
 // CHECK-ENCODING: [0xef,0xff,0x80,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef ff 80 c4 <unknown>
+// CHECK-UNKNOWN: c480ffef <unknown>
 
 prfh    #15, p7, [z31.d, #62]
 // CHECK-INST: prfh    #15, p7, [z31.d, #62]
 // CHECK-ENCODING: [0xef,0xff,0x9f,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef ff 9f c4 <unknown>
+// CHECK-UNKNOWN: c49fffef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/prfh.s b/llvm/test/MC/AArch64/SVE/prfh.s
index ea9f51def969e..825f1ca3ea091 100644
--- a/llvm/test/MC/AArch64/SVE/prfh.s
+++ b/llvm/test/MC/AArch64/SVE/prfh.s
@@ -16,169 +16,169 @@ prfh    #0, p0, [x0]
 // CHECK-INST: prfh	pldl1keep, p0, [x0]
 // CHECK-ENCODING: [0x00,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02000 <unknown>
 
 prfh	pldl1keep, p0, [x0]
 // CHECK-INST: prfh	pldl1keep, p0, [x0]
 // CHECK-ENCODING: [0x00,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02000 <unknown>
 
 prfh    #1, p0, [x0]
 // CHECK-INST: prfh	pldl1strm, p0, [x0]
 // CHECK-ENCODING: [0x01,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02001 <unknown>
 
 prfh	pldl1strm, p0, [x0]
 // CHECK-INST: prfh	pldl1strm, p0, [x0]
 // CHECK-ENCODING: [0x01,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02001 <unknown>
 
 prfh    #2, p0, [x0]
 // CHECK-INST: prfh	pldl2keep, p0, [x0]
 // CHECK-ENCODING: [0x02,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 02 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02002 <unknown>
 
 prfh	pldl2keep, p0, [x0]
 // CHECK-INST: prfh	pldl2keep, p0, [x0]
 // CHECK-ENCODING: [0x02,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 02 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02002 <unknown>
 
 prfh    #3, p0, [x0]
 // CHECK-INST: prfh	pldl2strm, p0, [x0]
 // CHECK-ENCODING: [0x03,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 03 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02003 <unknown>
 
 prfh	pldl2strm, p0, [x0]
 // CHECK-INST: prfh	pldl2strm, p0, [x0]
 // CHECK-ENCODING: [0x03,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 03 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02003 <unknown>
 
 prfh    #4, p0, [x0]
 // CHECK-INST: prfh	pldl3keep, p0, [x0]
 // CHECK-ENCODING: [0x04,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 04 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02004 <unknown>
 
 prfh	pldl3keep, p0, [x0]
 // CHECK-INST: prfh	pldl3keep, p0, [x0]
 // CHECK-ENCODING: [0x04,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 04 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02004 <unknown>
 
 prfh    #5, p0, [x0]
 // CHECK-INST: prfh	pldl3strm, p0, [x0]
 // CHECK-ENCODING: [0x05,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02005 <unknown>
 
 prfh	pldl3strm, p0, [x0]
 // CHECK-INST: prfh	pldl3strm, p0, [x0]
 // CHECK-ENCODING: [0x05,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02005 <unknown>
 
 prfh    #6, p0, [x0]
 // CHECK-INST: prfh	#6, p0, [x0]
 // CHECK-ENCODING: [0x06,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 06 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02006 <unknown>
 
 prfh    #7, p0, [x0]
 // CHECK-INST: prfh	#7, p0, [x0]
 // CHECK-ENCODING: [0x07,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 07 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02007 <unknown>
 
 prfh    #8, p0, [x0]
 // CHECK-INST: prfh	pstl1keep, p0, [x0]
 // CHECK-ENCODING: [0x08,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 08 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02008 <unknown>
 
 prfh	pstl1keep, p0, [x0]
 // CHECK-INST: prfh	pstl1keep, p0, [x0]
 // CHECK-ENCODING: [0x08,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 08 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02008 <unknown>
 
 prfh    #9, p0, [x0]
 // CHECK-INST: prfh	pstl1strm, p0, [x0]
 // CHECK-ENCODING: [0x09,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 09 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02009 <unknown>
 
 prfh	pstl1strm, p0, [x0]
 // CHECK-INST: prfh	pstl1strm, p0, [x0]
 // CHECK-ENCODING: [0x09,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 09 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c02009 <unknown>
 
 prfh    #10, p0, [x0]
 // CHECK-INST: prfh	pstl2keep, p0, [x0]
 // CHECK-ENCODING: [0x0a,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0a 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0200a <unknown>
 
 prfh	pstl2keep, p0, [x0]
 // CHECK-INST: prfh	pstl2keep, p0, [x0]
 // CHECK-ENCODING: [0x0a,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0a 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0200a <unknown>
 
 prfh    #11, p0, [x0]
 // CHECK-INST: prfh	pstl2strm, p0, [x0]
 // CHECK-ENCODING: [0x0b,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0b 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0200b <unknown>
 
 prfh	pstl2strm, p0, [x0]
 // CHECK-INST: prfh	pstl2strm, p0, [x0]
 // CHECK-ENCODING: [0x0b,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0b 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0200b <unknown>
 
 prfh    #12, p0, [x0]
 // CHECK-INST: prfh	pstl3keep, p0, [x0]
 // CHECK-ENCODING: [0x0c,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0c 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0200c <unknown>
 
 prfh	pstl3keep, p0, [x0]
 // CHECK-INST: prfh	pstl3keep, p0, [x0]
 // CHECK-ENCODING: [0x0c,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0c 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0200c <unknown>
 
 prfh    #13, p0, [x0]
 // CHECK-INST: prfh	pstl3strm, p0, [x0]
 // CHECK-ENCODING: [0x0d,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0d 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0200d <unknown>
 
 prfh	pstl3strm, p0, [x0]
 // CHECK-INST: prfh	pstl3strm, p0, [x0]
 // CHECK-ENCODING: [0x0d,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0d 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0200d <unknown>
 
 prfh    #14, p0, [x0]
 // CHECK-INST: prfh	#14, p0, [x0]
 // CHECK-ENCODING: [0x0e,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0e 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0200e <unknown>
 
 prfh    #15, p0, [x0]
 // CHECK-INST: prfh	#15, p0, [x0]
 // CHECK-ENCODING: [0x0f,0x20,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 20 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0200f <unknown>
 
 // --------------------------------------------------------------------------//
 // Test addressing modes
@@ -187,10 +187,10 @@ prfh    pldl1strm, p0, [x0, #-32, mul vl]
 // CHECK-INST: prfh     pldl1strm, p0, [x0, #-32, mul vl]
 // CHECK-ENCODING: [0x01,0x20,0xe0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 20 e0 85
+// CHECK-UNKNOWN: 85e02001
 
 prfh    pldl1strm, p0, [x0, #31, mul vl]
 // CHECK-INST: prfh     pldl1strm, p0, [x0, #31, mul vl]
 // CHECK-ENCODING: [0x01,0x20,0xdf,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 20 df 85
+// CHECK-UNKNOWN: 85df2001

diff  --git a/llvm/test/MC/AArch64/SVE/prfw-sve-only.s b/llvm/test/MC/AArch64/SVE/prfw-sve-only.s
index cfcea90517c5e..1118cad9f5136 100644
--- a/llvm/test/MC/AArch64/SVE/prfw-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/prfw-sve-only.s
@@ -18,52 +18,52 @@ prfw    pldl1keep, p0, [x0, z0.s, uxtw #2]
 // CHECK-INST: prfw    pldl1keep, p0, [x0, z0.s, uxtw #2]
 // CHECK-ENCODING: [0x00,0x40,0x20,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 20 84 <unknown>
+// CHECK-UNKNOWN: 84204000 <unknown>
 
 prfw    pldl3strm, p5, [x10, z21.s, sxtw #2]
 // CHECK-INST: prfw    pldl3strm, p5, [x10, z21.s, sxtw #2]
 // CHECK-ENCODING: [0x45,0x55,0x75,0x84]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 45 55 75 84 <unknown>
+// CHECK-UNKNOWN: 84755545 <unknown>
 
 prfw    #7, p3, [x13, z8.d, uxtw #2]
 // CHECK-INST: prfw    #7, p3, [x13, z8.d, uxtw #2]
 // CHECK-ENCODING: [0xa7,0x4d,0x28,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: a7 4d 28 c4 <unknown>
+// CHECK-UNKNOWN: c4284da7 <unknown>
 
 prfw    pldl1keep, p0, [x0, z0.d, sxtw #2]
 // CHECK-INST: prfw    pldl1keep, p0, [x0, z0.d, sxtw #2]
 // CHECK-ENCODING: [0x00,0x40,0x60,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 40 60 c4 <unknown>
+// CHECK-UNKNOWN: c4604000 <unknown>
 
 prfw    pldl3strm, p5, [x10, z21.d, lsl #2]
 // CHECK-INST: prfw    pldl3strm, p5, [x10, z21.d, lsl #2]
 // CHECK-ENCODING: [0x45,0xd5,0x75,0xc4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 45 d5 75 c4 <unknown>
+// CHECK-UNKNOWN: c475d545 <unknown>
 
 prfw    #15, p7, [z31.s, #0]
 // CHECK-INST: prfw    #15, p7, [z31.s]
 // CHECK-ENCODING: [0xef,0xff,0x00,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef ff 00 85 <unknown>
+// CHECK-UNKNOWN: 8500ffef <unknown>
 
 prfw    #15, p7, [z31.s, #124]
 // CHECK-INST: prfw    #15, p7, [z31.s, #124]
 // CHECK-ENCODING: [0xef,0xff,0x1f,0x85]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef ff 1f 85 <unknown>
+// CHECK-UNKNOWN: 851fffef <unknown>
 
 prfw    #15, p7, [z31.d, #0]
 // CHECK-INST: prfw    #15, p7, [z31.d]
 // CHECK-ENCODING: [0xef,0xff,0x00,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef ff 00 c5 <unknown>
+// CHECK-UNKNOWN: c500ffef <unknown>
 
 prfw    #15, p7, [z31.d, #124]
 // CHECK-INST: prfw    #15, p7, [z31.d, #124]
 // CHECK-ENCODING: [0xef,0xff,0x1f,0xc5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef ff 1f c5 <unknown>
+// CHECK-UNKNOWN: c51fffef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/prfw.s b/llvm/test/MC/AArch64/SVE/prfw.s
index a69f1d1fec720..95fea0e2d63f2 100644
--- a/llvm/test/MC/AArch64/SVE/prfw.s
+++ b/llvm/test/MC/AArch64/SVE/prfw.s
@@ -16,169 +16,169 @@ prfw    #0, p0, [x0]
 // CHECK-INST: prfw	pldl1keep, p0, [x0]
 // CHECK-ENCODING: [0x00,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04000 <unknown>
 
 prfw	pldl1keep, p0, [x0]
 // CHECK-INST: prfw	pldl1keep, p0, [x0]
 // CHECK-ENCODING: [0x00,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04000 <unknown>
 
 prfw    #1, p0, [x0]
 // CHECK-INST: prfw	pldl1strm, p0, [x0]
 // CHECK-ENCODING: [0x01,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04001 <unknown>
 
 prfw	pldl1strm, p0, [x0]
 // CHECK-INST: prfw	pldl1strm, p0, [x0]
 // CHECK-ENCODING: [0x01,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04001 <unknown>
 
 prfw    #2, p0, [x0]
 // CHECK-INST: prfw	pldl2keep, p0, [x0]
 // CHECK-ENCODING: [0x02,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 02 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04002 <unknown>
 
 prfw	pldl2keep, p0, [x0]
 // CHECK-INST: prfw	pldl2keep, p0, [x0]
 // CHECK-ENCODING: [0x02,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 02 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04002 <unknown>
 
 prfw    #3, p0, [x0]
 // CHECK-INST: prfw	pldl2strm, p0, [x0]
 // CHECK-ENCODING: [0x03,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 03 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04003 <unknown>
 
 prfw	pldl2strm, p0, [x0]
 // CHECK-INST: prfw	pldl2strm, p0, [x0]
 // CHECK-ENCODING: [0x03,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 03 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04003 <unknown>
 
 prfw    #4, p0, [x0]
 // CHECK-INST: prfw	pldl3keep, p0, [x0]
 // CHECK-ENCODING: [0x04,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 04 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04004 <unknown>
 
 prfw	pldl3keep, p0, [x0]
 // CHECK-INST: prfw	pldl3keep, p0, [x0]
 // CHECK-ENCODING: [0x04,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 04 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04004 <unknown>
 
 prfw    #5, p0, [x0]
 // CHECK-INST: prfw	pldl3strm, p0, [x0]
 // CHECK-ENCODING: [0x05,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04005 <unknown>
 
 prfw	pldl3strm, p0, [x0]
 // CHECK-INST: prfw	pldl3strm, p0, [x0]
 // CHECK-ENCODING: [0x05,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04005 <unknown>
 
 prfw    #6, p0, [x0]
 // CHECK-INST: prfw	#6, p0, [x0]
 // CHECK-ENCODING: [0x06,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 06 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04006 <unknown>
 
 prfw    #7, p0, [x0]
 // CHECK-INST: prfw	#7, p0, [x0]
 // CHECK-ENCODING: [0x07,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 07 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04007 <unknown>
 
 prfw    #8, p0, [x0]
 // CHECK-INST: prfw	pstl1keep, p0, [x0]
 // CHECK-ENCODING: [0x08,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 08 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04008 <unknown>
 
 prfw	pstl1keep, p0, [x0]
 // CHECK-INST: prfw	pstl1keep, p0, [x0]
 // CHECK-ENCODING: [0x08,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 08 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04008 <unknown>
 
 prfw    #9, p0, [x0]
 // CHECK-INST: prfw	pstl1strm, p0, [x0]
 // CHECK-ENCODING: [0x09,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 09 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04009 <unknown>
 
 prfw	pstl1strm, p0, [x0]
 // CHECK-INST: prfw	pstl1strm, p0, [x0]
 // CHECK-ENCODING: [0x09,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 09 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c04009 <unknown>
 
 prfw    #10, p0, [x0]
 // CHECK-INST: prfw	pstl2keep, p0, [x0]
 // CHECK-ENCODING: [0x0a,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0a 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0400a <unknown>
 
 prfw	pstl2keep, p0, [x0]
 // CHECK-INST: prfw	pstl2keep, p0, [x0]
 // CHECK-ENCODING: [0x0a,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0a 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0400a <unknown>
 
 prfw    #11, p0, [x0]
 // CHECK-INST: prfw	pstl2strm, p0, [x0]
 // CHECK-ENCODING: [0x0b,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0b 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0400b <unknown>
 
 prfw	pstl2strm, p0, [x0]
 // CHECK-INST: prfw	pstl2strm, p0, [x0]
 // CHECK-ENCODING: [0x0b,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0b 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0400b <unknown>
 
 prfw    #12, p0, [x0]
 // CHECK-INST: prfw	pstl3keep, p0, [x0]
 // CHECK-ENCODING: [0x0c,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0c 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0400c <unknown>
 
 prfw	pstl3keep, p0, [x0]
 // CHECK-INST: prfw	pstl3keep, p0, [x0]
 // CHECK-ENCODING: [0x0c,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0c 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0400c <unknown>
 
 prfw    #13, p0, [x0]
 // CHECK-INST: prfw	pstl3strm, p0, [x0]
 // CHECK-ENCODING: [0x0d,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0d 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0400d <unknown>
 
 prfw	pstl3strm, p0, [x0]
 // CHECK-INST: prfw	pstl3strm, p0, [x0]
 // CHECK-ENCODING: [0x0d,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0d 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0400d <unknown>
 
 prfw    #14, p0, [x0]
 // CHECK-INST: prfw	#14, p0, [x0]
 // CHECK-ENCODING: [0x0e,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0e 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0400e <unknown>
 
 prfw    #15, p0, [x0]
 // CHECK-INST: prfw	#15, p0, [x0]
 // CHECK-ENCODING: [0x0f,0x40,0xc0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 40 c0 85 <unknown>
+// CHECK-UNKNOWN: 85c0400f <unknown>
 
 // --------------------------------------------------------------------------//
 // Test addressing modes
@@ -187,10 +187,10 @@ prfw    pldl1strm, p0, [x0, #-32, mul vl]
 // CHECK-INST: prfw     pldl1strm, p0, [x0, #-32, mul vl]
 // CHECK-ENCODING: [0x01,0x40,0xe0,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 40 e0 85
+// CHECK-UNKNOWN: 85e04001
 
 prfw    pldl1strm, p0, [x0, #31, mul vl]
 // CHECK-INST: prfw     pldl1strm, p0, [x0, #31, mul vl]
 // CHECK-ENCODING: [0x01,0x40,0xdf,0x85]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 01 40 df 85
+// CHECK-UNKNOWN: 85df4001

diff  --git a/llvm/test/MC/AArch64/SVE/ptest.s b/llvm/test/MC/AArch64/SVE/ptest.s
index 456c76f5d5bd0..6b464e3cd2022 100644
--- a/llvm/test/MC/AArch64/SVE/ptest.s
+++ b/llvm/test/MC/AArch64/SVE/ptest.s
@@ -13,10 +13,10 @@ ptest p15, p0.b
 // CHECK-INST: ptest	p15, p0.b
 // CHECK-ENCODING: [0x00,0xfc,0x50,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fc 50 25 <unknown>
+// CHECK-UNKNOWN: 2550fc00 <unknown>
 
 ptest p15, p15.b
 // CHECK-INST: ptest	p15, p15.b
 // CHECK-ENCODING: [0xe0,0xfd,0x50,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fd 50 25 <unknown>
+// CHECK-UNKNOWN: 2550fde0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ptrue.s b/llvm/test/MC/AArch64/SVE/ptrue.s
index f18dbaa72c7a4..19a5ba6c3866a 100644
--- a/llvm/test/MC/AArch64/SVE/ptrue.s
+++ b/llvm/test/MC/AArch64/SVE/ptrue.s
@@ -17,25 +17,25 @@ ptrue   p0.b, pow2
 // CHECK-INST: ptrue   p0.b, pow2
 // CHECK-ENCODING: [0x00,0xe0,0x18,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 18 25 <unknown>
+// CHECK-UNKNOWN: 2518e000 <unknown>
 
 ptrue   p0.h, pow2
 // CHECK-INST: ptrue   p0.h, pow2
 // CHECK-ENCODING: [0x00,0xe0,0x58,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 58 25 <unknown>
+// CHECK-UNKNOWN: 2558e000 <unknown>
 
 ptrue   p0.s, pow2
 // CHECK-INST: ptrue   p0.s, pow2
 // CHECK-ENCODING: [0x00,0xe0,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e000 <unknown>
 
 ptrue   p0.d, pow2
 // CHECK-INST: ptrue   p0.d, pow2
 // CHECK-ENCODING: [0x00,0xe0,0xd8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 d8 25 <unknown>
+// CHECK-UNKNOWN: 25d8e000 <unknown>
 
 // ---------------------------------------------------------------------------//
 // Test all predicate sizes without explicit pattern
@@ -45,25 +45,25 @@ ptrue   p15.b
 // CHECK-INST: ptrue   p15.b
 // CHECK-ENCODING: [0xef,0xe3,0x18,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef e3 18 25 <unknown>
+// CHECK-UNKNOWN: 2518e3ef <unknown>
 
 ptrue   p15.h
 // CHECK-INST: ptrue   p15.h
 // CHECK-ENCODING: [0xef,0xe3,0x58,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef e3 58 25 <unknown>
+// CHECK-UNKNOWN: 2558e3ef <unknown>
 
 ptrue   p15.s
 // CHECK-INST: ptrue   p15.s
 // CHECK-ENCODING: [0xef,0xe3,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef e3 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e3ef <unknown>
 
 ptrue   p15.d
 // CHECK-INST: ptrue   p15.d
 // CHECK-ENCODING: [0xef,0xe3,0xd8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef e3 d8 25 <unknown>
+// CHECK-UNKNOWN: 25d8e3ef <unknown>
 
 // ---------------------------------------------------------------------------//
 // Test available patterns
@@ -73,103 +73,103 @@ ptrue   p7.s, #1
 // CHECK-INST: ptrue   p7.s, vl1
 // CHECK-ENCODING: [0x27,0xe0,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 27 e0 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e027 <unknown>
 
 ptrue   p7.s, vl1
 // CHECK-INST: ptrue   p7.s, vl1
 // CHECK-ENCODING: [0x27,0xe0,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 27 e0 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e027 <unknown>
 
 ptrue   p7.s, vl2
 // CHECK-INST: ptrue   p7.s, vl2
 // CHECK-ENCODING: [0x47,0xe0,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 47 e0 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e047 <unknown>
 
 ptrue   p7.s, vl3
 // CHECK-INST: ptrue   p7.s, vl3
 // CHECK-ENCODING: [0x67,0xe0,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 67 e0 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e067 <unknown>
 
 ptrue   p7.s, vl4
 // CHECK-INST: ptrue   p7.s, vl4
 // CHECK-ENCODING: [0x87,0xe0,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 87 e0 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e087 <unknown>
 
 ptrue   p7.s, vl5
 // CHECK-INST: ptrue   p7.s, vl5
 // CHECK-ENCODING: [0xa7,0xe0,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a7 e0 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e0a7 <unknown>
 
 ptrue   p7.s, vl6
 // CHECK-INST: ptrue   p7.s, vl6
 // CHECK-ENCODING: [0xc7,0xe0,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c7 e0 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e0c7 <unknown>
 
 ptrue   p7.s, vl7
 // CHECK-INST: ptrue   p7.s, vl7
 // CHECK-ENCODING: [0xe7,0xe0,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e7 e0 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e0e7 <unknown>
 
 ptrue   p7.s, vl8
 // CHECK-INST: ptrue   p7.s, vl8
 // CHECK-ENCODING: [0x07,0xe1,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 07 e1 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e107 <unknown>
 
 ptrue   p7.s, vl16
 // CHECK-INST: ptrue   p7.s, vl16
 // CHECK-ENCODING: [0x27,0xe1,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 27 e1 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e127 <unknown>
 
 ptrue   p7.s, vl32
 // CHECK-INST: ptrue   p7.s, vl32
 // CHECK-ENCODING: [0x47,0xe1,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 47 e1 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e147 <unknown>
 
 ptrue   p7.s, vl64
 // CHECK-INST: ptrue   p7.s, vl64
 // CHECK-ENCODING: [0x67,0xe1,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 67 e1 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e167 <unknown>
 
 ptrue   p7.s, vl128
 // CHECK-INST: ptrue   p7.s, vl128
 // CHECK-ENCODING: [0x87,0xe1,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 87 e1 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e187 <unknown>
 
 ptrue   p7.s, vl256
 // CHECK-INST: ptrue   p7.s, vl256
 // CHECK-ENCODING: [0xa7,0xe1,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a7 e1 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e1a7 <unknown>
 
 ptrue   p7.s, mul4
 // CHECK-INST: ptrue   p7.s, mul4
 // CHECK-ENCODING: [0xa7,0xe3,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a7 e3 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e3a7 <unknown>
 
 ptrue   p7.s, mul3
 // CHECK-INST: ptrue   p7.s, mul3
 // CHECK-ENCODING: [0xc7,0xe3,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c7 e3 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e3c7 <unknown>
 
 ptrue   p7.s, all
 // CHECK-INST: ptrue   p7.s
 // CHECK-ENCODING: [0xe7,0xe3,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e7 e3 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e3e7 <unknown>
 
 // ---------------------------------------------------------------------------//
 // Test immediate values not corresponding to a named pattern
@@ -179,88 +179,88 @@ ptrue   p7.s, #14
 // CHECK-INST: ptrue   p7.s, #14
 // CHECK-ENCODING: [0xc7,0xe1,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c7 e1 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e1c7 <unknown>
 
 ptrue   p7.s, #15
 // CHECK-INST: ptrue   p7.s, #15
 // CHECK-ENCODING: [0xe7,0xe1,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e7 e1 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e1e7 <unknown>
 
 ptrue   p7.s, #16
 // CHECK-INST: ptrue   p7.s, #16
 // CHECK-ENCODING: [0x07,0xe2,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 07 e2 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e207 <unknown>
 
 ptrue   p7.s, #17
 // CHECK-INST: ptrue   p7.s, #17
 // CHECK-ENCODING: [0x27,0xe2,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 27 e2 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e227 <unknown>
 
 ptrue   p7.s, #18
 // CHECK-INST: ptrue   p7.s, #18
 // CHECK-ENCODING: [0x47,0xe2,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 47 e2 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e247 <unknown>
 
 ptrue   p7.s, #19
 // CHECK-INST: ptrue   p7.s, #19
 // CHECK-ENCODING: [0x67,0xe2,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 67 e2 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e267 <unknown>
 
 ptrue   p7.s, #20
 // CHECK-INST: ptrue   p7.s, #20
 // CHECK-ENCODING: [0x87,0xe2,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 87 e2 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e287 <unknown>
 
 ptrue   p7.s, #21
 // CHECK-INST: ptrue   p7.s, #21
 // CHECK-ENCODING: [0xa7,0xe2,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a7 e2 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e2a7 <unknown>
 
 ptrue   p7.s, #22
 // CHECK-INST: ptrue   p7.s, #22
 // CHECK-ENCODING: [0xc7,0xe2,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c7 e2 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e2c7 <unknown>
 
 ptrue   p7.s, #23
 // CHECK-INST: ptrue   p7.s, #23
 // CHECK-ENCODING: [0xe7,0xe2,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e7 e2 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e2e7 <unknown>
 
 ptrue   p7.s, #24
 // CHECK-INST: ptrue   p7.s, #24
 // CHECK-ENCODING: [0x07,0xe3,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 07 e3 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e307 <unknown>
 
 ptrue   p7.s, #25
 // CHECK-INST: ptrue   p7.s, #25
 // CHECK-ENCODING: [0x27,0xe3,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 27 e3 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e327 <unknown>
 
 ptrue   p7.s, #26
 // CHECK-INST: ptrue   p7.s, #26
 // CHECK-ENCODING: [0x47,0xe3,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 47 e3 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e347 <unknown>
 
 ptrue   p7.s, #27
 // CHECK-INST: ptrue   p7.s, #27
 // CHECK-ENCODING: [0x67,0xe3,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 67 e3 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e367 <unknown>
 
 ptrue   p7.s, #28
 // CHECK-INST: ptrue   p7.s, #28
 // CHECK-ENCODING: [0x87,0xe3,0x98,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 87 e3 98 25 <unknown>
+// CHECK-UNKNOWN: 2598e387 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ptrues.s b/llvm/test/MC/AArch64/SVE/ptrues.s
index d9f4518e3857a..78c78c1b3d3f8 100644
--- a/llvm/test/MC/AArch64/SVE/ptrues.s
+++ b/llvm/test/MC/AArch64/SVE/ptrues.s
@@ -17,25 +17,25 @@ ptrues   p0.b, pow2
 // CHECK-INST: ptrues   p0.b, pow2
 // CHECK-ENCODING: [0x00,0xe0,0x19,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	00 e0 19 25  <unknown>
+// CHECK-UNKNOWN:	2519e000  <unknown>
 
 ptrues   p0.h, pow2
 // CHECK-INST: ptrues   p0.h, pow2
 // CHECK-ENCODING: [0x00,0xe0,0x59,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	00 e0 59 25  <unknown>
+// CHECK-UNKNOWN:	2559e000  <unknown>
 
 ptrues   p0.s, pow2
 // CHECK-INST: ptrues   p0.s, pow2
 // CHECK-ENCODING: [0x00,0xe0,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	00 e0 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e000  <unknown>
 
 ptrues   p0.d, pow2
 // CHECK-INST: ptrues   p0.d, pow2
 // CHECK-ENCODING: [0x00,0xe0,0xd9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	00 e0 d9 25  <unknown>
+// CHECK-UNKNOWN:	25d9e000  <unknown>
 
 // ---------------------------------------------------------------------------//
 // Test all predicate sizes without explicit pattern
@@ -45,25 +45,25 @@ ptrues   p15.b
 // CHECK-INST: ptrues   p15.b
 // CHECK-ENCODING: [0xef,0xe3,0x19,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	ef e3 19 25  <unknown>
+// CHECK-UNKNOWN:	2519e3ef  <unknown>
 
 ptrues   p15.h
 // CHECK-INST: ptrues   p15.h
 // CHECK-ENCODING: [0xef,0xe3,0x59,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	ef e3 59 25  <unknown>
+// CHECK-UNKNOWN:	2559e3ef  <unknown>
 
 ptrues   p15.s
 // CHECK-INST: ptrues   p15.s
 // CHECK-ENCODING: [0xef,0xe3,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	ef e3 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e3ef  <unknown>
 
 ptrues   p15.d
 // CHECK-INST: ptrues   p15.d
 // CHECK-ENCODING: [0xef,0xe3,0xd9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	ef e3 d9 25  <unknown>
+// CHECK-UNKNOWN:	25d9e3ef  <unknown>
 
 // ---------------------------------------------------------------------------//
 // Test available patterns
@@ -73,103 +73,103 @@ ptrues   p7.s, #1
 // CHECK-INST: ptrues   p7.s, vl1
 // CHECK-ENCODING: [0x27,0xe0,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	27 e0 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e027  <unknown>
 
 ptrues   p7.s, vl1
 // CHECK-INST: ptrues   p7.s, vl1
 // CHECK-ENCODING: [0x27,0xe0,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	27 e0 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e027  <unknown>
 
 ptrues   p7.s, vl2
 // CHECK-INST: ptrues   p7.s, vl2
 // CHECK-ENCODING: [0x47,0xe0,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	47 e0 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e047  <unknown>
 
 ptrues   p7.s, vl3
 // CHECK-INST: ptrues   p7.s, vl3
 // CHECK-ENCODING: [0x67,0xe0,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	67 e0 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e067  <unknown>
 
 ptrues   p7.s, vl4
 // CHECK-INST: ptrues   p7.s, vl4
 // CHECK-ENCODING: [0x87,0xe0,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	87 e0 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e087  <unknown>
 
 ptrues   p7.s, vl5
 // CHECK-INST: ptrues   p7.s, vl5
 // CHECK-ENCODING: [0xa7,0xe0,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	a7 e0 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e0a7  <unknown>
 
 ptrues   p7.s, vl6
 // CHECK-INST: ptrues   p7.s, vl6
 // CHECK-ENCODING: [0xc7,0xe0,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	c7 e0 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e0c7  <unknown>
 
 ptrues   p7.s, vl7
 // CHECK-INST: ptrues   p7.s, vl7
 // CHECK-ENCODING: [0xe7,0xe0,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	e7 e0 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e0e7  <unknown>
 
 ptrues   p7.s, vl8
 // CHECK-INST: ptrues   p7.s, vl8
 // CHECK-ENCODING: [0x07,0xe1,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	07 e1 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e107  <unknown>
 
 ptrues   p7.s, vl16
 // CHECK-INST: ptrues   p7.s, vl16
 // CHECK-ENCODING: [0x27,0xe1,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	27 e1 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e127  <unknown>
 
 ptrues   p7.s, vl32
 // CHECK-INST: ptrues   p7.s, vl32
 // CHECK-ENCODING: [0x47,0xe1,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	47 e1 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e147  <unknown>
 
 ptrues   p7.s, vl64
 // CHECK-INST: ptrues   p7.s, vl64
 // CHECK-ENCODING: [0x67,0xe1,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	67 e1 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e167  <unknown>
 
 ptrues   p7.s, vl128
 // CHECK-INST: ptrues   p7.s, vl128
 // CHECK-ENCODING: [0x87,0xe1,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	87 e1 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e187  <unknown>
 
 ptrues   p7.s, vl256
 // CHECK-INST: ptrues   p7.s, vl256
 // CHECK-ENCODING: [0xa7,0xe1,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	a7 e1 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e1a7  <unknown>
 
 ptrues   p7.s, mul4
 // CHECK-INST: ptrues   p7.s, mul4
 // CHECK-ENCODING: [0xa7,0xe3,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	a7 e3 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e3a7  <unknown>
 
 ptrues   p7.s, mul3
 // CHECK-INST: ptrues   p7.s, mul3
 // CHECK-ENCODING: [0xc7,0xe3,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	c7 e3 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e3c7  <unknown>
 
 ptrues   p7.s, all
 // CHECK-INST: ptrues   p7.s
 // CHECK-ENCODING: [0xe7,0xe3,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN:	e7 e3 99 25  <unknown>
+// CHECK-UNKNOWN:	2599e3e7  <unknown>
 
 // ---------------------------------------------------------------------------//
 // Test immediate values not corresponding to a named pattern
@@ -179,88 +179,88 @@ ptrues   p7.s, #14
 // CHECK-INST: ptrues   p7.s, #14
 // CHECK-ENCODING: [0xc7,0xe1,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c7 e1 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e1c7 <unknown>
 
 ptrues   p7.s, #15
 // CHECK-INST: ptrues   p7.s, #15
 // CHECK-ENCODING: [0xe7,0xe1,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e7 e1 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e1e7 <unknown>
 
 ptrues   p7.s, #16
 // CHECK-INST: ptrues   p7.s, #16
 // CHECK-ENCODING: [0x07,0xe2,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 07 e2 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e207 <unknown>
 
 ptrues   p7.s, #17
 // CHECK-INST: ptrues   p7.s, #17
 // CHECK-ENCODING: [0x27,0xe2,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 27 e2 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e227 <unknown>
 
 ptrues   p7.s, #18
 // CHECK-INST: ptrues   p7.s, #18
 // CHECK-ENCODING: [0x47,0xe2,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 47 e2 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e247 <unknown>
 
 ptrues   p7.s, #19
 // CHECK-INST: ptrues   p7.s, #19
 // CHECK-ENCODING: [0x67,0xe2,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 67 e2 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e267 <unknown>
 
 ptrues   p7.s, #20
 // CHECK-INST: ptrues   p7.s, #20
 // CHECK-ENCODING: [0x87,0xe2,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 87 e2 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e287 <unknown>
 
 ptrues   p7.s, #21
 // CHECK-INST: ptrues   p7.s, #21
 // CHECK-ENCODING: [0xa7,0xe2,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a7 e2 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e2a7 <unknown>
 
 ptrues   p7.s, #22
 // CHECK-INST: ptrues   p7.s, #22
 // CHECK-ENCODING: [0xc7,0xe2,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c7 e2 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e2c7 <unknown>
 
 ptrues   p7.s, #23
 // CHECK-INST: ptrues   p7.s, #23
 // CHECK-ENCODING: [0xe7,0xe2,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e7 e2 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e2e7 <unknown>
 
 ptrues   p7.s, #24
 // CHECK-INST: ptrues   p7.s, #24
 // CHECK-ENCODING: [0x07,0xe3,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 07 e3 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e307 <unknown>
 
 ptrues   p7.s, #25
 // CHECK-INST: ptrues   p7.s, #25
 // CHECK-ENCODING: [0x27,0xe3,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 27 e3 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e327 <unknown>
 
 ptrues   p7.s, #26
 // CHECK-INST: ptrues   p7.s, #26
 // CHECK-ENCODING: [0x47,0xe3,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 47 e3 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e347 <unknown>
 
 ptrues   p7.s, #27
 // CHECK-INST: ptrues   p7.s, #27
 // CHECK-ENCODING: [0x67,0xe3,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 67 e3 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e367 <unknown>
 
 ptrues   p7.s, #28
 // CHECK-INST: ptrues   p7.s, #28
 // CHECK-ENCODING: [0x87,0xe3,0x99,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 87 e3 99 25 <unknown>
+// CHECK-UNKNOWN: 2599e387 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/punpkhi.s b/llvm/test/MC/AArch64/SVE/punpkhi.s
index 341e736c433b6..0af1edcadae7c 100644
--- a/llvm/test/MC/AArch64/SVE/punpkhi.s
+++ b/llvm/test/MC/AArch64/SVE/punpkhi.s
@@ -13,10 +13,10 @@ punpkhi p0.h, p0.b
 // CHECK-INST: punpkhi	p0.h, p0.b
 // CHECK-ENCODING: [0x00,0x40,0x31,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 31 05 <unknown>
+// CHECK-UNKNOWN: 05314000 <unknown>
 
 punpkhi p15.h, p15.b
 // CHECK-INST: punpkhi	p15.h, p15.b
 // CHECK-ENCODING: [0xef,0x41,0x31,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 41 31 05 <unknown>
+// CHECK-UNKNOWN: 053141ef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/punpklo.s b/llvm/test/MC/AArch64/SVE/punpklo.s
index 0f9612ebb369f..f52f22e3fab7b 100644
--- a/llvm/test/MC/AArch64/SVE/punpklo.s
+++ b/llvm/test/MC/AArch64/SVE/punpklo.s
@@ -13,10 +13,10 @@ punpklo p0.h, p0.b
 // CHECK-INST: punpklo	p0.h, p0.b
 // CHECK-ENCODING: [0x00,0x40,0x30,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 30 05 <unknown>
+// CHECK-UNKNOWN: 05304000 <unknown>
 
 punpklo p15.h, p15.b
 // CHECK-INST: punpklo	p15.h, p15.b
 // CHECK-ENCODING: [0xef,0x41,0x30,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 41 30 05 <unknown>
+// CHECK-UNKNOWN: 053041ef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/rbit.s b/llvm/test/MC/AArch64/SVE/rbit.s
index ca03c5a66eee7..49785285f34c5 100644
--- a/llvm/test/MC/AArch64/SVE/rbit.s
+++ b/llvm/test/MC/AArch64/SVE/rbit.s
@@ -13,25 +13,25 @@ rbit  z0.b, p7/m, z31.b
 // CHECK-INST: rbit	z0.b, p7/m, z31.b
 // CHECK-ENCODING: [0xe0,0x9f,0x27,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 27 05 <unknown>
+// CHECK-UNKNOWN: 05279fe0 <unknown>
 
 rbit  z0.h, p7/m, z31.h
 // CHECK-INST: rbit	z0.h, p7/m, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x67,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 67 05 <unknown>
+// CHECK-UNKNOWN: 05679fe0 <unknown>
 
 rbit  z0.s, p7/m, z31.s
 // CHECK-INST: rbit	z0.s, p7/m, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0xa7,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f a7 05 <unknown>
+// CHECK-UNKNOWN: 05a79fe0 <unknown>
 
 rbit  z0.d, p7/m, z31.d
 // CHECK-INST: rbit	z0.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e7 05 <unknown>
+// CHECK-UNKNOWN: 05e79fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 rbit  z0.d, p7/m, z31.d
 // CHECK-INST: rbit	z0.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e7 05 <unknown>
+// CHECK-UNKNOWN: 05e79fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 rbit  z0.d, p7/m, z31.d
 // CHECK-INST: rbit	z0.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe7,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e7 05 <unknown>
+// CHECK-UNKNOWN: 05e79fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/rdffr.s b/llvm/test/MC/AArch64/SVE/rdffr.s
index 7f6e1ec4b3416..c7970f22001e7 100644
--- a/llvm/test/MC/AArch64/SVE/rdffr.s
+++ b/llvm/test/MC/AArch64/SVE/rdffr.s
@@ -13,22 +13,22 @@ rdffr   p0.b
 // CHECK-INST: rdffr   p0.b
 // CHECK-ENCODING: [0x00,0xf0,0x19,0x25]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 f0 19 25 <unknown>
+// CHECK-UNKNOWN: 2519f000 <unknown>
 
 rdffr   p15.b
 // CHECK-INST: rdffr   p15.b
 // CHECK-ENCODING: [0x0f,0xf0,0x19,0x25]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 0f f0 19 25 <unknown>
+// CHECK-UNKNOWN: 2519f00f <unknown>
 
 rdffr   p0.b, p0/z
 // CHECK-INST: rdffr   p0.b, p0/z
 // CHECK-ENCODING: [0x00,0xf0,0x18,0x25]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 f0 18 25 <unknown>
+// CHECK-UNKNOWN: 2518f000 <unknown>
 
 rdffr   p15.b, p15/z
 // CHECK-INST: rdffr   p15.b, p15/z
 // CHECK-ENCODING: [0xef,0xf1,0x18,0x25]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef f1 18 25 <unknown>
+// CHECK-UNKNOWN: 2518f1ef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/rdffrs.s b/llvm/test/MC/AArch64/SVE/rdffrs.s
index 583817aa2a0f7..2bce5eb9c470c 100644
--- a/llvm/test/MC/AArch64/SVE/rdffrs.s
+++ b/llvm/test/MC/AArch64/SVE/rdffrs.s
@@ -13,10 +13,10 @@ rdffrs  p0.b, p0/z
 // CHECK-INST: rdffrs  p0.b, p0/z
 // CHECK-ENCODING: [0x00,0xf0,0x58,0x25]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 f0 58 25 <unknown>
+// CHECK-UNKNOWN: 2558f000 <unknown>
 
 rdffrs  p15.b, p15/z
 // CHECK-INST: rdffrs  p15.b, p15/z
 // CHECK-ENCODING: [0xef,0xf1,0x58,0x25]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ef f1 58 25 <unknown>
+// CHECK-UNKNOWN: 2558f1ef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/rdvl.s b/llvm/test/MC/AArch64/SVE/rdvl.s
index d8c331736ed24..33f2f88f4b049 100644
--- a/llvm/test/MC/AArch64/SVE/rdvl.s
+++ b/llvm/test/MC/AArch64/SVE/rdvl.s
@@ -13,22 +13,22 @@ rdvl    x0, #0
 // CHECK-INST: rdvl    x0, #0
 // CHECK-ENCODING: [0x00,0x50,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 50 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf5000 <unknown>
 
 rdvl    xzr, #-1
 // CHECK-INST: rdvl    xzr, #-1
 // CHECK-ENCODING: [0xff,0x57,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 57 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf57ff <unknown>
 
 rdvl    x23, #31
 // CHECK-INST: rdvl    x23, #31
 // CHECK-ENCODING: [0xf7,0x53,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: f7 53 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf53f7 <unknown>
 
 rdvl    x21, #-32
 // CHECK-INST: rdvl    x21, #-32
 // CHECK-ENCODING: [0x15,0x54,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 15 54 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf5415 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/rev.s b/llvm/test/MC/AArch64/SVE/rev.s
index b02505f6fb627..7bcc6d2f03fe3 100644
--- a/llvm/test/MC/AArch64/SVE/rev.s
+++ b/llvm/test/MC/AArch64/SVE/rev.s
@@ -13,22 +13,22 @@ rev   z0.b, z31.b
 // CHECK-INST: rev	z0.b, z31.b
 // CHECK-ENCODING: [0xe0,0x3b,0x38,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3b 38 05 <unknown>
+// CHECK-UNKNOWN: 05383be0 <unknown>
 
 rev   z0.h, z31.h
 // CHECK-INST: rev	z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x3b,0x78,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3b 78 05 <unknown>
+// CHECK-UNKNOWN: 05783be0 <unknown>
 
 rev   z0.s, z31.s
 // CHECK-INST: rev	z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x3b,0xb8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3b b8 05 <unknown>
+// CHECK-UNKNOWN: 05b83be0 <unknown>
 
 rev   z0.d, z31.d
 // CHECK-INST: rev	z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x3b,0xf8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3b f8 05 <unknown>
+// CHECK-UNKNOWN: 05f83be0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/revb.s b/llvm/test/MC/AArch64/SVE/revb.s
index 3082058dca051..8ef967d36b816 100644
--- a/llvm/test/MC/AArch64/SVE/revb.s
+++ b/llvm/test/MC/AArch64/SVE/revb.s
@@ -13,19 +13,19 @@ revb  z0.h, p7/m, z31.h
 // CHECK-INST: revb	z0.h, p7/m, z31.h
 // CHECK-ENCODING: [0xe0,0x9f,0x64,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f 64 05 <unknown>
+// CHECK-UNKNOWN: 05649fe0 <unknown>
 
 revb  z0.s, p7/m, z31.s
 // CHECK-INST: revb	z0.s, p7/m, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0xa4,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f a4 05 <unknown>
+// CHECK-UNKNOWN: 05a49fe0 <unknown>
 
 revb  z0.d, p7/m, z31.d
 // CHECK-INST: revb	z0.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e4 05 <unknown>
+// CHECK-UNKNOWN: 05e49fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 revb  z0.d, p7/m, z31.d
 // CHECK-INST: revb	z0.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e4 05 <unknown>
+// CHECK-UNKNOWN: 05e49fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 revb  z0.d, p7/m, z31.d
 // CHECK-INST: revb	z0.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe4,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e4 05 <unknown>
+// CHECK-UNKNOWN: 05e49fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/revh.s b/llvm/test/MC/AArch64/SVE/revh.s
index 0143c78aab2a1..1ed724a7c8925 100644
--- a/llvm/test/MC/AArch64/SVE/revh.s
+++ b/llvm/test/MC/AArch64/SVE/revh.s
@@ -13,13 +13,13 @@ revh  z0.s, p7/m, z31.s
 // CHECK-INST: revh	z0.s, p7/m, z31.s
 // CHECK-ENCODING: [0xe0,0x9f,0xa5,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f a5 05 <unknown>
+// CHECK-UNKNOWN: 05a59fe0 <unknown>
 
 revh  z0.d, p7/m, z31.d
 // CHECK-INST: revh	z0.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e5 05 <unknown>
+// CHECK-UNKNOWN: 05e59fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -29,22 +29,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 revh  z0.d, p7/m, z31.d
 // CHECK-INST: revh	z0.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e5 05 <unknown>
+// CHECK-UNKNOWN: 05e59fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 revh  z0.d, p7/m, z31.d
 // CHECK-INST: revh	z0.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe5,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e5 05 <unknown>
+// CHECK-UNKNOWN: 05e59fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/revw.s b/llvm/test/MC/AArch64/SVE/revw.s
index 5bb5cc5ba26aa..c33c40c4bd679 100644
--- a/llvm/test/MC/AArch64/SVE/revw.s
+++ b/llvm/test/MC/AArch64/SVE/revw.s
@@ -13,7 +13,7 @@ revw  z0.d, p7/m, z31.d
 // CHECK-INST: revw	z0.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e6 05 <unknown>
+// CHECK-UNKNOWN: 05e69fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -23,22 +23,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 revw  z0.d, p7/m, z31.d
 // CHECK-INST: revw	z0.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e6 05 <unknown>
+// CHECK-UNKNOWN: 05e69fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 revw  z0.d, p7/m, z31.d
 // CHECK-INST: revw	z0.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe0,0x9f,0xe6,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 9f e6 05 <unknown>
+// CHECK-UNKNOWN: 05e69fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sabd.s b/llvm/test/MC/AArch64/SVE/sabd.s
index d0477f28a6748..429508b981ff0 100644
--- a/llvm/test/MC/AArch64/SVE/sabd.s
+++ b/llvm/test/MC/AArch64/SVE/sabd.s
@@ -13,25 +13,25 @@ sabd  z31.b, p7/m, z31.b, z31.b
 // CHECK-INST: sabd	z31.b, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x1f,0x0c,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 0c 04 <unknown>
+// CHECK-UNKNOWN: 040c1fff <unknown>
 
 sabd  z31.h, p7/m, z31.h, z31.h
 // CHECK-INST: sabd	z31.h, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x1f,0x4c,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 4c 04 <unknown>
+// CHECK-UNKNOWN: 044c1fff <unknown>
 
 sabd  z31.s, p7/m, z31.s, z31.s
 // CHECK-INST: sabd	z31.s, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1f,0x8c,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 8c 04 <unknown>
+// CHECK-UNKNOWN: 048c1fff <unknown>
 
 sabd  z31.d, p7/m, z31.d, z31.d
 // CHECK-INST: sabd	z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xcc,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f cc 04 <unknown>
+// CHECK-UNKNOWN: 04cc1fff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 sabd  z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: sabd	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xcc,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f cc 04 <unknown>
+// CHECK-UNKNOWN: 04cc1fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 sabd  z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: sabd	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xcc,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f cc 04 <unknown>
+// CHECK-UNKNOWN: 04cc1fe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/saddv.s b/llvm/test/MC/AArch64/SVE/saddv.s
index 0b7d819a46c9c..1400b9ac097af 100644
--- a/llvm/test/MC/AArch64/SVE/saddv.s
+++ b/llvm/test/MC/AArch64/SVE/saddv.s
@@ -13,16 +13,16 @@ saddv d0, p7, z31.b
 // CHECK-INST: saddv	d0, p7, z31.b
 // CHECK-ENCODING: [0xe0,0x3f,0x00,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 00 04 <unknown>
+// CHECK-UNKNOWN: 04003fe0 <unknown>
 
 saddv d0, p7, z31.h
 // CHECK-INST: saddv	d0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x40,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 40 04 <unknown>
+// CHECK-UNKNOWN: 04403fe0 <unknown>
 
 saddv d0, p7, z31.s
 // CHECK-INST: saddv	d0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x80,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 80 04 <unknown>
+// CHECK-UNKNOWN: 04803fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/scvtf.s b/llvm/test/MC/AArch64/SVE/scvtf.s
index 3c0f5d166cd96..04f2884ff071b 100644
--- a/llvm/test/MC/AArch64/SVE/scvtf.s
+++ b/llvm/test/MC/AArch64/SVE/scvtf.s
@@ -13,43 +13,43 @@ scvtf   z0.h, p0/m, z0.h
 // CHECK-INST: scvtf   z0.h, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x52,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 52 65 <unknown>
+// CHECK-UNKNOWN: 6552a000 <unknown>
 
 scvtf   z0.h, p0/m, z0.s
 // CHECK-INST: scvtf   z0.h, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x54,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 54 65 <unknown>
+// CHECK-UNKNOWN: 6554a000 <unknown>
 
 scvtf   z0.h, p0/m, z0.d
 // CHECK-INST: scvtf   z0.h, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0x56,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 56 65 <unknown>
+// CHECK-UNKNOWN: 6556a000 <unknown>
 
 scvtf   z0.s, p0/m, z0.s
 // CHECK-INST: scvtf   z0.s, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x94,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 94 65 <unknown>
+// CHECK-UNKNOWN: 6594a000 <unknown>
 
 scvtf   z0.s, p0/m, z0.d
 // CHECK-INST: scvtf   z0.s, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd4,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d4 65 <unknown>
+// CHECK-UNKNOWN: 65d4a000 <unknown>
 
 scvtf   z0.d, p0/m, z0.s
 // CHECK-INST: scvtf   z0.d, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0xd0,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d0 65 <unknown>
+// CHECK-UNKNOWN: 65d0a000 <unknown>
 
 scvtf   z0.d, p0/m, z0.d
 // CHECK-INST: scvtf   z0.d, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd6,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d6 65 <unknown>
+// CHECK-UNKNOWN: 65d6a000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -59,22 +59,22 @@ movprfx z5.d, p0/z, z7.d
 // CHECK-INST: movprfx	z5.d, p0/z, z7.d
 // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020e5 <unknown>
 
 scvtf   z5.d, p0/m, z0.d
 // CHECK-INST: scvtf	z5.d, p0/m, z0.d
 // CHECK-ENCODING: [0x05,0xa0,0xd6,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 a0 d6 65 <unknown>
+// CHECK-UNKNOWN: 65d6a005 <unknown>
 
 movprfx z5, z7
 // CHECK-INST: movprfx	z5, z7
 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce5 <unknown>
 
 scvtf   z5.d, p0/m, z0.d
 // CHECK-INST: scvtf	z5.d, p0/m, z0.d
 // CHECK-ENCODING: [0x05,0xa0,0xd6,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 a0 d6 65 <unknown>
+// CHECK-UNKNOWN: 65d6a005 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sdiv.s b/llvm/test/MC/AArch64/SVE/sdiv.s
index 5fa4da757b564..9bfbc2ef2c53a 100644
--- a/llvm/test/MC/AArch64/SVE/sdiv.s
+++ b/llvm/test/MC/AArch64/SVE/sdiv.s
@@ -13,13 +13,13 @@ sdiv   z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: sdiv	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x1f,0x94,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f 94 04 <unknown>
+// CHECK-UNKNOWN: 04941fe0 <unknown>
 
 sdiv   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: sdiv	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d4 04 <unknown>
+// CHECK-UNKNOWN: 04d41fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -29,22 +29,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 sdiv   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: sdiv	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d4 04 <unknown>
+// CHECK-UNKNOWN: 04d41fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sdiv   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: sdiv	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd4,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d4 04 <unknown>
+// CHECK-UNKNOWN: 04d41fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sdivr.s b/llvm/test/MC/AArch64/SVE/sdivr.s
index 20b7b4003cfb8..914d2c0555f83 100644
--- a/llvm/test/MC/AArch64/SVE/sdivr.s
+++ b/llvm/test/MC/AArch64/SVE/sdivr.s
@@ -13,13 +13,13 @@ sdivr  z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: sdivr	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x1f,0x96,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f 96 04 <unknown>
+// CHECK-UNKNOWN: 04961fe0 <unknown>
 
 sdivr  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: sdivr	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d6 04 <unknown>
+// CHECK-UNKNOWN: 04d61fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -29,22 +29,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 sdivr  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: sdivr	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d6 04 <unknown>
+// CHECK-UNKNOWN: 04d61fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sdivr  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: sdivr	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd6,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d6 04 <unknown>
+// CHECK-UNKNOWN: 04d61fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sdot.s b/llvm/test/MC/AArch64/SVE/sdot.s
index ae2b812ebdb90..980d1d33408c6 100644
--- a/llvm/test/MC/AArch64/SVE/sdot.s
+++ b/llvm/test/MC/AArch64/SVE/sdot.s
@@ -13,25 +13,25 @@ sdot  z0.s, z1.b, z31.b
 // CHECK-INST: sdot	z0.s, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x00,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f0020 <unknown>
 
 sdot  z0.d, z1.h, z31.h
 // CHECK-INST: sdot	z0.d, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x00,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 df 44 <unknown>
+// CHECK-UNKNOWN: 44df0020 <unknown>
 
 sdot  z0.s, z1.b, z7.b[3]
 // CHECK-INST: sdot	z0.s, z1.b, z7.b[3]
 // CHECK-ENCODING: [0x20,0x00,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf0020 <unknown>
 
 sdot  z0.d, z1.h, z15.h[1]
 // CHECK-INST: sdot	z0.d, z1.h, z15.h[1]
 // CHECK-ENCODING: [0x20,0x00,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff0020 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sdot  z0.d, z1.h, z31.h
 // CHECK-INST: sdot	z0.d, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x00,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 df 44 <unknown>
+// CHECK-UNKNOWN: 44df0020 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sdot  z0.d, z1.h, z15.h[1]
 // CHECK-INST: sdot	z0.d, z1.h, z15.h[1]
 // CHECK-ENCODING: [0x20,0x00,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 00 ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff0020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sel.s b/llvm/test/MC/AArch64/SVE/sel.s
index f91dd6bc5704f..875a65dc5a5a7 100644
--- a/llvm/test/MC/AArch64/SVE/sel.s
+++ b/llvm/test/MC/AArch64/SVE/sel.s
@@ -13,58 +13,58 @@ sel     p0.b, p0, p0.b, p0.b
 // CHECK-INST: mov     p0.b, p0/m, p0.b
 // CHECK-ENCODING: [0x10,0x42,0x00,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 10 42 00 25 <unknown>
+// CHECK-UNKNOWN: 25004210 <unknown>
 
 sel     p15.b, p15, p15.b, p15.b
 // CHECK-INST: mov     p15.b, p15/m, p15.b
 // CHECK-ENCODING: [0xff,0x7f,0x0f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 7f 0f 25 <unknown>
+// CHECK-UNKNOWN: 250f7fff <unknown>
 
 sel     z31.b, p15, z31.b, z31.b
 // CHECK-INST: mov     z31.b, p15/m, z31.b
 // CHECK-ENCODING: [0xff,0xff,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 3f 05 <unknown>
+// CHECK-UNKNOWN: 053fffff <unknown>
 
 sel     z31.h, p15, z31.h, z31.h
 // CHECK-INST: mov     z31.h, p15/m, z31.h
 // CHECK-ENCODING: [0xff,0xff,0x7f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 7f 05 <unknown>
+// CHECK-UNKNOWN: 057fffff <unknown>
 
 sel     z31.s, p15, z31.s, z31.s
 // CHECK-INST: mov     z31.s, p15/m, z31.s
 // CHECK-ENCODING: [0xff,0xff,0xbf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff bf 05 <unknown>
+// CHECK-UNKNOWN: 05bfffff <unknown>
 
 sel     z31.d, p15, z31.d, z31.d
 // CHECK-INST: mov     z31.d, p15/m, z31.d
 // CHECK-ENCODING: [0xff,0xff,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff ff 05 <unknown>
+// CHECK-UNKNOWN: 05ffffff <unknown>
 
 sel     z23.s, p11, z13.s, z8.s
 // CHECK-INST: sel     z23.s, p11, z13.s, z8.s
 // CHECK-ENCODING: [0xb7,0xed,0xa8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed a8 05 <unknown>
+// CHECK-UNKNOWN: 05a8edb7 <unknown>
 
 sel     z23.d, p11, z13.d, z8.d
 // CHECK-INST: sel     z23.d, p11, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0xed,0xe8,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed e8 05 <unknown>
+// CHECK-UNKNOWN: 05e8edb7 <unknown>
 
 sel     z23.h, p11, z13.h, z8.h
 // CHECK-INST: sel     z23.h, p11, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0xed,0x68,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 68 05 <unknown>
+// CHECK-UNKNOWN: 0568edb7 <unknown>
 
 sel     z23.b, p11, z13.b, z8.b
 // CHECK-INST: sel     z23.b, p11, z13.b, z8.b
 // CHECK-ENCODING: [0xb7,0xed,0x28,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 28 05 <unknown>
+// CHECK-UNKNOWN: 0528edb7 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/setffr.s b/llvm/test/MC/AArch64/SVE/setffr.s
index 23e024f4e0b15..47a5d0eb96a0d 100644
--- a/llvm/test/MC/AArch64/SVE/setffr.s
+++ b/llvm/test/MC/AArch64/SVE/setffr.s
@@ -13,4 +13,4 @@ setffr
 // CHECK-INST: setffr
 // CHECK-ENCODING: [0x00,0x90,0x2c,0x25]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 90 2c 25 <unknown>
+// CHECK-UNKNOWN: 252c9000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/smax.s b/llvm/test/MC/AArch64/SVE/smax.s
index 852e93cdcdcab..978f24d624173 100644
--- a/llvm/test/MC/AArch64/SVE/smax.s
+++ b/llvm/test/MC/AArch64/SVE/smax.s
@@ -13,73 +13,73 @@ smax    z0.b, z0.b, #-128
 // CHECK-INST: smax	z0.b, z0.b, #-128
 // CHECK-ENCODING: [0x00,0xd0,0x28,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d0 28 25 <unknown>
+// CHECK-UNKNOWN: 2528d000 <unknown>
 
 smax    z31.b, z31.b, #127
 // CHECK-INST: smax	z31.b, z31.b, #127
 // CHECK-ENCODING: [0xff,0xcf,0x28,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf 28 25 <unknown>
+// CHECK-UNKNOWN: 2528cfff <unknown>
 
 smax    z0.h, z0.h, #-128
 // CHECK-INST: smax	z0.h, z0.h, #-128
 // CHECK-ENCODING: [0x00,0xd0,0x68,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d0 68 25 <unknown>
+// CHECK-UNKNOWN: 2568d000 <unknown>
 
 smax    z31.h, z31.h, #127
 // CHECK-INST: smax	z31.h, z31.h, #127
 // CHECK-ENCODING: [0xff,0xcf,0x68,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf 68 25 <unknown>
+// CHECK-UNKNOWN: 2568cfff <unknown>
 
 smax    z0.s, z0.s, #-128
 // CHECK-INST: smax	z0.s, z0.s, #-128
 // CHECK-ENCODING: [0x00,0xd0,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d0 a8 25 <unknown>
+// CHECK-UNKNOWN: 25a8d000 <unknown>
 
 smax    z31.s, z31.s, #127
 // CHECK-INST: smax	z31.s, z31.s, #127
 // CHECK-ENCODING: [0xff,0xcf,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf a8 25 <unknown>
+// CHECK-UNKNOWN: 25a8cfff <unknown>
 
 smax    z0.d, z0.d, #-128
 // CHECK-INST: smax	z0.d, z0.d, #-128
 // CHECK-ENCODING: [0x00,0xd0,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d0 e8 25 <unknown>
+// CHECK-UNKNOWN: 25e8d000 <unknown>
 
 smax    z31.d, z31.d, #127
 // CHECK-INST: smax	z31.d, z31.d, #127
 // CHECK-ENCODING: [0xff,0xcf,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf e8 25 <unknown>
+// CHECK-UNKNOWN: 25e8cfff <unknown>
 
 smax    z31.b, p7/m, z31.b, z31.b
 // CHECK-INST: smax    z31.b, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x1f,0x08,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 08 04 <unknown>
+// CHECK-UNKNOWN: 04081fff <unknown>
 
 smax    z31.h, p7/m, z31.h, z31.h
 // CHECK-INST: smax    z31.h, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x1f,0x48,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 48 04 <unknown>
+// CHECK-UNKNOWN: 04481fff <unknown>
 
 smax    z31.s, p7/m, z31.s, z31.s
 // CHECK-INST: smax    z31.s, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1f,0x88,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 88 04 <unknown>
+// CHECK-UNKNOWN: 04881fff <unknown>
 
 smax    z31.d, p7/m, z31.d, z31.d
 // CHECK-INST: smax    z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xc8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f c8 04 <unknown>
+// CHECK-UNKNOWN: 04c81fff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -89,34 +89,34 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 smax    z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: smax	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xc8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f c8 04 <unknown>
+// CHECK-UNKNOWN: 04c81fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 smax    z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: smax	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xc8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f c8 04 <unknown>
+// CHECK-UNKNOWN: 04c81fe4 <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 smax    z31.d, z31.d, #127
 // CHECK-INST: smax	z31.d, z31.d, #127
 // CHECK-ENCODING: [0xff,0xcf,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf e8 25 <unknown>
+// CHECK-UNKNOWN: 25e8cfff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/smaxv.s b/llvm/test/MC/AArch64/SVE/smaxv.s
index 264af22058811..0dbad545ad48d 100644
--- a/llvm/test/MC/AArch64/SVE/smaxv.s
+++ b/llvm/test/MC/AArch64/SVE/smaxv.s
@@ -13,22 +13,22 @@ smaxv b0, p7, z31.b
 // CHECK-INST: smaxv	b0, p7, z31.b
 // CHECK-ENCODING: [0xe0,0x3f,0x08,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 08 04 <unknown>
+// CHECK-UNKNOWN: 04083fe0 <unknown>
 
 smaxv h0, p7, z31.h
 // CHECK-INST: smaxv	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x48,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 48 04 <unknown>
+// CHECK-UNKNOWN: 04483fe0 <unknown>
 
 smaxv s0, p7, z31.s
 // CHECK-INST: smaxv	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x88,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 88 04 <unknown>
+// CHECK-UNKNOWN: 04883fe0 <unknown>
 
 smaxv d0, p7, z31.d
 // CHECK-INST: smaxv	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xc8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f c8 04 <unknown>
+// CHECK-UNKNOWN: 04c83fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/smin.s b/llvm/test/MC/AArch64/SVE/smin.s
index 4ea5114f66c34..493d280c6eeae 100644
--- a/llvm/test/MC/AArch64/SVE/smin.s
+++ b/llvm/test/MC/AArch64/SVE/smin.s
@@ -13,73 +13,73 @@ smin    z0.b, z0.b, #-128
 // CHECK-INST: smin	z0.b, z0.b, #-128
 // CHECK-ENCODING: [0x00,0xd0,0x2a,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d0 2a 25 <unknown>
+// CHECK-UNKNOWN: 252ad000 <unknown>
 
 smin    z31.b, z31.b, #127
 // CHECK-INST: smin	z31.b, z31.b, #127
 // CHECK-ENCODING: [0xff,0xcf,0x2a,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf 2a 25 <unknown>
+// CHECK-UNKNOWN: 252acfff <unknown>
 
 smin    z0.h, z0.h, #-128
 // CHECK-INST: smin	z0.h, z0.h, #-128
 // CHECK-ENCODING: [0x00,0xd0,0x6a,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d0 6a 25 <unknown>
+// CHECK-UNKNOWN: 256ad000 <unknown>
 
 smin    z31.h, z31.h, #127
 // CHECK-INST: smin	z31.h, z31.h, #127
 // CHECK-ENCODING: [0xff,0xcf,0x6a,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf 6a 25 <unknown>
+// CHECK-UNKNOWN: 256acfff <unknown>
 
 smin    z0.s, z0.s, #-128
 // CHECK-INST: smin	z0.s, z0.s, #-128
 // CHECK-ENCODING: [0x00,0xd0,0xaa,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d0 aa 25 <unknown>
+// CHECK-UNKNOWN: 25aad000 <unknown>
 
 smin    z31.s, z31.s, #127
 // CHECK-INST: smin	z31.s, z31.s, #127
 // CHECK-ENCODING: [0xff,0xcf,0xaa,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf aa 25 <unknown>
+// CHECK-UNKNOWN: 25aacfff <unknown>
 
 smin    z0.d, z0.d, #-128
 // CHECK-INST: smin	z0.d, z0.d, #-128
 // CHECK-ENCODING: [0x00,0xd0,0xea,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 d0 ea 25 <unknown>
+// CHECK-UNKNOWN: 25ead000 <unknown>
 
 smin    z31.d, z31.d, #127
 // CHECK-INST: smin	z31.d, z31.d, #127
 // CHECK-ENCODING: [0xff,0xcf,0xea,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf ea 25 <unknown>
+// CHECK-UNKNOWN: 25eacfff <unknown>
 
 smin    z31.b, p7/m, z31.b, z31.b
 // CHECK-INST: smin	z31.b, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x1f,0x0a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 0a 04 <unknown>
+// CHECK-UNKNOWN: 040a1fff <unknown>
 
 smin    z31.h, p7/m, z31.h, z31.h
 // CHECK-INST: smin	z31.h, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x1f,0x4a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 4a 04 <unknown>
+// CHECK-UNKNOWN: 044a1fff <unknown>
 
 smin    z31.s, p7/m, z31.s, z31.s
 // CHECK-INST: smin	z31.s, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1f,0x8a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 8a 04 <unknown>
+// CHECK-UNKNOWN: 048a1fff <unknown>
 
 smin    z31.d, p7/m, z31.d, z31.d
 // CHECK-INST: smin	z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xca,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f ca 04 <unknown>
+// CHECK-UNKNOWN: 04ca1fff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -89,34 +89,34 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 smin    z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: smin	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xca,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f ca 04 <unknown>
+// CHECK-UNKNOWN: 04ca1fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 smin    z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: smin	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xca,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f ca 04 <unknown>
+// CHECK-UNKNOWN: 04ca1fe4 <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 smin    z31.d, z31.d, #127
 // CHECK-INST: smin	z31.d, z31.d, #127
 // CHECK-ENCODING: [0xff,0xcf,0xea,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff cf ea 25 <unknown>
+// CHECK-UNKNOWN: 25eacfff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sminv.s b/llvm/test/MC/AArch64/SVE/sminv.s
index e9795e4b6727f..124bf8617fd5f 100644
--- a/llvm/test/MC/AArch64/SVE/sminv.s
+++ b/llvm/test/MC/AArch64/SVE/sminv.s
@@ -13,22 +13,22 @@ sminv b0, p7, z31.b
 // CHECK-INST: sminv	b0, p7, z31.b
 // CHECK-ENCODING: [0xe0,0x3f,0x0a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 0a 04 <unknown>
+// CHECK-UNKNOWN: 040a3fe0 <unknown>
 
 sminv h0, p7, z31.h
 // CHECK-INST: sminv	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x4a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 4a 04 <unknown>
+// CHECK-UNKNOWN: 044a3fe0 <unknown>
 
 sminv s0, p7, z31.s
 // CHECK-INST: sminv	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x8a,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 8a 04 <unknown>
+// CHECK-UNKNOWN: 048a3fe0 <unknown>
 
 sminv d0, p7, z31.d
 // CHECK-INST: sminv	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xca,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f ca 04 <unknown>
+// CHECK-UNKNOWN: 04ca3fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/smulh.s b/llvm/test/MC/AArch64/SVE/smulh.s
index 67da62c315249..8bef4bea31619 100644
--- a/llvm/test/MC/AArch64/SVE/smulh.s
+++ b/llvm/test/MC/AArch64/SVE/smulh.s
@@ -13,25 +13,25 @@ smulh z0.b, p7/m, z0.b, z31.b
 // CHECK-INST: smulh	z0.b, p7/m, z0.b, z31.b
 // CHECK-ENCODING: [0xe0,0x1f,0x12,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f 12 04 <unknown>
+// CHECK-UNKNOWN: 04121fe0 <unknown>
 
 smulh z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: smulh	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x1f,0x52,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f 52 04 <unknown>
+// CHECK-UNKNOWN: 04521fe0 <unknown>
 
 smulh z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: smulh	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x1f,0x92,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f 92 04 <unknown>
+// CHECK-UNKNOWN: 04921fe0 <unknown>
 
 smulh z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: smulh	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d2 04 <unknown>
+// CHECK-UNKNOWN: 04d21fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 smulh z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: smulh	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d2 04 <unknown>
+// CHECK-UNKNOWN: 04d21fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 smulh z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: smulh	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd2,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d2 04 <unknown>
+// CHECK-UNKNOWN: 04d21fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/splice.s b/llvm/test/MC/AArch64/SVE/splice.s
index 7b88c51823566..10338c511f95b 100644
--- a/llvm/test/MC/AArch64/SVE/splice.s
+++ b/llvm/test/MC/AArch64/SVE/splice.s
@@ -13,25 +13,25 @@ splice  z31.b, p7, z31.b, z31.b
 // CHECK-INST: splice  z31.b, p7, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x9f,0x2c,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f 2c 05 <unknown>
+// CHECK-UNKNOWN: 052c9fff <unknown>
 
 splice  z31.h, p7, z31.h, z31.h
 // CHECK-INST: splice  z31.h, p7, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x9f,0x6c,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f 6c 05 <unknown>
+// CHECK-UNKNOWN: 056c9fff <unknown>
 
 splice  z31.s, p7, z31.s, z31.s
 // CHECK-INST: splice  z31.s, p7, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x9f,0xac,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f ac 05 <unknown>
+// CHECK-UNKNOWN: 05ac9fff <unknown>
 
 splice  z31.d, p7, z31.d, z31.d
 // CHECK-INST: splice  z31.d, p7, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x9f,0xec,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 9f ec 05 <unknown>
+// CHECK-UNKNOWN: 05ec9fff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,10 +41,10 @@ movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 splice  z4.d, p7, z4.d, z31.d
 // CHECK-INST: splice	z4.d, p7, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x9f,0xec,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 9f ec 05 <unknown>
+// CHECK-UNKNOWN: 05ec9fe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sqadd.s b/llvm/test/MC/AArch64/SVE/sqadd.s
index eca60892b2090..8b4f9076a3dbf 100644
--- a/llvm/test/MC/AArch64/SVE/sqadd.s
+++ b/llvm/test/MC/AArch64/SVE/sqadd.s
@@ -14,109 +14,109 @@ sqadd     z0.b, z0.b, z0.b
 // CHECK-INST: sqadd z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x10,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 10 20 04 <unknown>
+// CHECK-UNKNOWN: 04201000 <unknown>
 
 sqadd     z0.h, z0.h, z0.h
 // CHECK-INST: sqadd z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x10,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 10 60 04 <unknown>
+// CHECK-UNKNOWN: 04601000 <unknown>
 
 sqadd     z0.s, z0.s, z0.s
 // CHECK-INST: sqadd z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x10,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 10 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a01000 <unknown>
 
 sqadd     z0.d, z0.d, z0.d
 // CHECK-INST: sqadd z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x10,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 10 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e01000 <unknown>
 
 sqadd     z0.b, z0.b, #0
 // CHECK-INST: sqadd z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x24,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 24 25 <unknown>
+// CHECK-UNKNOWN: 2524c000 <unknown>
 
 sqadd     z31.b, z31.b, #255
 // CHECK-INST: sqadd z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x24,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 24 25 <unknown>
+// CHECK-UNKNOWN: 2524dfff <unknown>
 
 sqadd     z0.h, z0.h, #0
 // CHECK-INST: sqadd z0.h, z0.h, #0
 // CHECK-ENCODING: [0x00,0xc0,0x64,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 64 25 <unknown>
+// CHECK-UNKNOWN: 2564c000 <unknown>
 
 sqadd     z0.h, z0.h, #0, lsl #8
 // CHECK-INST: sqadd z0.h, z0.h, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0x64,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 64 25 <unknown>
+// CHECK-UNKNOWN: 2564e000 <unknown>
 
 sqadd     z31.h, z31.h, #255, lsl #8
 // CHECK-INST: sqadd z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x64,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 64 25 <unknown>
+// CHECK-UNKNOWN: 2564ffff <unknown>
 
 sqadd     z31.h, z31.h, #65280
 // CHECK-INST: sqadd z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x64,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 64 25 <unknown>
+// CHECK-UNKNOWN: 2564ffff <unknown>
 
 sqadd     z0.s, z0.s, #0
 // CHECK-INST: sqadd z0.s, z0.s, #0
 // CHECK-ENCODING: [0x00,0xc0,0xa4,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 a4 25 <unknown>
+// CHECK-UNKNOWN: 25a4c000 <unknown>
 
 sqadd     z0.s, z0.s, #0, lsl #8
 // CHECK-INST: sqadd z0.s, z0.s, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xa4,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 a4 25 <unknown>
+// CHECK-UNKNOWN: 25a4e000 <unknown>
 
 sqadd     z31.s, z31.s, #255, lsl #8
 // CHECK-INST: sqadd z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa4,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a4 25 <unknown>
+// CHECK-UNKNOWN: 25a4ffff <unknown>
 
 sqadd     z31.s, z31.s, #65280
 // CHECK-INST: sqadd z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa4,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a4 25 <unknown>
+// CHECK-UNKNOWN: 25a4ffff <unknown>
 
 sqadd     z0.d, z0.d, #0
 // CHECK-INST: sqadd z0.d, z0.d, #0
 // CHECK-ENCODING: [0x00,0xc0,0xe4,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 e4 25 <unknown>
+// CHECK-UNKNOWN: 25e4c000 <unknown>
 
 sqadd     z0.d, z0.d, #0, lsl #8
 // CHECK-INST: sqadd z0.d, z0.d, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xe4,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e4 25 <unknown>
+// CHECK-UNKNOWN: 25e4e000 <unknown>
 
 sqadd     z31.d, z31.d, #255, lsl #8
 // CHECK-INST: sqadd z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe4,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e4 25 <unknown>
+// CHECK-UNKNOWN: 25e4ffff <unknown>
 
 sqadd     z31.d, z31.d, #65280
 // CHECK-INST: sqadd z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe4,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e4 25 <unknown>
+// CHECK-UNKNOWN: 25e4ffff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -126,10 +126,10 @@ movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sqadd     z31.d, z31.d, #65280
 // CHECK-INST: sqadd	z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe4,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e4 25 <unknown>
+// CHECK-UNKNOWN: 25e4ffff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sqdecb.s b/llvm/test/MC/AArch64/SVE/sqdecb.s
index 3256429ea0f99..398446bf146d4 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecb.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecb.s
@@ -17,25 +17,25 @@ sqdecb  x0
 // CHECK-INST: sqdecb  x0
 // CHECK-ENCODING: [0xe0,0xfb,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fbe0 <unknown>
 
 sqdecb  x0, all
 // CHECK-INST: sqdecb  x0
 // CHECK-ENCODING: [0xe0,0xfb,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fbe0 <unknown>
 
 sqdecb  x0, all, mul #1
 // CHECK-INST: sqdecb  x0
 // CHECK-ENCODING: [0xe0,0xfb,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fbe0 <unknown>
 
 sqdecb  x0, all, mul #16
 // CHECK-INST: sqdecb  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xfb,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 3f 04 <unknown>
+// CHECK-UNKNOWN: 043ffbe0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ sqdecb  x0, w0
 // CHECK-INST: sqdecb  x0, w0
 // CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
+// CHECK-UNKNOWN: 0420fbe0 <unknown>
 
 sqdecb  x0, w0, all
 // CHECK-INST: sqdecb  x0, w0
 // CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
+// CHECK-UNKNOWN: 0420fbe0 <unknown>
 
 sqdecb  x0, w0, all, mul #1
 // CHECK-INST: sqdecb  x0, w0
 // CHECK-ENCODING: [0xe0,0xfb,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 20 04 <unknown>
+// CHECK-UNKNOWN: 0420fbe0 <unknown>
 
 sqdecb  x0, w0, all, mul #16
 // CHECK-INST: sqdecb  x0, w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xfb,0x2f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 2f 04 <unknown>
+// CHECK-UNKNOWN: 042ffbe0 <unknown>
 
 sqdecb  x0, w0, pow2
 // CHECK-INST: sqdecb  x0, w0, pow2
 // CHECK-ENCODING: [0x00,0xf8,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f8 20 04 <unknown>
+// CHECK-UNKNOWN: 0420f800 <unknown>
 
 sqdecb  x0, w0, pow2, mul #16
 // CHECK-INST: sqdecb  x0, w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xf8,0x2f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f8 2f 04 <unknown>
+// CHECK-UNKNOWN: 042ff800 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -87,172 +87,172 @@ sqdecb  x0, pow2
 // CHECK-INST: sqdecb  x0, pow2
 // CHECK-ENCODING: [0x00,0xf8,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f8 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f800 <unknown>
 
 sqdecb  x0, vl1
 // CHECK-INST: sqdecb  x0, vl1
 // CHECK-ENCODING: [0x20,0xf8,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f820 <unknown>
 
 sqdecb  x0, vl2
 // CHECK-INST: sqdecb  x0, vl2
 // CHECK-ENCODING: [0x40,0xf8,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f8 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f840 <unknown>
 
 sqdecb  x0, vl3
 // CHECK-INST: sqdecb  x0, vl3
 // CHECK-ENCODING: [0x60,0xf8,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f8 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f860 <unknown>
 
 sqdecb  x0, vl4
 // CHECK-INST: sqdecb  x0, vl4
 // CHECK-ENCODING: [0x80,0xf8,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f8 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f880 <unknown>
 
 sqdecb  x0, vl5
 // CHECK-INST: sqdecb  x0, vl5
 // CHECK-ENCODING: [0xa0,0xf8,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f8 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f8a0 <unknown>
 
 sqdecb  x0, vl6
 // CHECK-INST: sqdecb  x0, vl6
 // CHECK-ENCODING: [0xc0,0xf8,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f8 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f8c0 <unknown>
 
 sqdecb  x0, vl7
 // CHECK-INST: sqdecb  x0, vl7
 // CHECK-ENCODING: [0xe0,0xf8,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f8 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f8e0 <unknown>
 
 sqdecb  x0, vl8
 // CHECK-INST: sqdecb  x0, vl8
 // CHECK-ENCODING: [0x00,0xf9,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f9 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f900 <unknown>
 
 sqdecb  x0, vl16
 // CHECK-INST: sqdecb  x0, vl16
 // CHECK-ENCODING: [0x20,0xf9,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f9 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f920 <unknown>
 
 sqdecb  x0, vl32
 // CHECK-INST: sqdecb  x0, vl32
 // CHECK-ENCODING: [0x40,0xf9,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f9 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f940 <unknown>
 
 sqdecb  x0, vl64
 // CHECK-INST: sqdecb  x0, vl64
 // CHECK-ENCODING: [0x60,0xf9,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f9 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f960 <unknown>
 
 sqdecb  x0, vl128
 // CHECK-INST: sqdecb  x0, vl128
 // CHECK-ENCODING: [0x80,0xf9,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f9 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f980 <unknown>
 
 sqdecb  x0, vl256
 // CHECK-INST: sqdecb  x0, vl256
 // CHECK-ENCODING: [0xa0,0xf9,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f9 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f9a0 <unknown>
 
 sqdecb  x0, #14
 // CHECK-INST: sqdecb  x0, #14
 // CHECK-ENCODING: [0xc0,0xf9,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f9 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f9c0 <unknown>
 
 sqdecb  x0, #15
 // CHECK-INST: sqdecb  x0, #15
 // CHECK-ENCODING: [0xe0,0xf9,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f9 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f9e0 <unknown>
 
 sqdecb  x0, #16
 // CHECK-INST: sqdecb  x0, #16
 // CHECK-ENCODING: [0x00,0xfa,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fa 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fa00 <unknown>
 
 sqdecb  x0, #17
 // CHECK-INST: sqdecb  x0, #17
 // CHECK-ENCODING: [0x20,0xfa,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fa 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fa20 <unknown>
 
 sqdecb  x0, #18
 // CHECK-INST: sqdecb  x0, #18
 // CHECK-ENCODING: [0x40,0xfa,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fa 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fa40 <unknown>
 
 sqdecb  x0, #19
 // CHECK-INST: sqdecb  x0, #19
 // CHECK-ENCODING: [0x60,0xfa,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fa 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fa60 <unknown>
 
 sqdecb  x0, #20
 // CHECK-INST: sqdecb  x0, #20
 // CHECK-ENCODING: [0x80,0xfa,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fa 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fa80 <unknown>
 
 sqdecb  x0, #21
 // CHECK-INST: sqdecb  x0, #21
 // CHECK-ENCODING: [0xa0,0xfa,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fa 30 04 <unknown>
+// CHECK-UNKNOWN: 0430faa0 <unknown>
 
 sqdecb  x0, #22
 // CHECK-INST: sqdecb  x0, #22
 // CHECK-ENCODING: [0xc0,0xfa,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fa 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fac0 <unknown>
 
 sqdecb  x0, #23
 // CHECK-INST: sqdecb  x0, #23
 // CHECK-ENCODING: [0xe0,0xfa,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fa 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fae0 <unknown>
 
 sqdecb  x0, #24
 // CHECK-INST: sqdecb  x0, #24
 // CHECK-ENCODING: [0x00,0xfb,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fb 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fb00 <unknown>
 
 sqdecb  x0, #25
 // CHECK-INST: sqdecb  x0, #25
 // CHECK-ENCODING: [0x20,0xfb,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fb 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fb20 <unknown>
 
 sqdecb  x0, #26
 // CHECK-INST: sqdecb  x0, #26
 // CHECK-ENCODING: [0x40,0xfb,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fb 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fb40 <unknown>
 
 sqdecb  x0, #27
 // CHECK-INST: sqdecb  x0, #27
 // CHECK-ENCODING: [0x60,0xfb,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fb 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fb60 <unknown>
 
 sqdecb  x0, #28
 // CHECK-INST: sqdecb  x0, #28
 // CHECK-ENCODING: [0x80,0xfb,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fb 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fb80 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sqdecd.s b/llvm/test/MC/AArch64/SVE/sqdecd.s
index a0e342e75a8d5..e7b5b906be3a1 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecd.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecd.s
@@ -17,25 +17,25 @@ sqdecd  x0
 // CHECK-INST: sqdecd  x0
 // CHECK-ENCODING: [0xe0,0xfb,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fbe0 <unknown>
 
 sqdecd  x0, all
 // CHECK-INST: sqdecd  x0
 // CHECK-ENCODING: [0xe0,0xfb,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fbe0 <unknown>
 
 sqdecd  x0, all, mul #1
 // CHECK-INST: sqdecd  x0
 // CHECK-ENCODING: [0xe0,0xfb,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fbe0 <unknown>
 
 sqdecd  x0, all, mul #16
 // CHECK-INST: sqdecd  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xfb,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb ff 04 <unknown>
+// CHECK-UNKNOWN: 04fffbe0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ sqdecd  x0, w0
 // CHECK-INST: sqdecd  x0, w0
 // CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0fbe0 <unknown>
 
 sqdecd  x0, w0, all
 // CHECK-INST: sqdecd  x0, w0
 // CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0fbe0 <unknown>
 
 sqdecd  x0, w0, all, mul #1
 // CHECK-INST: sqdecd  x0, w0
 // CHECK-ENCODING: [0xe0,0xfb,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0fbe0 <unknown>
 
 sqdecd  x0, w0, all, mul #16
 // CHECK-INST: sqdecd  x0, w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xfb,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb ef 04 <unknown>
+// CHECK-UNKNOWN: 04effbe0 <unknown>
 
 sqdecd  x0, w0, pow2
 // CHECK-INST: sqdecd  x0, w0, pow2
 // CHECK-ENCODING: [0x00,0xf8,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f8 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0f800 <unknown>
 
 sqdecd  x0, w0, pow2, mul #16
 // CHECK-INST: sqdecd  x0, w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xf8,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f8 ef 04 <unknown>
+// CHECK-UNKNOWN: 04eff800 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -86,37 +86,37 @@ sqdecd  z0.d
 // CHECK-INST: sqdecd  z0.d
 // CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0cbe0 <unknown>
 
 sqdecd  z0.d, all
 // CHECK-INST: sqdecd  z0.d
 // CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0cbe0 <unknown>
 
 sqdecd  z0.d, all, mul #1
 // CHECK-INST: sqdecd  z0.d
 // CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0cbe0 <unknown>
 
 sqdecd  z0.d, all, mul #16
 // CHECK-INST: sqdecd  z0.d, all, mul #16
 // CHECK-ENCODING: [0xe0,0xcb,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb ef 04 <unknown>
+// CHECK-UNKNOWN: 04efcbe0 <unknown>
 
 sqdecd  z0.d, pow2
 // CHECK-INST: sqdecd  z0.d, pow2
 // CHECK-ENCODING: [0x00,0xc8,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c800 <unknown>
 
 sqdecd  z0.d, pow2, mul #16
 // CHECK-INST: sqdecd  z0.d, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc8,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 ef 04 <unknown>
+// CHECK-UNKNOWN: 04efc800 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -127,175 +127,175 @@ sqdecd  x0, pow2
 // CHECK-INST: sqdecd  x0, pow2
 // CHECK-ENCODING: [0x00,0xf8,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f8 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f800 <unknown>
 
 sqdecd  x0, vl1
 // CHECK-INST: sqdecd  x0, vl1
 // CHECK-ENCODING: [0x20,0xf8,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f820 <unknown>
 
 sqdecd  x0, vl2
 // CHECK-INST: sqdecd  x0, vl2
 // CHECK-ENCODING: [0x40,0xf8,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f8 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f840 <unknown>
 
 sqdecd  x0, vl3
 // CHECK-INST: sqdecd  x0, vl3
 // CHECK-ENCODING: [0x60,0xf8,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f8 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f860 <unknown>
 
 sqdecd  x0, vl4
 // CHECK-INST: sqdecd  x0, vl4
 // CHECK-ENCODING: [0x80,0xf8,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f8 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f880 <unknown>
 
 sqdecd  x0, vl5
 // CHECK-INST: sqdecd  x0, vl5
 // CHECK-ENCODING: [0xa0,0xf8,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f8 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f8a0 <unknown>
 
 sqdecd  x0, vl6
 // CHECK-INST: sqdecd  x0, vl6
 // CHECK-ENCODING: [0xc0,0xf8,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f8 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f8c0 <unknown>
 
 sqdecd  x0, vl7
 // CHECK-INST: sqdecd  x0, vl7
 // CHECK-ENCODING: [0xe0,0xf8,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f8 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f8e0 <unknown>
 
 sqdecd  x0, vl8
 // CHECK-INST: sqdecd  x0, vl8
 // CHECK-ENCODING: [0x00,0xf9,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f9 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f900 <unknown>
 
 sqdecd  x0, vl16
 // CHECK-INST: sqdecd  x0, vl16
 // CHECK-ENCODING: [0x20,0xf9,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f9 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f920 <unknown>
 
 sqdecd  x0, vl32
 // CHECK-INST: sqdecd  x0, vl32
 // CHECK-ENCODING: [0x40,0xf9,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f9 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f940 <unknown>
 
 sqdecd  x0, vl64
 // CHECK-INST: sqdecd  x0, vl64
 // CHECK-ENCODING: [0x60,0xf9,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f9 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f960 <unknown>
 
 sqdecd  x0, vl128
 // CHECK-INST: sqdecd  x0, vl128
 // CHECK-ENCODING: [0x80,0xf9,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f9 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f980 <unknown>
 
 sqdecd  x0, vl256
 // CHECK-INST: sqdecd  x0, vl256
 // CHECK-ENCODING: [0xa0,0xf9,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f9 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f9a0 <unknown>
 
 sqdecd  x0, #14
 // CHECK-INST: sqdecd  x0, #14
 // CHECK-ENCODING: [0xc0,0xf9,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f9 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f9c0 <unknown>
 
 sqdecd  x0, #15
 // CHECK-INST: sqdecd  x0, #15
 // CHECK-ENCODING: [0xe0,0xf9,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f9 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f9e0 <unknown>
 
 sqdecd  x0, #16
 // CHECK-INST: sqdecd  x0, #16
 // CHECK-ENCODING: [0x00,0xfa,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fa f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fa00 <unknown>
 
 sqdecd  x0, #17
 // CHECK-INST: sqdecd  x0, #17
 // CHECK-ENCODING: [0x20,0xfa,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fa f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fa20 <unknown>
 
 sqdecd  x0, #18
 // CHECK-INST: sqdecd  x0, #18
 // CHECK-ENCODING: [0x40,0xfa,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fa f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fa40 <unknown>
 
 sqdecd  x0, #19
 // CHECK-INST: sqdecd  x0, #19
 // CHECK-ENCODING: [0x60,0xfa,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fa f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fa60 <unknown>
 
 sqdecd  x0, #20
 // CHECK-INST: sqdecd  x0, #20
 // CHECK-ENCODING: [0x80,0xfa,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fa f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fa80 <unknown>
 
 sqdecd  x0, #21
 // CHECK-INST: sqdecd  x0, #21
 // CHECK-ENCODING: [0xa0,0xfa,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fa f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0faa0 <unknown>
 
 sqdecd  x0, #22
 // CHECK-INST: sqdecd  x0, #22
 // CHECK-ENCODING: [0xc0,0xfa,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fa f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fac0 <unknown>
 
 sqdecd  x0, #23
 // CHECK-INST: sqdecd  x0, #23
 // CHECK-ENCODING: [0xe0,0xfa,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fa f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fae0 <unknown>
 
 sqdecd  x0, #24
 // CHECK-INST: sqdecd  x0, #24
 // CHECK-ENCODING: [0x00,0xfb,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fb f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fb00 <unknown>
 
 sqdecd  x0, #25
 // CHECK-INST: sqdecd  x0, #25
 // CHECK-ENCODING: [0x20,0xfb,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fb f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fb20 <unknown>
 
 sqdecd  x0, #26
 // CHECK-INST: sqdecd  x0, #26
 // CHECK-ENCODING: [0x40,0xfb,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fb f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fb40 <unknown>
 
 sqdecd  x0, #27
 // CHECK-INST: sqdecd  x0, #27
 // CHECK-ENCODING: [0x60,0xfb,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fb f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fb60 <unknown>
 
 sqdecd  x0, #28
 // CHECK-INST: sqdecd  x0, #28
 // CHECK-ENCODING: [0x80,0xfb,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fb f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fb80 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -305,34 +305,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqdecd  z0.d
 // CHECK-INST: sqdecd	z0.d
 // CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0cbe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqdecd  z0.d, pow2, mul #16
 // CHECK-INST: sqdecd	z0.d, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc8,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 ef 04 <unknown>
+// CHECK-UNKNOWN: 04efc800 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqdecd  z0.d, pow2
 // CHECK-INST: sqdecd	z0.d, pow2
 // CHECK-ENCODING: [0x00,0xc8,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c800 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sqdech.s b/llvm/test/MC/AArch64/SVE/sqdech.s
index d083fb88930c9..a0c8da4f16751 100644
--- a/llvm/test/MC/AArch64/SVE/sqdech.s
+++ b/llvm/test/MC/AArch64/SVE/sqdech.s
@@ -17,25 +17,25 @@ sqdech  x0
 // CHECK-INST: sqdech  x0
 // CHECK-ENCODING: [0xe0,0xfb,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fbe0 <unknown>
 
 sqdech  x0, all
 // CHECK-INST: sqdech  x0
 // CHECK-ENCODING: [0xe0,0xfb,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fbe0 <unknown>
 
 sqdech  x0, all, mul #1
 // CHECK-INST: sqdech  x0
 // CHECK-ENCODING: [0xe0,0xfb,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fbe0 <unknown>
 
 sqdech  x0, all, mul #16
 // CHECK-INST: sqdech  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xfb,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 7f 04 <unknown>
+// CHECK-UNKNOWN: 047ffbe0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ sqdech  x0, w0
 // CHECK-INST: sqdech  x0, w0
 // CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
+// CHECK-UNKNOWN: 0460fbe0 <unknown>
 
 sqdech  x0, w0, all
 // CHECK-INST: sqdech  x0, w0
 // CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
+// CHECK-UNKNOWN: 0460fbe0 <unknown>
 
 sqdech  x0, w0, all, mul #1
 // CHECK-INST: sqdech  x0, w0
 // CHECK-ENCODING: [0xe0,0xfb,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 60 04 <unknown>
+// CHECK-UNKNOWN: 0460fbe0 <unknown>
 
 sqdech  x0, w0, all, mul #16
 // CHECK-INST: sqdech  x0, w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xfb,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb 6f 04 <unknown>
+// CHECK-UNKNOWN: 046ffbe0 <unknown>
 
 sqdech  x0, w0, pow2
 // CHECK-INST: sqdech  x0, w0, pow2
 // CHECK-ENCODING: [0x00,0xf8,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f8 60 04 <unknown>
+// CHECK-UNKNOWN: 0460f800 <unknown>
 
 sqdech  x0, w0, pow2, mul #16
 // CHECK-INST: sqdech  x0, w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xf8,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f8 6f 04 <unknown>
+// CHECK-UNKNOWN: 046ff800 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -86,37 +86,37 @@ sqdech  z0.h
 // CHECK-INST: sqdech  z0.h
 // CHECK-ENCODING: [0xe0,0xcb,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb 60 04 <unknown>
+// CHECK-UNKNOWN: 0460cbe0 <unknown>
 
 sqdech  z0.h, all
 // CHECK-INST: sqdech  z0.h
 // CHECK-ENCODING: [0xe0,0xcb,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb 60 04 <unknown>
+// CHECK-UNKNOWN: 0460cbe0 <unknown>
 
 sqdech  z0.h, all, mul #1
 // CHECK-INST: sqdech  z0.h
 // CHECK-ENCODING: [0xe0,0xcb,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb 60 04 <unknown>
+// CHECK-UNKNOWN: 0460cbe0 <unknown>
 
 sqdech  z0.h, all, mul #16
 // CHECK-INST: sqdech  z0.h, all, mul #16
 // CHECK-ENCODING: [0xe0,0xcb,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fcbe0 <unknown>
 
 sqdech  z0.h, pow2
 // CHECK-INST: sqdech  z0.h, pow2
 // CHECK-ENCODING: [0x00,0xc8,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c800 <unknown>
 
 sqdech  z0.h, pow2, mul #16
 // CHECK-INST: sqdech  z0.h, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc8,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fc800 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -127,175 +127,175 @@ sqdech  x0, pow2
 // CHECK-INST: sqdech  x0, pow2
 // CHECK-ENCODING: [0x00,0xf8,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f8 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f800 <unknown>
 
 sqdech  x0, vl1
 // CHECK-INST: sqdech  x0, vl1
 // CHECK-ENCODING: [0x20,0xf8,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f820 <unknown>
 
 sqdech  x0, vl2
 // CHECK-INST: sqdech  x0, vl2
 // CHECK-ENCODING: [0x40,0xf8,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f8 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f840 <unknown>
 
 sqdech  x0, vl3
 // CHECK-INST: sqdech  x0, vl3
 // CHECK-ENCODING: [0x60,0xf8,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f8 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f860 <unknown>
 
 sqdech  x0, vl4
 // CHECK-INST: sqdech  x0, vl4
 // CHECK-ENCODING: [0x80,0xf8,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f8 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f880 <unknown>
 
 sqdech  x0, vl5
 // CHECK-INST: sqdech  x0, vl5
 // CHECK-ENCODING: [0xa0,0xf8,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f8 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f8a0 <unknown>
 
 sqdech  x0, vl6
 // CHECK-INST: sqdech  x0, vl6
 // CHECK-ENCODING: [0xc0,0xf8,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f8 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f8c0 <unknown>
 
 sqdech  x0, vl7
 // CHECK-INST: sqdech  x0, vl7
 // CHECK-ENCODING: [0xe0,0xf8,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f8 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f8e0 <unknown>
 
 sqdech  x0, vl8
 // CHECK-INST: sqdech  x0, vl8
 // CHECK-ENCODING: [0x00,0xf9,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f9 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f900 <unknown>
 
 sqdech  x0, vl16
 // CHECK-INST: sqdech  x0, vl16
 // CHECK-ENCODING: [0x20,0xf9,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f9 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f920 <unknown>
 
 sqdech  x0, vl32
 // CHECK-INST: sqdech  x0, vl32
 // CHECK-ENCODING: [0x40,0xf9,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f9 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f940 <unknown>
 
 sqdech  x0, vl64
 // CHECK-INST: sqdech  x0, vl64
 // CHECK-ENCODING: [0x60,0xf9,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f9 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f960 <unknown>
 
 sqdech  x0, vl128
 // CHECK-INST: sqdech  x0, vl128
 // CHECK-ENCODING: [0x80,0xf9,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f9 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f980 <unknown>
 
 sqdech  x0, vl256
 // CHECK-INST: sqdech  x0, vl256
 // CHECK-ENCODING: [0xa0,0xf9,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f9 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f9a0 <unknown>
 
 sqdech  x0, #14
 // CHECK-INST: sqdech  x0, #14
 // CHECK-ENCODING: [0xc0,0xf9,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f9 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f9c0 <unknown>
 
 sqdech  x0, #15
 // CHECK-INST: sqdech  x0, #15
 // CHECK-ENCODING: [0xe0,0xf9,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f9 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f9e0 <unknown>
 
 sqdech  x0, #16
 // CHECK-INST: sqdech  x0, #16
 // CHECK-ENCODING: [0x00,0xfa,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fa 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fa00 <unknown>
 
 sqdech  x0, #17
 // CHECK-INST: sqdech  x0, #17
 // CHECK-ENCODING: [0x20,0xfa,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fa 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fa20 <unknown>
 
 sqdech  x0, #18
 // CHECK-INST: sqdech  x0, #18
 // CHECK-ENCODING: [0x40,0xfa,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fa 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fa40 <unknown>
 
 sqdech  x0, #19
 // CHECK-INST: sqdech  x0, #19
 // CHECK-ENCODING: [0x60,0xfa,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fa 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fa60 <unknown>
 
 sqdech  x0, #20
 // CHECK-INST: sqdech  x0, #20
 // CHECK-ENCODING: [0x80,0xfa,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fa 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fa80 <unknown>
 
 sqdech  x0, #21
 // CHECK-INST: sqdech  x0, #21
 // CHECK-ENCODING: [0xa0,0xfa,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fa 70 04 <unknown>
+// CHECK-UNKNOWN: 0470faa0 <unknown>
 
 sqdech  x0, #22
 // CHECK-INST: sqdech  x0, #22
 // CHECK-ENCODING: [0xc0,0xfa,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fa 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fac0 <unknown>
 
 sqdech  x0, #23
 // CHECK-INST: sqdech  x0, #23
 // CHECK-ENCODING: [0xe0,0xfa,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fa 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fae0 <unknown>
 
 sqdech  x0, #24
 // CHECK-INST: sqdech  x0, #24
 // CHECK-ENCODING: [0x00,0xfb,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fb 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fb00 <unknown>
 
 sqdech  x0, #25
 // CHECK-INST: sqdech  x0, #25
 // CHECK-ENCODING: [0x20,0xfb,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fb 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fb20 <unknown>
 
 sqdech  x0, #26
 // CHECK-INST: sqdech  x0, #26
 // CHECK-ENCODING: [0x40,0xfb,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fb 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fb40 <unknown>
 
 sqdech  x0, #27
 // CHECK-INST: sqdech  x0, #27
 // CHECK-ENCODING: [0x60,0xfb,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fb 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fb60 <unknown>
 
 sqdech  x0, #28
 // CHECK-INST: sqdech  x0, #28
 // CHECK-ENCODING: [0x80,0xfb,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fb 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fb80 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -305,34 +305,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqdech  z0.h
 // CHECK-INST: sqdech	z0.h
 // CHECK-ENCODING: [0xe0,0xcb,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb 60 04 <unknown>
+// CHECK-UNKNOWN: 0460cbe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqdech  z0.h, pow2, mul #16
 // CHECK-INST: sqdech	z0.h, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc8,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fc800 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqdech  z0.h, pow2
 // CHECK-INST: sqdech	z0.h, pow2
 // CHECK-ENCODING: [0x00,0xc8,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c800 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sqdecp.s b/llvm/test/MC/AArch64/SVE/sqdecp.s
index c2d56c28f25ea..4024ddf25395c 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecp.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecp.s
@@ -13,85 +13,85 @@ sqdecp  x0, p0.b
 // CHECK-INST: sqdecp x0, p0.b
 // CHECK-ENCODING: [0x00,0x8c,0x2a,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c 2a 25 <unknown>
+// CHECK-UNKNOWN: 252a8c00 <unknown>
 
 sqdecp  x0, p0.h
 // CHECK-INST: sqdecp x0, p0.h
 // CHECK-ENCODING: [0x00,0x8c,0x6a,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c 6a 25 <unknown>
+// CHECK-UNKNOWN: 256a8c00 <unknown>
 
 sqdecp  x0, p0.s
 // CHECK-INST: sqdecp x0, p0.s
 // CHECK-ENCODING: [0x00,0x8c,0xaa,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c aa 25 <unknown>
+// CHECK-UNKNOWN: 25aa8c00 <unknown>
 
 sqdecp  x0, p0.d
 // CHECK-INST: sqdecp x0, p0.d
 // CHECK-ENCODING: [0x00,0x8c,0xea,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c ea 25 <unknown>
+// CHECK-UNKNOWN: 25ea8c00 <unknown>
 
 sqdecp  xzr, p15.b, wzr
 // CHECK-INST: sqdecp xzr, p15.b, wzr
 // CHECK-ENCODING: [0xff,0x89,0x2a,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 2a 25 <unknown>
+// CHECK-UNKNOWN: 252a89ff <unknown>
 
 sqdecp  xzr, p15.h, wzr
 // CHECK-INST: sqdecp xzr, p15.h, wzr
 // CHECK-ENCODING: [0xff,0x89,0x6a,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 6a 25 <unknown>
+// CHECK-UNKNOWN: 256a89ff <unknown>
 
 sqdecp  xzr, p15.s, wzr
 // CHECK-INST: sqdecp xzr, p15.s, wzr
 // CHECK-ENCODING: [0xff,0x89,0xaa,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 aa 25 <unknown>
+// CHECK-UNKNOWN: 25aa89ff <unknown>
 
 sqdecp  xzr, p15.d, wzr
 // CHECK-INST: sqdecp xzr, p15.d, wzr
 // CHECK-ENCODING: [0xff,0x89,0xea,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 ea 25 <unknown>
+// CHECK-UNKNOWN: 25ea89ff <unknown>
 
 sqdecp  z0.h, p0
 // CHECK-INST: sqdecp z0.h, p0.h
 // CHECK-ENCODING: [0x00,0x80,0x6a,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 6a 25 <unknown>
+// CHECK-UNKNOWN: 256a8000 <unknown>
 
 sqdecp  z0.h, p0.h
 // CHECK-INST: sqdecp z0.h, p0.h
 // CHECK-ENCODING: [0x00,0x80,0x6a,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 6a 25 <unknown>
+// CHECK-UNKNOWN: 256a8000 <unknown>
 
 sqdecp  z0.s, p0
 // CHECK-INST: sqdecp z0.s, p0.s
 // CHECK-ENCODING: [0x00,0x80,0xaa,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 aa 25 <unknown>
+// CHECK-UNKNOWN: 25aa8000 <unknown>
 
 sqdecp  z0.s, p0.s
 // CHECK-INST: sqdecp z0.s, p0.s
 // CHECK-ENCODING: [0x00,0x80,0xaa,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 aa 25 <unknown>
+// CHECK-UNKNOWN: 25aa8000 <unknown>
 
 sqdecp  z0.d, p0
 // CHECK-INST: sqdecp z0.d, p0.d
 // CHECK-ENCODING: [0x00,0x80,0xea,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 ea 25 <unknown>
+// CHECK-UNKNOWN: 25ea8000 <unknown>
 
 sqdecp  z0.d, p0.d
 // CHECK-INST: sqdecp z0.d, p0.d
 // CHECK-ENCODING: [0x00,0x80,0xea,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 ea 25 <unknown>
+// CHECK-UNKNOWN: 25ea8000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -101,10 +101,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqdecp  z0.d, p0.d
 // CHECK-INST: sqdecp	z0.d, p0.d
 // CHECK-ENCODING: [0x00,0x80,0xea,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 ea 25 <unknown>
+// CHECK-UNKNOWN: 25ea8000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sqdecw.s b/llvm/test/MC/AArch64/SVE/sqdecw.s
index 339ab01c80fee..c5519e29680ef 100644
--- a/llvm/test/MC/AArch64/SVE/sqdecw.s
+++ b/llvm/test/MC/AArch64/SVE/sqdecw.s
@@ -17,25 +17,25 @@ sqdecw  x0
 // CHECK-INST: sqdecw  x0
 // CHECK-ENCODING: [0xe0,0xfb,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fbe0 <unknown>
 
 sqdecw  x0, all
 // CHECK-INST: sqdecw  x0
 // CHECK-ENCODING: [0xe0,0xfb,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fbe0 <unknown>
 
 sqdecw  x0, all, mul #1
 // CHECK-INST: sqdecw  x0
 // CHECK-ENCODING: [0xe0,0xfb,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fbe0 <unknown>
 
 sqdecw  x0, all, mul #16
 // CHECK-INST: sqdecw  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xfb,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb bf 04 <unknown>
+// CHECK-UNKNOWN: 04bffbe0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ sqdecw  x0, w0
 // CHECK-INST: sqdecw  x0, w0
 // CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0fbe0 <unknown>
 
 sqdecw  x0, w0, all
 // CHECK-INST: sqdecw  x0, w0
 // CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0fbe0 <unknown>
 
 sqdecw  x0, w0, all, mul #1
 // CHECK-INST: sqdecw  x0, w0
 // CHECK-ENCODING: [0xe0,0xfb,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0fbe0 <unknown>
 
 sqdecw  x0, w0, all, mul #16
 // CHECK-INST: sqdecw  x0, w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xfb,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fb af 04 <unknown>
+// CHECK-UNKNOWN: 04affbe0 <unknown>
 
 sqdecw  x0, w0, pow2
 // CHECK-INST: sqdecw  x0, w0, pow2
 // CHECK-ENCODING: [0x00,0xf8,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f8 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0f800 <unknown>
 
 sqdecw  x0, w0, pow2, mul #16
 // CHECK-INST: sqdecw  x0, w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xf8,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f8 af 04 <unknown>
+// CHECK-UNKNOWN: 04aff800 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -86,37 +86,37 @@ sqdecw  z0.s
 // CHECK-INST: sqdecw  z0.s
 // CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0cbe0 <unknown>
 
 sqdecw  z0.s, all
 // CHECK-INST: sqdecw  z0.s
 // CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0cbe0 <unknown>
 
 sqdecw  z0.s, all, mul #1
 // CHECK-INST: sqdecw  z0.s
 // CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0cbe0 <unknown>
 
 sqdecw  z0.s, all, mul #16
 // CHECK-INST: sqdecw  z0.s, all, mul #16
 // CHECK-ENCODING: [0xe0,0xcb,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb af 04 <unknown>
+// CHECK-UNKNOWN: 04afcbe0 <unknown>
 
 sqdecw  z0.s, pow2
 // CHECK-INST: sqdecw  z0.s, pow2
 // CHECK-ENCODING: [0x00,0xc8,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c800 <unknown>
 
 sqdecw  z0.s, pow2, mul #16
 // CHECK-INST: sqdecw  z0.s, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc8,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 af 04 <unknown>
+// CHECK-UNKNOWN: 04afc800 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -127,175 +127,175 @@ sqdecw  x0, pow2
 // CHECK-INST: sqdecw  x0, pow2
 // CHECK-ENCODING: [0x00,0xf8,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f8 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f800 <unknown>
 
 sqdecw  x0, vl1
 // CHECK-INST: sqdecw  x0, vl1
 // CHECK-ENCODING: [0x20,0xf8,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f8 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f820 <unknown>
 
 sqdecw  x0, vl2
 // CHECK-INST: sqdecw  x0, vl2
 // CHECK-ENCODING: [0x40,0xf8,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f8 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f840 <unknown>
 
 sqdecw  x0, vl3
 // CHECK-INST: sqdecw  x0, vl3
 // CHECK-ENCODING: [0x60,0xf8,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f8 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f860 <unknown>
 
 sqdecw  x0, vl4
 // CHECK-INST: sqdecw  x0, vl4
 // CHECK-ENCODING: [0x80,0xf8,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f8 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f880 <unknown>
 
 sqdecw  x0, vl5
 // CHECK-INST: sqdecw  x0, vl5
 // CHECK-ENCODING: [0xa0,0xf8,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f8 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f8a0 <unknown>
 
 sqdecw  x0, vl6
 // CHECK-INST: sqdecw  x0, vl6
 // CHECK-ENCODING: [0xc0,0xf8,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f8 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f8c0 <unknown>
 
 sqdecw  x0, vl7
 // CHECK-INST: sqdecw  x0, vl7
 // CHECK-ENCODING: [0xe0,0xf8,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f8 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f8e0 <unknown>
 
 sqdecw  x0, vl8
 // CHECK-INST: sqdecw  x0, vl8
 // CHECK-ENCODING: [0x00,0xf9,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f9 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f900 <unknown>
 
 sqdecw  x0, vl16
 // CHECK-INST: sqdecw  x0, vl16
 // CHECK-ENCODING: [0x20,0xf9,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f9 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f920 <unknown>
 
 sqdecw  x0, vl32
 // CHECK-INST: sqdecw  x0, vl32
 // CHECK-ENCODING: [0x40,0xf9,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f9 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f940 <unknown>
 
 sqdecw  x0, vl64
 // CHECK-INST: sqdecw  x0, vl64
 // CHECK-ENCODING: [0x60,0xf9,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f9 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f960 <unknown>
 
 sqdecw  x0, vl128
 // CHECK-INST: sqdecw  x0, vl128
 // CHECK-ENCODING: [0x80,0xf9,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f9 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f980 <unknown>
 
 sqdecw  x0, vl256
 // CHECK-INST: sqdecw  x0, vl256
 // CHECK-ENCODING: [0xa0,0xf9,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f9 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f9a0 <unknown>
 
 sqdecw  x0, #14
 // CHECK-INST: sqdecw  x0, #14
 // CHECK-ENCODING: [0xc0,0xf9,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f9 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f9c0 <unknown>
 
 sqdecw  x0, #15
 // CHECK-INST: sqdecw  x0, #15
 // CHECK-ENCODING: [0xe0,0xf9,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f9 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f9e0 <unknown>
 
 sqdecw  x0, #16
 // CHECK-INST: sqdecw  x0, #16
 // CHECK-ENCODING: [0x00,0xfa,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fa b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fa00 <unknown>
 
 sqdecw  x0, #17
 // CHECK-INST: sqdecw  x0, #17
 // CHECK-ENCODING: [0x20,0xfa,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fa b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fa20 <unknown>
 
 sqdecw  x0, #18
 // CHECK-INST: sqdecw  x0, #18
 // CHECK-ENCODING: [0x40,0xfa,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fa b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fa40 <unknown>
 
 sqdecw  x0, #19
 // CHECK-INST: sqdecw  x0, #19
 // CHECK-ENCODING: [0x60,0xfa,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fa b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fa60 <unknown>
 
 sqdecw  x0, #20
 // CHECK-INST: sqdecw  x0, #20
 // CHECK-ENCODING: [0x80,0xfa,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fa b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fa80 <unknown>
 
 sqdecw  x0, #21
 // CHECK-INST: sqdecw  x0, #21
 // CHECK-ENCODING: [0xa0,0xfa,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fa b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0faa0 <unknown>
 
 sqdecw  x0, #22
 // CHECK-INST: sqdecw  x0, #22
 // CHECK-ENCODING: [0xc0,0xfa,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fa b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fac0 <unknown>
 
 sqdecw  x0, #23
 // CHECK-INST: sqdecw  x0, #23
 // CHECK-ENCODING: [0xe0,0xfa,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fa b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fae0 <unknown>
 
 sqdecw  x0, #24
 // CHECK-INST: sqdecw  x0, #24
 // CHECK-ENCODING: [0x00,0xfb,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fb b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fb00 <unknown>
 
 sqdecw  x0, #25
 // CHECK-INST: sqdecw  x0, #25
 // CHECK-ENCODING: [0x20,0xfb,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fb b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fb20 <unknown>
 
 sqdecw  x0, #26
 // CHECK-INST: sqdecw  x0, #26
 // CHECK-ENCODING: [0x40,0xfb,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fb b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fb40 <unknown>
 
 sqdecw  x0, #27
 // CHECK-INST: sqdecw  x0, #27
 // CHECK-ENCODING: [0x60,0xfb,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fb b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fb60 <unknown>
 
 sqdecw  x0, #28
 // CHECK-INST: sqdecw  x0, #28
 // CHECK-ENCODING: [0x80,0xfb,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fb b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fb80 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -305,34 +305,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqdecw  z0.s
 // CHECK-INST: sqdecw	z0.s
 // CHECK-ENCODING: [0xe0,0xcb,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cb a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0cbe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqdecw  z0.s, pow2, mul #16
 // CHECK-INST: sqdecw	z0.s, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc8,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 af 04 <unknown>
+// CHECK-UNKNOWN: 04afc800 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqdecw  z0.s, pow2
 // CHECK-INST: sqdecw	z0.s, pow2
 // CHECK-ENCODING: [0x00,0xc8,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c8 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c800 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sqincb.s b/llvm/test/MC/AArch64/SVE/sqincb.s
index 17a06ee9580bf..651a9f150b295 100644
--- a/llvm/test/MC/AArch64/SVE/sqincb.s
+++ b/llvm/test/MC/AArch64/SVE/sqincb.s
@@ -17,25 +17,25 @@ sqincb  x0
 // CHECK-INST: sqincb  x0
 // CHECK-ENCODING: [0xe0,0xf3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f3e0 <unknown>
 
 sqincb  x0, all
 // CHECK-INST: sqincb  x0
 // CHECK-ENCODING: [0xe0,0xf3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f3e0 <unknown>
 
 sqincb  x0, all, mul #1
 // CHECK-INST: sqincb  x0
 // CHECK-ENCODING: [0xe0,0xf3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f3e0 <unknown>
 
 sqincb  x0, all, mul #16
 // CHECK-INST: sqincb  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf3,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 3f 04 <unknown>
+// CHECK-UNKNOWN: 043ff3e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ sqincb  x0, w0
 // CHECK-INST: sqincb  x0, w0
 // CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
+// CHECK-UNKNOWN: 0420f3e0 <unknown>
 
 sqincb  x0, w0, all
 // CHECK-INST: sqincb  x0, w0
 // CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
+// CHECK-UNKNOWN: 0420f3e0 <unknown>
 
 sqincb  x0, w0, all, mul #1
 // CHECK-INST: sqincb  x0, w0
 // CHECK-ENCODING: [0xe0,0xf3,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 20 04 <unknown>
+// CHECK-UNKNOWN: 0420f3e0 <unknown>
 
 sqincb  x0, w0, all, mul #16
 // CHECK-INST: sqincb  x0, w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf3,0x2f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 2f 04 <unknown>
+// CHECK-UNKNOWN: 042ff3e0 <unknown>
 
 sqincb  x0, w0, pow2
 // CHECK-INST: sqincb  x0, w0, pow2
 // CHECK-ENCODING: [0x00,0xf0,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f0 20 04 <unknown>
+// CHECK-UNKNOWN: 0420f000 <unknown>
 
 sqincb  x0, w0, pow2, mul #16
 // CHECK-INST: sqincb  x0, w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xf0,0x2f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f0 2f 04 <unknown>
+// CHECK-UNKNOWN: 042ff000 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -87,173 +87,173 @@ sqincb  x0, pow2
 // CHECK-INST: sqincb  x0, pow2
 // CHECK-ENCODING: [0x00,0xf0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f000 <unknown>
 
 sqincb  x0, vl1
 // CHECK-INST: sqincb  x0, vl1
 // CHECK-ENCODING: [0x20,0xf0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f020 <unknown>
 
 sqincb  x0, vl2
 // CHECK-INST: sqincb  x0, vl2
 // CHECK-ENCODING: [0x40,0xf0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f040 <unknown>
 
 sqincb  x0, vl3
 // CHECK-INST: sqincb  x0, vl3
 // CHECK-ENCODING: [0x60,0xf0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f060 <unknown>
 
 sqincb  x0, vl4
 // CHECK-INST: sqincb  x0, vl4
 // CHECK-ENCODING: [0x80,0xf0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f080 <unknown>
 
 sqincb  x0, vl5
 // CHECK-INST: sqincb  x0, vl5
 // CHECK-ENCODING: [0xa0,0xf0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f0a0 <unknown>
 
 sqincb  x0, vl6
 // CHECK-INST: sqincb  x0, vl6
 // CHECK-ENCODING: [0xc0,0xf0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f0c0 <unknown>
 
 sqincb  x0, vl7
 // CHECK-INST: sqincb  x0, vl7
 // CHECK-ENCODING: [0xe0,0xf0,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f0 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f0e0 <unknown>
 
 sqincb  x0, vl8
 // CHECK-INST: sqincb  x0, vl8
 // CHECK-ENCODING: [0x00,0xf1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f100 <unknown>
 
 sqincb  x0, vl16
 // CHECK-INST: sqincb  x0, vl16
 // CHECK-ENCODING: [0x20,0xf1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f120 <unknown>
 
 sqincb  x0, vl32
 // CHECK-INST: sqincb  x0, vl32
 // CHECK-ENCODING: [0x40,0xf1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f140 <unknown>
 
 sqincb  x0, vl64
 // CHECK-INST: sqincb  x0, vl64
 // CHECK-ENCODING: [0x60,0xf1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f160 <unknown>
 
 sqincb  x0, vl128
 // CHECK-INST: sqincb  x0, vl128
 // CHECK-ENCODING: [0x80,0xf1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f180 <unknown>
 
 sqincb  x0, vl256
 // CHECK-INST: sqincb  x0, vl256
 // CHECK-ENCODING: [0xa0,0xf1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f1a0 <unknown>
 
 sqincb  x0, #14
 // CHECK-INST: sqincb  x0, #14
 // CHECK-ENCODING: [0xc0,0xf1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f1c0 <unknown>
 
 sqincb  x0, #15
 // CHECK-INST: sqincb  x0, #15
 // CHECK-ENCODING: [0xe0,0xf1,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f1 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f1e0 <unknown>
 
 sqincb  x0, #16
 // CHECK-INST: sqincb  x0, #16
 // CHECK-ENCODING: [0x00,0xf2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f200 <unknown>
 
 sqincb  x0, #17
 // CHECK-INST: sqincb  x0, #17
 // CHECK-ENCODING: [0x20,0xf2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f220 <unknown>
 
 sqincb  x0, #18
 // CHECK-INST: sqincb  x0, #18
 // CHECK-ENCODING: [0x40,0xf2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f240 <unknown>
 
 sqincb  x0, #19
 // CHECK-INST: sqincb  x0, #19
 // CHECK-ENCODING: [0x60,0xf2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f260 <unknown>
 
 sqincb  x0, #20
 // CHECK-INST: sqincb  x0, #20
 // CHECK-ENCODING: [0x80,0xf2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f280 <unknown>
 
 sqincb  x0, #21
 // CHECK-INST: sqincb  x0, #21
 // CHECK-ENCODING: [0xa0,0xf2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f2a0 <unknown>
 
 sqincb  x0, #22
 // CHECK-INST: sqincb  x0, #22
 // CHECK-ENCODING: [0xc0,0xf2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f2c0 <unknown>
 
 sqincb  x0, #23
 // CHECK-INST: sqincb  x0, #23
 // CHECK-ENCODING: [0xe0,0xf2,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f2 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f2e0 <unknown>
 
 sqincb  x0, #24
 // CHECK-INST: sqincb  x0, #24
 // CHECK-ENCODING: [0x00,0xf3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f300 <unknown>
 
 sqincb  x0, #25
 // CHECK-INST: sqincb  x0, #25
 // CHECK-ENCODING: [0x20,0xf3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f320 <unknown>
 
 sqincb  x0, #26
 // CHECK-INST: sqincb  x0, #26
 // CHECK-ENCODING: [0x40,0xf3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f340 <unknown>
 
 sqincb  x0, #27
 // CHECK-INST: sqincb  x0, #27
 // CHECK-ENCODING: [0x60,0xf3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f360 <unknown>
 
 sqincb  x0, #28
 // CHECK-INST: sqincb  x0, #28
 // CHECK-ENCODING: [0x80,0xf3,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f3 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f380 <unknown>
 

diff  --git a/llvm/test/MC/AArch64/SVE/sqincd.s b/llvm/test/MC/AArch64/SVE/sqincd.s
index 03f199da7f9d1..5bc9c1e982f33 100644
--- a/llvm/test/MC/AArch64/SVE/sqincd.s
+++ b/llvm/test/MC/AArch64/SVE/sqincd.s
@@ -17,25 +17,25 @@ sqincd  x0
 // CHECK-INST: sqincd  x0
 // CHECK-ENCODING: [0xe0,0xf3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f3e0 <unknown>
 
 sqincd  x0, all
 // CHECK-INST: sqincd  x0
 // CHECK-ENCODING: [0xe0,0xf3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f3e0 <unknown>
 
 sqincd  x0, all, mul #1
 // CHECK-INST: sqincd  x0
 // CHECK-ENCODING: [0xe0,0xf3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f3e0 <unknown>
 
 sqincd  x0, all, mul #16
 // CHECK-INST: sqincd  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf3,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 ff 04 <unknown>
+// CHECK-UNKNOWN: 04fff3e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ sqincd  x0, w0
 // CHECK-INST: sqincd  x0, w0
 // CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0f3e0 <unknown>
 
 sqincd  x0, w0, all
 // CHECK-INST: sqincd  x0, w0
 // CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0f3e0 <unknown>
 
 sqincd  x0, w0, all, mul #1
 // CHECK-INST: sqincd  x0, w0
 // CHECK-ENCODING: [0xe0,0xf3,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0f3e0 <unknown>
 
 sqincd  x0, w0, all, mul #16
 // CHECK-INST: sqincd  x0, w0, all
 // CHECK-ENCODING: [0xe0,0xf3,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 ef 04 <unknown>
+// CHECK-UNKNOWN: 04eff3e0 <unknown>
 
 sqincd  x0, w0, pow2
 // CHECK-INST: sqincd  x0, w0, pow2
 // CHECK-ENCODING: [0x00,0xf0,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f0 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0f000 <unknown>
 
 sqincd  x0, w0, pow2, mul #16
 // CHECK-INST: sqincd  x0, w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xf0,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f0 ef 04 <unknown>
+// CHECK-UNKNOWN: 04eff000 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -86,37 +86,37 @@ sqincd  z0.d
 // CHECK-INST: sqincd  z0.d
 // CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c3e0 <unknown>
 
 sqincd  z0.d, all
 // CHECK-INST: sqincd  z0.d
 // CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c3e0 <unknown>
 
 sqincd  z0.d, all, mul #1
 // CHECK-INST: sqincd  z0.d
 // CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c3e0 <unknown>
 
 sqincd  z0.d, all, mul #16
 // CHECK-INST: sqincd  z0.d, all, mul #16
 // CHECK-ENCODING: [0xe0,0xc3,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 ef 04 <unknown>
+// CHECK-UNKNOWN: 04efc3e0 <unknown>
 
 sqincd  z0.d, pow2
 // CHECK-INST: sqincd  z0.d, pow2
 // CHECK-ENCODING: [0x00,0xc0,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c000 <unknown>
 
 sqincd  z0.d, pow2, mul #16
 // CHECK-INST: sqincd  z0.d, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc0,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 ef 04 <unknown>
+// CHECK-UNKNOWN: 04efc000 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -127,175 +127,175 @@ sqincd  x0, pow2
 // CHECK-INST: sqincd  x0, pow2
 // CHECK-ENCODING: [0x00,0xf0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f000 <unknown>
 
 sqincd  x0, vl1
 // CHECK-INST: sqincd  x0, vl1
 // CHECK-ENCODING: [0x20,0xf0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f020 <unknown>
 
 sqincd  x0, vl2
 // CHECK-INST: sqincd  x0, vl2
 // CHECK-ENCODING: [0x40,0xf0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f040 <unknown>
 
 sqincd  x0, vl3
 // CHECK-INST: sqincd  x0, vl3
 // CHECK-ENCODING: [0x60,0xf0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f060 <unknown>
 
 sqincd  x0, vl4
 // CHECK-INST: sqincd  x0, vl4
 // CHECK-ENCODING: [0x80,0xf0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f080 <unknown>
 
 sqincd  x0, vl5
 // CHECK-INST: sqincd  x0, vl5
 // CHECK-ENCODING: [0xa0,0xf0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f0a0 <unknown>
 
 sqincd  x0, vl6
 // CHECK-INST: sqincd  x0, vl6
 // CHECK-ENCODING: [0xc0,0xf0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f0c0 <unknown>
 
 sqincd  x0, vl7
 // CHECK-INST: sqincd  x0, vl7
 // CHECK-ENCODING: [0xe0,0xf0,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f0 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f0e0 <unknown>
 
 sqincd  x0, vl8
 // CHECK-INST: sqincd  x0, vl8
 // CHECK-ENCODING: [0x00,0xf1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f100 <unknown>
 
 sqincd  x0, vl16
 // CHECK-INST: sqincd  x0, vl16
 // CHECK-ENCODING: [0x20,0xf1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f120 <unknown>
 
 sqincd  x0, vl32
 // CHECK-INST: sqincd  x0, vl32
 // CHECK-ENCODING: [0x40,0xf1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f140 <unknown>
 
 sqincd  x0, vl64
 // CHECK-INST: sqincd  x0, vl64
 // CHECK-ENCODING: [0x60,0xf1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f160 <unknown>
 
 sqincd  x0, vl128
 // CHECK-INST: sqincd  x0, vl128
 // CHECK-ENCODING: [0x80,0xf1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f180 <unknown>
 
 sqincd  x0, vl256
 // CHECK-INST: sqincd  x0, vl256
 // CHECK-ENCODING: [0xa0,0xf1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f1a0 <unknown>
 
 sqincd  x0, #14
 // CHECK-INST: sqincd  x0, #14
 // CHECK-ENCODING: [0xc0,0xf1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f1c0 <unknown>
 
 sqincd  x0, #15
 // CHECK-INST: sqincd  x0, #15
 // CHECK-ENCODING: [0xe0,0xf1,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f1 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f1e0 <unknown>
 
 sqincd  x0, #16
 // CHECK-INST: sqincd  x0, #16
 // CHECK-ENCODING: [0x00,0xf2,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f2 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f200 <unknown>
 
 sqincd  x0, #17
 // CHECK-INST: sqincd  x0, #17
 // CHECK-ENCODING: [0x20,0xf2,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f2 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f220 <unknown>
 
 sqincd  x0, #18
 // CHECK-INST: sqincd  x0, #18
 // CHECK-ENCODING: [0x40,0xf2,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f2 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f240 <unknown>
 
 sqincd  x0, #19
 // CHECK-INST: sqincd  x0, #19
 // CHECK-ENCODING: [0x60,0xf2,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f2 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f260 <unknown>
 
 sqincd  x0, #20
 // CHECK-INST: sqincd  x0, #20
 // CHECK-ENCODING: [0x80,0xf2,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f2 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f280 <unknown>
 
 sqincd  x0, #21
 // CHECK-INST: sqincd  x0, #21
 // CHECK-ENCODING: [0xa0,0xf2,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f2 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f2a0 <unknown>
 
 sqincd  x0, #22
 // CHECK-INST: sqincd  x0, #22
 // CHECK-ENCODING: [0xc0,0xf2,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f2 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f2c0 <unknown>
 
 sqincd  x0, #23
 // CHECK-INST: sqincd  x0, #23
 // CHECK-ENCODING: [0xe0,0xf2,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f2 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f2e0 <unknown>
 
 sqincd  x0, #24
 // CHECK-INST: sqincd  x0, #24
 // CHECK-ENCODING: [0x00,0xf3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f300 <unknown>
 
 sqincd  x0, #25
 // CHECK-INST: sqincd  x0, #25
 // CHECK-ENCODING: [0x20,0xf3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f320 <unknown>
 
 sqincd  x0, #26
 // CHECK-INST: sqincd  x0, #26
 // CHECK-ENCODING: [0x40,0xf3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f340 <unknown>
 
 sqincd  x0, #27
 // CHECK-INST: sqincd  x0, #27
 // CHECK-ENCODING: [0x60,0xf3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f360 <unknown>
 
 sqincd  x0, #28
 // CHECK-INST: sqincd  x0, #28
 // CHECK-ENCODING: [0x80,0xf3,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f3 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f380 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -305,34 +305,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqincd  z0.d
 // CHECK-INST: sqincd	z0.d
 // CHECK-ENCODING: [0xe0,0xc3,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c3e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqincd  z0.d, pow2, mul #16
 // CHECK-INST: sqincd	z0.d, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc0,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 ef 04 <unknown>
+// CHECK-UNKNOWN: 04efc000 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqincd  z0.d, pow2
 // CHECK-INST: sqincd	z0.d, pow2
 // CHECK-ENCODING: [0x00,0xc0,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sqinch.s b/llvm/test/MC/AArch64/SVE/sqinch.s
index a8313d749069a..861519f51b44d 100644
--- a/llvm/test/MC/AArch64/SVE/sqinch.s
+++ b/llvm/test/MC/AArch64/SVE/sqinch.s
@@ -17,25 +17,25 @@ sqinch  x0
 // CHECK-INST: sqinch  x0
 // CHECK-ENCODING: [0xe0,0xf3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f3e0 <unknown>
 
 sqinch  x0, all
 // CHECK-INST: sqinch  x0
 // CHECK-ENCODING: [0xe0,0xf3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f3e0 <unknown>
 
 sqinch  x0, all, mul #1
 // CHECK-INST: sqinch  x0
 // CHECK-ENCODING: [0xe0,0xf3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f3e0 <unknown>
 
 sqinch  x0, all, mul #16
 // CHECK-INST: sqinch  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf3,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 7f 04 <unknown>
+// CHECK-UNKNOWN: 047ff3e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ sqinch  x0, w0
 // CHECK-INST: sqinch  x0, w0
 // CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
+// CHECK-UNKNOWN: 0460f3e0 <unknown>
 
 sqinch  x0, w0, all
 // CHECK-INST: sqinch  x0, w0
 // CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
+// CHECK-UNKNOWN: 0460f3e0 <unknown>
 
 sqinch  x0, w0, all, mul #1
 // CHECK-INST: sqinch  x0, w0
 // CHECK-ENCODING: [0xe0,0xf3,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 60 04 <unknown>
+// CHECK-UNKNOWN: 0460f3e0 <unknown>
 
 sqinch  x0, w0, all, mul #16
 // CHECK-INST: sqinch  x0, w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf3,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 6f 04 <unknown>
+// CHECK-UNKNOWN: 046ff3e0 <unknown>
 
 sqinch  x0, w0, pow2
 // CHECK-INST: sqinch  x0, w0, pow2
 // CHECK-ENCODING: [0x00,0xf0,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f0 60 04 <unknown>
+// CHECK-UNKNOWN: 0460f000 <unknown>
 
 sqinch  x0, w0, pow2, mul #16
 // CHECK-INST: sqinch  x0, w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xf0,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f0 6f 04 <unknown>
+// CHECK-UNKNOWN: 046ff000 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -86,37 +86,37 @@ sqinch  z0.h
 // CHECK-INST: sqinch  z0.h
 // CHECK-ENCODING: [0xe0,0xc3,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c3e0 <unknown>
 
 sqinch  z0.h, all
 // CHECK-INST: sqinch  z0.h
 // CHECK-ENCODING: [0xe0,0xc3,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c3e0 <unknown>
 
 sqinch  z0.h, all, mul #1
 // CHECK-INST: sqinch  z0.h
 // CHECK-ENCODING: [0xe0,0xc3,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c3e0 <unknown>
 
 sqinch  z0.h, all, mul #16
 // CHECK-INST: sqinch  z0.h, all, mul #16
 // CHECK-ENCODING: [0xe0,0xc3,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fc3e0 <unknown>
 
 sqinch  z0.h, pow2
 // CHECK-INST: sqinch  z0.h, pow2
 // CHECK-ENCODING: [0x00,0xc0,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c000 <unknown>
 
 sqinch  z0.h, pow2, mul #16
 // CHECK-INST: sqinch  z0.h, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc0,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fc000 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -127,175 +127,175 @@ sqinch  x0, pow2
 // CHECK-INST: sqinch  x0, pow2
 // CHECK-ENCODING: [0x00,0xf0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f000 <unknown>
 
 sqinch  x0, vl1
 // CHECK-INST: sqinch  x0, vl1
 // CHECK-ENCODING: [0x20,0xf0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f020 <unknown>
 
 sqinch  x0, vl2
 // CHECK-INST: sqinch  x0, vl2
 // CHECK-ENCODING: [0x40,0xf0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f040 <unknown>
 
 sqinch  x0, vl3
 // CHECK-INST: sqinch  x0, vl3
 // CHECK-ENCODING: [0x60,0xf0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f060 <unknown>
 
 sqinch  x0, vl4
 // CHECK-INST: sqinch  x0, vl4
 // CHECK-ENCODING: [0x80,0xf0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f080 <unknown>
 
 sqinch  x0, vl5
 // CHECK-INST: sqinch  x0, vl5
 // CHECK-ENCODING: [0xa0,0xf0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f0a0 <unknown>
 
 sqinch  x0, vl6
 // CHECK-INST: sqinch  x0, vl6
 // CHECK-ENCODING: [0xc0,0xf0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f0c0 <unknown>
 
 sqinch  x0, vl7
 // CHECK-INST: sqinch  x0, vl7
 // CHECK-ENCODING: [0xe0,0xf0,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f0 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f0e0 <unknown>
 
 sqinch  x0, vl8
 // CHECK-INST: sqinch  x0, vl8
 // CHECK-ENCODING: [0x00,0xf1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f100 <unknown>
 
 sqinch  x0, vl16
 // CHECK-INST: sqinch  x0, vl16
 // CHECK-ENCODING: [0x20,0xf1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f120 <unknown>
 
 sqinch  x0, vl32
 // CHECK-INST: sqinch  x0, vl32
 // CHECK-ENCODING: [0x40,0xf1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f140 <unknown>
 
 sqinch  x0, vl64
 // CHECK-INST: sqinch  x0, vl64
 // CHECK-ENCODING: [0x60,0xf1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f160 <unknown>
 
 sqinch  x0, vl128
 // CHECK-INST: sqinch  x0, vl128
 // CHECK-ENCODING: [0x80,0xf1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f180 <unknown>
 
 sqinch  x0, vl256
 // CHECK-INST: sqinch  x0, vl256
 // CHECK-ENCODING: [0xa0,0xf1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f1a0 <unknown>
 
 sqinch  x0, #14
 // CHECK-INST: sqinch  x0, #14
 // CHECK-ENCODING: [0xc0,0xf1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f1c0 <unknown>
 
 sqinch  x0, #15
 // CHECK-INST: sqinch  x0, #15
 // CHECK-ENCODING: [0xe0,0xf1,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f1 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f1e0 <unknown>
 
 sqinch  x0, #16
 // CHECK-INST: sqinch  x0, #16
 // CHECK-ENCODING: [0x00,0xf2,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f2 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f200 <unknown>
 
 sqinch  x0, #17
 // CHECK-INST: sqinch  x0, #17
 // CHECK-ENCODING: [0x20,0xf2,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f2 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f220 <unknown>
 
 sqinch  x0, #18
 // CHECK-INST: sqinch  x0, #18
 // CHECK-ENCODING: [0x40,0xf2,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f2 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f240 <unknown>
 
 sqinch  x0, #19
 // CHECK-INST: sqinch  x0, #19
 // CHECK-ENCODING: [0x60,0xf2,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f2 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f260 <unknown>
 
 sqinch  x0, #20
 // CHECK-INST: sqinch  x0, #20
 // CHECK-ENCODING: [0x80,0xf2,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f2 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f280 <unknown>
 
 sqinch  x0, #21
 // CHECK-INST: sqinch  x0, #21
 // CHECK-ENCODING: [0xa0,0xf2,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f2 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f2a0 <unknown>
 
 sqinch  x0, #22
 // CHECK-INST: sqinch  x0, #22
 // CHECK-ENCODING: [0xc0,0xf2,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f2 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f2c0 <unknown>
 
 sqinch  x0, #23
 // CHECK-INST: sqinch  x0, #23
 // CHECK-ENCODING: [0xe0,0xf2,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f2 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f2e0 <unknown>
 
 sqinch  x0, #24
 // CHECK-INST: sqinch  x0, #24
 // CHECK-ENCODING: [0x00,0xf3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f300 <unknown>
 
 sqinch  x0, #25
 // CHECK-INST: sqinch  x0, #25
 // CHECK-ENCODING: [0x20,0xf3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f320 <unknown>
 
 sqinch  x0, #26
 // CHECK-INST: sqinch  x0, #26
 // CHECK-ENCODING: [0x40,0xf3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f340 <unknown>
 
 sqinch  x0, #27
 // CHECK-INST: sqinch  x0, #27
 // CHECK-ENCODING: [0x60,0xf3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f360 <unknown>
 
 sqinch  x0, #28
 // CHECK-INST: sqinch  x0, #28
 // CHECK-ENCODING: [0x80,0xf3,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f3 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f380 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -305,34 +305,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqinch  z0.h
 // CHECK-INST: sqinch	z0.h
 // CHECK-ENCODING: [0xe0,0xc3,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c3e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqinch  z0.h, pow2, mul #16
 // CHECK-INST: sqinch	z0.h, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc0,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fc000 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqinch  z0.h, pow2
 // CHECK-INST: sqinch	z0.h, pow2
 // CHECK-ENCODING: [0x00,0xc0,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sqincp.s b/llvm/test/MC/AArch64/SVE/sqincp.s
index cb0bc0263a89f..f7f2ebfb5d349 100644
--- a/llvm/test/MC/AArch64/SVE/sqincp.s
+++ b/llvm/test/MC/AArch64/SVE/sqincp.s
@@ -13,85 +13,85 @@ sqincp  x0, p0.b
 // CHECK-INST: sqincp  x0, p0.b
 // CHECK-ENCODING: [0x00,0x8c,0x28,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c 28 25 <unknown>
+// CHECK-UNKNOWN: 25288c00 <unknown>
 
 sqincp  x0, p0.h
 // CHECK-INST: sqincp  x0, p0.h
 // CHECK-ENCODING: [0x00,0x8c,0x68,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c 68 25 <unknown>
+// CHECK-UNKNOWN: 25688c00 <unknown>
 
 sqincp  x0, p0.s
 // CHECK-INST: sqincp  x0, p0.s
 // CHECK-ENCODING: [0x00,0x8c,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c a8 25 <unknown>
+// CHECK-UNKNOWN: 25a88c00 <unknown>
 
 sqincp  x0, p0.d
 // CHECK-INST: sqincp  x0, p0.d
 // CHECK-ENCODING: [0x00,0x8c,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c e8 25 <unknown>
+// CHECK-UNKNOWN: 25e88c00 <unknown>
 
 sqincp  xzr, p15.b, wzr
 // CHECK-INST: sqincp  xzr, p15.b, wzr
 // CHECK-ENCODING: [0xff,0x89,0x28,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 28 25 <unknown>
+// CHECK-UNKNOWN: 252889ff <unknown>
 
 sqincp  xzr, p15.h, wzr
 // CHECK-INST: sqincp  xzr, p15.h, wzr
 // CHECK-ENCODING: [0xff,0x89,0x68,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 68 25 <unknown>
+// CHECK-UNKNOWN: 256889ff <unknown>
 
 sqincp  xzr, p15.s, wzr
 // CHECK-INST: sqincp  xzr, p15.s, wzr
 // CHECK-ENCODING: [0xff,0x89,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 a8 25 <unknown>
+// CHECK-UNKNOWN: 25a889ff <unknown>
 
 sqincp  xzr, p15.d, wzr
 // CHECK-INST: sqincp  xzr, p15.d, wzr
 // CHECK-ENCODING: [0xff,0x89,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 e8 25 <unknown>
+// CHECK-UNKNOWN: 25e889ff <unknown>
 
 sqincp  z0.h, p0
 // CHECK-INST: sqincp  z0.h, p0.h
 // CHECK-ENCODING: [0x00,0x80,0x68,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 68 25 <unknown>
+// CHECK-UNKNOWN: 25688000 <unknown>
 
 sqincp  z0.h, p0.h
 // CHECK-INST: sqincp  z0.h, p0.h
 // CHECK-ENCODING: [0x00,0x80,0x68,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 68 25 <unknown>
+// CHECK-UNKNOWN: 25688000 <unknown>
 
 sqincp  z0.s, p0
 // CHECK-INST: sqincp  z0.s, p0.s
 // CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 a8 25 <unknown>
+// CHECK-UNKNOWN: 25a88000 <unknown>
 
 sqincp  z0.s, p0.s
 // CHECK-INST: sqincp  z0.s, p0.s
 // CHECK-ENCODING: [0x00,0x80,0xa8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 a8 25 <unknown>
+// CHECK-UNKNOWN: 25a88000 <unknown>
 
 sqincp  z0.d, p0
 // CHECK-INST: sqincp  z0.d, p0.d
 // CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 e8 25 <unknown>
+// CHECK-UNKNOWN: 25e88000 <unknown>
 
 sqincp  z0.d, p0.d
 // CHECK-INST: sqincp  z0.d, p0.d
 // CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 e8 25 <unknown>
+// CHECK-UNKNOWN: 25e88000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -101,10 +101,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqincp  z0.d, p0.d
 // CHECK-INST: sqincp	z0.d, p0.d
 // CHECK-ENCODING: [0x00,0x80,0xe8,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 e8 25 <unknown>
+// CHECK-UNKNOWN: 25e88000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sqincw.s b/llvm/test/MC/AArch64/SVE/sqincw.s
index daf5548c35f34..1cc6f438e8eff 100644
--- a/llvm/test/MC/AArch64/SVE/sqincw.s
+++ b/llvm/test/MC/AArch64/SVE/sqincw.s
@@ -17,25 +17,25 @@ sqincw  x0
 // CHECK-INST: sqincw  x0
 // CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f3e0 <unknown>
 
 sqincw  x0, all
 // CHECK-INST: sqincw  x0
 // CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f3e0 <unknown>
 
 sqincw  x0, all, mul #1
 // CHECK-INST: sqincw  x0
 // CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f3e0 <unknown>
 
 sqincw  x0, all, mul #16
 // CHECK-INST: sqincw  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf3,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bff3e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ sqincw  x0, w0
 // CHECK-INST: sqincw  x0, w0
 // CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0f3e0 <unknown>
 
 sqincw  x0, w0, all
 // CHECK-INST: sqincw  x0, w0
 // CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0f3e0 <unknown>
 
 sqincw  x0, w0, all, mul #1
 // CHECK-INST: sqincw  x0, w0
 // CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0f3e0 <unknown>
 
 sqincw  x0, w0, all, mul #16
 // CHECK-INST: sqincw  x0, w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf3,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f3 af 04 <unknown>
+// CHECK-UNKNOWN: 04aff3e0 <unknown>
 
 sqincw  x0, w0, pow2
 // CHECK-INST: sqincw  x0, w0, pow2
 // CHECK-ENCODING: [0x00,0xf0,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f0 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0f000 <unknown>
 
 sqincw  x0, w0, pow2, mul #16
 // CHECK-INST: sqincw  x0, w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xf0,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f0 af 04 <unknown>
+// CHECK-UNKNOWN: 04aff000 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -86,37 +86,37 @@ sqincw  z0.s
 // CHECK-INST: sqincw  z0.s
 // CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c3e0 <unknown>
 
 sqincw  z0.s, all
 // CHECK-INST: sqincw  z0.s
 // CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c3e0 <unknown>
 
 sqincw  z0.s, all, mul #1
 // CHECK-INST: sqincw  z0.s
 // CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c3e0 <unknown>
 
 sqincw  z0.s, all, mul #16
 // CHECK-INST: sqincw  z0.s, all, mul #16
 // CHECK-ENCODING: [0xe0,0xc3,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 af 04 <unknown>
+// CHECK-UNKNOWN: 04afc3e0 <unknown>
 
 sqincw  z0.s, pow2
 // CHECK-INST: sqincw  z0.s, pow2
 // CHECK-ENCODING: [0x00,0xc0,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c000 <unknown>
 
 sqincw  z0.s, pow2, mul #16
 // CHECK-INST: sqincw  z0.s, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc0,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 af 04 <unknown>
+// CHECK-UNKNOWN: 04afc000 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -127,175 +127,175 @@ sqincw  x0, pow2
 // CHECK-INST: sqincw  x0, pow2
 // CHECK-ENCODING: [0x00,0xf0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f000 <unknown>
 
 sqincw  x0, vl1
 // CHECK-INST: sqincw  x0, vl1
 // CHECK-ENCODING: [0x20,0xf0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f020 <unknown>
 
 sqincw  x0, vl2
 // CHECK-INST: sqincw  x0, vl2
 // CHECK-ENCODING: [0x40,0xf0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f040 <unknown>
 
 sqincw  x0, vl3
 // CHECK-INST: sqincw  x0, vl3
 // CHECK-ENCODING: [0x60,0xf0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f060 <unknown>
 
 sqincw  x0, vl4
 // CHECK-INST: sqincw  x0, vl4
 // CHECK-ENCODING: [0x80,0xf0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f080 <unknown>
 
 sqincw  x0, vl5
 // CHECK-INST: sqincw  x0, vl5
 // CHECK-ENCODING: [0xa0,0xf0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f0a0 <unknown>
 
 sqincw  x0, vl6
 // CHECK-INST: sqincw  x0, vl6
 // CHECK-ENCODING: [0xc0,0xf0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f0c0 <unknown>
 
 sqincw  x0, vl7
 // CHECK-INST: sqincw  x0, vl7
 // CHECK-ENCODING: [0xe0,0xf0,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f0 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f0e0 <unknown>
 
 sqincw  x0, vl8
 // CHECK-INST: sqincw  x0, vl8
 // CHECK-ENCODING: [0x00,0xf1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f100 <unknown>
 
 sqincw  x0, vl16
 // CHECK-INST: sqincw  x0, vl16
 // CHECK-ENCODING: [0x20,0xf1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f120 <unknown>
 
 sqincw  x0, vl32
 // CHECK-INST: sqincw  x0, vl32
 // CHECK-ENCODING: [0x40,0xf1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f140 <unknown>
 
 sqincw  x0, vl64
 // CHECK-INST: sqincw  x0, vl64
 // CHECK-ENCODING: [0x60,0xf1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f160 <unknown>
 
 sqincw  x0, vl128
 // CHECK-INST: sqincw  x0, vl128
 // CHECK-ENCODING: [0x80,0xf1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f180 <unknown>
 
 sqincw  x0, vl256
 // CHECK-INST: sqincw  x0, vl256
 // CHECK-ENCODING: [0xa0,0xf1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f1a0 <unknown>
 
 sqincw  x0, #14
 // CHECK-INST: sqincw  x0, #14
 // CHECK-ENCODING: [0xc0,0xf1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f1c0 <unknown>
 
 sqincw  x0, #15
 // CHECK-INST: sqincw  x0, #15
 // CHECK-ENCODING: [0xe0,0xf1,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f1 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f1e0 <unknown>
 
 sqincw  x0, #16
 // CHECK-INST: sqincw  x0, #16
 // CHECK-ENCODING: [0x00,0xf2,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f2 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f200 <unknown>
 
 sqincw  x0, #17
 // CHECK-INST: sqincw  x0, #17
 // CHECK-ENCODING: [0x20,0xf2,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f2 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f220 <unknown>
 
 sqincw  x0, #18
 // CHECK-INST: sqincw  x0, #18
 // CHECK-ENCODING: [0x40,0xf2,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f2 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f240 <unknown>
 
 sqincw  x0, #19
 // CHECK-INST: sqincw  x0, #19
 // CHECK-ENCODING: [0x60,0xf2,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f2 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f260 <unknown>
 
 sqincw  x0, #20
 // CHECK-INST: sqincw  x0, #20
 // CHECK-ENCODING: [0x80,0xf2,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f2 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f280 <unknown>
 
 sqincw  x0, #21
 // CHECK-INST: sqincw  x0, #21
 // CHECK-ENCODING: [0xa0,0xf2,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f2 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f2a0 <unknown>
 
 sqincw  x0, #22
 // CHECK-INST: sqincw  x0, #22
 // CHECK-ENCODING: [0xc0,0xf2,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f2 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f2c0 <unknown>
 
 sqincw  x0, #23
 // CHECK-INST: sqincw  x0, #23
 // CHECK-ENCODING: [0xe0,0xf2,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f2 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f2e0 <unknown>
 
 sqincw  x0, #24
 // CHECK-INST: sqincw  x0, #24
 // CHECK-ENCODING: [0x00,0xf3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f300 <unknown>
 
 sqincw  x0, #25
 // CHECK-INST: sqincw  x0, #25
 // CHECK-ENCODING: [0x20,0xf3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f320 <unknown>
 
 sqincw  x0, #26
 // CHECK-INST: sqincw  x0, #26
 // CHECK-ENCODING: [0x40,0xf3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f340 <unknown>
 
 sqincw  x0, #27
 // CHECK-INST: sqincw  x0, #27
 // CHECK-ENCODING: [0x60,0xf3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f360 <unknown>
 
 sqincw  x0, #28
 // CHECK-INST: sqincw  x0, #28
 // CHECK-ENCODING: [0x80,0xf3,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f3 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f380 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -305,34 +305,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqincw  z0.s
 // CHECK-INST: sqincw	z0.s
 // CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c3 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c3e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqincw  z0.s, pow2, mul #16
 // CHECK-INST: sqincw	z0.s, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc0,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 af 04 <unknown>
+// CHECK-UNKNOWN: 04afc000 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqincw  z0.s, pow2
 // CHECK-INST: sqincw	z0.s, pow2
 // CHECK-ENCODING: [0x00,0xc0,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sqsub.s b/llvm/test/MC/AArch64/SVE/sqsub.s
index af7f323cce14a..c721b4a7bfbfd 100644
--- a/llvm/test/MC/AArch64/SVE/sqsub.s
+++ b/llvm/test/MC/AArch64/SVE/sqsub.s
@@ -14,109 +14,109 @@ sqsub     z0.b, z0.b, z0.b
 // CHECK-INST: sqsub z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x18,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 18 20 04 <unknown>
+// CHECK-UNKNOWN: 04201800 <unknown>
 
 sqsub     z0.h, z0.h, z0.h
 // CHECK-INST: sqsub z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x18,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 18 60 04 <unknown>
+// CHECK-UNKNOWN: 04601800 <unknown>
 
 sqsub     z0.s, z0.s, z0.s
 // CHECK-INST: sqsub z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x18,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 18 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a01800 <unknown>
 
 sqsub     z0.d, z0.d, z0.d
 // CHECK-INST: sqsub z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x18,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 18 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e01800 <unknown>
 
 sqsub     z0.b, z0.b, #0
 // CHECK-INST: sqsub z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x26,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 26 25 <unknown>
+// CHECK-UNKNOWN: 2526c000 <unknown>
 
 sqsub     z31.b, z31.b, #255
 // CHECK-INST: sqsub z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x26,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 26 25 <unknown>
+// CHECK-UNKNOWN: 2526dfff <unknown>
 
 sqsub     z0.h, z0.h, #0
 // CHECK-INST: sqsub z0.h, z0.h, #0
 // CHECK-ENCODING: [0x00,0xc0,0x66,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 66 25 <unknown>
+// CHECK-UNKNOWN: 2566c000 <unknown>
 
 sqsub     z0.h, z0.h, #0, lsl #8
 // CHECK-INST: sqsub z0.h, z0.h, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0x66,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 66 25 <unknown>
+// CHECK-UNKNOWN: 2566e000 <unknown>
 
 sqsub     z31.h, z31.h, #255, lsl #8
 // CHECK-INST: sqsub z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x66,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 66 25 <unknown>
+// CHECK-UNKNOWN: 2566ffff <unknown>
 
 sqsub     z31.h, z31.h, #65280
 // CHECK-INST: sqsub z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x66,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 66 25 <unknown>
+// CHECK-UNKNOWN: 2566ffff <unknown>
 
 sqsub     z0.s, z0.s, #0
 // CHECK-INST: sqsub z0.s, z0.s, #0
 // CHECK-ENCODING: [0x00,0xc0,0xa6,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 a6 25 <unknown>
+// CHECK-UNKNOWN: 25a6c000 <unknown>
 
 sqsub     z0.s, z0.s, #0, lsl #8
 // CHECK-INST: sqsub z0.s, z0.s, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xa6,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 a6 25 <unknown>
+// CHECK-UNKNOWN: 25a6e000 <unknown>
 
 sqsub     z31.s, z31.s, #255, lsl #8
 // CHECK-INST: sqsub z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa6,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a6 25 <unknown>
+// CHECK-UNKNOWN: 25a6ffff <unknown>
 
 sqsub     z31.s, z31.s, #65280
 // CHECK-INST: sqsub z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa6,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a6 25 <unknown>
+// CHECK-UNKNOWN: 25a6ffff <unknown>
 
 sqsub     z0.d, z0.d, #0
 // CHECK-INST: sqsub z0.d, z0.d, #0
 // CHECK-ENCODING: [0x00,0xc0,0xe6,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 e6 25 <unknown>
+// CHECK-UNKNOWN: 25e6c000 <unknown>
 
 sqsub     z0.d, z0.d, #0, lsl #8
 // CHECK-INST: sqsub z0.d, z0.d, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xe6,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e6 25 <unknown>
+// CHECK-UNKNOWN: 25e6e000 <unknown>
 
 sqsub     z31.d, z31.d, #255, lsl #8
 // CHECK-INST: sqsub z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe6,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e6 25 <unknown>
+// CHECK-UNKNOWN: 25e6ffff <unknown>
 
 sqsub     z31.d, z31.d, #65280
 // CHECK-INST: sqsub z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe6,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e6 25 <unknown>
+// CHECK-UNKNOWN: 25e6ffff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -126,10 +126,10 @@ movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sqsub     z31.d, z31.d, #65280
 // CHECK-INST: sqsub	z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe6,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e6 25 <unknown>
+// CHECK-UNKNOWN: 25e6ffff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st1b-sve-only.s b/llvm/test/MC/AArch64/SVE/st1b-sve-only.s
index 81102914c3038..0fbd54543089e 100644
--- a/llvm/test/MC/AArch64/SVE/st1b-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/st1b-sve-only.s
@@ -15,64 +15,64 @@ st1b    { z0.s }, p0, [x0, z0.s, uxtw]
 // CHECK-INST: st1b    { z0.s }, p0, [x0, z0.s, uxtw]
 // CHECK-ENCODING: [0x00,0x80,0x40,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 40 e4 <unknown>
+// CHECK-UNKNOWN: e4408000 <unknown>
 
 st1b    { z0.s }, p0, [x0, z0.s, sxtw]
 // CHECK-INST: st1b    { z0.s }, p0, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0xc0,0x40,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 40 e4 <unknown>
+// CHECK-UNKNOWN: e440c000 <unknown>
 
 st1b    { z0.d }, p0, [x0, z0.d, uxtw]
 // CHECK-INST: st1b    { z0.d }, p0, [x0, z0.d, uxtw]
 // CHECK-ENCODING: [0x00,0x80,0x00,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 00 e4 <unknown>
+// CHECK-UNKNOWN: e4008000 <unknown>
 
 st1b    { z0.d }, p0, [x0, z0.d, sxtw]
 // CHECK-INST: st1b    { z0.d }, p0, [x0, z0.d, sxtw]
 // CHECK-ENCODING: [0x00,0xc0,0x00,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 00 e4 <unknown>
+// CHECK-UNKNOWN: e400c000 <unknown>
 
 st1b    { z0.d }, p0, [x0, z0.d]
 // CHECK-INST: st1b    { z0.d }, p0, [x0, z0.d]
 // CHECK-ENCODING: [0x00,0xa0,0x00,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 00 e4 <unknown>
+// CHECK-UNKNOWN: e400a000 <unknown>
 
 st1b    { z31.s }, p7, [z31.s, #31]
 // CHECK-INST: st1b    { z31.s }, p7, [z31.s, #31]
 // CHECK-ENCODING: [0xff,0xbf,0x7f,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 7f e4 <unknown>
+// CHECK-UNKNOWN: e47fbfff <unknown>
 
 st1b    { z31.d }, p7, [z31.d, #31]
 // CHECK-INST: st1b    { z31.d }, p7, [z31.d, #31]
 // CHECK-ENCODING: [0xff,0xbf,0x5f,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 5f e4 <unknown>
+// CHECK-UNKNOWN: e45fbfff <unknown>
 
 st1b    { z0.s }, p7, [z0.s, #0]
 // CHECK-INST: st1b    { z0.s }, p7, [z0.s]
 // CHECK-ENCODING: [0x00,0xbc,0x60,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc 60 e4 <unknown>
+// CHECK-UNKNOWN: e460bc00 <unknown>
 
 st1b    { z0.s }, p7, [z0.s]
 // CHECK-INST: st1b    { z0.s }, p7, [z0.s]
 // CHECK-ENCODING: [0x00,0xbc,0x60,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc 60 e4 <unknown>
+// CHECK-UNKNOWN: e460bc00 <unknown>
 
 st1b    { z0.d }, p7, [z0.d, #0]
 // CHECK-INST: st1b    { z0.d }, p7, [z0.d]
 // CHECK-ENCODING: [0x00,0xbc,0x40,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc 40 e4 <unknown>
+// CHECK-UNKNOWN: e440bc00 <unknown>
 
 st1b    { z0.d }, p7, [z0.d]
 // CHECK-INST: st1b    { z0.d }, p7, [z0.d]
 // CHECK-ENCODING: [0x00,0xbc,0x40,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc 40 e4 <unknown>
+// CHECK-UNKNOWN: e440bc00 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st1b.s b/llvm/test/MC/AArch64/SVE/st1b.s
index e066aa0fdbde0..d737bfd063535 100644
--- a/llvm/test/MC/AArch64/SVE/st1b.s
+++ b/llvm/test/MC/AArch64/SVE/st1b.s
@@ -13,118 +13,118 @@ st1b    z0.b, p0, [x0]
 // CHECK-INST: st1b    { z0.b }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x00,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 00 e4 <unknown>
+// CHECK-UNKNOWN: e400e000 <unknown>
 
 st1b    z0.h, p0, [x0]
 // CHECK-INST: st1b    { z0.h }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x20,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 20 e4 <unknown>
+// CHECK-UNKNOWN: e420e000 <unknown>
 
 st1b    z0.s, p0, [x0]
 // CHECK-INST: st1b    { z0.s }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x40,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 40 e4 <unknown>
+// CHECK-UNKNOWN: e440e000 <unknown>
 
 st1b    z0.d, p0, [x0]
 // CHECK-INST: st1b    { z0.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x60,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 60 e4 <unknown>
+// CHECK-UNKNOWN: e460e000 <unknown>
 
 st1b    { z0.b }, p0, [x0]
 // CHECK-INST: st1b    { z0.b }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x00,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 00 e4 <unknown>
+// CHECK-UNKNOWN: e400e000 <unknown>
 
 st1b    { z0.h }, p0, [x0]
 // CHECK-INST: st1b    { z0.h }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x20,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 20 e4 <unknown>
+// CHECK-UNKNOWN: e420e000 <unknown>
 
 st1b    { z0.s }, p0, [x0]
 // CHECK-INST: st1b    { z0.s }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x40,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 40 e4 <unknown>
+// CHECK-UNKNOWN: e440e000 <unknown>
 
 st1b    { z0.d }, p0, [x0]
 // CHECK-INST: st1b    { z0.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x60,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 60 e4 <unknown>
+// CHECK-UNKNOWN: e460e000 <unknown>
 
 st1b    { z31.b }, p7, [sp, #-1, mul vl]
 // CHECK-INST: st1b    { z31.b }, p7, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xff,0x0f,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 0f e4 <unknown>
+// CHECK-UNKNOWN: e40fffff <unknown>
 
 st1b    { z21.b }, p5, [x10, #5, mul vl]
 // CHECK-INST: st1b    { z21.b }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x05,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 05 e4 <unknown>
+// CHECK-UNKNOWN: e405f555 <unknown>
 
 st1b    { z31.h }, p7, [sp, #-1, mul vl]
 // CHECK-INST: st1b    { z31.h }, p7, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xff,0x2f,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 2f e4 <unknown>
+// CHECK-UNKNOWN: e42fffff <unknown>
 
 st1b    { z21.h }, p5, [x10, #5, mul vl]
 // CHECK-INST: st1b    { z21.h }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x25,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 25 e4 <unknown>
+// CHECK-UNKNOWN: e425f555 <unknown>
 
 st1b    { z31.s }, p7, [sp, #-1, mul vl]
 // CHECK-INST: st1b    { z31.s }, p7, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xff,0x4f,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 4f e4 <unknown>
+// CHECK-UNKNOWN: e44fffff <unknown>
 
 st1b    { z21.s }, p5, [x10, #5, mul vl]
 // CHECK-INST: st1b    { z21.s }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x45,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 45 e4 <unknown>
+// CHECK-UNKNOWN: e445f555 <unknown>
 
 st1b    { z31.d }, p7, [sp, #-1, mul vl]
 // CHECK-INST: st1b    { z31.d }, p7, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xff,0x6f,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 6f e4 <unknown>
+// CHECK-UNKNOWN: e46fffff <unknown>
 
 st1b    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-INST: st1b    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x65,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 65 e4 <unknown>
+// CHECK-UNKNOWN: e465f555 <unknown>
 
 st1b    { z0.b }, p0, [x0, x0]
 // CHECK-INST: st1b    { z0.b }, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x40,0x00,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 00 e4 <unknown>
+// CHECK-UNKNOWN: e4004000 <unknown>
 
 st1b    { z0.h }, p0, [x0, x0]
 // CHECK-INST: st1b    { z0.h }, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x40,0x20,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 20 e4 <unknown>
+// CHECK-UNKNOWN: e4204000 <unknown>
 
 st1b    { z0.s }, p0, [x0, x0]
 // CHECK-INST: st1b    { z0.s }, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x40,0x40,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 40 e4 <unknown>
+// CHECK-UNKNOWN: e4404000 <unknown>
 
 st1b    { z0.d }, p0, [x0, x0]
 // CHECK-INST: st1b    { z0.d }, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x40,0x60,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 60 e4 <unknown>
+// CHECK-UNKNOWN: e4604000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st1d-sve-only.s b/llvm/test/MC/AArch64/SVE/st1d-sve-only.s
index 3fba716d0cb48..e9e974117ea1a 100644
--- a/llvm/test/MC/AArch64/SVE/st1d-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/st1d-sve-only.s
@@ -15,52 +15,52 @@ st1d    { z0.d }, p0, [x0, z0.d, uxtw]
 // CHECK-INST: st1d    { z0.d }, p0, [x0, z0.d, uxtw]
 // CHECK-ENCODING: [0x00,0x80,0x80,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 80 e5 <unknown>
+// CHECK-UNKNOWN: e5808000 <unknown>
 
 st1d    { z0.d }, p0, [x0, z0.d, sxtw]
 // CHECK-INST: st1d    { z0.d }, p0, [x0, z0.d, sxtw]
 // CHECK-ENCODING: [0x00,0xc0,0x80,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 80 e5 <unknown>
+// CHECK-UNKNOWN: e580c000 <unknown>
 
 st1d    { z0.d }, p0, [x0, z0.d, uxtw #3]
 // CHECK-INST: st1d    { z0.d }, p0, [x0, z0.d, uxtw #3]
 // CHECK-ENCODING: [0x00,0x80,0xa0,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 a0 e5 <unknown>
+// CHECK-UNKNOWN: e5a08000 <unknown>
 
 st1d    { z0.d }, p0, [x0, z0.d, sxtw #3]
 // CHECK-INST: st1d    { z0.d }, p0, [x0, z0.d, sxtw #3]
 // CHECK-ENCODING: [0x00,0xc0,0xa0,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 a0 e5 <unknown>
+// CHECK-UNKNOWN: e5a0c000 <unknown>
 
 st1d    { z0.d }, p0, [x0, z0.d]
 // CHECK-INST: st1d    { z0.d }, p0, [x0, z0.d]
 // CHECK-ENCODING: [0x00,0xa0,0x80,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 80 e5 <unknown>
+// CHECK-UNKNOWN: e580a000 <unknown>
 
 st1d    { z0.d }, p0, [x0, z0.d, lsl #3]
 // CHECK-INST: st1d    { z0.d }, p0, [x0, z0.d, lsl #3]
 // CHECK-ENCODING: [0x00,0xa0,0xa0,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 a0 e5 <unknown>
+// CHECK-UNKNOWN: e5a0a000 <unknown>
 
 st1d    { z31.d }, p7, [z31.d, #248]
 // CHECK-INST: st1d    { z31.d }, p7, [z31.d, #248]
 // CHECK-ENCODING: [0xff,0xbf,0xdf,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf df e5 <unknown>
+// CHECK-UNKNOWN: e5dfbfff <unknown>
 
 st1d    { z0.d }, p7, [z0.d, #0]
 // CHECK-INST: st1d    { z0.d }, p7, [z0.d]
 // CHECK-ENCODING: [0x00,0xbc,0xc0,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc c0 e5 <unknown>
+// CHECK-UNKNOWN: e5c0bc00 <unknown>
 
 st1d    { z0.d }, p7, [z0.d]
 // CHECK-INST: st1d    { z0.d }, p7, [z0.d]
 // CHECK-ENCODING: [0x00,0xbc,0xc0,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc c0 e5 <unknown>
+// CHECK-UNKNOWN: e5c0bc00 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st1d.s b/llvm/test/MC/AArch64/SVE/st1d.s
index 74db4f3f4f55c..64ccac509a7e9 100644
--- a/llvm/test/MC/AArch64/SVE/st1d.s
+++ b/llvm/test/MC/AArch64/SVE/st1d.s
@@ -13,28 +13,28 @@ st1d    z0.d, p0, [x0]
 // CHECK-INST: st1d    { z0.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xe0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e0 e5 <unknown>
+// CHECK-UNKNOWN: e5e0e000 <unknown>
 
 st1d    { z0.d }, p0, [x0]
 // CHECK-INST: st1d    { z0.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xe0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e0 e5 <unknown>
+// CHECK-UNKNOWN: e5e0e000 <unknown>
 
 st1d    { z31.d }, p7, [sp, #-1, mul vl]
 // CHECK-INST: st1d    { z31.d }, p7, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xff,0xef,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff ef e5 <unknown>
+// CHECK-UNKNOWN: e5efffff <unknown>
 
 st1d    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-INST: st1d    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xe5,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 e5 e5 <unknown>
+// CHECK-UNKNOWN: e5e5f555 <unknown>
 
 st1d    { z0.d }, p0, [x0, x0, lsl #3]
 // CHECK-INST: st1d    { z0.d }, p0, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x40,0xe0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 e0 e5 <unknown>
+// CHECK-UNKNOWN: e5e04000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st1h-sve-only.s b/llvm/test/MC/AArch64/SVE/st1h-sve-only.s
index 115b7e12e273a..01de34cfad556 100644
--- a/llvm/test/MC/AArch64/SVE/st1h-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/st1h-sve-only.s
@@ -15,94 +15,94 @@ st1h    { z0.s }, p0, [x0, z0.s, uxtw]
 // CHECK-INST: st1h    { z0.s }, p0, [x0, z0.s, uxtw]
 // CHECK-ENCODING: [0x00,0x80,0xc0,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 c0 e4 <unknown>
+// CHECK-UNKNOWN: e4c08000 <unknown>
 
 st1h    { z0.s }, p0, [x0, z0.s, sxtw]
 // CHECK-INST: st1h    { z0.s }, p0, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0xc0,0xc0,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 c0 e4 <unknown>
+// CHECK-UNKNOWN: e4c0c000 <unknown>
 
 st1h    { z0.d }, p0, [x0, z0.d, uxtw]
 // CHECK-INST: st1h    { z0.d }, p0, [x0, z0.d, uxtw]
 // CHECK-ENCODING: [0x00,0x80,0x80,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 80 e4 <unknown>
+// CHECK-UNKNOWN: e4808000 <unknown>
 
 st1h    { z0.d }, p0, [x0, z0.d, sxtw]
 // CHECK-INST: st1h    { z0.d }, p0, [x0, z0.d, sxtw]
 // CHECK-ENCODING: [0x00,0xc0,0x80,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 80 e4 <unknown>
+// CHECK-UNKNOWN: e480c000 <unknown>
 
 st1h    { z0.s }, p0, [x0, z0.s, uxtw #1]
 // CHECK-INST: st1h    { z0.s }, p0, [x0, z0.s, uxtw #1]
 // CHECK-ENCODING: [0x00,0x80,0xe0,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 e0 e4 <unknown>
+// CHECK-UNKNOWN: e4e08000 <unknown>
 
 st1h    { z0.s }, p0, [x0, z0.s, sxtw #1]
 // CHECK-INST: st1h    { z0.s }, p0, [x0, z0.s, sxtw #1]
 // CHECK-ENCODING: [0x00,0xc0,0xe0,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 e0 e4 <unknown>
+// CHECK-UNKNOWN: e4e0c000 <unknown>
 
 st1h    { z0.d }, p0, [x0, z0.d, uxtw #1]
 // CHECK-INST: st1h    { z0.d }, p0, [x0, z0.d, uxtw #1]
 // CHECK-ENCODING: [0x00,0x80,0xa0,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 a0 e4 <unknown>
+// CHECK-UNKNOWN: e4a08000 <unknown>
 
 st1h    { z0.d }, p0, [x0, z0.d, sxtw #1]
 // CHECK-INST: st1h    { z0.d }, p0, [x0, z0.d, sxtw #1]
 // CHECK-ENCODING: [0x00,0xc0,0xa0,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 a0 e4 <unknown>
+// CHECK-UNKNOWN: e4a0c000 <unknown>
 
 st1h    { z0.d }, p0, [x0, z0.d]
 // CHECK-INST: st1h    { z0.d }, p0, [x0, z0.d]
 // CHECK-ENCODING: [0x00,0xa0,0x80,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 80 e4 <unknown>
+// CHECK-UNKNOWN: e480a000 <unknown>
 
 st1h    { z0.d }, p0, [x0, z0.d, lsl #1]
 // CHECK-INST: st1h    { z0.d }, p0, [x0, z0.d, lsl #1]
 // CHECK-ENCODING: [0x00,0xa0,0xa0,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 a0 e4 <unknown>
+// CHECK-UNKNOWN: e4a0a000 <unknown>
 
 st1h    { z31.s }, p7, [z31.s, #62]
 // CHECK-INST: st1h    { z31.s }, p7, [z31.s, #62]
 // CHECK-ENCODING: [0xff,0xbf,0xff,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf ff e4 <unknown>
+// CHECK-UNKNOWN: e4ffbfff <unknown>
 
 st1h    { z31.d }, p7, [z31.d, #62]
 // CHECK-INST: st1h    { z31.d }, p7, [z31.d, #62]
 // CHECK-ENCODING: [0xff,0xbf,0xdf,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf df e4 <unknown>
+// CHECK-UNKNOWN: e4dfbfff <unknown>
 
 st1h    { z0.s }, p7, [z0.s, #0]
 // CHECK-INST: st1h    { z0.s }, p7, [z0.s]
 // CHECK-ENCODING: [0x00,0xbc,0xe0,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc e0 e4 <unknown>
+// CHECK-UNKNOWN: e4e0bc00 <unknown>
 
 st1h    { z0.s }, p7, [z0.s]
 // CHECK-INST: st1h    { z0.s }, p7, [z0.s]
 // CHECK-ENCODING: [0x00,0xbc,0xe0,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc e0 e4 <unknown>
+// CHECK-UNKNOWN: e4e0bc00 <unknown>
 
 st1h    { z0.d }, p7, [z0.d, #0]
 // CHECK-INST: st1h    { z0.d }, p7, [z0.d]
 // CHECK-ENCODING: [0x00,0xbc,0xc0,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc c0 e4 <unknown>
+// CHECK-UNKNOWN: e4c0bc00 <unknown>
 
 st1h    { z0.d }, p7, [z0.d]
 // CHECK-INST: st1h    { z0.d }, p7, [z0.d]
 // CHECK-ENCODING: [0x00,0xbc,0xc0,0xe4]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc c0 e4 <unknown>
+// CHECK-UNKNOWN: e4c0bc00 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st1h.s b/llvm/test/MC/AArch64/SVE/st1h.s
index ccd9ad1c82e58..c10a65275c03e 100644
--- a/llvm/test/MC/AArch64/SVE/st1h.s
+++ b/llvm/test/MC/AArch64/SVE/st1h.s
@@ -13,88 +13,88 @@ st1h    z0.h, p0, [x0]
 // CHECK-INST: st1h    { z0.h }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xa0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 a0 e4 <unknown>
+// CHECK-UNKNOWN: e4a0e000 <unknown>
 
 st1h    z0.s, p0, [x0]
 // CHECK-INST: st1h    { z0.s }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xc0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 c0 e4 <unknown>
+// CHECK-UNKNOWN: e4c0e000 <unknown>
 
 st1h    z0.d, p0, [x0]
 // CHECK-INST: st1h    { z0.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xe0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e0 e4 <unknown>
+// CHECK-UNKNOWN: e4e0e000 <unknown>
 
 st1h    { z0.h }, p0, [x0]
 // CHECK-INST: st1h    { z0.h }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xa0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 a0 e4 <unknown>
+// CHECK-UNKNOWN: e4a0e000 <unknown>
 
 st1h    { z0.s }, p0, [x0]
 // CHECK-INST: st1h    { z0.s }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xc0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 c0 e4 <unknown>
+// CHECK-UNKNOWN: e4c0e000 <unknown>
 
 st1h    { z0.d }, p0, [x0]
 // CHECK-INST: st1h    { z0.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xe0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e0 e4 <unknown>
+// CHECK-UNKNOWN: e4e0e000 <unknown>
 
 st1h    { z31.h }, p7, [sp, #-1, mul vl]
 // CHECK-INST: st1h    { z31.h }, p7, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xff,0xaf,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff af e4 <unknown>
+// CHECK-UNKNOWN: e4afffff <unknown>
 
 st1h    { z21.h }, p5, [x10, #5, mul vl]
 // CHECK-INST: st1h    { z21.h }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xa5,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 a5 e4 <unknown>
+// CHECK-UNKNOWN: e4a5f555 <unknown>
 
 st1h    { z31.s }, p7, [sp, #-1, mul vl]
 // CHECK-INST: st1h    { z31.s }, p7, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xff,0xcf,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff cf e4 <unknown>
+// CHECK-UNKNOWN: e4cfffff <unknown>
 
 st1h    { z21.s }, p5, [x10, #5, mul vl]
 // CHECK-INST: st1h    { z21.s }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xc5,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 c5 e4 <unknown>
+// CHECK-UNKNOWN: e4c5f555 <unknown>
 
 st1h    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-INST: st1h    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xe5,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 e5 e4 <unknown>
+// CHECK-UNKNOWN: e4e5f555 <unknown>
 
 st1h    { z31.d }, p7, [sp, #-1, mul vl]
 // CHECK-INST: st1h    { z31.d }, p7, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xff,0xef,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff ef e4 <unknown>
+// CHECK-UNKNOWN: e4efffff <unknown>
 
 st1h    { z0.h }, p0, [x0, x0, lsl #1]
 // CHECK-INST: st1h    { z0.h }, p0, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x40,0xa0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 a0 e4 <unknown>
+// CHECK-UNKNOWN: e4a04000 <unknown>
 
 st1h    { z0.s }, p0, [x0, x0, lsl #1]
 // CHECK-INST: st1h    { z0.s }, p0, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x40,0xc0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 c0 e4 <unknown>
+// CHECK-UNKNOWN: e4c04000 <unknown>
 
 st1h    { z0.d }, p0, [x0, x0, lsl #1]
 // CHECK-INST: st1h    { z0.d }, p0, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x40,0xe0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 e0 e4 <unknown>
+// CHECK-UNKNOWN: e4e04000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st1w-sve-only.s b/llvm/test/MC/AArch64/SVE/st1w-sve-only.s
index 3a054fe81aec8..307ed37109e43 100644
--- a/llvm/test/MC/AArch64/SVE/st1w-sve-only.s
+++ b/llvm/test/MC/AArch64/SVE/st1w-sve-only.s
@@ -15,94 +15,94 @@ st1w    { z0.s }, p0, [x0, z0.s, uxtw]
 // CHECK-INST: st1w    { z0.s }, p0, [x0, z0.s, uxtw]
 // CHECK-ENCODING: [0x00,0x80,0x40,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 40 e5 <unknown>
+// CHECK-UNKNOWN: e5408000 <unknown>
 
 st1w    { z0.s }, p0, [x0, z0.s, sxtw]
 // CHECK-INST: st1w    { z0.s }, p0, [x0, z0.s, sxtw]
 // CHECK-ENCODING: [0x00,0xc0,0x40,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 40 e5 <unknown>
+// CHECK-UNKNOWN: e540c000 <unknown>
 
 st1w    { z0.d }, p0, [x0, z0.d, uxtw]
 // CHECK-INST: st1w    { z0.d }, p0, [x0, z0.d, uxtw]
 // CHECK-ENCODING: [0x00,0x80,0x00,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 00 e5 <unknown>
+// CHECK-UNKNOWN: e5008000 <unknown>
 
 st1w    { z0.d }, p0, [x0, z0.d, sxtw]
 // CHECK-INST: st1w    { z0.d }, p0, [x0, z0.d, sxtw]
 // CHECK-ENCODING: [0x00,0xc0,0x00,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 00 e5 <unknown>
+// CHECK-UNKNOWN: e500c000 <unknown>
 
 st1w    { z0.s }, p0, [x0, z0.s, uxtw #2]
 // CHECK-INST: st1w    { z0.s }, p0, [x0, z0.s, uxtw #2]
 // CHECK-ENCODING: [0x00,0x80,0x60,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 60 e5 <unknown>
+// CHECK-UNKNOWN: e5608000 <unknown>
 
 st1w    { z0.s }, p0, [x0, z0.s, sxtw #2]
 // CHECK-INST: st1w    { z0.s }, p0, [x0, z0.s, sxtw #2]
 // CHECK-ENCODING: [0x00,0xc0,0x60,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 60 e5 <unknown>
+// CHECK-UNKNOWN: e560c000 <unknown>
 
 st1w    { z0.d }, p0, [x0, z0.d, uxtw #2]
 // CHECK-INST: st1w    { z0.d }, p0, [x0, z0.d, uxtw #2]
 // CHECK-ENCODING: [0x00,0x80,0x20,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 80 20 e5 <unknown>
+// CHECK-UNKNOWN: e5208000 <unknown>
 
 st1w    { z0.d }, p0, [x0, z0.d, sxtw #2]
 // CHECK-INST: st1w    { z0.d }, p0, [x0, z0.d, sxtw #2]
 // CHECK-ENCODING: [0x00,0xc0,0x20,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 c0 20 e5 <unknown>
+// CHECK-UNKNOWN: e520c000 <unknown>
 
 st1w    { z0.d }, p0, [x0, z0.d]
 // CHECK-INST: st1w    { z0.d }, p0, [x0, z0.d]
 // CHECK-ENCODING: [0x00,0xa0,0x00,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 00 e5 <unknown>
+// CHECK-UNKNOWN: e500a000 <unknown>
 
 st1w    { z0.d }, p0, [x0, z0.d, lsl #2]
 // CHECK-INST: st1w    { z0.d }, p0, [x0, z0.d, lsl #2]
 // CHECK-ENCODING: [0x00,0xa0,0x20,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 a0 20 e5 <unknown>
+// CHECK-UNKNOWN: e520a000 <unknown>
 
 st1w    { z31.s }, p7, [z31.s, #124]
 // CHECK-INST: st1w    { z31.s }, p7, [z31.s, #124]
 // CHECK-ENCODING: [0xff,0xbf,0x7f,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 7f e5 <unknown>
+// CHECK-UNKNOWN: e57fbfff <unknown>
 
 st1w    { z31.d }, p7, [z31.d, #124]
 // CHECK-INST: st1w    { z31.d }, p7, [z31.d, #124]
 // CHECK-ENCODING: [0xff,0xbf,0x5f,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: ff bf 5f e5 <unknown>
+// CHECK-UNKNOWN: e55fbfff <unknown>
 
 st1w    { z0.s }, p7, [z0.s, #0]
 // CHECK-INST: st1w    { z0.s }, p7, [z0.s]
 // CHECK-ENCODING: [0x00,0xbc,0x60,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc 60 e5 <unknown>
+// CHECK-UNKNOWN: e560bc00 <unknown>
 
 st1w    { z0.s }, p7, [z0.s]
 // CHECK-INST: st1w    { z0.s }, p7, [z0.s]
 // CHECK-ENCODING: [0x00,0xbc,0x60,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc 60 e5 <unknown>
+// CHECK-UNKNOWN: e560bc00 <unknown>
 
 st1w    { z0.d }, p7, [z0.d, #0]
 // CHECK-INST: st1w    { z0.d }, p7, [z0.d]
 // CHECK-ENCODING: [0x00,0xbc,0x40,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc 40 e5 <unknown>
+// CHECK-UNKNOWN: e540bc00 <unknown>
 
 st1w    { z0.d }, p7, [z0.d]
 // CHECK-INST: st1w    { z0.d }, p7, [z0.d]
 // CHECK-ENCODING: [0x00,0xbc,0x40,0xe5]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 bc 40 e5 <unknown>
+// CHECK-UNKNOWN: e540bc00 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st1w.s b/llvm/test/MC/AArch64/SVE/st1w.s
index fb78e0622770e..6009382cd150e 100644
--- a/llvm/test/MC/AArch64/SVE/st1w.s
+++ b/llvm/test/MC/AArch64/SVE/st1w.s
@@ -13,58 +13,58 @@ st1w    z0.s, p0, [x0]
 // CHECK-INST: st1w    { z0.s }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x40,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 40 e5 <unknown>
+// CHECK-UNKNOWN: e540e000 <unknown>
 
 st1w    z0.d, p0, [x0]
 // CHECK-INST: st1w    { z0.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x60,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 60 e5 <unknown>
+// CHECK-UNKNOWN: e560e000 <unknown>
 
 st1w    { z0.s }, p0, [x0]
 // CHECK-INST: st1w    { z0.s }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x40,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 40 e5 <unknown>
+// CHECK-UNKNOWN: e540e000 <unknown>
 
 st1w    { z0.d }, p0, [x0]
 // CHECK-INST: st1w    { z0.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x60,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 60 e5 <unknown>
+// CHECK-UNKNOWN: e560e000 <unknown>
 
 st1w    { z31.s }, p7, [sp, #-1, mul vl]
 // CHECK-INST: st1w    { z31.s }, p7, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xff,0x4f,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 4f e5 <unknown>
+// CHECK-UNKNOWN: e54fffff <unknown>
 
 st1w    { z21.s }, p5, [x10, #5, mul vl]
 // CHECK-INST: st1w    { z21.s }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x45,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 45 e5 <unknown>
+// CHECK-UNKNOWN: e545f555 <unknown>
 
 st1w    { z31.d }, p7, [sp, #-1, mul vl]
 // CHECK-INST: st1w    { z31.d }, p7, [sp, #-1, mul vl]
 // CHECK-ENCODING: [0xff,0xff,0x6f,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 6f e5 <unknown>
+// CHECK-UNKNOWN: e56fffff <unknown>
 
 st1w    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-INST: st1w    { z21.d }, p5, [x10, #5, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x65,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 65 e5 <unknown>
+// CHECK-UNKNOWN: e565f555 <unknown>
 
 st1w    { z0.s }, p0, [x0, x0, lsl #2]
 // CHECK-INST: st1w    { z0.s }, p0, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x40,0x40,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 40 e5 <unknown>
+// CHECK-UNKNOWN: e5404000 <unknown>
 
 st1w    { z0.d }, p0, [x0, x0, lsl #2]
 // CHECK-INST: st1w    { z0.d }, p0, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x40,0x60,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 60 e5 <unknown>
+// CHECK-UNKNOWN: e5604000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st2b.s b/llvm/test/MC/AArch64/SVE/st2b.s
index 792e164c8c6d6..a088379b55ca2 100644
--- a/llvm/test/MC/AArch64/SVE/st2b.s
+++ b/llvm/test/MC/AArch64/SVE/st2b.s
@@ -13,28 +13,28 @@ st2b    { z0.b, z1.b }, p0, [x0, x0]
 // CHECK-INST: st2b    { z0.b, z1.b }, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0x20,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 20 e4 <unknown>
+// CHECK-UNKNOWN: e4206000 <unknown>
 
 st2b    { z5.b, z6.b }, p3, [x17, x16]
 // CHECK-INST: st2b    { z5.b, z6.b }, p3, [x17, x16]
 // CHECK-ENCODING: [0x25,0x6e,0x30,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 6e 30 e4 <unknown>
+// CHECK-UNKNOWN: e4306e25 <unknown>
 
 st2b    { z0.b, z1.b }, p0, [x0]
 // CHECK-INST: st2b    { z0.b, z1.b }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x30,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 30 e4 <unknown>
+// CHECK-UNKNOWN: e430e000 <unknown>
 
 st2b    { z23.b, z24.b }, p3, [x13, #-16, mul vl]
 // CHECK-INST: st2b    { z23.b, z24.b }, p3, [x13, #-16, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x38,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 38 e4 <unknown>
+// CHECK-UNKNOWN: e438edb7 <unknown>
 
 st2b    { z21.b, z22.b }, p5, [x10, #10, mul vl]
 // CHECK-INST: st2b    { z21.b, z22.b }, p5, [x10, #10, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x35,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 35 e4 <unknown>
+// CHECK-UNKNOWN: e435f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st2d.s b/llvm/test/MC/AArch64/SVE/st2d.s
index bc363a16127c6..a16e038429b59 100644
--- a/llvm/test/MC/AArch64/SVE/st2d.s
+++ b/llvm/test/MC/AArch64/SVE/st2d.s
@@ -13,28 +13,28 @@ st2d    { z0.d, z1.d }, p0, [x0, x0, lsl #3]
 // CHECK-INST: st2d    { z0.d, z1.d }, p0, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x60,0xa0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 a0 e5 <unknown>
+// CHECK-UNKNOWN: e5a06000 <unknown>
 
 st2d    { z5.d, z6.d }, p3, [x17, x16, lsl #3]
 // CHECK-INST: st2d    { z5.d, z6.d }, p3, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0x6e,0xb0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 6e b0 e5 <unknown>
+// CHECK-UNKNOWN: e5b06e25 <unknown>
 
 st2d    { z0.d, z1.d }, p0, [x0]
 // CHECK-INST: st2d    { z0.d, z1.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xb0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 b0 e5 <unknown>
+// CHECK-UNKNOWN: e5b0e000 <unknown>
 
 st2d    { z23.d, z24.d }, p3, [x13, #-16, mul vl]
 // CHECK-INST: st2d    { z23.d, z24.d }, p3, [x13, #-16, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xb8,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed b8 e5 <unknown>
+// CHECK-UNKNOWN: e5b8edb7 <unknown>
 
 st2d    { z21.d, z22.d }, p5, [x10, #10, mul vl]
 // CHECK-INST: st2d    { z21.d, z22.d }, p5, [x10, #10, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xb5,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 b5 e5 <unknown>
+// CHECK-UNKNOWN: e5b5f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st2h.s b/llvm/test/MC/AArch64/SVE/st2h.s
index e670fbdaae1eb..70f32278dc1b1 100644
--- a/llvm/test/MC/AArch64/SVE/st2h.s
+++ b/llvm/test/MC/AArch64/SVE/st2h.s
@@ -13,28 +13,28 @@ st2h    { z0.h, z1.h }, p0, [x0, x0, lsl #1]
 // CHECK-INST: st2h    { z0.h, z1.h }, p0, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x60,0xa0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 a0 e4 <unknown>
+// CHECK-UNKNOWN: e4a06000 <unknown>
 
 st2h    { z5.h, z6.h }, p3, [x17, x16, lsl #1]
 // CHECK-INST: st2h    { z5.h, z6.h }, p3, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x6e,0xb0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 6e b0 e4 <unknown>
+// CHECK-UNKNOWN: e4b06e25 <unknown>
 
 st2h    { z0.h, z1.h }, p0, [x0]
 // CHECK-INST: st2h    { z0.h, z1.h }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xb0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 b0 e4 <unknown>
+// CHECK-UNKNOWN: e4b0e000 <unknown>
 
 st2h    { z23.h, z24.h }, p3, [x13, #-16, mul vl]
 // CHECK-INST: st2h    { z23.h, z24.h }, p3, [x13, #-16, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xb8,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed b8 e4 <unknown>
+// CHECK-UNKNOWN: e4b8edb7 <unknown>
 
 st2h    { z21.h, z22.h }, p5, [x10, #10, mul vl]
 // CHECK-INST: st2h    { z21.h, z22.h }, p5, [x10, #10, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xb5,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 b5 e4 <unknown>
+// CHECK-UNKNOWN: e4b5f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st2w.s b/llvm/test/MC/AArch64/SVE/st2w.s
index 42a08c25c9134..adb6e06af42a9 100644
--- a/llvm/test/MC/AArch64/SVE/st2w.s
+++ b/llvm/test/MC/AArch64/SVE/st2w.s
@@ -13,28 +13,28 @@ st2w    { z0.s, z1.s }, p0, [x0, x0, lsl #2]
 // CHECK-INST: st2w    { z0.s, z1.s }, p0, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x60,0x20,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 20 e5 <unknown>
+// CHECK-UNKNOWN: e5206000 <unknown>
 
 st2w    { z5.s, z6.s }, p3, [x17, x16, lsl #2]
 // CHECK-INST: st2w    { z5.s, z6.s }, p3, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0x6e,0x30,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 6e 30 e5 <unknown>
+// CHECK-UNKNOWN: e5306e25 <unknown>
 
 st2w    { z0.s, z1.s }, p0, [x0]
 // CHECK-INST: st2w    { z0.s, z1.s }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x30,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 30 e5 <unknown>
+// CHECK-UNKNOWN: e530e000 <unknown>
 
 st2w    { z23.s, z24.s }, p3, [x13, #-16, mul vl]
 // CHECK-INST: st2w    { z23.s, z24.s }, p3, [x13, #-16, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x38,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 38 e5 <unknown>
+// CHECK-UNKNOWN: e538edb7 <unknown>
 
 st2w    { z21.s, z22.s }, p5, [x10, #10, mul vl]
 // CHECK-INST: st2w    { z21.s, z22.s }, p5, [x10, #10, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x35,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 35 e5 <unknown>
+// CHECK-UNKNOWN: e535f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st3b.s b/llvm/test/MC/AArch64/SVE/st3b.s
index 2de14dc2560a5..7049a2da9b98b 100644
--- a/llvm/test/MC/AArch64/SVE/st3b.s
+++ b/llvm/test/MC/AArch64/SVE/st3b.s
@@ -13,28 +13,28 @@ st3b    { z0.b, z1.b, z2.b }, p0, [x0, x0]
 // CHECK-INST: st3b    { z0.b, z1.b, z2.b }, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0x40,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 40 e4 <unknown>
+// CHECK-UNKNOWN: e4406000 <unknown>
 
 st3b    { z5.b, z6.b, z7.b }, p3, [x17, x16]
 // CHECK-INST: st3b    { z5.b, z6.b, z7.b }, p3, [x17, x16]
 // CHECK-ENCODING: [0x25,0x6e,0x50,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 6e 50 e4 <unknown>
+// CHECK-UNKNOWN: e4506e25 <unknown>
 
 st3b    { z0.b, z1.b, z2.b }, p0, [x0]
 // CHECK-INST: st3b    { z0.b, z1.b, z2.b }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x50,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 50 e4 <unknown>
+// CHECK-UNKNOWN: e450e000 <unknown>
 
 st3b    { z23.b, z24.b, z25.b }, p3, [x13, #-24, mul vl]
 // CHECK-INST: st3b    { z23.b, z24.b, z25.b }, p3, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x58,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 58 e4 <unknown>
+// CHECK-UNKNOWN: e458edb7 <unknown>
 
 st3b    { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
 // CHECK-INST: st3b    { z21.b, z22.b, z23.b }, p5, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x55,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 55 e4 <unknown>
+// CHECK-UNKNOWN: e455f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st3d.s b/llvm/test/MC/AArch64/SVE/st3d.s
index 411ae396b6390..0a2285e7f0d47 100644
--- a/llvm/test/MC/AArch64/SVE/st3d.s
+++ b/llvm/test/MC/AArch64/SVE/st3d.s
@@ -13,28 +13,28 @@ st3d    { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3]
 // CHECK-INST: st3d    { z0.d, z1.d, z2.d }, p0, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x60,0xc0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 c0 e5 <unknown>
+// CHECK-UNKNOWN: e5c06000 <unknown>
 
 st3d    { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3]
 // CHECK-INST: st3d    { z5.d, z6.d, z7.d }, p3, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0x6e,0xd0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 6e d0 e5 <unknown>
+// CHECK-UNKNOWN: e5d06e25 <unknown>
 
 st3d    { z0.d, z1.d, z2.d }, p0, [x0]
 // CHECK-INST: st3d    { z0.d, z1.d, z2.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xd0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 d0 e5 <unknown>
+// CHECK-UNKNOWN: e5d0e000 <unknown>
 
 st3d    { z23.d, z24.d, z25.d }, p3, [x13, #-24, mul vl]
 // CHECK-INST: st3d    { z23.d, z24.d, z25.d }, p3, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xd8,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed d8 e5 <unknown>
+// CHECK-UNKNOWN: e5d8edb7 <unknown>
 
 st3d    { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
 // CHECK-INST: st3d    { z21.d, z22.d, z23.d }, p5, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xd5,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 d5 e5 <unknown>
+// CHECK-UNKNOWN: e5d5f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st3h.s b/llvm/test/MC/AArch64/SVE/st3h.s
index be373f422ebe9..c0a00d0bb87dc 100644
--- a/llvm/test/MC/AArch64/SVE/st3h.s
+++ b/llvm/test/MC/AArch64/SVE/st3h.s
@@ -13,28 +13,28 @@ st3h    { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1]
 // CHECK-INST: st3h    { z0.h, z1.h, z2.h }, p0, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x60,0xc0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 c0 e4 <unknown>
+// CHECK-UNKNOWN: e4c06000 <unknown>
 
 st3h    { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1]
 // CHECK-INST: st3h    { z5.h, z6.h, z7.h }, p3, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x6e,0xd0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 6e d0 e4 <unknown>
+// CHECK-UNKNOWN: e4d06e25 <unknown>
 
 st3h    { z0.h, z1.h, z2.h }, p0, [x0]
 // CHECK-INST: st3h    { z0.h, z1.h, z2.h }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xd0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 d0 e4 <unknown>
+// CHECK-UNKNOWN: e4d0e000 <unknown>
 
 st3h    { z23.h, z24.h, z25.h }, p3, [x13, #-24, mul vl]
 // CHECK-INST: st3h    { z23.h, z24.h, z25.h }, p3, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xd8,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed d8 e4 <unknown>
+// CHECK-UNKNOWN: e4d8edb7 <unknown>
 
 st3h    { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
 // CHECK-INST: st3h    { z21.h, z22.h, z23.h }, p5, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xd5,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 d5 e4 <unknown>
+// CHECK-UNKNOWN: e4d5f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st3w.s b/llvm/test/MC/AArch64/SVE/st3w.s
index d06a62d5ee978..7738c0e8cd0a1 100644
--- a/llvm/test/MC/AArch64/SVE/st3w.s
+++ b/llvm/test/MC/AArch64/SVE/st3w.s
@@ -13,28 +13,28 @@ st3w    { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2]
 // CHECK-INST: st3w    { z0.s, z1.s, z2.s }, p0, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x60,0x40,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 40 e5 <unknown>
+// CHECK-UNKNOWN: e5406000 <unknown>
 
 st3w    { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2]
 // CHECK-INST: st3w    { z5.s, z6.s, z7.s }, p3, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0x6e,0x50,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 6e 50 e5 <unknown>
+// CHECK-UNKNOWN: e5506e25 <unknown>
 
 st3w    { z0.s, z1.s, z2.s }, p0, [x0]
 // CHECK-INST: st3w    { z0.s, z1.s, z2.s }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x50,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 50 e5 <unknown>
+// CHECK-UNKNOWN: e550e000 <unknown>
 
 st3w    { z23.s, z24.s, z25.s }, p3, [x13, #-24, mul vl]
 // CHECK-INST: st3w    { z23.s, z24.s, z25.s }, p3, [x13, #-24, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x58,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 58 e5 <unknown>
+// CHECK-UNKNOWN: e558edb7 <unknown>
 
 st3w    { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
 // CHECK-INST: st3w    { z21.s, z22.s, z23.s }, p5, [x10, #15, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x55,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 55 e5 <unknown>
+// CHECK-UNKNOWN: e555f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st4b.s b/llvm/test/MC/AArch64/SVE/st4b.s
index c48e9a93e67aa..115e8e0fc605c 100644
--- a/llvm/test/MC/AArch64/SVE/st4b.s
+++ b/llvm/test/MC/AArch64/SVE/st4b.s
@@ -13,28 +13,28 @@ st4b    { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0]
 // CHECK-INST: st4b    { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0x60,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 60 e4 <unknown>
+// CHECK-UNKNOWN: e4606000 <unknown>
 
 st4b    { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16]
 // CHECK-INST: st4b    { z5.b, z6.b, z7.b, z8.b }, p3, [x17, x16]
 // CHECK-ENCODING: [0x25,0x6e,0x70,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 6e 70 e4 <unknown>
+// CHECK-UNKNOWN: e4706e25 <unknown>
 
 st4b    { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
 // CHECK-INST: st4b    { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x70,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 70 e4 <unknown>
+// CHECK-UNKNOWN: e470e000 <unknown>
 
 st4b    { z23.b, z24.b, z25.b, z26.b }, p3, [x13, #-32, mul vl]
 // CHECK-INST: st4b    { z23.b, z24.b, z25.b, z26.b }, p3, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x78,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 78 e4 <unknown>
+// CHECK-UNKNOWN: e478edb7 <unknown>
 
 st4b    { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
 // CHECK-INST: st4b    { z21.b, z22.b, z23.b, z24.b }, p5, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x75,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 75 e4 <unknown>
+// CHECK-UNKNOWN: e475f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st4d.s b/llvm/test/MC/AArch64/SVE/st4d.s
index dfff4debe3425..d1890839f571e 100644
--- a/llvm/test/MC/AArch64/SVE/st4d.s
+++ b/llvm/test/MC/AArch64/SVE/st4d.s
@@ -13,28 +13,28 @@ st4d    { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3]
 // CHECK-INST: st4d    { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x60,0xe0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 e0 e5 <unknown>
+// CHECK-UNKNOWN: e5e06000 <unknown>
 
 st4d    { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3]
 // CHECK-INST: st4d    { z5.d, z6.d, z7.d, z8.d }, p3, [x17, x16, lsl #3]
 // CHECK-ENCODING: [0x25,0x6e,0xf0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 6e f0 e5 <unknown>
+// CHECK-UNKNOWN: e5f06e25 <unknown>
 
 st4d    { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
 // CHECK-INST: st4d    { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xf0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 f0 e5 <unknown>
+// CHECK-UNKNOWN: e5f0e000 <unknown>
 
 st4d    { z23.d, z24.d, z25.d, z26.d }, p3, [x13, #-32, mul vl]
 // CHECK-INST: st4d    { z23.d, z24.d, z25.d, z26.d }, p3, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xf8,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed f8 e5 <unknown>
+// CHECK-UNKNOWN: e5f8edb7 <unknown>
 
 st4d    { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
 // CHECK-INST: st4d    { z21.d, z22.d, z23.d, z24.d }, p5, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xf5,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 f5 e5 <unknown>
+// CHECK-UNKNOWN: e5f5f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st4h.s b/llvm/test/MC/AArch64/SVE/st4h.s
index 20474225f99ca..1feb6f3ddf9ac 100644
--- a/llvm/test/MC/AArch64/SVE/st4h.s
+++ b/llvm/test/MC/AArch64/SVE/st4h.s
@@ -13,28 +13,28 @@ st4h    { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1]
 // CHECK-INST: st4h    { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x60,0xe0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 e0 e4 <unknown>
+// CHECK-UNKNOWN: e4e06000 <unknown>
 
 st4h    { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1]
 // CHECK-INST: st4h    { z5.h, z6.h, z7.h, z8.h }, p3, [x17, x16, lsl #1]
 // CHECK-ENCODING: [0x25,0x6e,0xf0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 6e f0 e4 <unknown>
+// CHECK-UNKNOWN: e4f06e25 <unknown>
 
 st4h    { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
 // CHECK-INST: st4h    { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0xf0,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 f0 e4 <unknown>
+// CHECK-UNKNOWN: e4f0e000 <unknown>
 
 st4h    { z23.h, z24.h, z25.h, z26.h }, p3, [x13, #-32, mul vl]
 // CHECK-INST: st4h    { z23.h, z24.h, z25.h, z26.h }, p3, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0xf8,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed f8 e4 <unknown>
+// CHECK-UNKNOWN: e4f8edb7 <unknown>
 
 st4h    { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
 // CHECK-INST: st4h    { z21.h, z22.h, z23.h, z24.h }, p5, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0xf5,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 f5 e4 <unknown>
+// CHECK-UNKNOWN: e4f5f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/st4w.s b/llvm/test/MC/AArch64/SVE/st4w.s
index 0f58c746dcf86..278b9652fbe06 100644
--- a/llvm/test/MC/AArch64/SVE/st4w.s
+++ b/llvm/test/MC/AArch64/SVE/st4w.s
@@ -13,28 +13,28 @@ st4w    { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2]
 // CHECK-INST: st4w    { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x60,0x60,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 60 e5 <unknown>
+// CHECK-UNKNOWN: e5606000 <unknown>
 
 st4w    { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2]
 // CHECK-INST: st4w    { z5.s, z6.s, z7.s, z8.s }, p3, [x17, x16, lsl #2]
 // CHECK-ENCODING: [0x25,0x6e,0x70,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 25 6e 70 e5 <unknown>
+// CHECK-UNKNOWN: e5706e25 <unknown>
 
 st4w    { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
 // CHECK-INST: st4w    { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x70,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 70 e5 <unknown>
+// CHECK-UNKNOWN: e570e000 <unknown>
 
 st4w    { z23.s, z24.s, z25.s, z26.s }, p3, [x13, #-32, mul vl]
 // CHECK-INST: st4w    { z23.s, z24.s, z25.s, z26.s }, p3, [x13, #-32, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x78,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 78 e5 <unknown>
+// CHECK-UNKNOWN: e578edb7 <unknown>
 
 st4w    { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
 // CHECK-INST: st4w    { z21.s, z22.s, z23.s, z24.s }, p5, [x10, #20, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x75,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 75 e5 <unknown>
+// CHECK-UNKNOWN: e575f555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/stnt1b.s b/llvm/test/MC/AArch64/SVE/stnt1b.s
index 89d2518b661bf..cde9cc79f4395 100644
--- a/llvm/test/MC/AArch64/SVE/stnt1b.s
+++ b/llvm/test/MC/AArch64/SVE/stnt1b.s
@@ -13,28 +13,28 @@ stnt1b  z0.b, p0, [x0]
 // CHECK-INST: stnt1b  { z0.b }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x10,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 10 e4 <unknown>
+// CHECK-UNKNOWN: e410e000 <unknown>
 
 stnt1b  { z0.b }, p0, [x0]
 // CHECK-INST: stnt1b  { z0.b }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x10,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 10 e4 <unknown>
+// CHECK-UNKNOWN: e410e000 <unknown>
 
 stnt1b  { z23.b }, p3, [x13, #-8, mul vl]
 // CHECK-INST: stnt1b  { z23.b }, p3, [x13, #-8, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x18,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 18 e4 <unknown>
+// CHECK-UNKNOWN: e418edb7 <unknown>
 
 stnt1b  { z21.b }, p5, [x10, #7, mul vl]
 // CHECK-INST: stnt1b  { z21.b }, p5, [x10, #7, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x17,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 17 e4 <unknown>
+// CHECK-UNKNOWN: e417f555 <unknown>
 
 stnt1b  { z0.b }, p0, [x0, x0]
 // CHECK-INST: stnt1b  { z0.b }, p0, [x0, x0]
 // CHECK-ENCODING: [0x00,0x60,0x00,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 00 e4 <unknown>
+// CHECK-UNKNOWN: e4006000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/stnt1d.s b/llvm/test/MC/AArch64/SVE/stnt1d.s
index f13b3b47d81f9..54d202bce25a6 100644
--- a/llvm/test/MC/AArch64/SVE/stnt1d.s
+++ b/llvm/test/MC/AArch64/SVE/stnt1d.s
@@ -13,28 +13,28 @@ stnt1d  z0.d, p0, [x0]
 // CHECK-INST: stnt1d  { z0.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x90,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 90 e5 <unknown>
+// CHECK-UNKNOWN: e590e000 <unknown>
 
 stnt1d  { z0.d }, p0, [x0]
 // CHECK-INST: stnt1d  { z0.d }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x90,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 90 e5 <unknown>
+// CHECK-UNKNOWN: e590e000 <unknown>
 
 stnt1d  { z23.d }, p3, [x13, #-8, mul vl]
 // CHECK-INST: stnt1d  { z23.d }, p3, [x13, #-8, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x98,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 98 e5 <unknown>
+// CHECK-UNKNOWN: e598edb7 <unknown>
 
 stnt1d  { z21.d }, p5, [x10, #7, mul vl]
 // CHECK-INST: stnt1d  { z21.d }, p5, [x10, #7, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x97,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 97 e5 <unknown>
+// CHECK-UNKNOWN: e597f555 <unknown>
 
 stnt1d  { z0.d }, p0, [x0, x0, lsl #3]
 // CHECK-INST: stnt1d  { z0.d }, p0, [x0, x0, lsl #3]
 // CHECK-ENCODING: [0x00,0x60,0x80,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 80 e5 <unknown>
+// CHECK-UNKNOWN: e5806000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/stnt1h.s b/llvm/test/MC/AArch64/SVE/stnt1h.s
index db011107b6929..4f218d412ac24 100644
--- a/llvm/test/MC/AArch64/SVE/stnt1h.s
+++ b/llvm/test/MC/AArch64/SVE/stnt1h.s
@@ -13,28 +13,28 @@ stnt1h  z0.h, p0, [x0]
 // CHECK-INST: stnt1h  { z0.h }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x90,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 90 e4 <unknown>
+// CHECK-UNKNOWN: e490e000 <unknown>
 
 stnt1h  { z0.h }, p0, [x0]
 // CHECK-INST: stnt1h  { z0.h }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x90,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 90 e4 <unknown>
+// CHECK-UNKNOWN: e490e000 <unknown>
 
 stnt1h  { z23.h }, p3, [x13, #-8, mul vl]
 // CHECK-INST: stnt1h  { z23.h }, p3, [x13, #-8, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x98,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 98 e4 <unknown>
+// CHECK-UNKNOWN: e498edb7 <unknown>
 
 stnt1h  { z21.h }, p5, [x10, #7, mul vl]
 // CHECK-INST: stnt1h  { z21.h }, p5, [x10, #7, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x97,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 97 e4 <unknown>
+// CHECK-UNKNOWN: e497f555 <unknown>
 
 stnt1h  { z0.h }, p0, [x0, x0, lsl #1]
 // CHECK-INST: stnt1h  { z0.h }, p0, [x0, x0, lsl #1]
 // CHECK-ENCODING: [0x00,0x60,0x80,0xe4]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 80 e4 <unknown>
+// CHECK-UNKNOWN: e4806000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/stnt1w.s b/llvm/test/MC/AArch64/SVE/stnt1w.s
index 07774437f50b5..9fe365f4af831 100644
--- a/llvm/test/MC/AArch64/SVE/stnt1w.s
+++ b/llvm/test/MC/AArch64/SVE/stnt1w.s
@@ -13,28 +13,28 @@ stnt1w  z0.s, p0, [x0]
 // CHECK-INST: stnt1w  { z0.s }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x10,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 10 e5 <unknown>
+// CHECK-UNKNOWN: e510e000 <unknown>
 
 stnt1w  { z0.s }, p0, [x0]
 // CHECK-INST: stnt1w  { z0.s }, p0, [x0]
 // CHECK-ENCODING: [0x00,0xe0,0x10,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 10 e5 <unknown>
+// CHECK-UNKNOWN: e510e000 <unknown>
 
 stnt1w  { z23.s }, p3, [x13, #-8, mul vl]
 // CHECK-INST: stnt1w  { z23.s }, p3, [x13, #-8, mul vl]
 // CHECK-ENCODING: [0xb7,0xed,0x18,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 ed 18 e5 <unknown>
+// CHECK-UNKNOWN: e518edb7 <unknown>
 
 stnt1w  { z21.s }, p5, [x10, #7, mul vl]
 // CHECK-INST: stnt1w  { z21.s }, p5, [x10, #7, mul vl]
 // CHECK-ENCODING: [0x55,0xf5,0x17,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 f5 17 e5 <unknown>
+// CHECK-UNKNOWN: e517f555 <unknown>
 
 stnt1w  { z0.s }, p0, [x0, x0, lsl #2]
 // CHECK-INST: stnt1w  { z0.s }, p0, [x0, x0, lsl #2]
 // CHECK-ENCODING: [0x00,0x60,0x00,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 00 e5 <unknown>
+// CHECK-UNKNOWN: e5006000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/str.s b/llvm/test/MC/AArch64/SVE/str.s
index 01e8c28b2c260..27e62af633645 100644
--- a/llvm/test/MC/AArch64/SVE/str.s
+++ b/llvm/test/MC/AArch64/SVE/str.s
@@ -13,34 +13,34 @@ str     z0, [x0]
 // CHECK-INST: str     z0, [x0]
 // CHECK-ENCODING: [0x00,0x40,0x80,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 80 e5 <unknown>
+// CHECK-UNKNOWN: e5804000 <unknown>
 
 str     z21, [x10, #-256, mul vl]
 // CHECK-INST: str     z21, [x10, #-256, mul vl]
 // CHECK-ENCODING: [0x55,0x41,0xa0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 41 a0 e5 <unknown>
+// CHECK-UNKNOWN: e5a04155 <unknown>
 
 str     z31, [sp, #255, mul vl]
 // CHECK-INST: str     z31, [sp, #255, mul vl]
 // CHECK-ENCODING: [0xff,0x5f,0x9f,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 5f 9f e5 <unknown>
+// CHECK-UNKNOWN: e59f5fff <unknown>
 
 str     p0, [x0]
 // CHECK-INST: str     p0, [x0]
 // CHECK-ENCODING: [0x00,0x00,0x80,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 80 e5 <unknown>
+// CHECK-UNKNOWN: e5800000 <unknown>
 
 str     p15, [sp, #-256, mul vl]
 // CHECK-INST: str     p15, [sp, #-256, mul vl]
 // CHECK-ENCODING: [0xef,0x03,0xa0,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 03 a0 e5 <unknown>
+// CHECK-UNKNOWN: e5a003ef <unknown>
 
 str     p5, [x10, #255, mul vl]
 // CHECK-INST: str     p5, [x10, #255, mul vl]
 // CHECK-ENCODING: [0x45,0x1d,0x9f,0xe5]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 45 1d 9f e5 <unknown>
+// CHECK-UNKNOWN: e59f1d45 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sub.s b/llvm/test/MC/AArch64/SVE/sub.s
index 29212bc5fd33f..aa22f8241e5c7 100644
--- a/llvm/test/MC/AArch64/SVE/sub.s
+++ b/llvm/test/MC/AArch64/SVE/sub.s
@@ -13,193 +13,193 @@ sub     z0.h, z0.h, z0.h
 // CHECK-INST: sub     z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x04,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 04 60 04 <unknown>
+// CHECK-UNKNOWN: 04600400 <unknown>
 
 sub     z21.b, z10.b, z21.b
 // CHECK-INST: sub     z21.b, z10.b, z21.b
 // CHECK-ENCODING: [0x55,0x05,0x35,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 05 35 04 <unknown>
+// CHECK-UNKNOWN: 04350555 <unknown>
 
 sub     z31.d, p7/m, z31.d, z31.d
 // CHECK-INST: sub     z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xc1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f c1 04 <unknown>
+// CHECK-UNKNOWN: 04c11fff <unknown>
 
 sub     z23.h, p3/m, z23.h, z13.h
 // CHECK-INST: sub     z23.h, p3/m, z23.h, z13.h
 // CHECK-ENCODING: [0xb7,0x0d,0x41,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 0d 41 04 <unknown>
+// CHECK-UNKNOWN: 04410db7 <unknown>
 
 sub     z31.h, z31.h, z31.h
 // CHECK-INST: sub     z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x07,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 07 7f 04 <unknown>
+// CHECK-UNKNOWN: 047f07ff <unknown>
 
 sub     z21.h, z10.h, z21.h
 // CHECK-INST: sub     z21.h, z10.h, z21.h
 // CHECK-ENCODING: [0x55,0x05,0x75,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 05 75 04 <unknown>
+// CHECK-UNKNOWN: 04750555 <unknown>
 
 sub     z31.b, z31.b, z31.b
 // CHECK-INST: sub     z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x07,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 07 3f 04 <unknown>
+// CHECK-UNKNOWN: 043f07ff <unknown>
 
 sub     z0.s, z0.s, z0.s
 // CHECK-INST: sub     z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x04,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 04 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a00400 <unknown>
 
 sub     z23.s, p3/m, z23.s, z13.s
 // CHECK-INST: sub     z23.s, p3/m, z23.s, z13.s
 // CHECK-ENCODING: [0xb7,0x0d,0x81,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 0d 81 04 <unknown>
+// CHECK-UNKNOWN: 04810db7 <unknown>
 
 sub     z23.b, z13.b, z8.b
 // CHECK-INST: sub     z23.b, z13.b, z8.b
 // CHECK-ENCODING: [0xb7,0x05,0x28,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 05 28 04 <unknown>
+// CHECK-UNKNOWN: 042805b7 <unknown>
 
 sub     z21.d, z10.d, z21.d
 // CHECK-INST: sub     z21.d, z10.d, z21.d
 // CHECK-ENCODING: [0x55,0x05,0xf5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 05 f5 04 <unknown>
+// CHECK-UNKNOWN: 04f50555 <unknown>
 
 sub     z21.s, z10.s, z21.s
 // CHECK-INST: sub     z21.s, z10.s, z21.s
 // CHECK-ENCODING: [0x55,0x05,0xb5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 05 b5 04 <unknown>
+// CHECK-UNKNOWN: 04b50555 <unknown>
 
 sub     z21.s, p5/m, z21.s, z10.s
 // CHECK-INST: sub     z21.s, p5/m, z21.s, z10.s
 // CHECK-ENCODING: [0x55,0x15,0x81,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 15 81 04 <unknown>
+// CHECK-UNKNOWN: 04811555 <unknown>
 
 sub     z31.s, p7/m, z31.s, z31.s
 // CHECK-INST: sub     z31.s, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1f,0x81,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 81 04 <unknown>
+// CHECK-UNKNOWN: 04811fff <unknown>
 
 sub     z0.d, p0/m, z0.d, z0.d
 // CHECK-INST: sub     z0.d, p0/m, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x00,0xc1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 c1 04 <unknown>
+// CHECK-UNKNOWN: 04c10000 <unknown>
 
 sub     z0.b, z0.b, z0.b
 // CHECK-INST: sub     z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x04,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 04 20 04 <unknown>
+// CHECK-UNKNOWN: 04200400 <unknown>
 
 sub     z23.d, z13.d, z8.d
 // CHECK-INST: sub     z23.d, z13.d, z8.d
 // CHECK-ENCODING: [0xb7,0x05,0xe8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 05 e8 04 <unknown>
+// CHECK-UNKNOWN: 04e805b7 <unknown>
 
 sub     z23.d, p3/m, z23.d, z13.d
 // CHECK-INST: sub     z23.d, p3/m, z23.d, z13.d
 // CHECK-ENCODING: [0xb7,0x0d,0xc1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 0d c1 04 <unknown>
+// CHECK-UNKNOWN: 04c10db7 <unknown>
 
 sub     z23.s, z13.s, z8.s
 // CHECK-INST: sub     z23.s, z13.s, z8.s
 // CHECK-ENCODING: [0xb7,0x05,0xa8,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 05 a8 04 <unknown>
+// CHECK-UNKNOWN: 04a805b7 <unknown>
 
 sub     z31.b, p7/m, z31.b, z31.b
 // CHECK-INST: sub     z31.b, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x1f,0x01,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 01 04 <unknown>
+// CHECK-UNKNOWN: 04011fff <unknown>
 
 sub     z0.h, p0/m, z0.h, z0.h
 // CHECK-INST: sub     z0.h, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x00,0x41,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 41 04 <unknown>
+// CHECK-UNKNOWN: 04410000 <unknown>
 
 sub     z31.d, z31.d, z31.d
 // CHECK-INST: sub     z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x07,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 07 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff07ff <unknown>
 
 sub     z31.h, p7/m, z31.h, z31.h
 // CHECK-INST: sub     z31.h, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x1f,0x41,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 41 04 <unknown>
+// CHECK-UNKNOWN: 04411fff <unknown>
 
 sub     z23.h, z13.h, z8.h
 // CHECK-INST: sub     z23.h, z13.h, z8.h
 // CHECK-ENCODING: [0xb7,0x05,0x68,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 05 68 04 <unknown>
+// CHECK-UNKNOWN: 046805b7 <unknown>
 
 sub     z21.b, p5/m, z21.b, z10.b
 // CHECK-INST: sub     z21.b, p5/m, z21.b, z10.b
 // CHECK-ENCODING: [0x55,0x15,0x01,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 15 01 04 <unknown>
+// CHECK-UNKNOWN: 04011555 <unknown>
 
 sub     z21.d, p5/m, z21.d, z10.d
 // CHECK-INST: sub     z21.d, p5/m, z21.d, z10.d
 // CHECK-ENCODING: [0x55,0x15,0xc1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 15 c1 04 <unknown>
+// CHECK-UNKNOWN: 04c11555 <unknown>
 
 sub     z0.d, z0.d, z0.d
 // CHECK-INST: sub     z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x04,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 04 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e00400 <unknown>
 
 sub     z31.s, z31.s, z31.s
 // CHECK-INST: sub     z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x07,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 07 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf07ff <unknown>
 
 sub     z0.b, p0/m, z0.b, z0.b
 // CHECK-INST: sub     z0.b, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x00,0x01,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 01 04 <unknown>
+// CHECK-UNKNOWN: 04010000 <unknown>
 
 sub     z0.s, p0/m, z0.s, z0.s
 // CHECK-INST: sub     z0.s, p0/m, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x00,0x81,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 81 04 <unknown>
+// CHECK-UNKNOWN: 04810000 <unknown>
 
 sub     z21.h, p5/m, z21.h, z10.h
 // CHECK-INST: sub     z21.h, p5/m, z21.h, z10.h
 // CHECK-ENCODING: [0x55,0x15,0x41,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 55 15 41 04 <unknown>
+// CHECK-UNKNOWN: 04411555 <unknown>
 
 sub     z23.b, p3/m, z23.b, z13.b
 // CHECK-INST: sub     z23.b, p3/m, z23.b, z13.b
 // CHECK-ENCODING: [0xb7,0x0d,0x01,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 0d 01 04 <unknown>
+// CHECK-UNKNOWN: 04010db7 <unknown>
 
 // -----------------------
 //
@@ -208,85 +208,85 @@ sub     z0.b, z0.b, #0
 // CHECK-INST: sub     z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x21,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 21 25 <unknown>
+// CHECK-UNKNOWN: 2521c000 <unknown>
 
 sub     z31.b, z31.b, #255
 // CHECK-INST: sub     z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x21,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 21 25 <unknown>
+// CHECK-UNKNOWN: 2521dfff <unknown>
 
 sub     z0.h, z0.h, #0
 // CHECK-INST: sub     z0.h, z0.h, #0
 // CHECK-ENCODING: [0x00,0xc0,0x61,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 61 25 <unknown>
+// CHECK-UNKNOWN: 2561c000 <unknown>
 
 sub     z0.h, z0.h, #0, lsl #8
 // CHECK-INST: sub     z0.h, z0.h, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0x61,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 61 25 <unknown>
+// CHECK-UNKNOWN: 2561e000 <unknown>
 
 sub     z31.h, z31.h, #255, lsl #8
 // CHECK-INST: sub     z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x61,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 61 25 <unknown>
+// CHECK-UNKNOWN: 2561ffff <unknown>
 
 sub     z31.h, z31.h, #65280
 // CHECK-INST: sub     z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x61,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 61 25 <unknown>
+// CHECK-UNKNOWN: 2561ffff <unknown>
 
 sub     z0.s, z0.s, #0
 // CHECK-INST: sub     z0.s, z0.s, #0
 // CHECK-ENCODING: [0x00,0xc0,0xa1,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 a1 25 <unknown>
+// CHECK-UNKNOWN: 25a1c000 <unknown>
 
 sub     z0.s, z0.s, #0, lsl #8
 // CHECK-INST: sub     z0.s, z0.s, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xa1,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 a1 25 <unknown>
+// CHECK-UNKNOWN: 25a1e000 <unknown>
 
 sub     z31.s, z31.s, #255, lsl #8
 // CHECK-INST: sub     z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa1,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a1 25 <unknown>
+// CHECK-UNKNOWN: 25a1ffff <unknown>
 
 sub     z31.s, z31.s, #65280
 // CHECK-INST: sub     z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa1,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a1 25 <unknown>
+// CHECK-UNKNOWN: 25a1ffff <unknown>
 
 sub     z0.d, z0.d, #0
 // CHECK-INST: sub     z0.d, z0.d, #0
 // CHECK-ENCODING: [0x00,0xc0,0xe1,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 e1 25 <unknown>
+// CHECK-UNKNOWN: 25e1c000 <unknown>
 
 sub     z0.d, z0.d, #0, lsl #8
 // CHECK-INST: sub     z0.d, z0.d, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xe1,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e1 25 <unknown>
+// CHECK-UNKNOWN: 25e1e000 <unknown>
 
 sub     z31.d, z31.d, #255, lsl #8
 // CHECK-INST: sub     z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe1,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e1 25 <unknown>
+// CHECK-UNKNOWN: 25e1ffff <unknown>
 
 sub     z31.d, z31.d, #65280
 // CHECK-INST: sub     z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe1,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e1 25 <unknown>
+// CHECK-UNKNOWN: 25e1ffff <unknown>
 
 
 
@@ -297,34 +297,34 @@ movprfx z23.b, p3/z, z30.b
 // CHECK-INST: movprfx	z23.b, p3/z, z30.b
 // CHECK-ENCODING: [0xd7,0x2f,0x10,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: d7 2f 10 04 <unknown>
+// CHECK-UNKNOWN: 04102fd7 <unknown>
 
 sub     z23.b, p3/m, z23.b, z13.b
 // CHECK-INST: sub	z23.b, p3/m, z23.b, z13.b
 // CHECK-ENCODING: [0xb7,0x0d,0x01,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 0d 01 04 <unknown>
+// CHECK-UNKNOWN: 04010db7 <unknown>
 
 movprfx z23, z30
 // CHECK-INST: movprfx	z23, z30
 // CHECK-ENCODING: [0xd7,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: d7 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bfd7 <unknown>
 
 sub     z23.b, p3/m, z23.b, z13.b
 // CHECK-INST: sub	z23.b, p3/m, z23.b, z13.b
 // CHECK-ENCODING: [0xb7,0x0d,0x01,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: b7 0d 01 04 <unknown>
+// CHECK-UNKNOWN: 04010db7 <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sub     z31.d, z31.d, #65280
 // CHECK-INST: sub	z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe1,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e1 25 <unknown>
+// CHECK-UNKNOWN: 25e1ffff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/subr.s b/llvm/test/MC/AArch64/SVE/subr.s
index 3e6b8db42f137..7207aa4ecce5d 100644
--- a/llvm/test/MC/AArch64/SVE/subr.s
+++ b/llvm/test/MC/AArch64/SVE/subr.s
@@ -14,109 +14,109 @@ subr    z0.b, p0/m, z0.b, z0.b
 // CHECK-INST: subr z0.b, p0/m, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x00,0x03,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 03 04 <unknown>
+// CHECK-UNKNOWN: 04030000 <unknown>
 
 subr    z0.h, p0/m, z0.h, z0.h
 // CHECK-INST: subr z0.h, p0/m, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x00,0x43,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 43 04 <unknown>
+// CHECK-UNKNOWN: 04430000 <unknown>
 
 subr    z0.s, p0/m, z0.s, z0.s
 // CHECK-INST: subr z0.s, p0/m, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x00,0x83,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 83 04 <unknown>
+// CHECK-UNKNOWN: 04830000 <unknown>
 
 subr    z0.d, p0/m, z0.d, z0.d
 // CHECK-INST: subr z0.d, p0/m, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x00,0xc3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 00 c3 04 <unknown>
+// CHECK-UNKNOWN: 04c30000 <unknown>
 
 subr    z0.b, z0.b, #0
 // CHECK-INST: subr z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x23,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 23 25 <unknown>
+// CHECK-UNKNOWN: 2523c000 <unknown>
 
 subr    z31.b, z31.b, #255
 // CHECK-INST: subr z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x23,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 23 25 <unknown>
+// CHECK-UNKNOWN: 2523dfff <unknown>
 
 subr    z0.h, z0.h, #0
 // CHECK-INST: subr z0.h, z0.h, #0
 // CHECK-ENCODING: [0x00,0xc0,0x63,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 63 25 <unknown>
+// CHECK-UNKNOWN: 2563c000 <unknown>
 
 subr    z0.h, z0.h, #0, lsl #8
 // CHECK-INST: subr z0.h, z0.h, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0x63,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 63 25 <unknown>
+// CHECK-UNKNOWN: 2563e000 <unknown>
 
 subr    z31.h, z31.h, #255, lsl #8
 // CHECK-INST: subr z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x63,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 63 25 <unknown>
+// CHECK-UNKNOWN: 2563ffff <unknown>
 
 subr    z31.h, z31.h, #65280
 // CHECK-INST: subr z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x63,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 63 25 <unknown>
+// CHECK-UNKNOWN: 2563ffff <unknown>
 
 subr    z0.s, z0.s, #0
 // CHECK-INST: subr z0.s, z0.s, #0
 // CHECK-ENCODING: [0x00,0xc0,0xa3,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 a3 25 <unknown>
+// CHECK-UNKNOWN: 25a3c000 <unknown>
 
 subr    z0.s, z0.s, #0, lsl #8
 // CHECK-INST: subr z0.s, z0.s, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xa3,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 a3 25 <unknown>
+// CHECK-UNKNOWN: 25a3e000 <unknown>
 
 subr    z31.s, z31.s, #255, lsl #8
 // CHECK-INST: subr z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa3,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a3 25 <unknown>
+// CHECK-UNKNOWN: 25a3ffff <unknown>
 
 subr    z31.s, z31.s, #65280
 // CHECK-INST: subr z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa3,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a3 25 <unknown>
+// CHECK-UNKNOWN: 25a3ffff <unknown>
 
 subr    z0.d, z0.d, #0
 // CHECK-INST: subr z0.d, z0.d, #0
 // CHECK-ENCODING: [0x00,0xc0,0xe3,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 e3 25 <unknown>
+// CHECK-UNKNOWN: 25e3c000 <unknown>
 
 subr    z0.d, z0.d, #0, lsl #8
 // CHECK-INST: subr z0.d, z0.d, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xe3,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e3 25 <unknown>
+// CHECK-UNKNOWN: 25e3e000 <unknown>
 
 subr    z31.d, z31.d, #255, lsl #8
 // CHECK-INST: subr z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe3,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e3 25 <unknown>
+// CHECK-UNKNOWN: 25e3ffff <unknown>
 
 subr    z31.d, z31.d, #65280
 // CHECK-INST: subr z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe3,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e3 25 <unknown>
+// CHECK-UNKNOWN: 25e3ffff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -126,34 +126,34 @@ movprfx z5.d, p0/z, z7.d
 // CHECK-INST: movprfx	z5.d, p0/z, z7.d
 // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020e5 <unknown>
 
 subr    z5.d, p0/m, z5.d, z0.d
 // CHECK-INST: subr	z5.d, p0/m, z5.d, z0.d
 // CHECK-ENCODING: [0x05,0x00,0xc3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 00 c3 04 <unknown>
+// CHECK-UNKNOWN: 04c30005 <unknown>
 
 movprfx z5, z7
 // CHECK-INST: movprfx	z5, z7
 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce5 <unknown>
 
 subr    z5.d, p0/m, z5.d, z0.d
 // CHECK-INST: subr	z5.d, p0/m, z5.d, z0.d
 // CHECK-ENCODING: [0x05,0x00,0xc3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 00 c3 04 <unknown>
+// CHECK-UNKNOWN: 04c30005 <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 subr    z31.d, z31.d, #65280
 // CHECK-INST: subr	z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe3,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e3 25 <unknown>
+// CHECK-UNKNOWN: 25e3ffff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sunpkhi.s b/llvm/test/MC/AArch64/SVE/sunpkhi.s
index 75eff230497c3..6978a3428dd78 100644
--- a/llvm/test/MC/AArch64/SVE/sunpkhi.s
+++ b/llvm/test/MC/AArch64/SVE/sunpkhi.s
@@ -13,16 +13,16 @@ sunpkhi z31.h, z31.b
 // CHECK-INST: sunpkhi	z31.h, z31.b
 // CHECK-ENCODING: [0xff,0x3b,0x71,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b 71 05 <unknown>
+// CHECK-UNKNOWN: 05713bff <unknown>
 
 sunpkhi z31.s, z31.h
 // CHECK-INST: sunpkhi	z31.s, z31.h
 // CHECK-ENCODING: [0xff,0x3b,0xb1,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b b1 05 <unknown>
+// CHECK-UNKNOWN: 05b13bff <unknown>
 
 sunpkhi z31.d, z31.s
 // CHECK-INST: sunpkhi	z31.d, z31.s
 // CHECK-ENCODING: [0xff,0x3b,0xf1,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b f1 05 <unknown>
+// CHECK-UNKNOWN: 05f13bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sunpklo.s b/llvm/test/MC/AArch64/SVE/sunpklo.s
index 2e0aa9b856c93..47730f785702c 100644
--- a/llvm/test/MC/AArch64/SVE/sunpklo.s
+++ b/llvm/test/MC/AArch64/SVE/sunpklo.s
@@ -13,16 +13,16 @@ sunpklo z31.h, z31.b
 // CHECK-INST: sunpklo	z31.h, z31.b
 // CHECK-ENCODING: [0xff,0x3b,0x70,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b 70 05 <unknown>
+// CHECK-UNKNOWN: 05703bff <unknown>
 
 sunpklo z31.s, z31.h
 // CHECK-INST: sunpklo	z31.s, z31.h
 // CHECK-ENCODING: [0xff,0x3b,0xb0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b b0 05 <unknown>
+// CHECK-UNKNOWN: 05b03bff <unknown>
 
 sunpklo z31.d, z31.s
 // CHECK-INST: sunpklo	z31.d, z31.s
 // CHECK-ENCODING: [0xff,0x3b,0xf0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b f0 05 <unknown>
+// CHECK-UNKNOWN: 05f03bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sxtb.s b/llvm/test/MC/AArch64/SVE/sxtb.s
index 7c5550d34fd5d..e483afdc19332 100644
--- a/llvm/test/MC/AArch64/SVE/sxtb.s
+++ b/llvm/test/MC/AArch64/SVE/sxtb.s
@@ -13,37 +13,37 @@ sxtb    z0.h, p0/m, z0.h
 // CHECK-INST: sxtb    z0.h, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x50,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 50 04 <unknown>
+// CHECK-UNKNOWN: 0450a000 <unknown>
 
 sxtb    z0.s, p0/m, z0.s
 // CHECK-INST: sxtb    z0.s, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x90,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 90 04 <unknown>
+// CHECK-UNKNOWN: 0490a000 <unknown>
 
 sxtb    z0.d, p0/m, z0.d
 // CHECK-INST: sxtb    z0.d, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d0a000 <unknown>
 
 sxtb    z31.h, p7/m, z31.h
 // CHECK-INST: sxtb    z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x50,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 50 04 <unknown>
+// CHECK-UNKNOWN: 0450bfff <unknown>
 
 sxtb    z31.s, p7/m, z31.s
 // CHECK-INST: sxtb    z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x90,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 90 04 <unknown>
+// CHECK-UNKNOWN: 0490bfff <unknown>
 
 sxtb    z31.d, p7/m, z31.d
 // CHECK-INST: sxtb    z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf d0 04 <unknown>
+// CHECK-UNKNOWN: 04d0bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -53,22 +53,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 sxtb    z4.d, p7/m, z31.d
 // CHECK-INST: sxtb	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d0 04 <unknown>
+// CHECK-UNKNOWN: 04d0bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 sxtb    z4.d, p7/m, z31.d
 // CHECK-INST: sxtb	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d0 04 <unknown>
+// CHECK-UNKNOWN: 04d0bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sxth.s b/llvm/test/MC/AArch64/SVE/sxth.s
index 10691f7bfd29f..86827480800a1 100644
--- a/llvm/test/MC/AArch64/SVE/sxth.s
+++ b/llvm/test/MC/AArch64/SVE/sxth.s
@@ -13,25 +13,25 @@ sxth    z0.s, p0/m, z0.s
 // CHECK-INST: sxth    z0.s, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x92,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 92 04 <unknown>
+// CHECK-UNKNOWN: 0492a000 <unknown>
 
 sxth    z0.d, p0/m, z0.d
 // CHECK-INST: sxth    z0.d, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd2,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d2 04 <unknown>
+// CHECK-UNKNOWN: 04d2a000 <unknown>
 
 sxth    z31.s, p7/m, z31.s
 // CHECK-INST: sxth    z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x92,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 92 04 <unknown>
+// CHECK-UNKNOWN: 0492bfff <unknown>
 
 sxth    z31.d, p7/m, z31.d
 // CHECK-INST: sxth    z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xd2,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf d2 04 <unknown>
+// CHECK-UNKNOWN: 04d2bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 sxth    z4.d, p7/m, z31.d
 // CHECK-INST: sxth	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd2,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d2 04 <unknown>
+// CHECK-UNKNOWN: 04d2bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 sxth    z4.d, p7/m, z31.d
 // CHECK-INST: sxth	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd2,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d2 04 <unknown>
+// CHECK-UNKNOWN: 04d2bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/sxtw.s b/llvm/test/MC/AArch64/SVE/sxtw.s
index be0799b9a2fe6..00fafc400c765 100644
--- a/llvm/test/MC/AArch64/SVE/sxtw.s
+++ b/llvm/test/MC/AArch64/SVE/sxtw.s
@@ -13,13 +13,13 @@ sxtw    z0.d, p0/m, z0.d
 // CHECK-INST: sxtw    z0.d, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd4,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d4 04 <unknown>
+// CHECK-UNKNOWN: 04d4a000 <unknown>
 
 sxtw    z31.d, p7/m, z31.d
 // CHECK-INST: sxtw    z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xd4,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf d4 04 <unknown>
+// CHECK-UNKNOWN: 04d4bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -29,22 +29,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 sxtw    z4.d, p7/m, z31.d
 // CHECK-INST: sxtw	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd4,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d4 04 <unknown>
+// CHECK-UNKNOWN: 04d4bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 sxtw    z4.d, p7/m, z31.d
 // CHECK-INST: sxtw	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd4,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d4 04 <unknown>
+// CHECK-UNKNOWN: 04d4bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/system-regs.s b/llvm/test/MC/AArch64/SVE/system-regs.s
index e3d914104e4f6..d851894c74cd4 100644
--- a/llvm/test/MC/AArch64/SVE/system-regs.s
+++ b/llvm/test/MC/AArch64/SVE/system-regs.s
@@ -11,52 +11,52 @@ mrs x3, ID_AA64ZFR0_EL1
 // CHECK-INST: mrs x3, ID_AA64ZFR0_EL1
 // CHECK-ENCODING: [0x83,0x04,0x38,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: 83 04 38 d5   mrs   x3, S3_0_C0_C4_4
+// CHECK-UNKNOWN: d5380483   mrs   x3, S3_0_C0_C4_4
 
 mrs x3, ZCR_EL1
 // CHECK-INST: mrs x3, ZCR_EL1
 // CHECK-ENCODING: [0x03,0x12,0x38,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: 03 12 38 d5   mrs   x3, S3_0_C1_C2_0
+// CHECK-UNKNOWN: d5381203   mrs   x3, S3_0_C1_C2_0
 
 mrs x3, ZCR_EL2
 // CHECK-INST: mrs x3, ZCR_EL2
 // CHECK-ENCODING: [0x03,0x12,0x3c,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: 03 12 3c d5   mrs   x3, S3_4_C1_C2_0
+// CHECK-UNKNOWN: d53c1203   mrs   x3, S3_4_C1_C2_0
 
 mrs x3, ZCR_EL3
 // CHECK-INST: mrs x3, ZCR_EL3
 // CHECK-ENCODING: [0x03,0x12,0x3e,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: 03 12 3e d5   mrs   x3, S3_6_C1_C2_0
+// CHECK-UNKNOWN: d53e1203   mrs   x3, S3_6_C1_C2_0
 
 mrs x3, ZCR_EL12
 // CHECK-INST: mrs x3, ZCR_EL12
 // CHECK-ENCODING: [0x03,0x12,0x3d,0xd5]
 // CHECK-ERROR: expected readable system register
-// CHECK-UNKNOWN: 03 12 3d d5   mrs   x3, S3_5_C1_C2_0
+// CHECK-UNKNOWN: d53d1203   mrs   x3, S3_5_C1_C2_0
 
 msr ZCR_EL1, x3
 // CHECK-INST: msr ZCR_EL1, x3
 // CHECK-ENCODING: [0x03,0x12,0x18,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: 03 12 18 d5   msr   S3_0_C1_C2_0, x3
+// CHECK-UNKNOWN: d5181203   msr   S3_0_C1_C2_0, x3
 
 msr ZCR_EL2, x3
 // CHECK-INST: msr ZCR_EL2, x3
 // CHECK-ENCODING: [0x03,0x12,0x1c,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: 03 12 1c d5   msr   S3_4_C1_C2_0, x3
+// CHECK-UNKNOWN: d51c1203   msr   S3_4_C1_C2_0, x3
 
 msr ZCR_EL3, x3
 // CHECK-INST: msr ZCR_EL3, x3
 // CHECK-ENCODING: [0x03,0x12,0x1e,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: 03 12 1e d5   msr   S3_6_C1_C2_0, x3
+// CHECK-UNKNOWN: d51e1203   msr   S3_6_C1_C2_0, x3
 
 msr ZCR_EL12, x3
 // CHECK-INST: msr ZCR_EL12, x3
 // CHECK-ENCODING: [0x03,0x12,0x1d,0xd5]
 // CHECK-ERROR: expected writable system register or pstate
-// CHECK-UNKNOWN: 03 12 1d d5   msr   S3_5_C1_C2_0, x3
+// CHECK-UNKNOWN: d51d1203   msr   S3_5_C1_C2_0, x3

diff  --git a/llvm/test/MC/AArch64/SVE/tbl.s b/llvm/test/MC/AArch64/SVE/tbl.s
index 3e8034cadd021..4f55cb4d88299 100644
--- a/llvm/test/MC/AArch64/SVE/tbl.s
+++ b/llvm/test/MC/AArch64/SVE/tbl.s
@@ -13,46 +13,46 @@ tbl  z31.b, z31.b, z31.b
 // CHECK-INST: tbl	z31.b, { z31.b }, z31.b
 // CHECK-ENCODING: [0xff,0x33,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 33 3f 05 <unknown>
+// CHECK-UNKNOWN: 053f33ff <unknown>
 
 tbl  z31.h, z31.h, z31.h
 // CHECK-INST: tbl	z31.h, { z31.h }, z31.h
 // CHECK-ENCODING: [0xff,0x33,0x7f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 33 7f 05 <unknown>
+// CHECK-UNKNOWN: 057f33ff <unknown>
 
 tbl  z31.s, z31.s, z31.s
 // CHECK-INST: tbl	z31.s, { z31.s }, z31.s
 // CHECK-ENCODING: [0xff,0x33,0xbf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 33 bf 05 <unknown>
+// CHECK-UNKNOWN: 05bf33ff <unknown>
 
 tbl  z31.d, z31.d, z31.d
 // CHECK-INST: tbl	z31.d, { z31.d }, z31.d
 // CHECK-ENCODING: [0xff,0x33,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 33 ff 05 <unknown>
+// CHECK-UNKNOWN: 05ff33ff <unknown>
 
 tbl  z31.b, { z31.b }, z31.b
 // CHECK-INST: tbl	z31.b, { z31.b }, z31.b
 // CHECK-ENCODING: [0xff,0x33,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 33 3f 05 <unknown>
+// CHECK-UNKNOWN: 053f33ff <unknown>
 
 tbl  z31.h, { z31.h }, z31.h
 // CHECK-INST: tbl	z31.h, { z31.h }, z31.h
 // CHECK-ENCODING: [0xff,0x33,0x7f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 33 7f 05 <unknown>
+// CHECK-UNKNOWN: 057f33ff <unknown>
 
 tbl  z31.s, { z31.s }, z31.s
 // CHECK-INST: tbl	z31.s, { z31.s }, z31.s
 // CHECK-ENCODING: [0xff,0x33,0xbf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 33 bf 05 <unknown>
+// CHECK-UNKNOWN: 05bf33ff <unknown>
 
 tbl  z31.d, { z31.d }, z31.d
 // CHECK-INST: tbl	z31.d, { z31.d }, z31.d
 // CHECK-ENCODING: [0xff,0x33,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 33 ff 05 <unknown>
+// CHECK-UNKNOWN: 05ff33ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/trn1.s b/llvm/test/MC/AArch64/SVE/trn1.s
index 27309c15b408a..2990e1a69e93f 100644
--- a/llvm/test/MC/AArch64/SVE/trn1.s
+++ b/llvm/test/MC/AArch64/SVE/trn1.s
@@ -13,46 +13,46 @@ trn1    z31.b, z31.b, z31.b
 // CHECK-INST: trn1	z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x73,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 73 3f 05 <unknown>
+// CHECK-UNKNOWN: 053f73ff <unknown>
 
 trn1    z31.h, z31.h, z31.h
 // CHECK-INST: trn1	z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x73,0x7f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 73 7f 05 <unknown>
+// CHECK-UNKNOWN: 057f73ff <unknown>
 
 trn1    z31.s, z31.s, z31.s
 // CHECK-INST: trn1	z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x73,0xbf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 73 bf 05 <unknown>
+// CHECK-UNKNOWN: 05bf73ff <unknown>
 
 trn1    z31.d, z31.d, z31.d
 // CHECK-INST: trn1	z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x73,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 73 ff 05 <unknown>
+// CHECK-UNKNOWN: 05ff73ff <unknown>
 
 trn1    p15.b, p15.b, p15.b
 // CHECK-INST: trn1	p15.b, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x51,0x2f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 51 2f 05 <unknown>
+// CHECK-UNKNOWN: 052f51ef <unknown>
 
 trn1    p15.s, p15.s, p15.s
 // CHECK-INST: trn1	p15.s, p15.s, p15.s
 // CHECK-ENCODING: [0xef,0x51,0xaf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 51 af 05 <unknown>
+// CHECK-UNKNOWN: 05af51ef <unknown>
 
 trn1    p15.h, p15.h, p15.h
 // CHECK-INST: trn1	p15.h, p15.h, p15.h
 // CHECK-ENCODING: [0xef,0x51,0x6f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 51 6f 05 <unknown>
+// CHECK-UNKNOWN: 056f51ef <unknown>
 
 trn1    p15.d, p15.d, p15.d
 // CHECK-INST: trn1	p15.d, p15.d, p15.d
 // CHECK-ENCODING: [0xef,0x51,0xef,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 51 ef 05 <unknown>
+// CHECK-UNKNOWN: 05ef51ef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/trn2.s b/llvm/test/MC/AArch64/SVE/trn2.s
index 90c648b048dd9..e79a406898f51 100644
--- a/llvm/test/MC/AArch64/SVE/trn2.s
+++ b/llvm/test/MC/AArch64/SVE/trn2.s
@@ -13,46 +13,46 @@ trn2    z31.b, z31.b, z31.b
 // CHECK-INST: trn2	z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x77,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 77 3f 05 <unknown>
+// CHECK-UNKNOWN: 053f77ff <unknown>
 
 trn2    z31.h, z31.h, z31.h
 // CHECK-INST: trn2	z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x77,0x7f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 77 7f 05 <unknown>
+// CHECK-UNKNOWN: 057f77ff <unknown>
 
 trn2    z31.s, z31.s, z31.s
 // CHECK-INST: trn2	z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x77,0xbf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 77 bf 05 <unknown>
+// CHECK-UNKNOWN: 05bf77ff <unknown>
 
 trn2    z31.d, z31.d, z31.d
 // CHECK-INST: trn2	z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x77,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 77 ff 05 <unknown>
+// CHECK-UNKNOWN: 05ff77ff <unknown>
 
 trn2    p15.b, p15.b, p15.b
 // CHECK-INST: trn2	p15.b, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x55,0x2f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 55 2f 05 <unknown>
+// CHECK-UNKNOWN: 052f55ef <unknown>
 
 trn2    p15.s, p15.s, p15.s
 // CHECK-INST: trn2	p15.s, p15.s, p15.s
 // CHECK-ENCODING: [0xef,0x55,0xaf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 55 af 05 <unknown>
+// CHECK-UNKNOWN: 05af55ef <unknown>
 
 trn2    p15.h, p15.h, p15.h
 // CHECK-INST: trn2	p15.h, p15.h, p15.h
 // CHECK-ENCODING: [0xef,0x55,0x6f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 55 6f 05 <unknown>
+// CHECK-UNKNOWN: 056f55ef <unknown>
 
 trn2    p15.d, p15.d, p15.d
 // CHECK-INST: trn2	p15.d, p15.d, p15.d
 // CHECK-ENCODING: [0xef,0x55,0xef,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 55 ef 05 <unknown>
+// CHECK-UNKNOWN: 05ef55ef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uabd.s b/llvm/test/MC/AArch64/SVE/uabd.s
index 86eb77bab5f0b..28389c157bcbd 100644
--- a/llvm/test/MC/AArch64/SVE/uabd.s
+++ b/llvm/test/MC/AArch64/SVE/uabd.s
@@ -13,25 +13,25 @@ uabd  z31.b, p7/m, z31.b, z31.b
 // CHECK-INST: uabd	z31.b, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x1f,0x0d,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 0d 04 <unknown>
+// CHECK-UNKNOWN: 040d1fff <unknown>
 
 uabd  z31.h, p7/m, z31.h, z31.h
 // CHECK-INST: uabd	z31.h, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x1f,0x4d,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 4d 04 <unknown>
+// CHECK-UNKNOWN: 044d1fff <unknown>
 
 uabd  z31.s, p7/m, z31.s, z31.s
 // CHECK-INST: uabd	z31.s, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1f,0x8d,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 8d 04 <unknown>
+// CHECK-UNKNOWN: 048d1fff <unknown>
 
 uabd  z31.d, p7/m, z31.d, z31.d
 // CHECK-INST: uabd	z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xcd,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f cd 04 <unknown>
+// CHECK-UNKNOWN: 04cd1fff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 uabd  z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: uabd	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xcd,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f cd 04 <unknown>
+// CHECK-UNKNOWN: 04cd1fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 uabd  z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: uabd	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xcd,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f cd 04 <unknown>
+// CHECK-UNKNOWN: 04cd1fe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uaddv.s b/llvm/test/MC/AArch64/SVE/uaddv.s
index f17c57881057a..887d3acef82f1 100644
--- a/llvm/test/MC/AArch64/SVE/uaddv.s
+++ b/llvm/test/MC/AArch64/SVE/uaddv.s
@@ -13,22 +13,22 @@ uaddv d0, p7, z31.b
 // CHECK-INST: uaddv	d0, p7, z31.b
 // CHECK-ENCODING: [0xe0,0x3f,0x01,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 01 04 <unknown>
+// CHECK-UNKNOWN: 04013fe0 <unknown>
 
 uaddv d0, p7, z31.h
 // CHECK-INST: uaddv	d0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x41,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 41 04 <unknown>
+// CHECK-UNKNOWN: 04413fe0 <unknown>
 
 uaddv d0, p7, z31.s
 // CHECK-INST: uaddv	d0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x81,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 81 04 <unknown>
+// CHECK-UNKNOWN: 04813fe0 <unknown>
 
 uaddv d0, p7, z31.d
 // CHECK-INST: uaddv	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xc1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f c1 04 <unknown>
+// CHECK-UNKNOWN: 04c13fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/ucvtf.s b/llvm/test/MC/AArch64/SVE/ucvtf.s
index 687694ffe3f59..f02fbbc83aa89 100644
--- a/llvm/test/MC/AArch64/SVE/ucvtf.s
+++ b/llvm/test/MC/AArch64/SVE/ucvtf.s
@@ -13,43 +13,43 @@ ucvtf   z0.h, p0/m, z0.h
 // CHECK-INST: ucvtf   z0.h, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x53,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 53 65 <unknown>
+// CHECK-UNKNOWN: 6553a000 <unknown>
 
 ucvtf   z0.h, p0/m, z0.s
 // CHECK-INST: ucvtf   z0.h, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x55,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 55 65 <unknown>
+// CHECK-UNKNOWN: 6555a000 <unknown>
 
 ucvtf   z0.h, p0/m, z0.d
 // CHECK-INST: ucvtf   z0.h, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0x57,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 57 65 <unknown>
+// CHECK-UNKNOWN: 6557a000 <unknown>
 
 ucvtf   z0.s, p0/m, z0.s
 // CHECK-INST: ucvtf   z0.s, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x95,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 95 65 <unknown>
+// CHECK-UNKNOWN: 6595a000 <unknown>
 
 ucvtf   z0.s, p0/m, z0.d
 // CHECK-INST: ucvtf   z0.s, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd5,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d5 65 <unknown>
+// CHECK-UNKNOWN: 65d5a000 <unknown>
 
 ucvtf   z0.d, p0/m, z0.s
 // CHECK-INST: ucvtf   z0.d, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0xd1,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d1 65 <unknown>
+// CHECK-UNKNOWN: 65d1a000 <unknown>
 
 ucvtf   z0.d, p0/m, z0.d
 // CHECK-INST: ucvtf   z0.d, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd7,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d7 65 <unknown>
+// CHECK-UNKNOWN: 65d7a000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -59,22 +59,22 @@ movprfx z5.d, p0/z, z7.d
 // CHECK-INST: movprfx	z5.d, p0/z, z7.d
 // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020e5 <unknown>
 
 ucvtf   z5.d, p0/m, z0.d
 // CHECK-INST: ucvtf	z5.d, p0/m, z0.d
 // CHECK-ENCODING: [0x05,0xa0,0xd7,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 a0 d7 65 <unknown>
+// CHECK-UNKNOWN: 65d7a005 <unknown>
 
 movprfx z5, z7
 // CHECK-INST: movprfx	z5, z7
 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce5 <unknown>
 
 ucvtf   z5.d, p0/m, z0.d
 // CHECK-INST: ucvtf	z5.d, p0/m, z0.d
 // CHECK-ENCODING: [0x05,0xa0,0xd7,0x65]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 05 a0 d7 65 <unknown>
+// CHECK-UNKNOWN: 65d7a005 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/udiv.s b/llvm/test/MC/AArch64/SVE/udiv.s
index 064611f2050b4..7e8093f712d0e 100644
--- a/llvm/test/MC/AArch64/SVE/udiv.s
+++ b/llvm/test/MC/AArch64/SVE/udiv.s
@@ -13,13 +13,13 @@ udiv   z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: udiv	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x1f,0x95,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f 95 04 <unknown>
+// CHECK-UNKNOWN: 04951fe0 <unknown>
 
 udiv   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: udiv	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d5 04 <unknown>
+// CHECK-UNKNOWN: 04d51fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -29,22 +29,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 udiv   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: udiv	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d5 04 <unknown>
+// CHECK-UNKNOWN: 04d51fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 udiv   z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: udiv	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d5 04 <unknown>
+// CHECK-UNKNOWN: 04d51fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/udivr.s b/llvm/test/MC/AArch64/SVE/udivr.s
index 74cee765c5f0e..a57b6740d3ed0 100644
--- a/llvm/test/MC/AArch64/SVE/udivr.s
+++ b/llvm/test/MC/AArch64/SVE/udivr.s
@@ -13,13 +13,13 @@ udivr  z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: udivr	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x1f,0x97,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f 97 04 <unknown>
+// CHECK-UNKNOWN: 04971fe0 <unknown>
 
 udivr  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: udivr	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d7 04 <unknown>
+// CHECK-UNKNOWN: 04d71fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -29,22 +29,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 udivr  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: udivr	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d7 04 <unknown>
+// CHECK-UNKNOWN: 04d71fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 udivr  z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: udivr	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd7,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d7 04 <unknown>
+// CHECK-UNKNOWN: 04d71fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/udot.s b/llvm/test/MC/AArch64/SVE/udot.s
index 146214fcc5f3a..04a204f5c6899 100644
--- a/llvm/test/MC/AArch64/SVE/udot.s
+++ b/llvm/test/MC/AArch64/SVE/udot.s
@@ -13,25 +13,25 @@ udot  z0.s, z1.b, z31.b
 // CHECK-INST: udot	z0.s, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x04,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 04 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f0420 <unknown>
 
 udot  z0.d, z1.h, z31.h
 // CHECK-INST: udot	z0.d, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x04,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 04 df 44 <unknown>
+// CHECK-UNKNOWN: 44df0420 <unknown>
 
 udot  z0.s, z1.b, z7.b[3]
 // CHECK-INST: udot	z0.s, z1.b, z7.b[3]
 // CHECK-ENCODING: [0x20,0x04,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 04 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf0420 <unknown>
 
 udot  z0.d, z1.h, z15.h[1]
 // CHECK-INST: udot	z0.d, z1.h, z15.h[1]
 // CHECK-ENCODING: [0x20,0x04,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 04 ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff0420 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 udot  z0.d, z1.h, z31.h
 // CHECK-INST: udot	z0.d, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x04,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 04 df 44 <unknown>
+// CHECK-UNKNOWN: 44df0420 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 udot  z0.d, z1.h, z15.h[1]
 // CHECK-INST: udot	z0.d, z1.h, z15.h[1]
 // CHECK-ENCODING: [0x20,0x04,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 04 ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff0420 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/umax.s b/llvm/test/MC/AArch64/SVE/umax.s
index 8a0545bb8a300..368c190ba2bd3 100644
--- a/llvm/test/MC/AArch64/SVE/umax.s
+++ b/llvm/test/MC/AArch64/SVE/umax.s
@@ -13,73 +13,73 @@ umax    z0.b, z0.b, #0
 // CHECK-INST: umax	z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x29,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 29 25 <unknown>
+// CHECK-UNKNOWN: 2529c000 <unknown>
 
 umax    z31.b, z31.b, #255
 // CHECK-INST: umax	z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x29,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 29 25 <unknown>
+// CHECK-UNKNOWN: 2529dfff <unknown>
 
 umax    z0.b, z0.b, #0
 // CHECK-INST: umax	z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x29,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 29 25 <unknown>
+// CHECK-UNKNOWN: 2529c000 <unknown>
 
 umax    z31.b, z31.b, #255
 // CHECK-INST: umax	z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x29,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 29 25 <unknown>
+// CHECK-UNKNOWN: 2529dfff <unknown>
 
 umax    z0.b, z0.b, #0
 // CHECK-INST: umax	z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x29,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 29 25 <unknown>
+// CHECK-UNKNOWN: 2529c000 <unknown>
 
 umax    z31.b, z31.b, #255
 // CHECK-INST: umax	z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x29,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 29 25 <unknown>
+// CHECK-UNKNOWN: 2529dfff <unknown>
 
 umax    z0.b, z0.b, #0
 // CHECK-INST: umax	z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x29,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 29 25 <unknown>
+// CHECK-UNKNOWN: 2529c000 <unknown>
 
 umax    z31.b, z31.b, #255
 // CHECK-INST: umax	z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x29,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 29 25 <unknown>
+// CHECK-UNKNOWN: 2529dfff <unknown>
 
 umax    z31.b, p7/m, z31.b, z31.b
 // CHECK-INST: umax    z31.b, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x1f,0x09,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 09 04 <unknown>
+// CHECK-UNKNOWN: 04091fff <unknown>
 
 umax    z31.h, p7/m, z31.h, z31.h
 // CHECK-INST: umax    z31.h, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x1f,0x49,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 49 04 <unknown>
+// CHECK-UNKNOWN: 04491fff <unknown>
 
 umax    z31.s, p7/m, z31.s, z31.s
 // CHECK-INST: umax    z31.s, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1f,0x89,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 89 04 <unknown>
+// CHECK-UNKNOWN: 04891fff <unknown>
 
 umax    z31.d, p7/m, z31.d, z31.d
 // CHECK-INST: umax    z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xc9,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f c9 04 <unknown>
+// CHECK-UNKNOWN: 04c91fff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -89,34 +89,34 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 umax    z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: umax	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xc9,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f c9 04 <unknown>
+// CHECK-UNKNOWN: 04c91fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 umax    z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: umax	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xc9,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f c9 04 <unknown>
+// CHECK-UNKNOWN: 04c91fe4 <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 umax    z31.b, z31.b, #255
 // CHECK-INST: umax	z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x29,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 29 25 <unknown>
+// CHECK-UNKNOWN: 2529dfff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/umaxv.s b/llvm/test/MC/AArch64/SVE/umaxv.s
index 98a00f5ddb9f1..49944b601ec3c 100644
--- a/llvm/test/MC/AArch64/SVE/umaxv.s
+++ b/llvm/test/MC/AArch64/SVE/umaxv.s
@@ -13,22 +13,22 @@ umaxv b0, p7, z31.b
 // CHECK-INST: umaxv	b0, p7, z31.b
 // CHECK-ENCODING: [0xe0,0x3f,0x09,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 09 04 <unknown>
+// CHECK-UNKNOWN: 04093fe0 <unknown>
 
 umaxv h0, p7, z31.h
 // CHECK-INST: umaxv	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x49,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 49 04 <unknown>
+// CHECK-UNKNOWN: 04493fe0 <unknown>
 
 umaxv s0, p7, z31.s
 // CHECK-INST: umaxv	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x89,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 89 04 <unknown>
+// CHECK-UNKNOWN: 04893fe0 <unknown>
 
 umaxv d0, p7, z31.d
 // CHECK-INST: umaxv	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xc9,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f c9 04 <unknown>
+// CHECK-UNKNOWN: 04c93fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/umin.s b/llvm/test/MC/AArch64/SVE/umin.s
index f855920c52646..bb325d5b6b35b 100644
--- a/llvm/test/MC/AArch64/SVE/umin.s
+++ b/llvm/test/MC/AArch64/SVE/umin.s
@@ -13,73 +13,73 @@ umin    z0.b, z0.b, #0
 // CHECK-INST: umin	z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x2b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 2b 25 <unknown>
+// CHECK-UNKNOWN: 252bc000 <unknown>
 
 umin    z31.b, z31.b, #255
 // CHECK-INST: umin	z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x2b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 2b 25 <unknown>
+// CHECK-UNKNOWN: 252bdfff <unknown>
 
 umin    z0.b, z0.b, #0
 // CHECK-INST: umin	z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x2b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 2b 25 <unknown>
+// CHECK-UNKNOWN: 252bc000 <unknown>
 
 umin    z31.b, z31.b, #255
 // CHECK-INST: umin	z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x2b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 2b 25 <unknown>
+// CHECK-UNKNOWN: 252bdfff <unknown>
 
 umin    z0.b, z0.b, #0
 // CHECK-INST: umin	z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x2b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 2b 25 <unknown>
+// CHECK-UNKNOWN: 252bc000 <unknown>
 
 umin    z31.b, z31.b, #255
 // CHECK-INST: umin	z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x2b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 2b 25 <unknown>
+// CHECK-UNKNOWN: 252bdfff <unknown>
 
 umin    z0.b, z0.b, #0
 // CHECK-INST: umin	z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x2b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 2b 25 <unknown>
+// CHECK-UNKNOWN: 252bc000 <unknown>
 
 umin    z31.b, z31.b, #255
 // CHECK-INST: umin	z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x2b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 2b 25 <unknown>
+// CHECK-UNKNOWN: 252bdfff <unknown>
 
 umin    z31.b, p7/m, z31.b, z31.b
 // CHECK-INST: umin	z31.b, p7/m, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x1f,0x0b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 0b 04 <unknown>
+// CHECK-UNKNOWN: 040b1fff <unknown>
 
 umin    z31.h, p7/m, z31.h, z31.h
 // CHECK-INST: umin	z31.h, p7/m, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x1f,0x4b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 4b 04 <unknown>
+// CHECK-UNKNOWN: 044b1fff <unknown>
 
 umin    z31.s, p7/m, z31.s, z31.s
 // CHECK-INST: umin	z31.s, p7/m, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1f,0x8b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 8b 04 <unknown>
+// CHECK-UNKNOWN: 048b1fff <unknown>
 
 umin    z31.d, p7/m, z31.d, z31.d
 // CHECK-INST: umin	z31.d, p7/m, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x1f,0xcb,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f cb 04 <unknown>
+// CHECK-UNKNOWN: 04cb1fff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -89,34 +89,34 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 umin    z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: umin	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xcb,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f cb 04 <unknown>
+// CHECK-UNKNOWN: 04cb1fe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 umin    z4.d, p7/m, z4.d, z31.d
 // CHECK-INST: umin	z4.d, p7/m, z4.d, z31.d
 // CHECK-ENCODING: [0xe4,0x1f,0xcb,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 1f cb 04 <unknown>
+// CHECK-UNKNOWN: 04cb1fe4 <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 umin    z31.b, z31.b, #255
 // CHECK-INST: umin	z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x2b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 2b 25 <unknown>
+// CHECK-UNKNOWN: 252bdfff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uminv.s b/llvm/test/MC/AArch64/SVE/uminv.s
index b62e13dc82d02..8fe6a39c8fe93 100644
--- a/llvm/test/MC/AArch64/SVE/uminv.s
+++ b/llvm/test/MC/AArch64/SVE/uminv.s
@@ -13,22 +13,22 @@ uminv b0, p7, z31.b
 // CHECK-INST: uminv	b0, p7, z31.b
 // CHECK-ENCODING: [0xe0,0x3f,0x0b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 0b 04 <unknown>
+// CHECK-UNKNOWN: 040b3fe0 <unknown>
 
 uminv h0, p7, z31.h
 // CHECK-INST: uminv	h0, p7, z31.h
 // CHECK-ENCODING: [0xe0,0x3f,0x4b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 4b 04 <unknown>
+// CHECK-UNKNOWN: 044b3fe0 <unknown>
 
 uminv s0, p7, z31.s
 // CHECK-INST: uminv	s0, p7, z31.s
 // CHECK-ENCODING: [0xe0,0x3f,0x8b,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f 8b 04 <unknown>
+// CHECK-UNKNOWN: 048b3fe0 <unknown>
 
 uminv d0, p7, z31.d
 // CHECK-INST: uminv	d0, p7, z31.d
 // CHECK-ENCODING: [0xe0,0x3f,0xcb,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3f cb 04 <unknown>
+// CHECK-UNKNOWN: 04cb3fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/umulh.s b/llvm/test/MC/AArch64/SVE/umulh.s
index 26da956c6b6d5..f888e3ccd1643 100644
--- a/llvm/test/MC/AArch64/SVE/umulh.s
+++ b/llvm/test/MC/AArch64/SVE/umulh.s
@@ -13,25 +13,25 @@ umulh z0.b, p7/m, z0.b, z31.b
 // CHECK-INST: umulh	z0.b, p7/m, z0.b, z31.b
 // CHECK-ENCODING: [0xe0,0x1f,0x13,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f 13 04 <unknown>
+// CHECK-UNKNOWN: 04131fe0 <unknown>
 
 umulh z0.h, p7/m, z0.h, z31.h
 // CHECK-INST: umulh	z0.h, p7/m, z0.h, z31.h
 // CHECK-ENCODING: [0xe0,0x1f,0x53,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f 53 04 <unknown>
+// CHECK-UNKNOWN: 04531fe0 <unknown>
 
 umulh z0.s, p7/m, z0.s, z31.s
 // CHECK-INST: umulh	z0.s, p7/m, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0x1f,0x93,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f 93 04 <unknown>
+// CHECK-UNKNOWN: 04931fe0 <unknown>
 
 umulh z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: umulh	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d3 04 <unknown>
+// CHECK-UNKNOWN: 04d31fe0 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z0.d, p7/z, z7.d
 // CHECK-INST: movprfx	z0.d, p7/z, z7.d
 // CHECK-ENCODING: [0xe0,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03ce0 <unknown>
 
 umulh z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: umulh	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d3 04 <unknown>
+// CHECK-UNKNOWN: 04d31fe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 umulh z0.d, p7/m, z0.d, z31.d
 // CHECK-INST: umulh	z0.d, p7/m, z0.d, z31.d
 // CHECK-ENCODING: [0xe0,0x1f,0xd3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 1f d3 04 <unknown>
+// CHECK-UNKNOWN: 04d31fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uqadd.s b/llvm/test/MC/AArch64/SVE/uqadd.s
index fffcbe4f85cbf..401050348b0ce 100644
--- a/llvm/test/MC/AArch64/SVE/uqadd.s
+++ b/llvm/test/MC/AArch64/SVE/uqadd.s
@@ -14,109 +14,109 @@ uqadd     z0.b, z0.b, z0.b
 // CHECK-INST: uqadd z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x14,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 14 20 04 <unknown>
+// CHECK-UNKNOWN: 04201400 <unknown>
 
 uqadd     z0.h, z0.h, z0.h
 // CHECK-INST: uqadd z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x14,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 14 60 04 <unknown>
+// CHECK-UNKNOWN: 04601400 <unknown>
 
 uqadd     z0.s, z0.s, z0.s
 // CHECK-INST: uqadd z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x14,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 14 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a01400 <unknown>
 
 uqadd     z0.d, z0.d, z0.d
 // CHECK-INST: uqadd z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x14,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 14 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e01400 <unknown>
 
 uqadd     z0.b, z0.b, #0
 // CHECK-INST: uqadd z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x25,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 25 25 <unknown>
+// CHECK-UNKNOWN: 2525c000 <unknown>
 
 uqadd     z31.b, z31.b, #255
 // CHECK-INST: uqadd z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x25,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 25 25 <unknown>
+// CHECK-UNKNOWN: 2525dfff <unknown>
 
 uqadd     z0.h, z0.h, #0
 // CHECK-INST: uqadd z0.h, z0.h, #0
 // CHECK-ENCODING: [0x00,0xc0,0x65,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 65 25 <unknown>
+// CHECK-UNKNOWN: 2565c000 <unknown>
 
 uqadd     z0.h, z0.h, #0, lsl #8
 // CHECK-INST: uqadd z0.h, z0.h, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0x65,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 65 25 <unknown>
+// CHECK-UNKNOWN: 2565e000 <unknown>
 
 uqadd     z31.h, z31.h, #255, lsl #8
 // CHECK-INST: uqadd z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x65,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 65 25 <unknown>
+// CHECK-UNKNOWN: 2565ffff <unknown>
 
 uqadd     z31.h, z31.h, #65280
 // CHECK-INST: uqadd z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x65,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 65 25 <unknown>
+// CHECK-UNKNOWN: 2565ffff <unknown>
 
 uqadd     z0.s, z0.s, #0
 // CHECK-INST: uqadd z0.s, z0.s, #0
 // CHECK-ENCODING: [0x00,0xc0,0xa5,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 a5 25 <unknown>
+// CHECK-UNKNOWN: 25a5c000 <unknown>
 
 uqadd     z0.s, z0.s, #0, lsl #8
 // CHECK-INST: uqadd z0.s, z0.s, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xa5,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 a5 25 <unknown>
+// CHECK-UNKNOWN: 25a5e000 <unknown>
 
 uqadd     z31.s, z31.s, #255, lsl #8
 // CHECK-INST: uqadd z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa5,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a5 25 <unknown>
+// CHECK-UNKNOWN: 25a5ffff <unknown>
 
 uqadd     z31.s, z31.s, #65280
 // CHECK-INST: uqadd z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa5,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a5 25 <unknown>
+// CHECK-UNKNOWN: 25a5ffff <unknown>
 
 uqadd     z0.d, z0.d, #0
 // CHECK-INST: uqadd z0.d, z0.d, #0
 // CHECK-ENCODING: [0x00,0xc0,0xe5,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 e5 25 <unknown>
+// CHECK-UNKNOWN: 25e5c000 <unknown>
 
 uqadd     z0.d, z0.d, #0, lsl #8
 // CHECK-INST: uqadd z0.d, z0.d, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xe5,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e5 25 <unknown>
+// CHECK-UNKNOWN: 25e5e000 <unknown>
 
 uqadd     z31.d, z31.d, #255, lsl #8
 // CHECK-INST: uqadd z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe5,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e5 25 <unknown>
+// CHECK-UNKNOWN: 25e5ffff <unknown>
 
 uqadd     z31.d, z31.d, #65280
 // CHECK-INST: uqadd z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe5,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e5 25 <unknown>
+// CHECK-UNKNOWN: 25e5ffff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -126,10 +126,10 @@ movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uqadd     z31.d, z31.d, #65280
 // CHECK-INST: uqadd	z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe5,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e5 25 <unknown>
+// CHECK-UNKNOWN: 25e5ffff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uqdecb.s b/llvm/test/MC/AArch64/SVE/uqdecb.s
index ee3f6febb04cf..4cea5f0f6353c 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecb.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecb.s
@@ -17,25 +17,25 @@ uqdecb  x0
 // CHECK-INST: uqdecb  x0
 // CHECK-ENCODING: [0xe0,0xff,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 30 04 <unknown>
+// CHECK-UNKNOWN: 0430ffe0 <unknown>
 
 uqdecb  x0, all
 // CHECK-INST: uqdecb  x0
 // CHECK-ENCODING: [0xe0,0xff,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 30 04 <unknown>
+// CHECK-UNKNOWN: 0430ffe0 <unknown>
 
 uqdecb  x0, all, mul #1
 // CHECK-INST: uqdecb  x0
 // CHECK-ENCODING: [0xe0,0xff,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 30 04 <unknown>
+// CHECK-UNKNOWN: 0430ffe0 <unknown>
 
 uqdecb  x0, all, mul #16
 // CHECK-INST: uqdecb  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xff,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 3f 04 <unknown>
+// CHECK-UNKNOWN: 043fffe0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ uqdecb  w0
 // CHECK-INST: uqdecb  w0
 // CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
+// CHECK-UNKNOWN: 0420ffe0 <unknown>
 
 uqdecb  w0, all
 // CHECK-INST: uqdecb  w0
 // CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
+// CHECK-UNKNOWN: 0420ffe0 <unknown>
 
 uqdecb  w0, all, mul #1
 // CHECK-INST: uqdecb  w0
 // CHECK-ENCODING: [0xe0,0xff,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 20 04 <unknown>
+// CHECK-UNKNOWN: 0420ffe0 <unknown>
 
 uqdecb  w0, all, mul #16
 // CHECK-INST: uqdecb  w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xff,0x2f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 2f 04 <unknown>
+// CHECK-UNKNOWN: 042fffe0 <unknown>
 
 uqdecb  w0, pow2
 // CHECK-INST: uqdecb  w0, pow2
 // CHECK-ENCODING: [0x00,0xfc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420fc00 <unknown>
 
 uqdecb  w0, pow2, mul #16
 // CHECK-INST: uqdecb  w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xfc,0x2f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fc 2f 04 <unknown>
+// CHECK-UNKNOWN: 042ffc00 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -87,172 +87,172 @@ uqdecb  x0, pow2
 // CHECK-INST: uqdecb  x0, pow2
 // CHECK-ENCODING: [0x00,0xfc,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fc 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fc00 <unknown>
 
 uqdecb  x0, vl1
 // CHECK-INST: uqdecb  x0, vl1
 // CHECK-ENCODING: [0x20,0xfc,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fc 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fc20 <unknown>
 
 uqdecb  x0, vl2
 // CHECK-INST: uqdecb  x0, vl2
 // CHECK-ENCODING: [0x40,0xfc,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fc 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fc40 <unknown>
 
 uqdecb  x0, vl3
 // CHECK-INST: uqdecb  x0, vl3
 // CHECK-ENCODING: [0x60,0xfc,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fc 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fc60 <unknown>
 
 uqdecb  x0, vl4
 // CHECK-INST: uqdecb  x0, vl4
 // CHECK-ENCODING: [0x80,0xfc,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fc 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fc80 <unknown>
 
 uqdecb  x0, vl5
 // CHECK-INST: uqdecb  x0, vl5
 // CHECK-ENCODING: [0xa0,0xfc,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fc 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fca0 <unknown>
 
 uqdecb  x0, vl6
 // CHECK-INST: uqdecb  x0, vl6
 // CHECK-ENCODING: [0xc0,0xfc,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fc 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fcc0 <unknown>
 
 uqdecb  x0, vl7
 // CHECK-INST: uqdecb  x0, vl7
 // CHECK-ENCODING: [0xe0,0xfc,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fc 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fce0 <unknown>
 
 uqdecb  x0, vl8
 // CHECK-INST: uqdecb  x0, vl8
 // CHECK-ENCODING: [0x00,0xfd,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fd 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fd00 <unknown>
 
 uqdecb  x0, vl16
 // CHECK-INST: uqdecb  x0, vl16
 // CHECK-ENCODING: [0x20,0xfd,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fd 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fd20 <unknown>
 
 uqdecb  x0, vl32
 // CHECK-INST: uqdecb  x0, vl32
 // CHECK-ENCODING: [0x40,0xfd,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fd 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fd40 <unknown>
 
 uqdecb  x0, vl64
 // CHECK-INST: uqdecb  x0, vl64
 // CHECK-ENCODING: [0x60,0xfd,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fd 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fd60 <unknown>
 
 uqdecb  x0, vl128
 // CHECK-INST: uqdecb  x0, vl128
 // CHECK-ENCODING: [0x80,0xfd,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fd 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fd80 <unknown>
 
 uqdecb  x0, vl256
 // CHECK-INST: uqdecb  x0, vl256
 // CHECK-ENCODING: [0xa0,0xfd,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fd 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fda0 <unknown>
 
 uqdecb  x0, #14
 // CHECK-INST: uqdecb  x0, #14
 // CHECK-ENCODING: [0xc0,0xfd,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fd 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fdc0 <unknown>
 
 uqdecb  x0, #15
 // CHECK-INST: uqdecb  x0, #15
 // CHECK-ENCODING: [0xe0,0xfd,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fd 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fde0 <unknown>
 
 uqdecb  x0, #16
 // CHECK-INST: uqdecb  x0, #16
 // CHECK-ENCODING: [0x00,0xfe,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fe 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fe00 <unknown>
 
 uqdecb  x0, #17
 // CHECK-INST: uqdecb  x0, #17
 // CHECK-ENCODING: [0x20,0xfe,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fe 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fe20 <unknown>
 
 uqdecb  x0, #18
 // CHECK-INST: uqdecb  x0, #18
 // CHECK-ENCODING: [0x40,0xfe,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fe 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fe40 <unknown>
 
 uqdecb  x0, #19
 // CHECK-INST: uqdecb  x0, #19
 // CHECK-ENCODING: [0x60,0xfe,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fe 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fe60 <unknown>
 
 uqdecb  x0, #20
 // CHECK-INST: uqdecb  x0, #20
 // CHECK-ENCODING: [0x80,0xfe,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fe 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fe80 <unknown>
 
 uqdecb  x0, #21
 // CHECK-INST: uqdecb  x0, #21
 // CHECK-ENCODING: [0xa0,0xfe,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fe 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fea0 <unknown>
 
 uqdecb  x0, #22
 // CHECK-INST: uqdecb  x0, #22
 // CHECK-ENCODING: [0xc0,0xfe,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fe 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fec0 <unknown>
 
 uqdecb  x0, #23
 // CHECK-INST: uqdecb  x0, #23
 // CHECK-ENCODING: [0xe0,0xfe,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fe 30 04 <unknown>
+// CHECK-UNKNOWN: 0430fee0 <unknown>
 
 uqdecb  x0, #24
 // CHECK-INST: uqdecb  x0, #24
 // CHECK-ENCODING: [0x00,0xff,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 ff 30 04 <unknown>
+// CHECK-UNKNOWN: 0430ff00 <unknown>
 
 uqdecb  x0, #25
 // CHECK-INST: uqdecb  x0, #25
 // CHECK-ENCODING: [0x20,0xff,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 ff 30 04 <unknown>
+// CHECK-UNKNOWN: 0430ff20 <unknown>
 
 uqdecb  x0, #26
 // CHECK-INST: uqdecb  x0, #26
 // CHECK-ENCODING: [0x40,0xff,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 ff 30 04 <unknown>
+// CHECK-UNKNOWN: 0430ff40 <unknown>
 
 uqdecb  x0, #27
 // CHECK-INST: uqdecb  x0, #27
 // CHECK-ENCODING: [0x60,0xff,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 ff 30 04 <unknown>
+// CHECK-UNKNOWN: 0430ff60 <unknown>
 
 uqdecb  x0, #28
 // CHECK-INST: uqdecb  x0, #28
 // CHECK-ENCODING: [0x80,0xff,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 ff 30 04 <unknown>
+// CHECK-UNKNOWN: 0430ff80 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uqdecd.s b/llvm/test/MC/AArch64/SVE/uqdecd.s
index 1ff9deb6ccea7..d94f2d76daade 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecd.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecd.s
@@ -17,25 +17,25 @@ uqdecd  x0
 // CHECK-INST: uqdecd  x0
 // CHECK-ENCODING: [0xe0,0xff,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0ffe0 <unknown>
 
 uqdecd  x0, all
 // CHECK-INST: uqdecd  x0
 // CHECK-ENCODING: [0xe0,0xff,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0ffe0 <unknown>
 
 uqdecd  x0, all, mul #1
 // CHECK-INST: uqdecd  x0
 // CHECK-ENCODING: [0xe0,0xff,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0ffe0 <unknown>
 
 uqdecd  x0, all, mul #16
 // CHECK-INST: uqdecd  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xff,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff ff 04 <unknown>
+// CHECK-UNKNOWN: 04ffffe0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ uqdecd  w0
 // CHECK-INST: uqdecd  w0
 // CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0ffe0 <unknown>
 
 uqdecd  w0, all
 // CHECK-INST: uqdecd  w0
 // CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0ffe0 <unknown>
 
 uqdecd  w0, all, mul #1
 // CHECK-INST: uqdecd  w0
 // CHECK-ENCODING: [0xe0,0xff,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0ffe0 <unknown>
 
 uqdecd  w0, all, mul #16
 // CHECK-INST: uqdecd  w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xff,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff ef 04 <unknown>
+// CHECK-UNKNOWN: 04efffe0 <unknown>
 
 uqdecd  w0, pow2
 // CHECK-INST: uqdecd  w0, pow2
 // CHECK-ENCODING: [0x00,0xfc,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fc e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0fc00 <unknown>
 
 uqdecd  w0, pow2, mul #16
 // CHECK-INST: uqdecd  w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xfc,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fc ef 04 <unknown>
+// CHECK-UNKNOWN: 04effc00 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -86,37 +86,37 @@ uqdecd  z0.d
 // CHECK-INST: uqdecd  z0.d
 // CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0cfe0 <unknown>
 
 uqdecd  z0.d, all
 // CHECK-INST: uqdecd  z0.d
 // CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0cfe0 <unknown>
 
 uqdecd  z0.d, all, mul #1
 // CHECK-INST: uqdecd  z0.d
 // CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0cfe0 <unknown>
 
 uqdecd  z0.d, all, mul #16
 // CHECK-INST: uqdecd  z0.d, all, mul #16
 // CHECK-ENCODING: [0xe0,0xcf,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf ef 04 <unknown>
+// CHECK-UNKNOWN: 04efcfe0 <unknown>
 
 uqdecd  z0.d, pow2
 // CHECK-INST: uqdecd  z0.d, pow2
 // CHECK-ENCODING: [0x00,0xcc,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0cc00 <unknown>
 
 uqdecd  z0.d, pow2, mul #16
 // CHECK-INST: uqdecd  z0.d, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xcc,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc ef 04 <unknown>
+// CHECK-UNKNOWN: 04efcc00 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -127,175 +127,175 @@ uqdecd  x0, pow2
 // CHECK-INST: uqdecd  x0, pow2
 // CHECK-ENCODING: [0x00,0xfc,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fc f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fc00 <unknown>
 
 uqdecd  x0, vl1
 // CHECK-INST: uqdecd  x0, vl1
 // CHECK-ENCODING: [0x20,0xfc,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fc f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fc20 <unknown>
 
 uqdecd  x0, vl2
 // CHECK-INST: uqdecd  x0, vl2
 // CHECK-ENCODING: [0x40,0xfc,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fc f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fc40 <unknown>
 
 uqdecd  x0, vl3
 // CHECK-INST: uqdecd  x0, vl3
 // CHECK-ENCODING: [0x60,0xfc,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fc f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fc60 <unknown>
 
 uqdecd  x0, vl4
 // CHECK-INST: uqdecd  x0, vl4
 // CHECK-ENCODING: [0x80,0xfc,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fc f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fc80 <unknown>
 
 uqdecd  x0, vl5
 // CHECK-INST: uqdecd  x0, vl5
 // CHECK-ENCODING: [0xa0,0xfc,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fc f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fca0 <unknown>
 
 uqdecd  x0, vl6
 // CHECK-INST: uqdecd  x0, vl6
 // CHECK-ENCODING: [0xc0,0xfc,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fc f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fcc0 <unknown>
 
 uqdecd  x0, vl7
 // CHECK-INST: uqdecd  x0, vl7
 // CHECK-ENCODING: [0xe0,0xfc,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fc f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fce0 <unknown>
 
 uqdecd  x0, vl8
 // CHECK-INST: uqdecd  x0, vl8
 // CHECK-ENCODING: [0x00,0xfd,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fd f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fd00 <unknown>
 
 uqdecd  x0, vl16
 // CHECK-INST: uqdecd  x0, vl16
 // CHECK-ENCODING: [0x20,0xfd,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fd f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fd20 <unknown>
 
 uqdecd  x0, vl32
 // CHECK-INST: uqdecd  x0, vl32
 // CHECK-ENCODING: [0x40,0xfd,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fd f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fd40 <unknown>
 
 uqdecd  x0, vl64
 // CHECK-INST: uqdecd  x0, vl64
 // CHECK-ENCODING: [0x60,0xfd,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fd f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fd60 <unknown>
 
 uqdecd  x0, vl128
 // CHECK-INST: uqdecd  x0, vl128
 // CHECK-ENCODING: [0x80,0xfd,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fd f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fd80 <unknown>
 
 uqdecd  x0, vl256
 // CHECK-INST: uqdecd  x0, vl256
 // CHECK-ENCODING: [0xa0,0xfd,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fd f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fda0 <unknown>
 
 uqdecd  x0, #14
 // CHECK-INST: uqdecd  x0, #14
 // CHECK-ENCODING: [0xc0,0xfd,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fd f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fdc0 <unknown>
 
 uqdecd  x0, #15
 // CHECK-INST: uqdecd  x0, #15
 // CHECK-ENCODING: [0xe0,0xfd,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fd f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fde0 <unknown>
 
 uqdecd  x0, #16
 // CHECK-INST: uqdecd  x0, #16
 // CHECK-ENCODING: [0x00,0xfe,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fe f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fe00 <unknown>
 
 uqdecd  x0, #17
 // CHECK-INST: uqdecd  x0, #17
 // CHECK-ENCODING: [0x20,0xfe,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fe f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fe20 <unknown>
 
 uqdecd  x0, #18
 // CHECK-INST: uqdecd  x0, #18
 // CHECK-ENCODING: [0x40,0xfe,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fe f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fe40 <unknown>
 
 uqdecd  x0, #19
 // CHECK-INST: uqdecd  x0, #19
 // CHECK-ENCODING: [0x60,0xfe,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fe f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fe60 <unknown>
 
 uqdecd  x0, #20
 // CHECK-INST: uqdecd  x0, #20
 // CHECK-ENCODING: [0x80,0xfe,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fe f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fe80 <unknown>
 
 uqdecd  x0, #21
 // CHECK-INST: uqdecd  x0, #21
 // CHECK-ENCODING: [0xa0,0xfe,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fe f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fea0 <unknown>
 
 uqdecd  x0, #22
 // CHECK-INST: uqdecd  x0, #22
 // CHECK-ENCODING: [0xc0,0xfe,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fe f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fec0 <unknown>
 
 uqdecd  x0, #23
 // CHECK-INST: uqdecd  x0, #23
 // CHECK-ENCODING: [0xe0,0xfe,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fe f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0fee0 <unknown>
 
 uqdecd  x0, #24
 // CHECK-INST: uqdecd  x0, #24
 // CHECK-ENCODING: [0x00,0xff,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 ff f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0ff00 <unknown>
 
 uqdecd  x0, #25
 // CHECK-INST: uqdecd  x0, #25
 // CHECK-ENCODING: [0x20,0xff,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 ff f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0ff20 <unknown>
 
 uqdecd  x0, #26
 // CHECK-INST: uqdecd  x0, #26
 // CHECK-ENCODING: [0x40,0xff,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 ff f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0ff40 <unknown>
 
 uqdecd  x0, #27
 // CHECK-INST: uqdecd  x0, #27
 // CHECK-ENCODING: [0x60,0xff,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 ff f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0ff60 <unknown>
 
 uqdecd  x0, #28
 // CHECK-INST: uqdecd  x0, #28
 // CHECK-ENCODING: [0x80,0xff,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 ff f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0ff80 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -305,34 +305,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqdecd  z0.d
 // CHECK-INST: uqdecd	z0.d
 // CHECK-ENCODING: [0xe0,0xcf,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0cfe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqdecd  z0.d, pow2, mul #16
 // CHECK-INST: uqdecd	z0.d, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xcc,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc ef 04 <unknown>
+// CHECK-UNKNOWN: 04efcc00 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqdecd  z0.d, pow2
 // CHECK-INST: uqdecd	z0.d, pow2
 // CHECK-ENCODING: [0x00,0xcc,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0cc00 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uqdech.s b/llvm/test/MC/AArch64/SVE/uqdech.s
index e5a0fd17ae3ba..5f6e089641fdd 100644
--- a/llvm/test/MC/AArch64/SVE/uqdech.s
+++ b/llvm/test/MC/AArch64/SVE/uqdech.s
@@ -17,25 +17,25 @@ uqdech  x0
 // CHECK-INST: uqdech  x0
 // CHECK-ENCODING: [0xe0,0xff,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 70 04 <unknown>
+// CHECK-UNKNOWN: 0470ffe0 <unknown>
 
 uqdech  x0, all
 // CHECK-INST: uqdech  x0
 // CHECK-ENCODING: [0xe0,0xff,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 70 04 <unknown>
+// CHECK-UNKNOWN: 0470ffe0 <unknown>
 
 uqdech  x0, all, mul #1
 // CHECK-INST: uqdech  x0
 // CHECK-ENCODING: [0xe0,0xff,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 70 04 <unknown>
+// CHECK-UNKNOWN: 0470ffe0 <unknown>
 
 uqdech  x0, all, mul #16
 // CHECK-INST: uqdech  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xff,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 7f 04 <unknown>
+// CHECK-UNKNOWN: 047fffe0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ uqdech  w0
 // CHECK-INST: uqdech  w0
 // CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
+// CHECK-UNKNOWN: 0460ffe0 <unknown>
 
 uqdech  w0, all
 // CHECK-INST: uqdech  w0
 // CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
+// CHECK-UNKNOWN: 0460ffe0 <unknown>
 
 uqdech  w0, all, mul #1
 // CHECK-INST: uqdech  w0
 // CHECK-ENCODING: [0xe0,0xff,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 60 04 <unknown>
+// CHECK-UNKNOWN: 0460ffe0 <unknown>
 
 uqdech  w0, all, mul #16
 // CHECK-INST: uqdech  w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xff,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fffe0 <unknown>
 
 uqdech  w0, pow2
 // CHECK-INST: uqdech  w0, pow2
 // CHECK-ENCODING: [0x00,0xfc,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fc 60 04 <unknown>
+// CHECK-UNKNOWN: 0460fc00 <unknown>
 
 uqdech  w0, pow2, mul #16
 // CHECK-INST: uqdech  w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xfc,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fc 6f 04 <unknown>
+// CHECK-UNKNOWN: 046ffc00 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -86,37 +86,37 @@ uqdech  z0.h
 // CHECK-INST: uqdech  z0.h
 // CHECK-ENCODING: [0xe0,0xcf,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf 60 04 <unknown>
+// CHECK-UNKNOWN: 0460cfe0 <unknown>
 
 uqdech  z0.h, all
 // CHECK-INST: uqdech  z0.h
 // CHECK-ENCODING: [0xe0,0xcf,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf 60 04 <unknown>
+// CHECK-UNKNOWN: 0460cfe0 <unknown>
 
 uqdech  z0.h, all, mul #1
 // CHECK-INST: uqdech  z0.h
 // CHECK-ENCODING: [0xe0,0xcf,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf 60 04 <unknown>
+// CHECK-UNKNOWN: 0460cfe0 <unknown>
 
 uqdech  z0.h, all, mul #16
 // CHECK-INST: uqdech  z0.h, all, mul #16
 // CHECK-ENCODING: [0xe0,0xcf,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fcfe0 <unknown>
 
 uqdech  z0.h, pow2
 // CHECK-INST: uqdech  z0.h, pow2
 // CHECK-ENCODING: [0x00,0xcc,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc 60 04 <unknown>
+// CHECK-UNKNOWN: 0460cc00 <unknown>
 
 uqdech  z0.h, pow2, mul #16
 // CHECK-INST: uqdech  z0.h, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xcc,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fcc00 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -127,175 +127,175 @@ uqdech  x0, pow2
 // CHECK-INST: uqdech  x0, pow2
 // CHECK-ENCODING: [0x00,0xfc,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fc 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fc00 <unknown>
 
 uqdech  x0, vl1
 // CHECK-INST: uqdech  x0, vl1
 // CHECK-ENCODING: [0x20,0xfc,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fc 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fc20 <unknown>
 
 uqdech  x0, vl2
 // CHECK-INST: uqdech  x0, vl2
 // CHECK-ENCODING: [0x40,0xfc,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fc 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fc40 <unknown>
 
 uqdech  x0, vl3
 // CHECK-INST: uqdech  x0, vl3
 // CHECK-ENCODING: [0x60,0xfc,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fc 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fc60 <unknown>
 
 uqdech  x0, vl4
 // CHECK-INST: uqdech  x0, vl4
 // CHECK-ENCODING: [0x80,0xfc,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fc 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fc80 <unknown>
 
 uqdech  x0, vl5
 // CHECK-INST: uqdech  x0, vl5
 // CHECK-ENCODING: [0xa0,0xfc,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fc 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fca0 <unknown>
 
 uqdech  x0, vl6
 // CHECK-INST: uqdech  x0, vl6
 // CHECK-ENCODING: [0xc0,0xfc,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fc 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fcc0 <unknown>
 
 uqdech  x0, vl7
 // CHECK-INST: uqdech  x0, vl7
 // CHECK-ENCODING: [0xe0,0xfc,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fc 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fce0 <unknown>
 
 uqdech  x0, vl8
 // CHECK-INST: uqdech  x0, vl8
 // CHECK-ENCODING: [0x00,0xfd,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fd 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fd00 <unknown>
 
 uqdech  x0, vl16
 // CHECK-INST: uqdech  x0, vl16
 // CHECK-ENCODING: [0x20,0xfd,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fd 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fd20 <unknown>
 
 uqdech  x0, vl32
 // CHECK-INST: uqdech  x0, vl32
 // CHECK-ENCODING: [0x40,0xfd,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fd 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fd40 <unknown>
 
 uqdech  x0, vl64
 // CHECK-INST: uqdech  x0, vl64
 // CHECK-ENCODING: [0x60,0xfd,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fd 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fd60 <unknown>
 
 uqdech  x0, vl128
 // CHECK-INST: uqdech  x0, vl128
 // CHECK-ENCODING: [0x80,0xfd,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fd 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fd80 <unknown>
 
 uqdech  x0, vl256
 // CHECK-INST: uqdech  x0, vl256
 // CHECK-ENCODING: [0xa0,0xfd,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fd 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fda0 <unknown>
 
 uqdech  x0, #14
 // CHECK-INST: uqdech  x0, #14
 // CHECK-ENCODING: [0xc0,0xfd,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fd 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fdc0 <unknown>
 
 uqdech  x0, #15
 // CHECK-INST: uqdech  x0, #15
 // CHECK-ENCODING: [0xe0,0xfd,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fd 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fde0 <unknown>
 
 uqdech  x0, #16
 // CHECK-INST: uqdech  x0, #16
 // CHECK-ENCODING: [0x00,0xfe,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fe 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fe00 <unknown>
 
 uqdech  x0, #17
 // CHECK-INST: uqdech  x0, #17
 // CHECK-ENCODING: [0x20,0xfe,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fe 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fe20 <unknown>
 
 uqdech  x0, #18
 // CHECK-INST: uqdech  x0, #18
 // CHECK-ENCODING: [0x40,0xfe,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fe 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fe40 <unknown>
 
 uqdech  x0, #19
 // CHECK-INST: uqdech  x0, #19
 // CHECK-ENCODING: [0x60,0xfe,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fe 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fe60 <unknown>
 
 uqdech  x0, #20
 // CHECK-INST: uqdech  x0, #20
 // CHECK-ENCODING: [0x80,0xfe,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fe 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fe80 <unknown>
 
 uqdech  x0, #21
 // CHECK-INST: uqdech  x0, #21
 // CHECK-ENCODING: [0xa0,0xfe,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fe 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fea0 <unknown>
 
 uqdech  x0, #22
 // CHECK-INST: uqdech  x0, #22
 // CHECK-ENCODING: [0xc0,0xfe,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fe 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fec0 <unknown>
 
 uqdech  x0, #23
 // CHECK-INST: uqdech  x0, #23
 // CHECK-ENCODING: [0xe0,0xfe,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fe 70 04 <unknown>
+// CHECK-UNKNOWN: 0470fee0 <unknown>
 
 uqdech  x0, #24
 // CHECK-INST: uqdech  x0, #24
 // CHECK-ENCODING: [0x00,0xff,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 ff 70 04 <unknown>
+// CHECK-UNKNOWN: 0470ff00 <unknown>
 
 uqdech  x0, #25
 // CHECK-INST: uqdech  x0, #25
 // CHECK-ENCODING: [0x20,0xff,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 ff 70 04 <unknown>
+// CHECK-UNKNOWN: 0470ff20 <unknown>
 
 uqdech  x0, #26
 // CHECK-INST: uqdech  x0, #26
 // CHECK-ENCODING: [0x40,0xff,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 ff 70 04 <unknown>
+// CHECK-UNKNOWN: 0470ff40 <unknown>
 
 uqdech  x0, #27
 // CHECK-INST: uqdech  x0, #27
 // CHECK-ENCODING: [0x60,0xff,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 ff 70 04 <unknown>
+// CHECK-UNKNOWN: 0470ff60 <unknown>
 
 uqdech  x0, #28
 // CHECK-INST: uqdech  x0, #28
 // CHECK-ENCODING: [0x80,0xff,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 ff 70 04 <unknown>
+// CHECK-UNKNOWN: 0470ff80 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -305,34 +305,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqdech  z0.h
 // CHECK-INST: uqdech	z0.h
 // CHECK-ENCODING: [0xe0,0xcf,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf 60 04 <unknown>
+// CHECK-UNKNOWN: 0460cfe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqdech  z0.h, pow2, mul #16
 // CHECK-INST: uqdech	z0.h, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xcc,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fcc00 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqdech  z0.h, pow2
 // CHECK-INST: uqdech	z0.h, pow2
 // CHECK-ENCODING: [0x00,0xcc,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc 60 04 <unknown>
+// CHECK-UNKNOWN: 0460cc00 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uqdecp.s b/llvm/test/MC/AArch64/SVE/uqdecp.s
index 91f3b3d9f545b..05af51b4f451d 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecp.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecp.s
@@ -13,85 +13,85 @@ uqdecp  x0, p0.b
 // CHECK-INST: uqdecp x0, p0.b
 // CHECK-ENCODING: [0x00,0x8c,0x2b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c 2b 25 <unknown>
+// CHECK-UNKNOWN: 252b8c00 <unknown>
 
 uqdecp  x0, p0.h
 // CHECK-INST: uqdecp x0, p0.h
 // CHECK-ENCODING: [0x00,0x8c,0x6b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c 6b 25 <unknown>
+// CHECK-UNKNOWN: 256b8c00 <unknown>
 
 uqdecp  x0, p0.s
 // CHECK-INST: uqdecp x0, p0.s
 // CHECK-ENCODING: [0x00,0x8c,0xab,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c ab 25 <unknown>
+// CHECK-UNKNOWN: 25ab8c00 <unknown>
 
 uqdecp  x0, p0.d
 // CHECK-INST: uqdecp x0, p0.d
 // CHECK-ENCODING: [0x00,0x8c,0xeb,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c eb 25 <unknown>
+// CHECK-UNKNOWN: 25eb8c00 <unknown>
 
 uqdecp  wzr, p15.b
 // CHECK-INST: uqdecp wzr, p15.b
 // CHECK-ENCODING: [0xff,0x89,0x2b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 2b 25 <unknown>
+// CHECK-UNKNOWN: 252b89ff <unknown>
 
 uqdecp  wzr, p15.h
 // CHECK-INST: uqdecp wzr, p15.h
 // CHECK-ENCODING: [0xff,0x89,0x6b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 6b 25 <unknown>
+// CHECK-UNKNOWN: 256b89ff <unknown>
 
 uqdecp  wzr, p15.s
 // CHECK-INST: uqdecp wzr, p15.s
 // CHECK-ENCODING: [0xff,0x89,0xab,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 ab 25 <unknown>
+// CHECK-UNKNOWN: 25ab89ff <unknown>
 
 uqdecp  wzr, p15.d
 // CHECK-INST: uqdecp wzr, p15.d
 // CHECK-ENCODING: [0xff,0x89,0xeb,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 eb 25 <unknown>
+// CHECK-UNKNOWN: 25eb89ff <unknown>
 
 uqdecp  z0.h, p0
 // CHECK-INST: uqdecp z0.h, p0.h
 // CHECK-ENCODING: [0x00,0x80,0x6b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 6b 25 <unknown>
+// CHECK-UNKNOWN: 256b8000 <unknown>
 
 uqdecp  z0.h, p0.h
 // CHECK-INST: uqdecp z0.h, p0.h
 // CHECK-ENCODING: [0x00,0x80,0x6b,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 6b 25 <unknown>
+// CHECK-UNKNOWN: 256b8000 <unknown>
 
 uqdecp  z0.s, p0
 // CHECK-INST: uqdecp z0.s, p0.s
 // CHECK-ENCODING: [0x00,0x80,0xab,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 ab 25 <unknown>
+// CHECK-UNKNOWN: 25ab8000 <unknown>
 
 uqdecp  z0.s, p0.s
 // CHECK-INST: uqdecp z0.s, p0.s
 // CHECK-ENCODING: [0x00,0x80,0xab,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 ab 25 <unknown>
+// CHECK-UNKNOWN: 25ab8000 <unknown>
 
 uqdecp  z0.d, p0
 // CHECK-INST: uqdecp z0.d, p0.d
 // CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 eb 25 <unknown>
+// CHECK-UNKNOWN: 25eb8000 <unknown>
 
 uqdecp  z0.d, p0.d
 // CHECK-INST: uqdecp z0.d, p0.d
 // CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 eb 25 <unknown>
+// CHECK-UNKNOWN: 25eb8000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -101,10 +101,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqdecp  z0.d, p0.d
 // CHECK-INST: uqdecp	z0.d, p0.d
 // CHECK-ENCODING: [0x00,0x80,0xeb,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 eb 25 <unknown>
+// CHECK-UNKNOWN: 25eb8000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uqdecw.s b/llvm/test/MC/AArch64/SVE/uqdecw.s
index c07e4e301fbaf..0dad243071f8c 100644
--- a/llvm/test/MC/AArch64/SVE/uqdecw.s
+++ b/llvm/test/MC/AArch64/SVE/uqdecw.s
@@ -17,25 +17,25 @@ uqdecw  x0
 // CHECK-INST: uqdecw  x0
 // CHECK-ENCODING: [0xe0,0xff,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0ffe0 <unknown>
 
 uqdecw  x0, all
 // CHECK-INST: uqdecw  x0
 // CHECK-ENCODING: [0xe0,0xff,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0ffe0 <unknown>
 
 uqdecw  x0, all, mul #1
 // CHECK-INST: uqdecw  x0
 // CHECK-ENCODING: [0xe0,0xff,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0ffe0 <unknown>
 
 uqdecw  x0, all, mul #16
 // CHECK-INST: uqdecw  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xff,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff bf 04 <unknown>
+// CHECK-UNKNOWN: 04bfffe0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ uqdecw  w0
 // CHECK-INST: uqdecw  w0
 // CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0ffe0 <unknown>
 
 uqdecw  w0, all
 // CHECK-INST: uqdecw  w0
 // CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0ffe0 <unknown>
 
 uqdecw  w0, all, mul #1
 // CHECK-INST: uqdecw  w0
 // CHECK-ENCODING: [0xe0,0xff,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0ffe0 <unknown>
 
 uqdecw  w0, all, mul #16
 // CHECK-INST: uqdecw  w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xff,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 ff af 04 <unknown>
+// CHECK-UNKNOWN: 04afffe0 <unknown>
 
 uqdecw  w0, pow2
 // CHECK-INST: uqdecw  w0, pow2
 // CHECK-ENCODING: [0x00,0xfc,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fc a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0fc00 <unknown>
 
 uqdecw  w0, pow2, mul #16
 // CHECK-INST: uqdecw  w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xfc,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fc af 04 <unknown>
+// CHECK-UNKNOWN: 04affc00 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -86,37 +86,37 @@ uqdecw  z0.s
 // CHECK-INST: uqdecw  z0.s
 // CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0cfe0 <unknown>
 
 uqdecw  z0.s, all
 // CHECK-INST: uqdecw  z0.s
 // CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0cfe0 <unknown>
 
 uqdecw  z0.s, all, mul #1
 // CHECK-INST: uqdecw  z0.s
 // CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0cfe0 <unknown>
 
 uqdecw  z0.s, all, mul #16
 // CHECK-INST: uqdecw  z0.s, all, mul #16
 // CHECK-ENCODING: [0xe0,0xcf,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf af 04 <unknown>
+// CHECK-UNKNOWN: 04afcfe0 <unknown>
 
 uqdecw  z0.s, pow2
 // CHECK-INST: uqdecw  z0.s, pow2
 // CHECK-ENCODING: [0x00,0xcc,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0cc00 <unknown>
 
 uqdecw  z0.s, pow2, mul #16
 // CHECK-INST: uqdecw  z0.s, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xcc,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc af 04 <unknown>
+// CHECK-UNKNOWN: 04afcc00 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -127,175 +127,175 @@ uqdecw  x0, pow2
 // CHECK-INST: uqdecw  x0, pow2
 // CHECK-ENCODING: [0x00,0xfc,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fc b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fc00 <unknown>
 
 uqdecw  x0, vl1
 // CHECK-INST: uqdecw  x0, vl1
 // CHECK-ENCODING: [0x20,0xfc,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fc b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fc20 <unknown>
 
 uqdecw  x0, vl2
 // CHECK-INST: uqdecw  x0, vl2
 // CHECK-ENCODING: [0x40,0xfc,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fc b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fc40 <unknown>
 
 uqdecw  x0, vl3
 // CHECK-INST: uqdecw  x0, vl3
 // CHECK-ENCODING: [0x60,0xfc,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fc b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fc60 <unknown>
 
 uqdecw  x0, vl4
 // CHECK-INST: uqdecw  x0, vl4
 // CHECK-ENCODING: [0x80,0xfc,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fc b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fc80 <unknown>
 
 uqdecw  x0, vl5
 // CHECK-INST: uqdecw  x0, vl5
 // CHECK-ENCODING: [0xa0,0xfc,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fc b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fca0 <unknown>
 
 uqdecw  x0, vl6
 // CHECK-INST: uqdecw  x0, vl6
 // CHECK-ENCODING: [0xc0,0xfc,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fc b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fcc0 <unknown>
 
 uqdecw  x0, vl7
 // CHECK-INST: uqdecw  x0, vl7
 // CHECK-ENCODING: [0xe0,0xfc,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fc b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fce0 <unknown>
 
 uqdecw  x0, vl8
 // CHECK-INST: uqdecw  x0, vl8
 // CHECK-ENCODING: [0x00,0xfd,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fd b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fd00 <unknown>
 
 uqdecw  x0, vl16
 // CHECK-INST: uqdecw  x0, vl16
 // CHECK-ENCODING: [0x20,0xfd,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fd b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fd20 <unknown>
 
 uqdecw  x0, vl32
 // CHECK-INST: uqdecw  x0, vl32
 // CHECK-ENCODING: [0x40,0xfd,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fd b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fd40 <unknown>
 
 uqdecw  x0, vl64
 // CHECK-INST: uqdecw  x0, vl64
 // CHECK-ENCODING: [0x60,0xfd,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fd b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fd60 <unknown>
 
 uqdecw  x0, vl128
 // CHECK-INST: uqdecw  x0, vl128
 // CHECK-ENCODING: [0x80,0xfd,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fd b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fd80 <unknown>
 
 uqdecw  x0, vl256
 // CHECK-INST: uqdecw  x0, vl256
 // CHECK-ENCODING: [0xa0,0xfd,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fd b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fda0 <unknown>
 
 uqdecw  x0, #14
 // CHECK-INST: uqdecw  x0, #14
 // CHECK-ENCODING: [0xc0,0xfd,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fd b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fdc0 <unknown>
 
 uqdecw  x0, #15
 // CHECK-INST: uqdecw  x0, #15
 // CHECK-ENCODING: [0xe0,0xfd,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fd b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fde0 <unknown>
 
 uqdecw  x0, #16
 // CHECK-INST: uqdecw  x0, #16
 // CHECK-ENCODING: [0x00,0xfe,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 fe b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fe00 <unknown>
 
 uqdecw  x0, #17
 // CHECK-INST: uqdecw  x0, #17
 // CHECK-ENCODING: [0x20,0xfe,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 fe b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fe20 <unknown>
 
 uqdecw  x0, #18
 // CHECK-INST: uqdecw  x0, #18
 // CHECK-ENCODING: [0x40,0xfe,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 fe b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fe40 <unknown>
 
 uqdecw  x0, #19
 // CHECK-INST: uqdecw  x0, #19
 // CHECK-ENCODING: [0x60,0xfe,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 fe b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fe60 <unknown>
 
 uqdecw  x0, #20
 // CHECK-INST: uqdecw  x0, #20
 // CHECK-ENCODING: [0x80,0xfe,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 fe b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fe80 <unknown>
 
 uqdecw  x0, #21
 // CHECK-INST: uqdecw  x0, #21
 // CHECK-ENCODING: [0xa0,0xfe,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 fe b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fea0 <unknown>
 
 uqdecw  x0, #22
 // CHECK-INST: uqdecw  x0, #22
 // CHECK-ENCODING: [0xc0,0xfe,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 fe b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fec0 <unknown>
 
 uqdecw  x0, #23
 // CHECK-INST: uqdecw  x0, #23
 // CHECK-ENCODING: [0xe0,0xfe,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 fe b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0fee0 <unknown>
 
 uqdecw  x0, #24
 // CHECK-INST: uqdecw  x0, #24
 // CHECK-ENCODING: [0x00,0xff,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 ff b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0ff00 <unknown>
 
 uqdecw  x0, #25
 // CHECK-INST: uqdecw  x0, #25
 // CHECK-ENCODING: [0x20,0xff,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 ff b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0ff20 <unknown>
 
 uqdecw  x0, #26
 // CHECK-INST: uqdecw  x0, #26
 // CHECK-ENCODING: [0x40,0xff,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 ff b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0ff40 <unknown>
 
 uqdecw  x0, #27
 // CHECK-INST: uqdecw  x0, #27
 // CHECK-ENCODING: [0x60,0xff,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 ff b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0ff60 <unknown>
 
 uqdecw  x0, #28
 // CHECK-INST: uqdecw  x0, #28
 // CHECK-ENCODING: [0x80,0xff,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 ff b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0ff80 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -305,34 +305,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqdecw  z0.s
 // CHECK-INST: uqdecw	z0.s
 // CHECK-ENCODING: [0xe0,0xcf,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 cf a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0cfe0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqdecw  z0.s, pow2, mul #16
 // CHECK-INST: uqdecw	z0.s, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xcc,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc af 04 <unknown>
+// CHECK-UNKNOWN: 04afcc00 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqdecw  z0.s, pow2
 // CHECK-INST: uqdecw	z0.s, pow2
 // CHECK-ENCODING: [0x00,0xcc,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 cc a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0cc00 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uqincb.s b/llvm/test/MC/AArch64/SVE/uqincb.s
index f5f97adce6093..d8093e2199358 100644
--- a/llvm/test/MC/AArch64/SVE/uqincb.s
+++ b/llvm/test/MC/AArch64/SVE/uqincb.s
@@ -17,25 +17,25 @@ uqincb  x0
 // CHECK-INST: uqincb  x0
 // CHECK-ENCODING: [0xe0,0xf7,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f7e0 <unknown>
 
 uqincb  x0, all
 // CHECK-INST: uqincb  x0
 // CHECK-ENCODING: [0xe0,0xf7,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f7e0 <unknown>
 
 uqincb  x0, all, mul #1
 // CHECK-INST: uqincb  x0
 // CHECK-ENCODING: [0xe0,0xf7,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f7e0 <unknown>
 
 uqincb  x0, all, mul #16
 // CHECK-INST: uqincb  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf7,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 3f 04 <unknown>
+// CHECK-UNKNOWN: 043ff7e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ uqincb  w0
 // CHECK-INST: uqincb  w0
 // CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
+// CHECK-UNKNOWN: 0420f7e0 <unknown>
 
 uqincb  w0, all
 // CHECK-INST: uqincb  w0
 // CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
+// CHECK-UNKNOWN: 0420f7e0 <unknown>
 
 uqincb  w0, all, mul #1
 // CHECK-INST: uqincb  w0
 // CHECK-ENCODING: [0xe0,0xf7,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 20 04 <unknown>
+// CHECK-UNKNOWN: 0420f7e0 <unknown>
 
 uqincb  w0, all, mul #16
 // CHECK-INST: uqincb  w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf7,0x2f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 2f 04 <unknown>
+// CHECK-UNKNOWN: 042ff7e0 <unknown>
 
 uqincb  w0, pow2
 // CHECK-INST: uqincb  w0, pow2
 // CHECK-ENCODING: [0x00,0xf4,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f4 20 04 <unknown>
+// CHECK-UNKNOWN: 0420f400 <unknown>
 
 uqincb  w0, pow2, mul #16
 // CHECK-INST: uqincb  w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xf4,0x2f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f4 2f 04 <unknown>
+// CHECK-UNKNOWN: 042ff400 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -87,172 +87,172 @@ uqincb  x0, pow2
 // CHECK-INST: uqincb  x0, pow2
 // CHECK-ENCODING: [0x00,0xf4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f400 <unknown>
 
 uqincb  x0, vl1
 // CHECK-INST: uqincb  x0, vl1
 // CHECK-ENCODING: [0x20,0xf4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f420 <unknown>
 
 uqincb  x0, vl2
 // CHECK-INST: uqincb  x0, vl2
 // CHECK-ENCODING: [0x40,0xf4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f440 <unknown>
 
 uqincb  x0, vl3
 // CHECK-INST: uqincb  x0, vl3
 // CHECK-ENCODING: [0x60,0xf4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f460 <unknown>
 
 uqincb  x0, vl4
 // CHECK-INST: uqincb  x0, vl4
 // CHECK-ENCODING: [0x80,0xf4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f480 <unknown>
 
 uqincb  x0, vl5
 // CHECK-INST: uqincb  x0, vl5
 // CHECK-ENCODING: [0xa0,0xf4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f4a0 <unknown>
 
 uqincb  x0, vl6
 // CHECK-INST: uqincb  x0, vl6
 // CHECK-ENCODING: [0xc0,0xf4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f4c0 <unknown>
 
 uqincb  x0, vl7
 // CHECK-INST: uqincb  x0, vl7
 // CHECK-ENCODING: [0xe0,0xf4,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f4 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f4e0 <unknown>
 
 uqincb  x0, vl8
 // CHECK-INST: uqincb  x0, vl8
 // CHECK-ENCODING: [0x00,0xf5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f500 <unknown>
 
 uqincb  x0, vl16
 // CHECK-INST: uqincb  x0, vl16
 // CHECK-ENCODING: [0x20,0xf5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f520 <unknown>
 
 uqincb  x0, vl32
 // CHECK-INST: uqincb  x0, vl32
 // CHECK-ENCODING: [0x40,0xf5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f540 <unknown>
 
 uqincb  x0, vl64
 // CHECK-INST: uqincb  x0, vl64
 // CHECK-ENCODING: [0x60,0xf5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f560 <unknown>
 
 uqincb  x0, vl128
 // CHECK-INST: uqincb  x0, vl128
 // CHECK-ENCODING: [0x80,0xf5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f580 <unknown>
 
 uqincb  x0, vl256
 // CHECK-INST: uqincb  x0, vl256
 // CHECK-ENCODING: [0xa0,0xf5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f5a0 <unknown>
 
 uqincb  x0, #14
 // CHECK-INST: uqincb  x0, #14
 // CHECK-ENCODING: [0xc0,0xf5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f5c0 <unknown>
 
 uqincb  x0, #15
 // CHECK-INST: uqincb  x0, #15
 // CHECK-ENCODING: [0xe0,0xf5,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f5 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f5e0 <unknown>
 
 uqincb  x0, #16
 // CHECK-INST: uqincb  x0, #16
 // CHECK-ENCODING: [0x00,0xf6,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f6 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f600 <unknown>
 
 uqincb  x0, #17
 // CHECK-INST: uqincb  x0, #17
 // CHECK-ENCODING: [0x20,0xf6,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f6 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f620 <unknown>
 
 uqincb  x0, #18
 // CHECK-INST: uqincb  x0, #18
 // CHECK-ENCODING: [0x40,0xf6,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f6 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f640 <unknown>
 
 uqincb  x0, #19
 // CHECK-INST: uqincb  x0, #19
 // CHECK-ENCODING: [0x60,0xf6,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f6 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f660 <unknown>
 
 uqincb  x0, #20
 // CHECK-INST: uqincb  x0, #20
 // CHECK-ENCODING: [0x80,0xf6,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f6 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f680 <unknown>
 
 uqincb  x0, #21
 // CHECK-INST: uqincb  x0, #21
 // CHECK-ENCODING: [0xa0,0xf6,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f6 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f6a0 <unknown>
 
 uqincb  x0, #22
 // CHECK-INST: uqincb  x0, #22
 // CHECK-ENCODING: [0xc0,0xf6,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f6 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f6c0 <unknown>
 
 uqincb  x0, #23
 // CHECK-INST: uqincb  x0, #23
 // CHECK-ENCODING: [0xe0,0xf6,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f6 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f6e0 <unknown>
 
 uqincb  x0, #24
 // CHECK-INST: uqincb  x0, #24
 // CHECK-ENCODING: [0x00,0xf7,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f7 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f700 <unknown>
 
 uqincb  x0, #25
 // CHECK-INST: uqincb  x0, #25
 // CHECK-ENCODING: [0x20,0xf7,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f7 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f720 <unknown>
 
 uqincb  x0, #26
 // CHECK-INST: uqincb  x0, #26
 // CHECK-ENCODING: [0x40,0xf7,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f7 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f740 <unknown>
 
 uqincb  x0, #27
 // CHECK-INST: uqincb  x0, #27
 // CHECK-ENCODING: [0x60,0xf7,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f7 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f760 <unknown>
 
 uqincb  x0, #28
 // CHECK-INST: uqincb  x0, #28
 // CHECK-ENCODING: [0x80,0xf7,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f7 30 04 <unknown>
+// CHECK-UNKNOWN: 0430f780 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uqincd.s b/llvm/test/MC/AArch64/SVE/uqincd.s
index 982e7df6be1ed..1e49fecce4f13 100644
--- a/llvm/test/MC/AArch64/SVE/uqincd.s
+++ b/llvm/test/MC/AArch64/SVE/uqincd.s
@@ -17,25 +17,25 @@ uqincd  x0
 // CHECK-INST: uqincd  x0
 // CHECK-ENCODING: [0xe0,0xf7,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f7e0 <unknown>
 
 uqincd  x0, all
 // CHECK-INST: uqincd  x0
 // CHECK-ENCODING: [0xe0,0xf7,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f7e0 <unknown>
 
 uqincd  x0, all, mul #1
 // CHECK-INST: uqincd  x0
 // CHECK-ENCODING: [0xe0,0xf7,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f7e0 <unknown>
 
 uqincd  x0, all, mul #16
 // CHECK-INST: uqincd  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf7,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 ff 04 <unknown>
+// CHECK-UNKNOWN: 04fff7e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ uqincd  w0
 // CHECK-INST: uqincd  w0
 // CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0f7e0 <unknown>
 
 uqincd  w0, all
 // CHECK-INST: uqincd  w0
 // CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0f7e0 <unknown>
 
 uqincd  w0, all, mul #1
 // CHECK-INST: uqincd  w0
 // CHECK-ENCODING: [0xe0,0xf7,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0f7e0 <unknown>
 
 uqincd  w0, all, mul #16
 // CHECK-INST: uqincd  w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf7,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 ef 04 <unknown>
+// CHECK-UNKNOWN: 04eff7e0 <unknown>
 
 uqincd  w0, pow2
 // CHECK-INST: uqincd  w0, pow2
 // CHECK-ENCODING: [0x00,0xf4,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f4 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0f400 <unknown>
 
 uqincd  w0, pow2, mul #16
 // CHECK-INST: uqincd  w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xf4,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f4 ef 04 <unknown>
+// CHECK-UNKNOWN: 04eff400 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -86,37 +86,37 @@ uqincd  z0.d
 // CHECK-INST: uqincd  z0.d
 // CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c7e0 <unknown>
 
 uqincd  z0.d, all
 // CHECK-INST: uqincd  z0.d
 // CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c7e0 <unknown>
 
 uqincd  z0.d, all, mul #1
 // CHECK-INST: uqincd  z0.d
 // CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c7e0 <unknown>
 
 uqincd  z0.d, all, mul #16
 // CHECK-INST: uqincd  z0.d, all, mul #16
 // CHECK-ENCODING: [0xe0,0xc7,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 ef 04 <unknown>
+// CHECK-UNKNOWN: 04efc7e0 <unknown>
 
 uqincd  z0.d, pow2
 // CHECK-INST: uqincd  z0.d, pow2
 // CHECK-ENCODING: [0x00,0xc4,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c400 <unknown>
 
 uqincd  z0.d, pow2, mul #16
 // CHECK-INST: uqincd  z0.d, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc4,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 ef 04 <unknown>
+// CHECK-UNKNOWN: 04efc400 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -127,175 +127,175 @@ uqincd  x0, pow2
 // CHECK-INST: uqincd  x0, pow2
 // CHECK-ENCODING: [0x00,0xf4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f400 <unknown>
 
 uqincd  x0, vl1
 // CHECK-INST: uqincd  x0, vl1
 // CHECK-ENCODING: [0x20,0xf4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f420 <unknown>
 
 uqincd  x0, vl2
 // CHECK-INST: uqincd  x0, vl2
 // CHECK-ENCODING: [0x40,0xf4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f440 <unknown>
 
 uqincd  x0, vl3
 // CHECK-INST: uqincd  x0, vl3
 // CHECK-ENCODING: [0x60,0xf4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f460 <unknown>
 
 uqincd  x0, vl4
 // CHECK-INST: uqincd  x0, vl4
 // CHECK-ENCODING: [0x80,0xf4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f480 <unknown>
 
 uqincd  x0, vl5
 // CHECK-INST: uqincd  x0, vl5
 // CHECK-ENCODING: [0xa0,0xf4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f4a0 <unknown>
 
 uqincd  x0, vl6
 // CHECK-INST: uqincd  x0, vl6
 // CHECK-ENCODING: [0xc0,0xf4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f4c0 <unknown>
 
 uqincd  x0, vl7
 // CHECK-INST: uqincd  x0, vl7
 // CHECK-ENCODING: [0xe0,0xf4,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f4 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f4e0 <unknown>
 
 uqincd  x0, vl8
 // CHECK-INST: uqincd  x0, vl8
 // CHECK-ENCODING: [0x00,0xf5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f500 <unknown>
 
 uqincd  x0, vl16
 // CHECK-INST: uqincd  x0, vl16
 // CHECK-ENCODING: [0x20,0xf5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f520 <unknown>
 
 uqincd  x0, vl32
 // CHECK-INST: uqincd  x0, vl32
 // CHECK-ENCODING: [0x40,0xf5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f540 <unknown>
 
 uqincd  x0, vl64
 // CHECK-INST: uqincd  x0, vl64
 // CHECK-ENCODING: [0x60,0xf5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f560 <unknown>
 
 uqincd  x0, vl128
 // CHECK-INST: uqincd  x0, vl128
 // CHECK-ENCODING: [0x80,0xf5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f580 <unknown>
 
 uqincd  x0, vl256
 // CHECK-INST: uqincd  x0, vl256
 // CHECK-ENCODING: [0xa0,0xf5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f5a0 <unknown>
 
 uqincd  x0, #14
 // CHECK-INST: uqincd  x0, #14
 // CHECK-ENCODING: [0xc0,0xf5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f5c0 <unknown>
 
 uqincd  x0, #15
 // CHECK-INST: uqincd  x0, #15
 // CHECK-ENCODING: [0xe0,0xf5,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f5 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f5e0 <unknown>
 
 uqincd  x0, #16
 // CHECK-INST: uqincd  x0, #16
 // CHECK-ENCODING: [0x00,0xf6,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f6 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f600 <unknown>
 
 uqincd  x0, #17
 // CHECK-INST: uqincd  x0, #17
 // CHECK-ENCODING: [0x20,0xf6,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f6 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f620 <unknown>
 
 uqincd  x0, #18
 // CHECK-INST: uqincd  x0, #18
 // CHECK-ENCODING: [0x40,0xf6,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f6 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f640 <unknown>
 
 uqincd  x0, #19
 // CHECK-INST: uqincd  x0, #19
 // CHECK-ENCODING: [0x60,0xf6,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f6 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f660 <unknown>
 
 uqincd  x0, #20
 // CHECK-INST: uqincd  x0, #20
 // CHECK-ENCODING: [0x80,0xf6,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f6 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f680 <unknown>
 
 uqincd  x0, #21
 // CHECK-INST: uqincd  x0, #21
 // CHECK-ENCODING: [0xa0,0xf6,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f6 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f6a0 <unknown>
 
 uqincd  x0, #22
 // CHECK-INST: uqincd  x0, #22
 // CHECK-ENCODING: [0xc0,0xf6,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f6 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f6c0 <unknown>
 
 uqincd  x0, #23
 // CHECK-INST: uqincd  x0, #23
 // CHECK-ENCODING: [0xe0,0xf6,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f6 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f6e0 <unknown>
 
 uqincd  x0, #24
 // CHECK-INST: uqincd  x0, #24
 // CHECK-ENCODING: [0x00,0xf7,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f7 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f700 <unknown>
 
 uqincd  x0, #25
 // CHECK-INST: uqincd  x0, #25
 // CHECK-ENCODING: [0x20,0xf7,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f7 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f720 <unknown>
 
 uqincd  x0, #26
 // CHECK-INST: uqincd  x0, #26
 // CHECK-ENCODING: [0x40,0xf7,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f7 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f740 <unknown>
 
 uqincd  x0, #27
 // CHECK-INST: uqincd  x0, #27
 // CHECK-ENCODING: [0x60,0xf7,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f7 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f760 <unknown>
 
 uqincd  x0, #28
 // CHECK-INST: uqincd  x0, #28
 // CHECK-ENCODING: [0x80,0xf7,0xf0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f7 f0 04 <unknown>
+// CHECK-UNKNOWN: 04f0f780 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -305,34 +305,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqincd  z0.d
 // CHECK-INST: uqincd	z0.d
 // CHECK-ENCODING: [0xe0,0xc7,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c7e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqincd  z0.d, pow2, mul #16
 // CHECK-INST: uqincd	z0.d, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc4,0xef,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 ef 04 <unknown>
+// CHECK-UNKNOWN: 04efc400 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqincd  z0.d, pow2
 // CHECK-INST: uqincd	z0.d, pow2
 // CHECK-ENCODING: [0x00,0xc4,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 e0 04 <unknown>
+// CHECK-UNKNOWN: 04e0c400 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uqinch.s b/llvm/test/MC/AArch64/SVE/uqinch.s
index 4aba36c248e7d..a43be3c6ac291 100644
--- a/llvm/test/MC/AArch64/SVE/uqinch.s
+++ b/llvm/test/MC/AArch64/SVE/uqinch.s
@@ -18,25 +18,25 @@ uqinch  x0
 // CHECK-INST: uqinch  x0
 // CHECK-ENCODING: [0xe0,0xf7,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f7e0 <unknown>
 
 uqinch  x0, all
 // CHECK-INST: uqinch  x0
 // CHECK-ENCODING: [0xe0,0xf7,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f7e0 <unknown>
 
 uqinch  x0, all, mul #1
 // CHECK-INST: uqinch  x0
 // CHECK-ENCODING: [0xe0,0xf7,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f7e0 <unknown>
 
 uqinch  x0, all, mul #16
 // CHECK-INST: uqinch  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf7,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 7f 04 <unknown>
+// CHECK-UNKNOWN: 047ff7e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -47,37 +47,37 @@ uqinch  w0
 // CHECK-INST: uqinch  w0
 // CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
+// CHECK-UNKNOWN: 0460f7e0 <unknown>
 
 uqinch  w0, all
 // CHECK-INST: uqinch  w0
 // CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
+// CHECK-UNKNOWN: 0460f7e0 <unknown>
 
 uqinch  w0, all, mul #1
 // CHECK-INST: uqinch  w0
 // CHECK-ENCODING: [0xe0,0xf7,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 60 04 <unknown>
+// CHECK-UNKNOWN: 0460f7e0 <unknown>
 
 uqinch  w0, all, mul #16
 // CHECK-INST: uqinch  w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf7,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 6f 04 <unknown>
+// CHECK-UNKNOWN: 046ff7e0 <unknown>
 
 uqinch  w0, pow2
 // CHECK-INST: uqinch  w0, pow2
 // CHECK-ENCODING: [0x00,0xf4,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f4 60 04 <unknown>
+// CHECK-UNKNOWN: 0460f400 <unknown>
 
 uqinch  w0, pow2, mul #16
 // CHECK-INST: uqinch  w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xf4,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f4 6f 04 <unknown>
+// CHECK-UNKNOWN: 046ff400 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -88,37 +88,37 @@ uqinch  z0.h
 // CHECK-INST: uqinch  z0.h
 // CHECK-ENCODING: [0xe0,0xc7,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c7e0 <unknown>
 
 uqinch  z0.h, all
 // CHECK-INST: uqinch  z0.h
 // CHECK-ENCODING: [0xe0,0xc7,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c7e0 <unknown>
 
 uqinch  z0.h, all, mul #1
 // CHECK-INST: uqinch  z0.h
 // CHECK-ENCODING: [0xe0,0xc7,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c7e0 <unknown>
 
 uqinch  z0.h, all, mul #16
 // CHECK-INST: uqinch  z0.h, all, mul #16
 // CHECK-ENCODING: [0xe0,0xc7,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fc7e0 <unknown>
 
 uqinch  z0.h, pow2
 // CHECK-INST: uqinch  z0.h, pow2
 // CHECK-ENCODING: [0x00,0xc4,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c400 <unknown>
 
 uqinch  z0.h, pow2, mul #16
 // CHECK-INST: uqinch  z0.h, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc4,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fc400 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -129,175 +129,175 @@ uqinch  x0, pow2
 // CHECK-INST: uqinch  x0, pow2
 // CHECK-ENCODING: [0x00,0xf4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f400 <unknown>
 
 uqinch  x0, vl1
 // CHECK-INST: uqinch  x0, vl1
 // CHECK-ENCODING: [0x20,0xf4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f420 <unknown>
 
 uqinch  x0, vl2
 // CHECK-INST: uqinch  x0, vl2
 // CHECK-ENCODING: [0x40,0xf4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f440 <unknown>
 
 uqinch  x0, vl3
 // CHECK-INST: uqinch  x0, vl3
 // CHECK-ENCODING: [0x60,0xf4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f460 <unknown>
 
 uqinch  x0, vl4
 // CHECK-INST: uqinch  x0, vl4
 // CHECK-ENCODING: [0x80,0xf4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f480 <unknown>
 
 uqinch  x0, vl5
 // CHECK-INST: uqinch  x0, vl5
 // CHECK-ENCODING: [0xa0,0xf4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f4a0 <unknown>
 
 uqinch  x0, vl6
 // CHECK-INST: uqinch  x0, vl6
 // CHECK-ENCODING: [0xc0,0xf4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f4c0 <unknown>
 
 uqinch  x0, vl7
 // CHECK-INST: uqinch  x0, vl7
 // CHECK-ENCODING: [0xe0,0xf4,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f4 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f4e0 <unknown>
 
 uqinch  x0, vl8
 // CHECK-INST: uqinch  x0, vl8
 // CHECK-ENCODING: [0x00,0xf5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f500 <unknown>
 
 uqinch  x0, vl16
 // CHECK-INST: uqinch  x0, vl16
 // CHECK-ENCODING: [0x20,0xf5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f520 <unknown>
 
 uqinch  x0, vl32
 // CHECK-INST: uqinch  x0, vl32
 // CHECK-ENCODING: [0x40,0xf5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f540 <unknown>
 
 uqinch  x0, vl64
 // CHECK-INST: uqinch  x0, vl64
 // CHECK-ENCODING: [0x60,0xf5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f560 <unknown>
 
 uqinch  x0, vl128
 // CHECK-INST: uqinch  x0, vl128
 // CHECK-ENCODING: [0x80,0xf5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f580 <unknown>
 
 uqinch  x0, vl256
 // CHECK-INST: uqinch  x0, vl256
 // CHECK-ENCODING: [0xa0,0xf5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f5a0 <unknown>
 
 uqinch  x0, #14
 // CHECK-INST: uqinch  x0, #14
 // CHECK-ENCODING: [0xc0,0xf5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f5c0 <unknown>
 
 uqinch  x0, #15
 // CHECK-INST: uqinch  x0, #15
 // CHECK-ENCODING: [0xe0,0xf5,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f5 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f5e0 <unknown>
 
 uqinch  x0, #16
 // CHECK-INST: uqinch  x0, #16
 // CHECK-ENCODING: [0x00,0xf6,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f6 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f600 <unknown>
 
 uqinch  x0, #17
 // CHECK-INST: uqinch  x0, #17
 // CHECK-ENCODING: [0x20,0xf6,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f6 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f620 <unknown>
 
 uqinch  x0, #18
 // CHECK-INST: uqinch  x0, #18
 // CHECK-ENCODING: [0x40,0xf6,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f6 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f640 <unknown>
 
 uqinch  x0, #19
 // CHECK-INST: uqinch  x0, #19
 // CHECK-ENCODING: [0x60,0xf6,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f6 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f660 <unknown>
 
 uqinch  x0, #20
 // CHECK-INST: uqinch  x0, #20
 // CHECK-ENCODING: [0x80,0xf6,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f6 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f680 <unknown>
 
 uqinch  x0, #21
 // CHECK-INST: uqinch  x0, #21
 // CHECK-ENCODING: [0xa0,0xf6,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f6 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f6a0 <unknown>
 
 uqinch  x0, #22
 // CHECK-INST: uqinch  x0, #22
 // CHECK-ENCODING: [0xc0,0xf6,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f6 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f6c0 <unknown>
 
 uqinch  x0, #23
 // CHECK-INST: uqinch  x0, #23
 // CHECK-ENCODING: [0xe0,0xf6,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f6 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f6e0 <unknown>
 
 uqinch  x0, #24
 // CHECK-INST: uqinch  x0, #24
 // CHECK-ENCODING: [0x00,0xf7,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f7 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f700 <unknown>
 
 uqinch  x0, #25
 // CHECK-INST: uqinch  x0, #25
 // CHECK-ENCODING: [0x20,0xf7,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f7 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f720 <unknown>
 
 uqinch  x0, #26
 // CHECK-INST: uqinch  x0, #26
 // CHECK-ENCODING: [0x40,0xf7,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f7 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f740 <unknown>
 
 uqinch  x0, #27
 // CHECK-INST: uqinch  x0, #27
 // CHECK-ENCODING: [0x60,0xf7,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f7 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f760 <unknown>
 
 uqinch  x0, #28
 // CHECK-INST: uqinch  x0, #28
 // CHECK-ENCODING: [0x80,0xf7,0x70,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f7 70 04 <unknown>
+// CHECK-UNKNOWN: 0470f780 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -307,34 +307,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqinch  z0.h
 // CHECK-INST: uqinch	z0.h
 // CHECK-ENCODING: [0xe0,0xc7,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c7e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqinch  z0.h, pow2, mul #16
 // CHECK-INST: uqinch	z0.h, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc4,0x6f,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 6f 04 <unknown>
+// CHECK-UNKNOWN: 046fc400 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqinch  z0.h, pow2
 // CHECK-INST: uqinch	z0.h, pow2
 // CHECK-ENCODING: [0x00,0xc4,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 60 04 <unknown>
+// CHECK-UNKNOWN: 0460c400 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uqincp.s b/llvm/test/MC/AArch64/SVE/uqincp.s
index ea56080a01dcc..dbae0bddac3d0 100644
--- a/llvm/test/MC/AArch64/SVE/uqincp.s
+++ b/llvm/test/MC/AArch64/SVE/uqincp.s
@@ -13,85 +13,85 @@ uqincp  x0, p0.b
 // CHECK-INST: uqincp  x0, p0.b
 // CHECK-ENCODING: [0x00,0x8c,0x29,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c 29 25 <unknown>
+// CHECK-UNKNOWN: 25298c00 <unknown>
 
 uqincp  x0, p0.h
 // CHECK-INST: uqincp  x0, p0.h
 // CHECK-ENCODING: [0x00,0x8c,0x69,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c 69 25 <unknown>
+// CHECK-UNKNOWN: 25698c00 <unknown>
 
 uqincp  x0, p0.s
 // CHECK-INST: uqincp  x0, p0.s
 // CHECK-ENCODING: [0x00,0x8c,0xa9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c a9 25 <unknown>
+// CHECK-UNKNOWN: 25a98c00 <unknown>
 
 uqincp  x0, p0.d
 // CHECK-INST: uqincp  x0, p0.d
 // CHECK-ENCODING: [0x00,0x8c,0xe9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 8c e9 25 <unknown>
+// CHECK-UNKNOWN: 25e98c00 <unknown>
 
 uqincp  wzr, p15.b
 // CHECK-INST: uqincp  wzr, p15.b
 // CHECK-ENCODING: [0xff,0x89,0x29,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 29 25 <unknown>
+// CHECK-UNKNOWN: 252989ff <unknown>
 
 uqincp  wzr, p15.h
 // CHECK-INST: uqincp  wzr, p15.h
 // CHECK-ENCODING: [0xff,0x89,0x69,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 69 25 <unknown>
+// CHECK-UNKNOWN: 256989ff <unknown>
 
 uqincp  wzr, p15.s
 // CHECK-INST: uqincp  wzr, p15.s
 // CHECK-ENCODING: [0xff,0x89,0xa9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 a9 25 <unknown>
+// CHECK-UNKNOWN: 25a989ff <unknown>
 
 uqincp  wzr, p15.d
 // CHECK-INST: uqincp  wzr, p15.d
 // CHECK-ENCODING: [0xff,0x89,0xe9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 89 e9 25 <unknown>
+// CHECK-UNKNOWN: 25e989ff <unknown>
 
 uqincp  z0.h, p0
 // CHECK-INST: uqincp  z0.h, p0.h
 // CHECK-ENCODING: [0x00,0x80,0x69,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 69 25 <unknown>
+// CHECK-UNKNOWN: 25698000 <unknown>
 
 uqincp  z0.h, p0.h
 // CHECK-INST: uqincp  z0.h, p0.h
 // CHECK-ENCODING: [0x00,0x80,0x69,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 69 25 <unknown>
+// CHECK-UNKNOWN: 25698000 <unknown>
 
 uqincp  z0.s, p0
 // CHECK-INST: uqincp  z0.s, p0.s
 // CHECK-ENCODING: [0x00,0x80,0xa9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 a9 25 <unknown>
+// CHECK-UNKNOWN: 25a98000 <unknown>
 
 uqincp  z0.s, p0.s
 // CHECK-INST: uqincp  z0.s, p0.s
 // CHECK-ENCODING: [0x00,0x80,0xa9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 a9 25 <unknown>
+// CHECK-UNKNOWN: 25a98000 <unknown>
 
 uqincp  z0.d, p0
 // CHECK-INST: uqincp  z0.d, p0.d
 // CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 e9 25 <unknown>
+// CHECK-UNKNOWN: 25e98000 <unknown>
 
 uqincp  z0.d, p0.d
 // CHECK-INST: uqincp  z0.d, p0.d
 // CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 e9 25 <unknown>
+// CHECK-UNKNOWN: 25e98000 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -101,10 +101,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqincp  z0.d, p0.d
 // CHECK-INST: uqincp	z0.d, p0.d
 // CHECK-ENCODING: [0x00,0x80,0xe9,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 80 e9 25 <unknown>
+// CHECK-UNKNOWN: 25e98000 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uqincw.s b/llvm/test/MC/AArch64/SVE/uqincw.s
index 8b76b6564e196..47a65eba4d2b6 100644
--- a/llvm/test/MC/AArch64/SVE/uqincw.s
+++ b/llvm/test/MC/AArch64/SVE/uqincw.s
@@ -17,25 +17,25 @@ uqincw  x0
 // CHECK-INST: uqincw  x0
 // CHECK-ENCODING: [0xe0,0xf7,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f7e0 <unknown>
 
 uqincw  x0, all
 // CHECK-INST: uqincw  x0
 // CHECK-ENCODING: [0xe0,0xf7,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f7e0 <unknown>
 
 uqincw  x0, all, mul #1
 // CHECK-INST: uqincw  x0
 // CHECK-ENCODING: [0xe0,0xf7,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f7e0 <unknown>
 
 uqincw  x0, all, mul #16
 // CHECK-INST: uqincw  x0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf7,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bff7e0 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -46,37 +46,37 @@ uqincw  w0
 // CHECK-INST: uqincw  w0
 // CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0f7e0 <unknown>
 
 uqincw  w0, all
 // CHECK-INST: uqincw  w0
 // CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0f7e0 <unknown>
 
 uqincw  w0, all, mul #1
 // CHECK-INST: uqincw  w0
 // CHECK-ENCODING: [0xe0,0xf7,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0f7e0 <unknown>
 
 uqincw  w0, all, mul #16
 // CHECK-INST: uqincw  w0, all, mul #16
 // CHECK-ENCODING: [0xe0,0xf7,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f7 af 04 <unknown>
+// CHECK-UNKNOWN: 04aff7e0 <unknown>
 
 uqincw  w0, pow2
 // CHECK-INST: uqincw  w0, pow2
 // CHECK-ENCODING: [0x00,0xf4,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f4 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0f400 <unknown>
 
 uqincw  w0, pow2, mul #16
 // CHECK-INST: uqincw  w0, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xf4,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f4 af 04 <unknown>
+// CHECK-UNKNOWN: 04aff400 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -86,37 +86,37 @@ uqincw  z0.s
 // CHECK-INST: uqincw  z0.s
 // CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c7e0 <unknown>
 
 uqincw  z0.s, all
 // CHECK-INST: uqincw  z0.s
 // CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c7e0 <unknown>
 
 uqincw  z0.s, all, mul #1
 // CHECK-INST: uqincw  z0.s
 // CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c7e0 <unknown>
 
 uqincw  z0.s, all, mul #16
 // CHECK-INST: uqincw  z0.s, all, mul #16
 // CHECK-ENCODING: [0xe0,0xc7,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 af 04 <unknown>
+// CHECK-UNKNOWN: 04afc7e0 <unknown>
 
 uqincw  z0.s, pow2
 // CHECK-INST: uqincw  z0.s, pow2
 // CHECK-ENCODING: [0x00,0xc4,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c400 <unknown>
 
 uqincw  z0.s, pow2, mul #16
 // CHECK-INST: uqincw  z0.s, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc4,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 af 04 <unknown>
+// CHECK-UNKNOWN: 04afc400 <unknown>
 
 
 // ---------------------------------------------------------------------------//
@@ -127,175 +127,175 @@ uqincw  x0, pow2
 // CHECK-INST: uqincw  x0, pow2
 // CHECK-ENCODING: [0x00,0xf4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f400 <unknown>
 
 uqincw  x0, vl1
 // CHECK-INST: uqincw  x0, vl1
 // CHECK-ENCODING: [0x20,0xf4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f420 <unknown>
 
 uqincw  x0, vl2
 // CHECK-INST: uqincw  x0, vl2
 // CHECK-ENCODING: [0x40,0xf4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f440 <unknown>
 
 uqincw  x0, vl3
 // CHECK-INST: uqincw  x0, vl3
 // CHECK-ENCODING: [0x60,0xf4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f460 <unknown>
 
 uqincw  x0, vl4
 // CHECK-INST: uqincw  x0, vl4
 // CHECK-ENCODING: [0x80,0xf4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f480 <unknown>
 
 uqincw  x0, vl5
 // CHECK-INST: uqincw  x0, vl5
 // CHECK-ENCODING: [0xa0,0xf4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f4a0 <unknown>
 
 uqincw  x0, vl6
 // CHECK-INST: uqincw  x0, vl6
 // CHECK-ENCODING: [0xc0,0xf4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f4c0 <unknown>
 
 uqincw  x0, vl7
 // CHECK-INST: uqincw  x0, vl7
 // CHECK-ENCODING: [0xe0,0xf4,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f4 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f4e0 <unknown>
 
 uqincw  x0, vl8
 // CHECK-INST: uqincw  x0, vl8
 // CHECK-ENCODING: [0x00,0xf5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f500 <unknown>
 
 uqincw  x0, vl16
 // CHECK-INST: uqincw  x0, vl16
 // CHECK-ENCODING: [0x20,0xf5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f520 <unknown>
 
 uqincw  x0, vl32
 // CHECK-INST: uqincw  x0, vl32
 // CHECK-ENCODING: [0x40,0xf5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f540 <unknown>
 
 uqincw  x0, vl64
 // CHECK-INST: uqincw  x0, vl64
 // CHECK-ENCODING: [0x60,0xf5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f560 <unknown>
 
 uqincw  x0, vl128
 // CHECK-INST: uqincw  x0, vl128
 // CHECK-ENCODING: [0x80,0xf5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f580 <unknown>
 
 uqincw  x0, vl256
 // CHECK-INST: uqincw  x0, vl256
 // CHECK-ENCODING: [0xa0,0xf5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f5a0 <unknown>
 
 uqincw  x0, #14
 // CHECK-INST: uqincw  x0, #14
 // CHECK-ENCODING: [0xc0,0xf5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f5c0 <unknown>
 
 uqincw  x0, #15
 // CHECK-INST: uqincw  x0, #15
 // CHECK-ENCODING: [0xe0,0xf5,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f5 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f5e0 <unknown>
 
 uqincw  x0, #16
 // CHECK-INST: uqincw  x0, #16
 // CHECK-ENCODING: [0x00,0xf6,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f6 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f600 <unknown>
 
 uqincw  x0, #17
 // CHECK-INST: uqincw  x0, #17
 // CHECK-ENCODING: [0x20,0xf6,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f6 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f620 <unknown>
 
 uqincw  x0, #18
 // CHECK-INST: uqincw  x0, #18
 // CHECK-ENCODING: [0x40,0xf6,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f6 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f640 <unknown>
 
 uqincw  x0, #19
 // CHECK-INST: uqincw  x0, #19
 // CHECK-ENCODING: [0x60,0xf6,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f6 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f660 <unknown>
 
 uqincw  x0, #20
 // CHECK-INST: uqincw  x0, #20
 // CHECK-ENCODING: [0x80,0xf6,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f6 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f680 <unknown>
 
 uqincw  x0, #21
 // CHECK-INST: uqincw  x0, #21
 // CHECK-ENCODING: [0xa0,0xf6,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: a0 f6 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f6a0 <unknown>
 
 uqincw  x0, #22
 // CHECK-INST: uqincw  x0, #22
 // CHECK-ENCODING: [0xc0,0xf6,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c0 f6 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f6c0 <unknown>
 
 uqincw  x0, #23
 // CHECK-INST: uqincw  x0, #23
 // CHECK-ENCODING: [0xe0,0xf6,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 f6 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f6e0 <unknown>
 
 uqincw  x0, #24
 // CHECK-INST: uqincw  x0, #24
 // CHECK-ENCODING: [0x00,0xf7,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 f7 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f700 <unknown>
 
 uqincw  x0, #25
 // CHECK-INST: uqincw  x0, #25
 // CHECK-ENCODING: [0x20,0xf7,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 20 f7 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f720 <unknown>
 
 uqincw  x0, #26
 // CHECK-INST: uqincw  x0, #26
 // CHECK-ENCODING: [0x40,0xf7,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 40 f7 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f740 <unknown>
 
 uqincw  x0, #27
 // CHECK-INST: uqincw  x0, #27
 // CHECK-ENCODING: [0x60,0xf7,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 60 f7 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f760 <unknown>
 
 uqincw  x0, #28
 // CHECK-INST: uqincw  x0, #28
 // CHECK-ENCODING: [0x80,0xf7,0xb0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 80 f7 b0 04 <unknown>
+// CHECK-UNKNOWN: 04b0f780 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -305,34 +305,34 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqincw  z0.s
 // CHECK-INST: uqincw	z0.s
 // CHECK-ENCODING: [0xe0,0xc7,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 c7 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c7e0 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqincw  z0.s, pow2, mul #16
 // CHECK-INST: uqincw	z0.s, pow2, mul #16
 // CHECK-ENCODING: [0x00,0xc4,0xaf,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 af 04 <unknown>
+// CHECK-UNKNOWN: 04afc400 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uqincw  z0.s, pow2
 // CHECK-INST: uqincw	z0.s, pow2
 // CHECK-ENCODING: [0x00,0xc4,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c4 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a0c400 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uqsub.s b/llvm/test/MC/AArch64/SVE/uqsub.s
index ddb677b83b3aa..0ca78cf44e5e6 100644
--- a/llvm/test/MC/AArch64/SVE/uqsub.s
+++ b/llvm/test/MC/AArch64/SVE/uqsub.s
@@ -14,109 +14,109 @@ uqsub     z0.b, z0.b, z0.b
 // CHECK-INST: uqsub z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x1c,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 1c 20 04 <unknown>
+// CHECK-UNKNOWN: 04201c00 <unknown>
 
 uqsub     z0.h, z0.h, z0.h
 // CHECK-INST: uqsub z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x1c,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 1c 60 04 <unknown>
+// CHECK-UNKNOWN: 04601c00 <unknown>
 
 uqsub     z0.s, z0.s, z0.s
 // CHECK-INST: uqsub z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x1c,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 1c a0 04 <unknown>
+// CHECK-UNKNOWN: 04a01c00 <unknown>
 
 uqsub     z0.d, z0.d, z0.d
 // CHECK-INST: uqsub z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x1c,0xe0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 1c e0 04 <unknown>
+// CHECK-UNKNOWN: 04e01c00 <unknown>
 
 uqsub     z0.b, z0.b, #0
 // CHECK-INST: uqsub z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xc0,0x27,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 27 25 <unknown>
+// CHECK-UNKNOWN: 2527c000 <unknown>
 
 uqsub     z31.b, z31.b, #255
 // CHECK-INST: uqsub z31.b, z31.b, #255
 // CHECK-ENCODING: [0xff,0xdf,0x27,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff df 27 25 <unknown>
+// CHECK-UNKNOWN: 2527dfff <unknown>
 
 uqsub     z0.h, z0.h, #0
 // CHECK-INST: uqsub z0.h, z0.h, #0
 // CHECK-ENCODING: [0x00,0xc0,0x67,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 67 25 <unknown>
+// CHECK-UNKNOWN: 2567c000 <unknown>
 
 uqsub     z0.h, z0.h, #0, lsl #8
 // CHECK-INST: uqsub z0.h, z0.h, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0x67,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 67 25 <unknown>
+// CHECK-UNKNOWN: 2567e000 <unknown>
 
 uqsub     z31.h, z31.h, #255, lsl #8
 // CHECK-INST: uqsub z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x67,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 67 25 <unknown>
+// CHECK-UNKNOWN: 2567ffff <unknown>
 
 uqsub     z31.h, z31.h, #65280
 // CHECK-INST: uqsub z31.h, z31.h, #65280
 // CHECK-ENCODING: [0xff,0xff,0x67,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff 67 25 <unknown>
+// CHECK-UNKNOWN: 2567ffff <unknown>
 
 uqsub     z0.s, z0.s, #0
 // CHECK-INST: uqsub z0.s, z0.s, #0
 // CHECK-ENCODING: [0x00,0xc0,0xa7,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 a7 25 <unknown>
+// CHECK-UNKNOWN: 25a7c000 <unknown>
 
 uqsub     z0.s, z0.s, #0, lsl #8
 // CHECK-INST: uqsub z0.s, z0.s, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xa7,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 a7 25 <unknown>
+// CHECK-UNKNOWN: 25a7e000 <unknown>
 
 uqsub     z31.s, z31.s, #255, lsl #8
 // CHECK-INST: uqsub z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa7,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a7 25 <unknown>
+// CHECK-UNKNOWN: 25a7ffff <unknown>
 
 uqsub     z31.s, z31.s, #65280
 // CHECK-INST: uqsub z31.s, z31.s, #65280
 // CHECK-ENCODING: [0xff,0xff,0xa7,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff a7 25 <unknown>
+// CHECK-UNKNOWN: 25a7ffff <unknown>
 
 uqsub     z0.d, z0.d, #0
 // CHECK-INST: uqsub z0.d, z0.d, #0
 // CHECK-ENCODING: [0x00,0xc0,0xe7,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 c0 e7 25 <unknown>
+// CHECK-UNKNOWN: 25e7c000 <unknown>
 
 uqsub     z0.d, z0.d, #0, lsl #8
 // CHECK-INST: uqsub z0.d, z0.d, #0, lsl #8
 // CHECK-ENCODING: [0x00,0xe0,0xe7,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 e0 e7 25 <unknown>
+// CHECK-UNKNOWN: 25e7e000 <unknown>
 
 uqsub     z31.d, z31.d, #255, lsl #8
 // CHECK-INST: uqsub z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe7,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e7 25 <unknown>
+// CHECK-UNKNOWN: 25e7ffff <unknown>
 
 uqsub     z31.d, z31.d, #65280
 // CHECK-INST: uqsub z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe7,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e7 25 <unknown>
+// CHECK-UNKNOWN: 25e7ffff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -126,10 +126,10 @@ movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uqsub     z31.d, z31.d, #65280
 // CHECK-INST: uqsub	z31.d, z31.d, #65280
 // CHECK-ENCODING: [0xff,0xff,0xe7,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff ff e7 25 <unknown>
+// CHECK-UNKNOWN: 25e7ffff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uunpkhi.s b/llvm/test/MC/AArch64/SVE/uunpkhi.s
index 84c316ef943ca..17320985ad5a8 100644
--- a/llvm/test/MC/AArch64/SVE/uunpkhi.s
+++ b/llvm/test/MC/AArch64/SVE/uunpkhi.s
@@ -13,16 +13,16 @@ uunpkhi z31.h, z31.b
 // CHECK-INST: uunpkhi	z31.h, z31.b
 // CHECK-ENCODING: [0xff,0x3b,0x73,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b 73 05 <unknown>
+// CHECK-UNKNOWN: 05733bff <unknown>
 
 uunpkhi z31.s, z31.h
 // CHECK-INST: uunpkhi	z31.s, z31.h
 // CHECK-ENCODING: [0xff,0x3b,0xb3,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b b3 05 <unknown>
+// CHECK-UNKNOWN: 05b33bff <unknown>
 
 uunpkhi z31.d, z31.s
 // CHECK-INST: uunpkhi	z31.d, z31.s
 // CHECK-ENCODING: [0xff,0x3b,0xf3,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b f3 05 <unknown>
+// CHECK-UNKNOWN: 05f33bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uunpklo.s b/llvm/test/MC/AArch64/SVE/uunpklo.s
index 13ebe716e6406..debcd826522e9 100644
--- a/llvm/test/MC/AArch64/SVE/uunpklo.s
+++ b/llvm/test/MC/AArch64/SVE/uunpklo.s
@@ -13,16 +13,16 @@ uunpklo z31.h, z31.b
 // CHECK-INST: uunpklo	z31.h, z31.b
 // CHECK-ENCODING: [0xff,0x3b,0x72,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b 72 05 <unknown>
+// CHECK-UNKNOWN: 05723bff <unknown>
 
 uunpklo z31.s, z31.h
 // CHECK-INST: uunpklo	z31.s, z31.h
 // CHECK-ENCODING: [0xff,0x3b,0xb2,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b b2 05 <unknown>
+// CHECK-UNKNOWN: 05b23bff <unknown>
 
 uunpklo z31.d, z31.s
 // CHECK-INST: uunpklo	z31.d, z31.s
 // CHECK-ENCODING: [0xff,0x3b,0xf2,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 3b f2 05 <unknown>
+// CHECK-UNKNOWN: 05f23bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uxtb.s b/llvm/test/MC/AArch64/SVE/uxtb.s
index bd2dee947f3e4..7141b0a549be3 100644
--- a/llvm/test/MC/AArch64/SVE/uxtb.s
+++ b/llvm/test/MC/AArch64/SVE/uxtb.s
@@ -13,37 +13,37 @@ uxtb    z0.h, p0/m, z0.h
 // CHECK-INST: uxtb    z0.h, p0/m, z0.h
 // CHECK-ENCODING: [0x00,0xa0,0x51,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 51 04 <unknown>
+// CHECK-UNKNOWN: 0451a000 <unknown>
 
 uxtb    z0.s, p0/m, z0.s
 // CHECK-INST: uxtb    z0.s, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x91,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 91 04 <unknown>
+// CHECK-UNKNOWN: 0491a000 <unknown>
 
 uxtb    z0.d, p0/m, z0.d
 // CHECK-INST: uxtb    z0.d, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d1 04 <unknown>
+// CHECK-UNKNOWN: 04d1a000 <unknown>
 
 uxtb    z31.h, p7/m, z31.h
 // CHECK-INST: uxtb    z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x51,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 51 04 <unknown>
+// CHECK-UNKNOWN: 0451bfff <unknown>
 
 uxtb    z31.s, p7/m, z31.s
 // CHECK-INST: uxtb    z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x91,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 91 04 <unknown>
+// CHECK-UNKNOWN: 0491bfff <unknown>
 
 uxtb    z31.d, p7/m, z31.d
 // CHECK-INST: uxtb    z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xd1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf d1 04 <unknown>
+// CHECK-UNKNOWN: 04d1bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -53,22 +53,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 uxtb    z4.d, p7/m, z31.d
 // CHECK-INST: uxtb	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d1 04 <unknown>
+// CHECK-UNKNOWN: 04d1bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 uxtb    z4.d, p7/m, z31.d
 // CHECK-INST: uxtb	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd1,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d1 04 <unknown>
+// CHECK-UNKNOWN: 04d1bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uxth.s b/llvm/test/MC/AArch64/SVE/uxth.s
index 5e0b3d6248d9a..afe981b2a75e4 100644
--- a/llvm/test/MC/AArch64/SVE/uxth.s
+++ b/llvm/test/MC/AArch64/SVE/uxth.s
@@ -13,25 +13,25 @@ uxth    z0.s, p0/m, z0.s
 // CHECK-INST: uxth    z0.s, p0/m, z0.s
 // CHECK-ENCODING: [0x00,0xa0,0x93,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 93 04 <unknown>
+// CHECK-UNKNOWN: 0493a000 <unknown>
 
 uxth    z0.d, p0/m, z0.d
 // CHECK-INST: uxth    z0.d, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d3 04 <unknown>
+// CHECK-UNKNOWN: 04d3a000 <unknown>
 
 uxth    z31.s, p7/m, z31.s
 // CHECK-INST: uxth    z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x93,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf 93 04 <unknown>
+// CHECK-UNKNOWN: 0493bfff <unknown>
 
 uxth    z31.d, p7/m, z31.d
 // CHECK-INST: uxth    z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xd3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf d3 04 <unknown>
+// CHECK-UNKNOWN: 04d3bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 uxth    z4.d, p7/m, z31.d
 // CHECK-INST: uxth	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d3 04 <unknown>
+// CHECK-UNKNOWN: 04d3bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 uxth    z4.d, p7/m, z31.d
 // CHECK-INST: uxth	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd3,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d3 04 <unknown>
+// CHECK-UNKNOWN: 04d3bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uxtw.s b/llvm/test/MC/AArch64/SVE/uxtw.s
index fa5565db323de..27f4c740d004e 100644
--- a/llvm/test/MC/AArch64/SVE/uxtw.s
+++ b/llvm/test/MC/AArch64/SVE/uxtw.s
@@ -13,13 +13,13 @@ uxtw    z0.d, p0/m, z0.d
 // CHECK-INST: uxtw    z0.d, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0xd5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 a0 d5 04 <unknown>
+// CHECK-UNKNOWN: 04d5a000 <unknown>
 
 uxtw    z31.d, p7/m, z31.d
 // CHECK-INST: uxtw    z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xd5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bf d5 04 <unknown>
+// CHECK-UNKNOWN: 04d5bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -29,22 +29,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 uxtw    z4.d, p7/m, z31.d
 // CHECK-INST: uxtw	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d5 04 <unknown>
+// CHECK-UNKNOWN: 04d5bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 uxtw    z4.d, p7/m, z31.d
 // CHECK-INST: uxtw	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0xd5,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e4 bf d5 04 <unknown>
+// CHECK-UNKNOWN: 04d5bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uzp1.s b/llvm/test/MC/AArch64/SVE/uzp1.s
index 11d35d1186ef9..15bbf06aba5cf 100644
--- a/llvm/test/MC/AArch64/SVE/uzp1.s
+++ b/llvm/test/MC/AArch64/SVE/uzp1.s
@@ -13,46 +13,46 @@ uzp1    z31.b, z31.b, z31.b
 // CHECK-INST: uzp1	z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x6b,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 6b 3f 05 <unknown>
+// CHECK-UNKNOWN: 053f6bff <unknown>
 
 uzp1    z31.h, z31.h, z31.h
 // CHECK-INST: uzp1	z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x6b,0x7f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 6b 7f 05 <unknown>
+// CHECK-UNKNOWN: 057f6bff <unknown>
 
 uzp1    z31.s, z31.s, z31.s
 // CHECK-INST: uzp1	z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x6b,0xbf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 6b bf 05 <unknown>
+// CHECK-UNKNOWN: 05bf6bff <unknown>
 
 uzp1    z31.d, z31.d, z31.d
 // CHECK-INST: uzp1	z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x6b,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 6b ff 05 <unknown>
+// CHECK-UNKNOWN: 05ff6bff <unknown>
 
 uzp1    p15.b, p15.b, p15.b
 // CHECK-INST: uzp1	p15.b, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x49,0x2f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 49 2f 05 <unknown>
+// CHECK-UNKNOWN: 052f49ef <unknown>
 
 uzp1    p15.s, p15.s, p15.s
 // CHECK-INST: uzp1	p15.s, p15.s, p15.s
 // CHECK-ENCODING: [0xef,0x49,0xaf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 49 af 05 <unknown>
+// CHECK-UNKNOWN: 05af49ef <unknown>
 
 uzp1    p15.h, p15.h, p15.h
 // CHECK-INST: uzp1	p15.h, p15.h, p15.h
 // CHECK-ENCODING: [0xef,0x49,0x6f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 49 6f 05 <unknown>
+// CHECK-UNKNOWN: 056f49ef <unknown>
 
 uzp1    p15.d, p15.d, p15.d
 // CHECK-INST: uzp1	p15.d, p15.d, p15.d
 // CHECK-ENCODING: [0xef,0x49,0xef,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 49 ef 05 <unknown>
+// CHECK-UNKNOWN: 05ef49ef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/uzp2.s b/llvm/test/MC/AArch64/SVE/uzp2.s
index 7b0bed67c608a..ef7b095cec045 100644
--- a/llvm/test/MC/AArch64/SVE/uzp2.s
+++ b/llvm/test/MC/AArch64/SVE/uzp2.s
@@ -13,46 +13,46 @@ uzp2    z31.b, z31.b, z31.b
 // CHECK-INST: uzp2	z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x6f,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 6f 3f 05 <unknown>
+// CHECK-UNKNOWN: 053f6fff <unknown>
 
 uzp2    z31.h, z31.h, z31.h
 // CHECK-INST: uzp2	z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x6f,0x7f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 6f 7f 05 <unknown>
+// CHECK-UNKNOWN: 057f6fff <unknown>
 
 uzp2    z31.s, z31.s, z31.s
 // CHECK-INST: uzp2	z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x6f,0xbf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 6f bf 05 <unknown>
+// CHECK-UNKNOWN: 05bf6fff <unknown>
 
 uzp2    z31.d, z31.d, z31.d
 // CHECK-INST: uzp2	z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x6f,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 6f ff 05 <unknown>
+// CHECK-UNKNOWN: 05ff6fff <unknown>
 
 uzp2    p15.b, p15.b, p15.b
 // CHECK-INST: uzp2	p15.b, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x4d,0x2f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 4d 2f 05 <unknown>
+// CHECK-UNKNOWN: 052f4def <unknown>
 
 uzp2    p15.s, p15.s, p15.s
 // CHECK-INST: uzp2	p15.s, p15.s, p15.s
 // CHECK-ENCODING: [0xef,0x4d,0xaf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 4d af 05 <unknown>
+// CHECK-UNKNOWN: 05af4def <unknown>
 
 uzp2    p15.h, p15.h, p15.h
 // CHECK-INST: uzp2	p15.h, p15.h, p15.h
 // CHECK-ENCODING: [0xef,0x4d,0x6f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 4d 6f 05 <unknown>
+// CHECK-UNKNOWN: 056f4def <unknown>
 
 uzp2    p15.d, p15.d, p15.d
 // CHECK-INST: uzp2	p15.d, p15.d, p15.d
 // CHECK-ENCODING: [0xef,0x4d,0xef,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 4d ef 05 <unknown>
+// CHECK-UNKNOWN: 05ef4def <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/whilele.s b/llvm/test/MC/AArch64/SVE/whilele.s
index cb068a8ffd81e..b7dbb7a72f83d 100644
--- a/llvm/test/MC/AArch64/SVE/whilele.s
+++ b/llvm/test/MC/AArch64/SVE/whilele.s
@@ -13,58 +13,58 @@ whilele  p15.b, xzr, x0
 // CHECK-INST: whilele	p15.b, xzr, x0
 // CHECK-ENCODING: [0xff,0x17,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 17 20 25 <unknown>
+// CHECK-UNKNOWN: 252017ff <unknown>
 
 whilele  p15.b, x0, xzr
 // CHECK-INST: whilele	p15.b, x0, xzr
 // CHECK-ENCODING: [0x1f,0x14,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 14 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f141f <unknown>
 
 whilele  p15.b, wzr, w0
 // CHECK-INST: whilele	p15.b, wzr, w0
 // CHECK-ENCODING: [0xff,0x07,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 07 20 25 <unknown>
+// CHECK-UNKNOWN: 252007ff <unknown>
 
 whilele  p15.b, w0, wzr
 // CHECK-INST: whilele	p15.b, w0, wzr
 // CHECK-ENCODING: [0x1f,0x04,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 04 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f041f <unknown>
 
 whilele  p15.h, x0, xzr
 // CHECK-INST: whilele	p15.h, x0, xzr
 // CHECK-ENCODING: [0x1f,0x14,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 14 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f141f <unknown>
 
 whilele  p15.h, w0, wzr
 // CHECK-INST: whilele	p15.h, w0, wzr
 // CHECK-ENCODING: [0x1f,0x04,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 04 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f041f <unknown>
 
 whilele  p15.s, x0, xzr
 // CHECK-INST: whilele	p15.s, x0, xzr
 // CHECK-ENCODING: [0x1f,0x14,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 14 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf141f <unknown>
 
 whilele  p15.s, w0, wzr
 // CHECK-INST: whilele	p15.s, w0, wzr
 // CHECK-ENCODING: [0x1f,0x04,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 04 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf041f <unknown>
 
 whilele  p15.d, w0, wzr
 // CHECK-INST: whilele	p15.d, w0, wzr
 // CHECK-ENCODING: [0x1f,0x04,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 04 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff041f <unknown>
 
 whilele  p15.d, x0, xzr
 // CHECK-INST: whilele	p15.d, x0, xzr
 // CHECK-ENCODING: [0x1f,0x14,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 14 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff141f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/whilelo.s b/llvm/test/MC/AArch64/SVE/whilelo.s
index 3b5fa77e40588..f0e29a108993a 100644
--- a/llvm/test/MC/AArch64/SVE/whilelo.s
+++ b/llvm/test/MC/AArch64/SVE/whilelo.s
@@ -13,58 +13,58 @@ whilelo  p15.b, xzr, x0
 // CHECK-INST: whilelo	p15.b, xzr, x0
 // CHECK-ENCODING: [0xef,0x1f,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 1f 20 25 <unknown>
+// CHECK-UNKNOWN: 25201fef <unknown>
 
 whilelo  p15.b, x0, xzr
 // CHECK-INST: whilelo	p15.b, x0, xzr
 // CHECK-ENCODING: [0x0f,0x1c,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 1c 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f1c0f <unknown>
 
 whilelo  p15.b, wzr, w0
 // CHECK-INST: whilelo	p15.b, wzr, w0
 // CHECK-ENCODING: [0xef,0x0f,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 0f 20 25 <unknown>
+// CHECK-UNKNOWN: 25200fef <unknown>
 
 whilelo  p15.b, w0, wzr
 // CHECK-INST: whilelo	p15.b, w0, wzr
 // CHECK-ENCODING: [0x0f,0x0c,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 0c 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f0c0f <unknown>
 
 whilelo  p15.h, x0, xzr
 // CHECK-INST: whilelo	p15.h, x0, xzr
 // CHECK-ENCODING: [0x0f,0x1c,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 1c 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f1c0f <unknown>
 
 whilelo  p15.h, w0, wzr
 // CHECK-INST: whilelo	p15.h, w0, wzr
 // CHECK-ENCODING: [0x0f,0x0c,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 0c 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f0c0f <unknown>
 
 whilelo  p15.s, x0, xzr
 // CHECK-INST: whilelo	p15.s, x0, xzr
 // CHECK-ENCODING: [0x0f,0x1c,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 1c bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf1c0f <unknown>
 
 whilelo  p15.s, w0, wzr
 // CHECK-INST: whilelo	p15.s, w0, wzr
 // CHECK-ENCODING: [0x0f,0x0c,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 0c bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf0c0f <unknown>
 
 whilelo  p15.d, w0, wzr
 // CHECK-INST: whilelo	p15.d, w0, wzr
 // CHECK-ENCODING: [0x0f,0x0c,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 0c ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff0c0f <unknown>
 
 whilelo  p15.d, x0, xzr
 // CHECK-INST: whilelo	p15.d, x0, xzr
 // CHECK-ENCODING: [0x0f,0x1c,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 1c ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff1c0f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/whilels.s b/llvm/test/MC/AArch64/SVE/whilels.s
index 02f4133429b26..59a40a61091a6 100644
--- a/llvm/test/MC/AArch64/SVE/whilels.s
+++ b/llvm/test/MC/AArch64/SVE/whilels.s
@@ -13,58 +13,58 @@ whilels  p15.b, xzr, x0
 // CHECK-INST: whilels	p15.b, xzr, x0
 // CHECK-ENCODING: [0xff,0x1f,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 1f 20 25 <unknown>
+// CHECK-UNKNOWN: 25201fff <unknown>
 
 whilels  p15.b, x0, xzr
 // CHECK-INST: whilels	p15.b, x0, xzr
 // CHECK-ENCODING: [0x1f,0x1c,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 1c 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f1c1f <unknown>
 
 whilels  p15.b, wzr, w0
 // CHECK-INST: whilels	p15.b, wzr, w0
 // CHECK-ENCODING: [0xff,0x0f,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 0f 20 25 <unknown>
+// CHECK-UNKNOWN: 25200fff <unknown>
 
 whilels  p15.b, w0, wzr
 // CHECK-INST: whilels	p15.b, w0, wzr
 // CHECK-ENCODING: [0x1f,0x0c,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 0c 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f0c1f <unknown>
 
 whilels  p15.h, x0, xzr
 // CHECK-INST: whilels	p15.h, x0, xzr
 // CHECK-ENCODING: [0x1f,0x1c,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 1c 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f1c1f <unknown>
 
 whilels  p15.h, w0, wzr
 // CHECK-INST: whilels	p15.h, w0, wzr
 // CHECK-ENCODING: [0x1f,0x0c,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 0c 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f0c1f <unknown>
 
 whilels  p15.s, x0, xzr
 // CHECK-INST: whilels	p15.s, x0, xzr
 // CHECK-ENCODING: [0x1f,0x1c,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 1c bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf1c1f <unknown>
 
 whilels  p15.s, w0, wzr
 // CHECK-INST: whilels	p15.s, w0, wzr
 // CHECK-ENCODING: [0x1f,0x0c,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 0c bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf0c1f <unknown>
 
 whilels  p15.d, w0, wzr
 // CHECK-INST: whilels	p15.d, w0, wzr
 // CHECK-ENCODING: [0x1f,0x0c,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 0c ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff0c1f <unknown>
 
 whilels  p15.d, x0, xzr
 // CHECK-INST: whilels	p15.d, x0, xzr
 // CHECK-ENCODING: [0x1f,0x1c,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 1f 1c ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff1c1f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/whilelt.s b/llvm/test/MC/AArch64/SVE/whilelt.s
index 0f85431370ef5..0bac347a5979a 100644
--- a/llvm/test/MC/AArch64/SVE/whilelt.s
+++ b/llvm/test/MC/AArch64/SVE/whilelt.s
@@ -13,58 +13,58 @@ whilelt  p15.b, xzr, x0
 // CHECK-INST: whilelt	p15.b, xzr, x0
 // CHECK-ENCODING: [0xef,0x17,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 17 20 25 <unknown>
+// CHECK-UNKNOWN: 252017ef <unknown>
 
 whilelt  p15.b, x0, xzr
 // CHECK-INST: whilelt	p15.b, x0, xzr
 // CHECK-ENCODING: [0x0f,0x14,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 14 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f140f <unknown>
 
 whilelt  p15.b, wzr, w0
 // CHECK-INST: whilelt	p15.b, wzr, w0
 // CHECK-ENCODING: [0xef,0x07,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 07 20 25 <unknown>
+// CHECK-UNKNOWN: 252007ef <unknown>
 
 whilelt  p15.b, w0, wzr
 // CHECK-INST: whilelt	p15.b, w0, wzr
 // CHECK-ENCODING: [0x0f,0x04,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 04 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f040f <unknown>
 
 whilelt  p15.h, x0, xzr
 // CHECK-INST: whilelt	p15.h, x0, xzr
 // CHECK-ENCODING: [0x0f,0x14,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 14 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f140f <unknown>
 
 whilelt  p15.h, w0, wzr
 // CHECK-INST: whilelt	p15.h, w0, wzr
 // CHECK-ENCODING: [0x0f,0x04,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 04 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f040f <unknown>
 
 whilelt  p15.s, x0, xzr
 // CHECK-INST: whilelt	p15.s, x0, xzr
 // CHECK-ENCODING: [0x0f,0x14,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 14 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf140f <unknown>
 
 whilelt  p15.s, w0, wzr
 // CHECK-INST: whilelt	p15.s, w0, wzr
 // CHECK-ENCODING: [0x0f,0x04,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 04 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf040f <unknown>
 
 whilelt  p15.d, w0, wzr
 // CHECK-INST: whilelt	p15.d, w0, wzr
 // CHECK-ENCODING: [0x0f,0x04,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 04 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff040f <unknown>
 
 whilelt  p15.d, x0, xzr
 // CHECK-INST: whilelt	p15.d, x0, xzr
 // CHECK-ENCODING: [0x0f,0x14,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 0f 14 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff140f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/wrffr.s b/llvm/test/MC/AArch64/SVE/wrffr.s
index b383ace863031..1c33b1c11cedc 100644
--- a/llvm/test/MC/AArch64/SVE/wrffr.s
+++ b/llvm/test/MC/AArch64/SVE/wrffr.s
@@ -13,10 +13,10 @@ wrffr   p0.b
 // CHECK-INST: wrffr   p0.b
 // CHECK-ENCODING: [0x00,0x90,0x28,0x25]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: 00 90 28 25 <unknown>
+// CHECK-UNKNOWN: 25289000 <unknown>
 
 wrffr   p15.b
 // CHECK-INST: wrffr   p15.b
 // CHECK-ENCODING: [0xe0,0x91,0x28,0x25]
 // CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: e0 91 28 25 <unknown>
+// CHECK-UNKNOWN: 252891e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/zip1.s b/llvm/test/MC/AArch64/SVE/zip1.s
index a9bc1057cec95..581cf8b6b5046 100644
--- a/llvm/test/MC/AArch64/SVE/zip1.s
+++ b/llvm/test/MC/AArch64/SVE/zip1.s
@@ -13,94 +13,94 @@ zip1    z0.b, z0.b, z0.b
 // CHECK-INST: zip1    z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x60,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 20 05 <unknown>
+// CHECK-UNKNOWN: 05206000 <unknown>
 
 zip1    z0.h, z0.h, z0.h
 // CHECK-INST: zip1    z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x60,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 60 05 <unknown>
+// CHECK-UNKNOWN: 05606000 <unknown>
 
 zip1    z0.s, z0.s, z0.s
 // CHECK-INST: zip1    z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x60,0xa0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 a0 05 <unknown>
+// CHECK-UNKNOWN: 05a06000 <unknown>
 
 zip1    z0.d, z0.d, z0.d
 // CHECK-INST: zip1    z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x60,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 60 e0 05 <unknown>
+// CHECK-UNKNOWN: 05e06000 <unknown>
 
 zip1    z31.b, z31.b, z31.b
 // CHECK-INST: zip1    z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x63,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 63 3f 05 <unknown>
+// CHECK-UNKNOWN: 053f63ff <unknown>
 
 zip1    z31.h, z31.h, z31.h
 // CHECK-INST: zip1    z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x63,0x7f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 63 7f 05 <unknown>
+// CHECK-UNKNOWN: 057f63ff <unknown>
 
 zip1    z31.s, z31.s, z31.s
 // CHECK-INST: zip1    z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x63,0xbf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 63 bf 05 <unknown>
+// CHECK-UNKNOWN: 05bf63ff <unknown>
 
 zip1    z31.d, z31.d, z31.d
 // CHECK-INST: zip1    z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x63,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 63 ff 05 <unknown>
+// CHECK-UNKNOWN: 05ff63ff <unknown>
 
 zip1    p0.b, p0.b, p0.b
 // CHECK-INST: zip1    p0.b, p0.b, p0.b
 // CHECK-ENCODING: [0x00,0x40,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 20 05 <unknown>
+// CHECK-UNKNOWN: 05204000 <unknown>
 
 zip1    p0.h, p0.h, p0.h
 // CHECK-INST: zip1    p0.h, p0.h, p0.h
 // CHECK-ENCODING: [0x00,0x40,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 60 05 <unknown>
+// CHECK-UNKNOWN: 05604000 <unknown>
 
 zip1    p0.s, p0.s, p0.s
 // CHECK-INST: zip1    p0.s, p0.s, p0.s
 // CHECK-ENCODING: [0x00,0x40,0xa0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 a0 05 <unknown>
+// CHECK-UNKNOWN: 05a04000 <unknown>
 
 zip1    p0.d, p0.d, p0.d
 // CHECK-INST: zip1    p0.d, p0.d, p0.d
 // CHECK-ENCODING: [0x00,0x40,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 40 e0 05 <unknown>
+// CHECK-UNKNOWN: 05e04000 <unknown>
 
 zip1    p15.b, p15.b, p15.b
 // CHECK-INST: zip1    p15.b, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x41,0x2f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 41 2f 05 <unknown>
+// CHECK-UNKNOWN: 052f41ef <unknown>
 
 zip1    p15.s, p15.s, p15.s
 // CHECK-INST: zip1    p15.s, p15.s, p15.s
 // CHECK-ENCODING: [0xef,0x41,0xaf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 41 af 05 <unknown>
+// CHECK-UNKNOWN: 05af41ef <unknown>
 
 zip1    p15.h, p15.h, p15.h
 // CHECK-INST: zip1    p15.h, p15.h, p15.h
 // CHECK-ENCODING: [0xef,0x41,0x6f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 41 6f 05 <unknown>
+// CHECK-UNKNOWN: 056f41ef <unknown>
 
 zip1    p15.d, p15.d, p15.d
 // CHECK-INST: zip1    p15.d, p15.d, p15.d
 // CHECK-ENCODING: [0xef,0x41,0xef,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 41 ef 05 <unknown>
+// CHECK-UNKNOWN: 05ef41ef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE/zip2.s b/llvm/test/MC/AArch64/SVE/zip2.s
index 5524d54abeaa2..e209b3ec027e7 100644
--- a/llvm/test/MC/AArch64/SVE/zip2.s
+++ b/llvm/test/MC/AArch64/SVE/zip2.s
@@ -13,94 +13,94 @@ zip2    z0.b, z0.b, z0.b
 // CHECK-INST: zip2    z0.b, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x64,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 64 20 05 <unknown>
+// CHECK-UNKNOWN: 05206400 <unknown>
 
 zip2    z0.h, z0.h, z0.h
 // CHECK-INST: zip2    z0.h, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x64,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 64 60 05 <unknown>
+// CHECK-UNKNOWN: 05606400 <unknown>
 
 zip2    z0.s, z0.s, z0.s
 // CHECK-INST: zip2    z0.s, z0.s, z0.s
 // CHECK-ENCODING: [0x00,0x64,0xa0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 64 a0 05 <unknown>
+// CHECK-UNKNOWN: 05a06400 <unknown>
 
 zip2    z0.d, z0.d, z0.d
 // CHECK-INST: zip2    z0.d, z0.d, z0.d
 // CHECK-ENCODING: [0x00,0x64,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 64 e0 05 <unknown>
+// CHECK-UNKNOWN: 05e06400 <unknown>
 
 zip2    z31.b, z31.b, z31.b
 // CHECK-INST: zip2    z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x67,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 67 3f 05 <unknown>
+// CHECK-UNKNOWN: 053f67ff <unknown>
 
 zip2    z31.h, z31.h, z31.h
 // CHECK-INST: zip2    z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x67,0x7f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 67 7f 05 <unknown>
+// CHECK-UNKNOWN: 057f67ff <unknown>
 
 zip2    z31.s, z31.s, z31.s
 // CHECK-INST: zip2    z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x67,0xbf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 67 bf 05 <unknown>
+// CHECK-UNKNOWN: 05bf67ff <unknown>
 
 zip2    z31.d, z31.d, z31.d
 // CHECK-INST: zip2    z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x67,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff 67 ff 05 <unknown>
+// CHECK-UNKNOWN: 05ff67ff <unknown>
 
 zip2    p0.b, p0.b, p0.b
 // CHECK-INST: zip2    p0.b, p0.b, p0.b
 // CHECK-ENCODING: [0x00,0x44,0x20,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 44 20 05 <unknown>
+// CHECK-UNKNOWN: 05204400 <unknown>
 
 zip2    p0.h, p0.h, p0.h
 // CHECK-INST: zip2    p0.h, p0.h, p0.h
 // CHECK-ENCODING: [0x00,0x44,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 44 60 05 <unknown>
+// CHECK-UNKNOWN: 05604400 <unknown>
 
 zip2    p0.s, p0.s, p0.s
 // CHECK-INST: zip2    p0.s, p0.s, p0.s
 // CHECK-ENCODING: [0x00,0x44,0xa0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 44 a0 05 <unknown>
+// CHECK-UNKNOWN: 05a04400 <unknown>
 
 zip2    p0.d, p0.d, p0.d
 // CHECK-INST: zip2    p0.d, p0.d, p0.d
 // CHECK-ENCODING: [0x00,0x44,0xe0,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 00 44 e0 05 <unknown>
+// CHECK-UNKNOWN: 05e04400 <unknown>
 
 zip2    p15.b, p15.b, p15.b
 // CHECK-INST: zip2    p15.b, p15.b, p15.b
 // CHECK-ENCODING: [0xef,0x45,0x2f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 45 2f 05 <unknown>
+// CHECK-UNKNOWN: 052f45ef <unknown>
 
 zip2    p15.h, p15.h, p15.h
 // CHECK-INST: zip2    p15.h, p15.h, p15.h
 // CHECK-ENCODING: [0xef,0x45,0x6f,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 45 6f 05 <unknown>
+// CHECK-UNKNOWN: 056f45ef <unknown>
 
 zip2    p15.s, p15.s, p15.s
 // CHECK-INST: zip2    p15.s, p15.s, p15.s
 // CHECK-ENCODING: [0xef,0x45,0xaf,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 45 af 05 <unknown>
+// CHECK-UNKNOWN: 05af45ef <unknown>
 
 zip2    p15.d, p15.d, p15.d
 // CHECK-INST: zip2    p15.d, p15.d, p15.d
 // CHECK-ENCODING: [0xef,0x45,0xef,0x05]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ef 45 ef 05 <unknown>
+// CHECK-UNKNOWN: 05ef45ef <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/adclb.s b/llvm/test/MC/AArch64/SVE2/adclb.s
index 80a225a55725b..80462dcc06385 100644
--- a/llvm/test/MC/AArch64/SVE2/adclb.s
+++ b/llvm/test/MC/AArch64/SVE2/adclb.s
@@ -13,13 +13,13 @@ adclb z0.s, z1.s, z31.s
 // CHECK-INST: adclb z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xd0,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d0 1f 45 <unknown>
+// CHECK-UNKNOWN: 451fd020 <unknown>
 
 adclb z0.d, z1.d, z31.d
 // CHECK-INST: adclb z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xd0,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d0 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fd020 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -29,10 +29,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 adclb z0.d, z1.d, z31.d
 // CHECK-INST: adclb z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xd0,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d0 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fd020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/adclt.s b/llvm/test/MC/AArch64/SVE2/adclt.s
index 468f4d55cf1af..075f0294688d7 100644
--- a/llvm/test/MC/AArch64/SVE2/adclt.s
+++ b/llvm/test/MC/AArch64/SVE2/adclt.s
@@ -13,13 +13,13 @@ adclt z0.s, z1.s, z31.s
 // CHECK-INST: adclt z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xd4,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d4 1f 45 <unknown>
+// CHECK-UNKNOWN: 451fd420 <unknown>
 
 adclt z0.d, z1.d, z31.d
 // CHECK-INST: adclt z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xd4,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d4 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fd420 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -29,10 +29,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 adclt z0.d, z1.d, z31.d
 // CHECK-INST: adclt z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xd4,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d4 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fd420 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/addhnb.s b/llvm/test/MC/AArch64/SVE2/addhnb.s
index a994f94b2fa37..c4b40eb6a6de4 100644
--- a/llvm/test/MC/AArch64/SVE2/addhnb.s
+++ b/llvm/test/MC/AArch64/SVE2/addhnb.s
@@ -14,16 +14,16 @@ addhnb z0.b, z1.h, z31.h
 // CHECK-INST: addhnb	z0.b, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x60,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 60 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f6020 <unknown>
 
 addhnb z0.h, z1.s, z31.s
 // CHECK-INST: addhnb	z0.h, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x60,0xbf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 60 bf 45 <unknown>
+// CHECK-UNKNOWN: 45bf6020 <unknown>
 
 addhnb z0.s, z1.d, z31.d
 // CHECK-INST: addhnb	z0.s, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x60,0xff,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 60 ff 45 <unknown>
+// CHECK-UNKNOWN: 45ff6020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/addhnt.s b/llvm/test/MC/AArch64/SVE2/addhnt.s
index 0dbeb93b9cc20..0eee22d0ed9a6 100644
--- a/llvm/test/MC/AArch64/SVE2/addhnt.s
+++ b/llvm/test/MC/AArch64/SVE2/addhnt.s
@@ -14,16 +14,16 @@ addhnt z0.b, z1.h, z31.h
 // CHECK-INST: addhnt	z0.b, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x64,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 64 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f6420 <unknown>
 
 addhnt z0.h, z1.s, z31.s
 // CHECK-INST: addhnt	z0.h, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x64,0xbf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 64 bf 45 <unknown>
+// CHECK-UNKNOWN: 45bf6420 <unknown>
 
 addhnt z0.s, z1.d, z31.d
 // CHECK-INST: addhnt	z0.s, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x64,0xff,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 64 ff 45 <unknown>
+// CHECK-UNKNOWN: 45ff6420 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/addp.s b/llvm/test/MC/AArch64/SVE2/addp.s
index e9a9b3f59fc55..55b570fd6bf0e 100644
--- a/llvm/test/MC/AArch64/SVE2/addp.s
+++ b/llvm/test/MC/AArch64/SVE2/addp.s
@@ -13,25 +13,25 @@ addp z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: addp z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0xa0,0x11,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 11 44 <unknown>
+// CHECK-UNKNOWN: 4411a020 <unknown>
 
 addp z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: addp z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0xa0,0x51,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 51 44 <unknown>
+// CHECK-UNKNOWN: 4451a020 <unknown>
 
 addp z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: addp z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0xbf,0x91,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd bf 91 44 <unknown>
+// CHECK-UNKNOWN: 4491bfdd <unknown>
 
 addp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: addp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df bf d1 44 <unknown>
+// CHECK-UNKNOWN: 44d1bfdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 addp z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: addp z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xa3,0xd1,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df a3 d1 44 <unknown>
+// CHECK-UNKNOWN: 44d1a3df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 addp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: addp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xbf,0xd1,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df bf d1 44 <unknown>
+// CHECK-UNKNOWN: 44d1bfdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/aesd.s b/llvm/test/MC/AArch64/SVE2/aesd.s
index c5c71741f195f..44eb9b68fd44e 100644
--- a/llvm/test/MC/AArch64/SVE2/aesd.s
+++ b/llvm/test/MC/AArch64/SVE2/aesd.s
@@ -14,4 +14,4 @@ aesd z0.b, z0.b, z31.b
 // CHECK-INST: aesd z0.b, z0.b, z31.b
 // CHECK-ENCODING: [0xe0,0xe7,0x22,0x45]
 // CHECK-ERROR: instruction requires: sve2-aes
-// CHECK-UNKNOWN: e0 e7 22 45 <unknown>
+// CHECK-UNKNOWN: 4522e7e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/aese.s b/llvm/test/MC/AArch64/SVE2/aese.s
index 28829205a1ed1..e64f2137ad39a 100644
--- a/llvm/test/MC/AArch64/SVE2/aese.s
+++ b/llvm/test/MC/AArch64/SVE2/aese.s
@@ -14,4 +14,4 @@ aese z0.b, z0.b, z31.b
 // CHECK-INST: aese z0.b, z0.b, z31.b
 // CHECK-ENCODING: [0xe0,0xe3,0x22,0x45]
 // CHECK-ERROR: instruction requires: sve2-aes
-// CHECK-UNKNOWN: e0 e3 22 45 <unknown>
+// CHECK-UNKNOWN: 4522e3e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/aesimc.s b/llvm/test/MC/AArch64/SVE2/aesimc.s
index 1a9a1893e22d5..c868ed0badf49 100644
--- a/llvm/test/MC/AArch64/SVE2/aesimc.s
+++ b/llvm/test/MC/AArch64/SVE2/aesimc.s
@@ -14,10 +14,10 @@ aesimc z0.b, z0.b
 // CHECK-INST: aesimc z0.b, z0.b
 // CHECK-ENCODING: [0x00,0xe4,0x20,0x45]
 // CHECK-ERROR: instruction requires: sve2-aes
-// CHECK-UNKNOWN: 00 e4 20 45 <unknown>
+// CHECK-UNKNOWN: 4520e400 <unknown>
 
 aesimc z31.b, z31.b
 // CHECK-INST: aesimc z31.b, z31.b
 // CHECK-ENCODING: [0x1f,0xe4,0x20,0x45]
 // CHECK-ERROR: instruction requires: sve2-aes
-// CHECK-UNKNOWN: 1f e4 20 45 <unknown>
+// CHECK-UNKNOWN: 4520e41f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/aesmc.s b/llvm/test/MC/AArch64/SVE2/aesmc.s
index f172426970b03..e158d2b1e0b56 100644
--- a/llvm/test/MC/AArch64/SVE2/aesmc.s
+++ b/llvm/test/MC/AArch64/SVE2/aesmc.s
@@ -14,10 +14,10 @@ aesmc z0.b, z0.b
 // CHECK-INST: aesmc z0.b, z0.b
 // CHECK-ENCODING: [0x00,0xe0,0x20,0x45]
 // CHECK-ERROR: instruction requires: sve2-aes
-// CHECK-UNKNOWN: 00 e0 20 45 <unknown>
+// CHECK-UNKNOWN: 4520e000 <unknown>
 
 aesmc z31.b, z31.b
 // CHECK-INST: aesmc z31.b, z31.b
 // CHECK-ENCODING: [0x1f,0xe0,0x20,0x45]
 // CHECK-ERROR: instruction requires: sve2-aes
-// CHECK-UNKNOWN: 1f e0 20 45 <unknown>
+// CHECK-UNKNOWN: 4520e01f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/bcax.s b/llvm/test/MC/AArch64/SVE2/bcax.s
index e504d924ce062..0f44d65d5eaaa 100644
--- a/llvm/test/MC/AArch64/SVE2/bcax.s
+++ b/llvm/test/MC/AArch64/SVE2/bcax.s
@@ -13,7 +13,7 @@ bcax z29.d, z29.d, z30.d, z31.d
 // CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d
 // CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fd 3b 7e 04 <unknown>
+// CHECK-UNKNOWN: 047e3bfd <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -23,19 +23,19 @@ bcax z29.b, z29.b, z30.b, z31.b
 // CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d
 // CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fd 3b 7e 04 <unknown>
+// CHECK-UNKNOWN: 047e3bfd <unknown>
 
 bcax z29.h, z29.h, z30.h, z31.h
 // CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d
 // CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fd 3b 7e 04 <unknown>
+// CHECK-UNKNOWN: 047e3bfd <unknown>
 
 bcax z29.s, z29.s, z30.s, z31.s
 // CHECK-INST: bcax z29.d, z29.d, z30.d, z31.d
 // CHECK-ENCODING: [0xfd,0x3b,0x7e,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fd 3b 7e 04 <unknown>
+// CHECK-UNKNOWN: 047e3bfd <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -45,10 +45,10 @@ movprfx z31, z7
 // CHECK-INST: movprfx z31, z7
 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcff <unknown>
 
 bcax z31.d, z31.d, z30.d, z29.d
 // CHECK-INST: bcax z31.d, z31.d, z30.d, z29.d
 // CHECK-ENCODING: [0xbf,0x3b,0x7e,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: bf 3b 7e 04 <unknown>
+// CHECK-UNKNOWN: 047e3bbf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/bdep.s b/llvm/test/MC/AArch64/SVE2/bdep.s
index f7433fbdc22f7..a6ef95d9f2619 100644
--- a/llvm/test/MC/AArch64/SVE2/bdep.s
+++ b/llvm/test/MC/AArch64/SVE2/bdep.s
@@ -13,22 +13,22 @@ bdep z0.b, z1.b, z31.b
 // CHECK-INST: bdep z0.b, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0xb4,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2-bitperm
-// CHECK-UNKNOWN: 20 b4 1f 45 <unknown>
+// CHECK-UNKNOWN: 451fb420 <unknown>
 
 bdep z0.h, z1.h, z31.h
 // CHECK-INST: bdep z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0xb4,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2-bitperm
-// CHECK-UNKNOWN: 20 b4 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fb420 <unknown>
 
 bdep z0.s, z1.s, z31.s
 // CHECK-INST: bdep z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xb4,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2-bitperm
-// CHECK-UNKNOWN: 20 b4 9f 45 <unknown>
+// CHECK-UNKNOWN: 459fb420 <unknown>
 
 bdep z0.d, z1.d, z31.d
 // CHECK-INST: bdep z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xb4,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2-bitperm
-// CHECK-UNKNOWN: 20 b4 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfb420 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/bext.s b/llvm/test/MC/AArch64/SVE2/bext.s
index 7565cea9e5839..43272205ab897 100644
--- a/llvm/test/MC/AArch64/SVE2/bext.s
+++ b/llvm/test/MC/AArch64/SVE2/bext.s
@@ -13,22 +13,22 @@ bext z0.b, z1.b, z31.b
 // CHECK-INST: bext z0.b, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0xb0,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2-bitperm
-// CHECK-UNKNOWN: 20 b0 1f 45 <unknown>
+// CHECK-UNKNOWN: 451fb020 <unknown>
 
 bext z0.h, z1.h, z31.h
 // CHECK-INST: bext z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0xb0,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2-bitperm
-// CHECK-UNKNOWN: 20 b0 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fb020 <unknown>
 
 bext z0.s, z1.s, z31.s
 // CHECK-INST: bext z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xb0,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2-bitperm
-// CHECK-UNKNOWN: 20 b0 9f 45 <unknown>
+// CHECK-UNKNOWN: 459fb020 <unknown>
 
 bext z0.d, z1.d, z31.d
 // CHECK-INST: bext z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xb0,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2-bitperm
-// CHECK-UNKNOWN: 20 b0 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfb020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/bgrp.s b/llvm/test/MC/AArch64/SVE2/bgrp.s
index bf8480698116e..fb96946dc3c53 100644
--- a/llvm/test/MC/AArch64/SVE2/bgrp.s
+++ b/llvm/test/MC/AArch64/SVE2/bgrp.s
@@ -13,22 +13,22 @@ bgrp z0.b, z1.b, z31.b
 // CHECK-INST: bgrp z0.b, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0xb8,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2-bitperm
-// CHECK-UNKNOWN: 20 b8 1f 45 <unknown>
+// CHECK-UNKNOWN: 451fb820 <unknown>
 
 bgrp z0.h, z1.h, z31.h
 // CHECK-INST: bgrp z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0xb8,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2-bitperm
-// CHECK-UNKNOWN: 20 b8 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fb820 <unknown>
 
 bgrp z0.s, z1.s, z31.s
 // CHECK-INST: bgrp z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xb8,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2-bitperm
-// CHECK-UNKNOWN: 20 b8 9f 45 <unknown>
+// CHECK-UNKNOWN: 459fb820 <unknown>
 
 bgrp z0.d, z1.d, z31.d
 // CHECK-INST: bgrp z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xb8,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2-bitperm
-// CHECK-UNKNOWN: 20 b8 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfb820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/bsl.s b/llvm/test/MC/AArch64/SVE2/bsl.s
index 4743ef61c492b..faa23e309374f 100644
--- a/llvm/test/MC/AArch64/SVE2/bsl.s
+++ b/llvm/test/MC/AArch64/SVE2/bsl.s
@@ -13,7 +13,7 @@ bsl z0.d, z0.d, z1.d, z2.d
 // CHECK-INST: bsl z0.d, z0.d, z1.d, z2.d
 // CHECK-ENCODING: [0x40,0x3c,0x21,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 40 3c 21 04 <unknown>
+// CHECK-UNKNOWN: 04213c40 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -23,10 +23,10 @@ movprfx z31, z7
 // CHECK-INST: movprfx z31, z7
 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcff <unknown>
 
 bsl z31.d, z31.d, z30.d, z29.d
 // CHECK-INST: bsl z31.d, z31.d, z30.d, z29.d
 // CHECK-ENCODING: [0xbf,0x3f,0x3e,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: bf 3f 3e 04 <unknown>
+// CHECK-UNKNOWN: 043e3fbf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/bsl1n.s b/llvm/test/MC/AArch64/SVE2/bsl1n.s
index e410f98565d4f..b9359f8792e5d 100644
--- a/llvm/test/MC/AArch64/SVE2/bsl1n.s
+++ b/llvm/test/MC/AArch64/SVE2/bsl1n.s
@@ -13,7 +13,7 @@ bsl1n z0.d, z0.d, z1.d, z2.d
 // CHECK-INST: bsl1n z0.d, z0.d, z1.d, z2.d
 // CHECK-ENCODING: [0x40,0x3c,0x61,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 40 3c 61 04 <unknown>
+// CHECK-UNKNOWN: 04613c40 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -23,10 +23,10 @@ movprfx z31, z7
 // CHECK-INST: movprfx z31, z7
 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcff <unknown>
 
 bsl1n z31.d, z31.d, z30.d, z29.d
 // CHECK-INST: bsl1n z31.d, z31.d, z30.d, z29.d
 // CHECK-ENCODING: [0xbf,0x3f,0x7e,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: bf 3f 7e 04 <unknown>
+// CHECK-UNKNOWN: 047e3fbf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/bsl2n.s b/llvm/test/MC/AArch64/SVE2/bsl2n.s
index bd5ee94e63c48..d22dd5453506e 100644
--- a/llvm/test/MC/AArch64/SVE2/bsl2n.s
+++ b/llvm/test/MC/AArch64/SVE2/bsl2n.s
@@ -13,7 +13,7 @@ bsl2n z0.d, z0.d, z1.d, z2.d
 // CHECK-INST: bsl2n z0.d, z0.d, z1.d, z2.d
 // CHECK-ENCODING: [0x40,0x3c,0xa1,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 40 3c a1 04 <unknown>
+// CHECK-UNKNOWN: 04a13c40 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -23,10 +23,10 @@ movprfx z31, z7
 // CHECK-INST: movprfx z31, z7
 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcff <unknown>
 
 bsl2n z31.d, z31.d, z30.d, z29.d
 // CHECK-INST: bsl2n z31.d, z31.d, z30.d, z29.d
 // CHECK-ENCODING: [0xbf,0x3f,0xbe,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: bf 3f be 04 <unknown>
+// CHECK-UNKNOWN: 04be3fbf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/cadd.s b/llvm/test/MC/AArch64/SVE2/cadd.s
index 8bdbb9f570de2..9884e6289e291 100644
--- a/llvm/test/MC/AArch64/SVE2/cadd.s
+++ b/llvm/test/MC/AArch64/SVE2/cadd.s
@@ -13,49 +13,49 @@ cadd   z0.b, z0.b, z0.b, #90
 // CHECK-INST: cadd   z0.b, z0.b, z0.b, #90
 // CHECK-ENCODING: [0x00,0xd8,0x00,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 d8 00 45 <unknown>
+// CHECK-UNKNOWN: 4500d800 <unknown>
 
 cadd   z0.h, z0.h, z0.h, #90
 // CHECK-INST: cadd   z0.h, z0.h, z0.h, #90
 // CHECK-ENCODING: [0x00,0xd8,0x40,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 d8 40 45 <unknown>
+// CHECK-UNKNOWN: 4540d800 <unknown>
 
 cadd   z0.s, z0.s, z0.s, #90
 // CHECK-INST: cadd   z0.s, z0.s, z0.s, #90
 // CHECK-ENCODING: [0x00,0xd8,0x80,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 d8 80 45 <unknown>
+// CHECK-UNKNOWN: 4580d800 <unknown>
 
 cadd   z0.d, z0.d, z0.d, #90
 // CHECK-INST: cadd   z0.d, z0.d, z0.d, #90
 // CHECK-ENCODING: [0x00,0xd8,0xc0,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 d8 c0 45 <unknown>
+// CHECK-UNKNOWN: 45c0d800 <unknown>
 
 cadd   z31.b, z31.b, z31.b, #270
 // CHECK-INST: cadd   z31.b, z31.b, z31.b, #270
 // CHECK-ENCODING: [0xff,0xdf,0x00,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff df 00 45 <unknown>
+// CHECK-UNKNOWN: 4500dfff <unknown>
 
 cadd   z31.h, z31.h, z31.h, #270
 // CHECK-INST: cadd   z31.h, z31.h, z31.h, #270
 // CHECK-ENCODING: [0xff,0xdf,0x40,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff df 40 45 <unknown>
+// CHECK-UNKNOWN: 4540dfff <unknown>
 
 cadd   z31.s, z31.s, z31.s, #270
 // CHECK-INST: cadd   z31.s, z31.s, z31.s, #270
 // CHECK-ENCODING: [0xff,0xdf,0x80,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff df 80 45 <unknown>
+// CHECK-UNKNOWN: 4580dfff <unknown>
 
 cadd   z31.d, z31.d, z31.d, #270
 // CHECK-INST: cadd   z31.d, z31.d, z31.d, #270
 // CHECK-ENCODING: [0xff,0xdf,0xc0,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff df c0 45 <unknown>
+// CHECK-UNKNOWN: 45c0dfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -65,10 +65,10 @@ movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 cadd   z4.d, z4.d, z31.d, #270
 // CHECK-INST: cadd	z4.d, z4.d, z31.d, #270
 // CHECK-ENCODING: [0xe4,0xdf,0xc0,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 df c0 45 <unknown>
+// CHECK-UNKNOWN: 45c0dfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/cdot.s b/llvm/test/MC/AArch64/SVE2/cdot.s
index ac81aafb010ff..5cb6278f7dd81 100644
--- a/llvm/test/MC/AArch64/SVE2/cdot.s
+++ b/llvm/test/MC/AArch64/SVE2/cdot.s
@@ -13,61 +13,61 @@ cdot  z0.s, z1.b, z31.b, #0
 // CHECK-INST: cdot	z0.s, z1.b, z31.b, #0
 // CHECK-ENCODING: [0x20,0x10,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 10 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f1020 <unknown>
 
 cdot  z0.d, z1.h, z31.h, #0
 // CHECK-INST: cdot	z0.d, z1.h, z31.h, #0
 // CHECK-ENCODING: [0x20,0x10,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 10 df 44 <unknown>
+// CHECK-UNKNOWN: 44df1020 <unknown>
 
 cdot  z0.d, z1.h, z31.h, #90
 // CHECK-INST: cdot	z0.d, z1.h, z31.h, #90
 // CHECK-ENCODING: [0x20,0x14,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 14 df 44 <unknown>
+// CHECK-UNKNOWN: 44df1420 <unknown>
 
 cdot  z0.d, z1.h, z31.h, #180
 // CHECK-INST: cdot	z0.d, z1.h, z31.h, #180
 // CHECK-ENCODING: [0x20,0x18,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 18 df 44 <unknown>
+// CHECK-UNKNOWN: 44df1820 <unknown>
 
 cdot  z0.d, z1.h, z31.h, #270
 // CHECK-INST: cdot	z0.d, z1.h, z31.h, #270
 // CHECK-ENCODING: [0x20,0x1c,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 1c df 44 <unknown>
+// CHECK-UNKNOWN: 44df1c20 <unknown>
 
 cdot  z0.s, z1.b, z7.b[3], #0
 // CHECK-INST: cdot	z0.s, z1.b, z7.b[3], #0
 // CHECK-ENCODING: [0x20,0x40,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 40 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf4020 <unknown>
 
 cdot  z0.d, z1.h, z15.h[1], #0
 // CHECK-INST: cdot	z0.d, z1.h, z15.h[1], #0
 // CHECK-ENCODING: [0x20,0x40,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 40 ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff4020 <unknown>
 
 cdot  z5.d, z6.h, z3.h[0], #90
 // CHECK-INST: cdot	z5.d, z6.h, z3.h[0], #90
 // CHECK-ENCODING: [0xc5,0x44,0xe3,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: c5 44 e3 44 <unknown>
+// CHECK-UNKNOWN: 44e344c5 <unknown>
 
 cdot  z29.d, z30.h, z0.h[0], #180
 // CHECK-INST: cdot z29.d, z30.h, z0.h[0], #180
 // CHECK-ENCODING: [0xdd,0x4b,0xe0,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 4b e0 44 <unknown>
+// CHECK-UNKNOWN: 44e04bdd <unknown>
 
 cdot  z31.d, z30.h, z7.h[1], #270
 // CHECK-INST: cdot z31.d, z30.h, z7.h[1], #270
 // CHECK-ENCODING: [0xdf,0x4f,0xf7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 4f f7 44 <unknown>
+// CHECK-UNKNOWN: 44f74fdf <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -77,22 +77,22 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 cdot  z0.d, z1.h, z31.h, #0
 // CHECK-INST: cdot	z0.d, z1.h, z31.h, #0
 // CHECK-ENCODING: [0x20,0x10,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 10 df 44 <unknown>
+// CHECK-UNKNOWN: 44df1020 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 cdot  z0.d, z1.h, z15.h[1], #0
 // CHECK-INST: cdot z0.d, z1.h, z15.h[1], #0
 // CHECK-ENCODING: [0x20,0x40,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 40 ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff4020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/cmla.s b/llvm/test/MC/AArch64/SVE2/cmla.s
index 319a2c6351b4c..47ecc290a7abc 100644
--- a/llvm/test/MC/AArch64/SVE2/cmla.s
+++ b/llvm/test/MC/AArch64/SVE2/cmla.s
@@ -13,121 +13,121 @@ cmla   z0.b, z1.b, z2.b, #0
 // CHECK-INST: cmla   z0.b, z1.b, z2.b, #0
 // CHECK-ENCODING: [0x20,0x20,0x02,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 20 02 44 <unknown>
+// CHECK-UNKNOWN: 44022020 <unknown>
 
 cmla   z0.h, z1.h, z2.h, #0
 // CHECK-INST: cmla   z0.h, z1.h, z2.h, #0
 // CHECK-ENCODING: [0x20,0x20,0x42,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 20 42 44 <unknown>
+// CHECK-UNKNOWN: 44422020 <unknown>
 
 cmla   z0.s, z1.s, z2.s, #0
 // CHECK-INST: cmla   z0.s, z1.s, z2.s, #0
 // CHECK-ENCODING: [0x20,0x20,0x82,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 20 82 44 <unknown>
+// CHECK-UNKNOWN: 44822020 <unknown>
 
 cmla   z0.d, z1.d, z2.d, #0
 // CHECK-INST: cmla   z0.d, z1.d, z2.d, #0
 // CHECK-ENCODING: [0x20,0x20,0xc2,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 20 c2 44 <unknown>
+// CHECK-UNKNOWN: 44c22020 <unknown>
 
 cmla   z29.b, z30.b, z31.b, #90
 // CHECK-INST: cmla   z29.b, z30.b, z31.b, #90
 // CHECK-ENCODING: [0xdd,0x27,0x1f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 27 1f 44 <unknown>
+// CHECK-UNKNOWN: 441f27dd <unknown>
 
 cmla   z29.h, z30.h, z31.h, #90
 // CHECK-INST: cmla   z29.h, z30.h, z31.h, #90
 // CHECK-ENCODING: [0xdd,0x27,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 27 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f27dd <unknown>
 
 cmla   z29.s, z30.s, z31.s, #90
 // CHECK-INST: cmla   z29.s, z30.s, z31.s, #90
 // CHECK-ENCODING: [0xdd,0x27,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 27 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f27dd <unknown>
 
 cmla   z29.d, z30.d, z31.d, #90
 // CHECK-INST: cmla   z29.d, z30.d, z31.d, #90
 // CHECK-ENCODING: [0xdd,0x27,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 27 df 44 <unknown>
+// CHECK-UNKNOWN: 44df27dd <unknown>
 
 cmla   z31.b, z31.b, z31.b, #180
 // CHECK-INST: cmla   z31.b, z31.b, z31.b, #180
 // CHECK-ENCODING: [0xff,0x2b,0x1f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2b 1f 44 <unknown>
+// CHECK-UNKNOWN: 441f2bff <unknown>
 
 cmla   z31.h, z31.h, z31.h, #180
 // CHECK-INST: cmla   z31.h, z31.h, z31.h, #180
 // CHECK-ENCODING: [0xff,0x2b,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2b 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f2bff <unknown>
 
 cmla   z31.s, z31.s, z31.s, #180
 // CHECK-INST: cmla   z31.s, z31.s, z31.s, #180
 // CHECK-ENCODING: [0xff,0x2b,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2b 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f2bff <unknown>
 
 cmla   z31.d, z31.d, z31.d, #180
 // CHECK-INST: cmla   z31.d, z31.d, z31.d, #180
 // CHECK-ENCODING: [0xff,0x2b,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2b df 44 <unknown>
+// CHECK-UNKNOWN: 44df2bff <unknown>
 
 cmla   z15.b, z16.b, z17.b, #270
 // CHECK-INST: cmla   z15.b, z16.b, z17.b, #270
 // CHECK-ENCODING: [0x0f,0x2e,0x11,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 2e 11 44 <unknown>
+// CHECK-UNKNOWN: 44112e0f <unknown>
 
 cmla   z15.h, z16.h, z17.h, #270
 // CHECK-INST: cmla   z15.h, z16.h, z17.h, #270
 // CHECK-ENCODING: [0x0f,0x2e,0x51,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 2e 51 44 <unknown>
+// CHECK-UNKNOWN: 44512e0f <unknown>
 
 cmla   z15.s, z16.s, z17.s, #270
 // CHECK-INST: cmla   z15.s, z16.s, z17.s, #270
 // CHECK-ENCODING: [0x0f,0x2e,0x91,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 2e 91 44 <unknown>
+// CHECK-UNKNOWN: 44912e0f <unknown>
 
 cmla   z15.d, z16.d, z17.d, #270
 // CHECK-INST: cmla   z15.d, z16.d, z17.d, #270
 // CHECK-ENCODING: [0x0f,0x2e,0xd1,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 2e d1 44 <unknown>
+// CHECK-UNKNOWN: 44d12e0f <unknown>
 
 cmla   z0.h, z1.h, z2.h[0], #0
 // CHECK-INST: cmla   z0.h, z1.h, z2.h[0], #0
 // CHECK-ENCODING: [0x20,0x60,0xa2,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 60 a2 44 <unknown>
+// CHECK-UNKNOWN: 44a26020 <unknown>
 
 cmla   z0.s, z1.s, z2.s[0], #0
 // CHECK-INST: cmla   z0.s, z1.s, z2.s[0], #0
 // CHECK-ENCODING: [0x20,0x60,0xe2,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 60 e2 44 <unknown>
+// CHECK-UNKNOWN: 44e26020 <unknown>
 
 cmla   z31.h, z30.h, z7.h[0], #180
 // CHECK-INST: cmla   z31.h, z30.h, z7.h[0], #180
 // CHECK-ENCODING: [0xdf,0x6b,0xa7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 6b a7 44 <unknown>
+// CHECK-UNKNOWN: 44a76bdf <unknown>
 
 cmla   z31.s, z30.s, z7.s[0], #180
 // CHECK-INST: cmla   z31.s, z30.s, z7.s[0], #180
 // CHECK-ENCODING: [0xdf,0x6b,0xe7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 6b e7 44 <unknown>
+// CHECK-UNKNOWN: 44e76bdf <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -137,22 +137,22 @@ movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 cmla   z4.d, z31.d, z31.d, #270
 // CHECK-INST: cmla   z4.d, z31.d, z31.d, #270
 // CHECK-ENCODING: [0xe4,0x2f,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 2f df 44 <unknown>
+// CHECK-UNKNOWN: 44df2fe4 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 cmla   z21.s, z10.s, z5.s[1], #90
 // CHECK-INST: cmla	z21.s, z10.s, z5.s[1], #90
 // CHECK-ENCODING: [0x55,0x65,0xf5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 65 f5 44 <unknown>
+// CHECK-UNKNOWN: 44f56555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/eor3.s b/llvm/test/MC/AArch64/SVE2/eor3.s
index bbc8e906154f2..42fa83ebb44ae 100644
--- a/llvm/test/MC/AArch64/SVE2/eor3.s
+++ b/llvm/test/MC/AArch64/SVE2/eor3.s
@@ -13,7 +13,7 @@ eor3 z29.d, z29.d, z30.d, z31.d
 // CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d
 // CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fd 3b 3e 04 <unknown>
+// CHECK-UNKNOWN: 043e3bfd <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -23,19 +23,19 @@ eor3 z29.b, z29.b, z30.b, z31.b
 // CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d
 // CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fd 3b 3e 04 <unknown>
+// CHECK-UNKNOWN: 043e3bfd <unknown>
 
 eor3 z29.h, z29.h, z30.h, z31.h
 // CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d
 // CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fd 3b 3e 04 <unknown>
+// CHECK-UNKNOWN: 043e3bfd <unknown>
 
 eor3 z29.s, z29.s, z30.s, z31.s
 // CHECK-INST: eor3 z29.d, z29.d, z30.d, z31.d
 // CHECK-ENCODING: [0xfd,0x3b,0x3e,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fd 3b 3e 04 <unknown>
+// CHECK-UNKNOWN: 043e3bfd <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -45,10 +45,10 @@ movprfx z31, z7
 // CHECK-INST: movprfx z31, z7
 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcff <unknown>
 
 eor3 z31.d, z31.d, z30.d, z29.d
 // CHECK-INST: eor3 z31.d, z31.d, z30.d, z29.d
 // CHECK-ENCODING: [0xbf,0x3b,0x3e,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: bf 3b 3e 04 <unknown>
+// CHECK-UNKNOWN: 043e3bbf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/eorbt.s b/llvm/test/MC/AArch64/SVE2/eorbt.s
index fb2fec7928c73..3dd15c0f140fc 100644
--- a/llvm/test/MC/AArch64/SVE2/eorbt.s
+++ b/llvm/test/MC/AArch64/SVE2/eorbt.s
@@ -13,25 +13,25 @@ eorbt z0.b, z1.b, z31.b
 // CHECK-INST: eorbt z0.b, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x90,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 90 1f 45 <unknown>
+// CHECK-UNKNOWN: 451f9020 <unknown>
 
 eorbt z0.h, z1.h, z31.h
 // CHECK-INST: eorbt z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x90,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 90 5f 45 <unknown>
+// CHECK-UNKNOWN: 455f9020 <unknown>
 
 eorbt z0.s, z1.s, z31.s
 // CHECK-INST: eorbt z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x90,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 90 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f9020 <unknown>
 
 eorbt z0.d, z1.d, z31.d
 // CHECK-INST: eorbt z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x90,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 90 df 45 <unknown>
+// CHECK-UNKNOWN: 45df9020 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,10 +41,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 eorbt z0.d, z1.d, z31.d
 // CHECK-INST: eorbt z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x90,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 90 df 45 <unknown>
+// CHECK-UNKNOWN: 45df9020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/eortb.s b/llvm/test/MC/AArch64/SVE2/eortb.s
index f67718a842a63..12fa399a0a79b 100644
--- a/llvm/test/MC/AArch64/SVE2/eortb.s
+++ b/llvm/test/MC/AArch64/SVE2/eortb.s
@@ -13,25 +13,25 @@ eortb z0.b, z1.b, z31.b
 // CHECK-INST: eortb z0.b, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x94,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 94 1f 45 <unknown>
+// CHECK-UNKNOWN: 451f9420 <unknown>
 
 eortb z0.h, z1.h, z31.h
 // CHECK-INST: eortb z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x94,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 94 5f 45 <unknown>
+// CHECK-UNKNOWN: 455f9420 <unknown>
 
 eortb z0.s, z1.s, z31.s
 // CHECK-INST: eortb z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x94,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 94 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f9420 <unknown>
 
 eortb z0.d, z1.d, z31.d
 // CHECK-INST: eortb z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x94,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 94 df 45 <unknown>
+// CHECK-UNKNOWN: 45df9420 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,10 +41,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 eortb z0.d, z1.d, z31.d
 // CHECK-INST: eortb z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x94,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 94 df 45 <unknown>
+// CHECK-UNKNOWN: 45df9420 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ext.s b/llvm/test/MC/AArch64/SVE2/ext.s
index f97007859eb8a..2272a470bbb36 100644
--- a/llvm/test/MC/AArch64/SVE2/ext.s
+++ b/llvm/test/MC/AArch64/SVE2/ext.s
@@ -13,10 +13,10 @@ ext z0.b, { z1.b, z2.b }, #0
 // CHECK-INST: ext z0.b, { z1.b, z2.b }, #0
 // CHECK-ENCODING: [0x20,0x00,0x60,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 00 60 05 <unknown>
+// CHECK-UNKNOWN: 05600020 <unknown>
 
 ext z31.b, { z30.b, z31.b }, #255
 // CHECK-INST: ext z31.b, { z30.b, z31.b }, #255
 // CHECK-ENCODING: [0xdf,0x1f,0x7f,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 1f 7f 05 <unknown>
+// CHECK-UNKNOWN: 057f1fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/faddp.s b/llvm/test/MC/AArch64/SVE2/faddp.s
index ce1dd77af59bb..e6b212c940e00 100644
--- a/llvm/test/MC/AArch64/SVE2/faddp.s
+++ b/llvm/test/MC/AArch64/SVE2/faddp.s
@@ -13,19 +13,19 @@ faddp z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: faddp z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x50,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 50 64 <unknown>
+// CHECK-UNKNOWN: 64508020 <unknown>
 
 faddp z29.s, p3/m, z29.s, z30.s
 // CHECK-INST: faddp z29.s, p3/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x8f,0x90,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 8f 90 64 <unknown>
+// CHECK-UNKNOWN: 64908fdd <unknown>
 
 faddp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: faddp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd0,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d0 64 <unknown>
+// CHECK-UNKNOWN: 64d09fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -34,22 +34,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 faddp z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: faddp z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd0,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d0 64 <unknown>
+// CHECK-UNKNOWN: 64d083df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 faddp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: faddp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd0,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d0 64 <unknown>
+// CHECK-UNKNOWN: 64d09fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/fcvtlt.s b/llvm/test/MC/AArch64/SVE2/fcvtlt.s
index 525f71bd81c03..7e46e5441dd84 100644
--- a/llvm/test/MC/AArch64/SVE2/fcvtlt.s
+++ b/llvm/test/MC/AArch64/SVE2/fcvtlt.s
@@ -14,10 +14,10 @@ fcvtlt z0.s, p0/m, z1.h
 // CHECK-INST: fcvtlt z0.s, p0/m, z1.h
 // CHECK-ENCODING: [0x20,0xa0,0x89,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 89 64 <unknown>
+// CHECK-UNKNOWN: 6489a020 <unknown>
 
 fcvtlt z30.d, p7/m, z31.s
 // CHECK-INST: fcvtlt z30.d, p7/m, z31.s
 // CHECK-ENCODING: [0xfe,0xbf,0xcb,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fe bf cb 64 <unknown>
+// CHECK-UNKNOWN: 64cbbffe <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/fcvtnt.s b/llvm/test/MC/AArch64/SVE2/fcvtnt.s
index 4c213571aeda8..b22bc500b3eee 100644
--- a/llvm/test/MC/AArch64/SVE2/fcvtnt.s
+++ b/llvm/test/MC/AArch64/SVE2/fcvtnt.s
@@ -14,10 +14,10 @@ fcvtnt z0.h, p0/m, z1.s
 // CHECK-INST: fcvtnt z0.h, p0/m, z1.s
 // CHECK-ENCODING: [0x20,0xa0,0x88,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 88 64 <unknown>
+// CHECK-UNKNOWN: 6488a020 <unknown>
 
 fcvtnt z30.s, p7/m, z31.d
 // CHECK-INST: fcvtnt z30.s, p7/m, z31.d
 // CHECK-ENCODING: [0xfe,0xbf,0xca,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fe bf ca 64 <unknown>
+// CHECK-UNKNOWN: 64cabffe <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/fcvtx.s b/llvm/test/MC/AArch64/SVE2/fcvtx.s
index 5b147e0462172..c68623ca28b24 100644
--- a/llvm/test/MC/AArch64/SVE2/fcvtx.s
+++ b/llvm/test/MC/AArch64/SVE2/fcvtx.s
@@ -14,13 +14,13 @@ fcvtx    z0.s, p0/m, z0.d
 // CHECK-INST: fcvtx    z0.s, p0/m, z0.d
 // CHECK-ENCODING: [0x00,0xa0,0x0a,0x65]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 a0 0a 65 <unknown>
+// CHECK-UNKNOWN: 650aa000 <unknown>
 
 fcvtx    z30.s, p7/m, z31.d
 // CHECK-INST: fcvtx    z30.s, p7/m, z31.d
 // CHECK-ENCODING: [0xfe,0xbf,0x0a,0x65]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fe bf 0a 65 <unknown>
+// CHECK-UNKNOWN: 650abffe <unknown>
 
 
 
@@ -31,22 +31,22 @@ movprfx z5.d, p0/z, z7.d
 // CHECK-INST: movprfx	z5.d, p0/z, z7.d
 // CHECK-ENCODING: [0xe5,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020e5 <unknown>
 
 fcvtx    z5.s, p0/m, z0.d
 // CHECK-INST: fcvtx	z5.s, p0/m, z0.d
 // CHECK-ENCODING: [0x05,0xa0,0x0a,0x65]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 05 a0 0a 65 <unknown>
+// CHECK-UNKNOWN: 650aa005 <unknown>
 
 movprfx z5, z7
 // CHECK-INST: movprfx	z5, z7
 // CHECK-ENCODING: [0xe5,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e5 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce5 <unknown>
 
 fcvtx    z5.s, p0/m, z0.d
 // CHECK-INST: fcvtx	z5.s, p0/m, z0.d
 // CHECK-ENCODING: [0x05,0xa0,0x0a,0x65]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 05 a0 0a 65 <unknown>
+// CHECK-UNKNOWN: 650aa005 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/fcvtxnt.s b/llvm/test/MC/AArch64/SVE2/fcvtxnt.s
index 249bed0d3e1bf..d906146d7ed70 100644
--- a/llvm/test/MC/AArch64/SVE2/fcvtxnt.s
+++ b/llvm/test/MC/AArch64/SVE2/fcvtxnt.s
@@ -14,10 +14,10 @@ fcvtxnt z0.s, p0/m, z1.d
 // CHECK-INST: fcvtxnt z0.s, p0/m, z1.d
 // CHECK-ENCODING: [0x20,0xa0,0x0a,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 0a 64 <unknown>
+// CHECK-UNKNOWN: 640aa020 <unknown>
 
 fcvtxnt z30.s, p7/m, z31.d
 // CHECK-INST: fcvtxnt z30.s, p7/m, z31.d
 // CHECK-ENCODING: [0xfe,0xbf,0x0a,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fe bf 0a 64 <unknown>
+// CHECK-UNKNOWN: 640abffe <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/flogb.s b/llvm/test/MC/AArch64/SVE2/flogb.s
index 8236bc428a017..2f9143e82564b 100644
--- a/llvm/test/MC/AArch64/SVE2/flogb.s
+++ b/llvm/test/MC/AArch64/SVE2/flogb.s
@@ -13,19 +13,19 @@ flogb    z31.h, p7/m, z31.h
 // CHECK-INST: flogb	z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x1a,0x65]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff bf 1a 65 <unknown>
+// CHECK-UNKNOWN: 651abfff <unknown>
 
 flogb    z31.s, p7/m, z31.s
 // CHECK-INST: flogb	z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x1c,0x65]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff bf 1c 65 <unknown>
+// CHECK-UNKNOWN: 651cbfff <unknown>
 
 flogb    z31.d, p7/m, z31.d
 // CHECK-INST: flogb	z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0x1e,0x65]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff bf 1e 65 <unknown>
+// CHECK-UNKNOWN: 651ebfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,22 +35,22 @@ movprfx z4.d, p7/z, z6.d
 // CHECK-INST: movprfx	z4.d, p7/z, z6.d
 // CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
+// CHECK-UNKNOWN: 04d03cc4 <unknown>
 
 flogb    z4.d, p7/m, z31.d
 // CHECK-INST: flogb	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0x1e,0x65]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 bf 1e 65 <unknown>
+// CHECK-UNKNOWN: 651ebfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 flogb    z4.d, p7/m, z31.d
 // CHECK-INST: flogb	z4.d, p7/m, z31.d
 // CHECK-ENCODING: [0xe4,0xbf,0x1e,0x65]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 bf 1e 65 <unknown>
+// CHECK-UNKNOWN: 651ebfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/fmaxnmp.s b/llvm/test/MC/AArch64/SVE2/fmaxnmp.s
index 947b5686fd9a8..6cff54ca2380b 100644
--- a/llvm/test/MC/AArch64/SVE2/fmaxnmp.s
+++ b/llvm/test/MC/AArch64/SVE2/fmaxnmp.s
@@ -13,19 +13,19 @@ fmaxnmp z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: fmaxnmp z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x54,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 54 64 <unknown>
+// CHECK-UNKNOWN: 64548020 <unknown>
 
 fmaxnmp z29.s, p3/m, z29.s, z30.s
 // CHECK-INST: fmaxnmp z29.s, p3/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x8f,0x94,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 8f 94 64 <unknown>
+// CHECK-UNKNOWN: 64948fdd <unknown>
 
 fmaxnmp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: fmaxnmp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd4,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d4 64 <unknown>
+// CHECK-UNKNOWN: 64d49fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -34,22 +34,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 fmaxnmp z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: fmaxnmp z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd4,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d4 64 <unknown>
+// CHECK-UNKNOWN: 64d483df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 fmaxnmp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: fmaxnmp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd4,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d4 64 <unknown>
+// CHECK-UNKNOWN: 64d49fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/fmaxp.s b/llvm/test/MC/AArch64/SVE2/fmaxp.s
index d9268cb33b93e..edfc38e2f0c8d 100644
--- a/llvm/test/MC/AArch64/SVE2/fmaxp.s
+++ b/llvm/test/MC/AArch64/SVE2/fmaxp.s
@@ -13,19 +13,19 @@ fmaxp z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: fmaxp z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x56,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 56 64 <unknown>
+// CHECK-UNKNOWN: 64568020 <unknown>
 
 fmaxp z29.s, p3/m, z29.s, z30.s
 // CHECK-INST: fmaxp z29.s, p3/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x8f,0x96,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 8f 96 64 <unknown>
+// CHECK-UNKNOWN: 64968fdd <unknown>
 
 fmaxp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: fmaxp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd6,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d6 64 <unknown>
+// CHECK-UNKNOWN: 64d69fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -34,22 +34,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 fmaxp z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: fmaxp z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd6,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d6 64 <unknown>
+// CHECK-UNKNOWN: 64d683df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 fmaxp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: fmaxp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd6,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d6 64 <unknown>
+// CHECK-UNKNOWN: 64d69fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/fminnmp.s b/llvm/test/MC/AArch64/SVE2/fminnmp.s
index 5d0765707995c..155db5462cbd9 100644
--- a/llvm/test/MC/AArch64/SVE2/fminnmp.s
+++ b/llvm/test/MC/AArch64/SVE2/fminnmp.s
@@ -13,19 +13,19 @@ fminnmp z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: fminnmp z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x55,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 55 64 <unknown>
+// CHECK-UNKNOWN: 64558020 <unknown>
 
 fminnmp z29.s, p3/m, z29.s, z30.s
 // CHECK-INST: fminnmp z29.s, p3/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x8f,0x95,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 8f 95 64 <unknown>
+// CHECK-UNKNOWN: 64958fdd <unknown>
 
 fminnmp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: fminnmp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd5,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d5 64 <unknown>
+// CHECK-UNKNOWN: 64d59fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -34,22 +34,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 fminnmp z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: fminnmp z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd5,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d5 64 <unknown>
+// CHECK-UNKNOWN: 64d583df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 fminnmp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: fminnmp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd5,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d5 64 <unknown>
+// CHECK-UNKNOWN: 64d59fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/fminp.s b/llvm/test/MC/AArch64/SVE2/fminp.s
index bf02b374b7426..d2e912f6c96ca 100644
--- a/llvm/test/MC/AArch64/SVE2/fminp.s
+++ b/llvm/test/MC/AArch64/SVE2/fminp.s
@@ -13,19 +13,19 @@ fminp z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: fminp z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x57,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 57 64 <unknown>
+// CHECK-UNKNOWN: 64578020 <unknown>
 
 fminp z29.s, p3/m, z29.s, z30.s
 // CHECK-INST: fminp z29.s, p3/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x8f,0x97,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 8f 97 64 <unknown>
+// CHECK-UNKNOWN: 64978fdd <unknown>
 
 fminp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: fminp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd7,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d7 64 <unknown>
+// CHECK-UNKNOWN: 64d79fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -34,22 +34,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 fminp z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: fminp z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd7,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d7 64 <unknown>
+// CHECK-UNKNOWN: 64d783df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 fminp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: fminp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd7,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d7 64 <unknown>
+// CHECK-UNKNOWN: 64d79fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/fmlalb.s b/llvm/test/MC/AArch64/SVE2/fmlalb.s
index 25cfbd52dbe18..c22cb5319b2b9 100644
--- a/llvm/test/MC/AArch64/SVE2/fmlalb.s
+++ b/llvm/test/MC/AArch64/SVE2/fmlalb.s
@@ -14,19 +14,19 @@ fmlalb z29.s, z30.h, z31.h
 // CHECK-INST: fmlalb z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x83,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 83 bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf83dd <unknown>
 
 fmlalb z0.s, z1.h, z7.h[0]
 // CHECK-INST: fmlalb	z0.s, z1.h, z7.h[0]
 // CHECK-ENCODING: [0x20,0x40,0xa7,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 40 a7 64 <unknown>
+// CHECK-UNKNOWN: 64a74020 <unknown>
 
 fmlalb z30.s, z31.h, z7.h[7]
 // CHECK-INST: fmlalb z30.s, z31.h, z7.h[7]
 // CHECK-ENCODING: [0xfe,0x4b,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fe 4b bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf4bfe <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -35,22 +35,22 @@ movprfx z29, z28
 // CHECK-INST: movprfx	z29, z28
 // CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf9d <unknown>
 
 fmlalb z29.s, z30.h, z31.h
 // CHECK-INST: fmlalb z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x83,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 83 bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf83dd <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 fmlalb z21.s, z1.h, z7.h[7]
 // CHECK-INST: fmlalb	z21.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x35,0x48,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 48 bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf4835 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/fmlalt.s b/llvm/test/MC/AArch64/SVE2/fmlalt.s
index d6d65e4ece96b..b1dd859eceb96 100644
--- a/llvm/test/MC/AArch64/SVE2/fmlalt.s
+++ b/llvm/test/MC/AArch64/SVE2/fmlalt.s
@@ -14,19 +14,19 @@ fmlalt z29.s, z30.h, z31.h
 // CHECK-INST: fmlalt z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x87,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 87 bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf87dd <unknown>
 
 fmlalt z0.s, z1.h, z7.h[0]
 // CHECK-INST: fmlalt	z0.s, z1.h, z7.h[0]
 // CHECK-ENCODING: [0x20,0x44,0xa7,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 44 a7 64 <unknown>
+// CHECK-UNKNOWN: 64a74420 <unknown>
 
 fmlalt z30.s, z31.h, z7.h[7]
 // CHECK-INST: fmlalt z30.s, z31.h, z7.h[7]
 // CHECK-ENCODING: [0xfe,0x4f,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fe 4f bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf4ffe <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -35,22 +35,22 @@ movprfx z29, z28
 // CHECK-INST: movprfx	z29, z28
 // CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf9d <unknown>
 
 fmlalt z29.s, z30.h, z31.h
 // CHECK-INST: fmlalt z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x87,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 87 bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf87dd <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 fmlalt z21.s, z1.h, z7.h[7]
 // CHECK-INST: fmlalt	z21.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x35,0x4c,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 4c bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf4c35 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/fmlslb.s b/llvm/test/MC/AArch64/SVE2/fmlslb.s
index cd25c2c3188ad..8a89b0d43b69e 100644
--- a/llvm/test/MC/AArch64/SVE2/fmlslb.s
+++ b/llvm/test/MC/AArch64/SVE2/fmlslb.s
@@ -14,19 +14,19 @@ fmlslb z29.s, z30.h, z31.h
 // CHECK-INST: fmlslb z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd a3 bf 64 <unknown>
+// CHECK-UNKNOWN: 64bfa3dd <unknown>
 
 fmlslb z0.s, z1.h, z7.h[0]
 // CHECK-INST: fmlslb	z0.s, z1.h, z7.h[0]
 // CHECK-ENCODING: [0x20,0x60,0xa7,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 60 a7 64 <unknown>
+// CHECK-UNKNOWN: 64a76020 <unknown>
 
 fmlslb z30.s, z31.h, z7.h[7]
 // CHECK-INST: fmlslb z30.s, z31.h, z7.h[7]
 // CHECK-ENCODING: [0xfe,0x6b,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fe 6b bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf6bfe <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -35,22 +35,22 @@ movprfx z29, z28
 // CHECK-INST: movprfx	z29, z28
 // CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf9d <unknown>
 
 fmlslb z29.s, z30.h, z31.h
 // CHECK-INST: fmlslb z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd a3 bf 64 <unknown>
+// CHECK-UNKNOWN: 64bfa3dd <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 fmlslb z21.s, z1.h, z7.h[7]
 // CHECK-INST: fmlslb	z21.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x35,0x68,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 68 bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf6835 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/fmlslt.s b/llvm/test/MC/AArch64/SVE2/fmlslt.s
index 7b3f1b6d4bf2e..4458c1ad0071a 100644
--- a/llvm/test/MC/AArch64/SVE2/fmlslt.s
+++ b/llvm/test/MC/AArch64/SVE2/fmlslt.s
@@ -14,19 +14,19 @@ fmlslt z29.s, z30.h, z31.h
 // CHECK-INST: fmlslt z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd a7 bf 64 <unknown>
+// CHECK-UNKNOWN: 64bfa7dd <unknown>
 
 fmlslt z0.s, z1.h, z7.h[0]
 // CHECK-INST: fmlslt	z0.s, z1.h, z7.h[0]
 // CHECK-ENCODING: [0x20,0x64,0xa7,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 64 a7 64 <unknown>
+// CHECK-UNKNOWN: 64a76420 <unknown>
 
 fmlslt z30.s, z31.h, z7.h[7]
 // CHECK-INST: fmlslt z30.s, z31.h, z7.h[7]
 // CHECK-ENCODING: [0xfe,0x6f,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fe 6f bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf6ffe <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -35,22 +35,22 @@ movprfx z29, z28
 // CHECK-INST: movprfx	z29, z28
 // CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf9d <unknown>
 
 fmlslt z29.s, z30.h, z31.h
 // CHECK-INST: fmlslt z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd a7 bf 64 <unknown>
+// CHECK-UNKNOWN: 64bfa7dd <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 fmlslt z21.s, z1.h, z7.h[7]
 // CHECK-INST: fmlslt	z21.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x35,0x6c,0xbf,0x64]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 6c bf 64 <unknown>
+// CHECK-UNKNOWN: 64bf6c35 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/histcnt.s b/llvm/test/MC/AArch64/SVE2/histcnt.s
index 64b7ea87f41d2..140e13190009a 100644
--- a/llvm/test/MC/AArch64/SVE2/histcnt.s
+++ b/llvm/test/MC/AArch64/SVE2/histcnt.s
@@ -14,10 +14,10 @@ histcnt z0.s, p0/z, z1.s, z2.s
 // CHECK-INST: histcnt z0.s, p0/z, z1.s, z2.s
 // CHECK-ENCODING: [0x20,0xc0,0xa2,0x45]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 c0 a2 45 <unknown>
+// CHECK-UNKNOWN: 45a2c020 <unknown>
 
 histcnt z29.d, p7/z, z30.d, z31.d
 // CHECK-INST: histcnt z29.d, p7/z, z30.d, z31.d
 // CHECK-ENCODING: [0xdd,0xdf,0xff,0x45]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: dd df ff 45 <unknown>
+// CHECK-UNKNOWN: 45ffdfdd <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/histseg.s b/llvm/test/MC/AArch64/SVE2/histseg.s
index 4ff7ebee88f8c..54f3d5bab5a5d 100644
--- a/llvm/test/MC/AArch64/SVE2/histseg.s
+++ b/llvm/test/MC/AArch64/SVE2/histseg.s
@@ -14,4 +14,4 @@ histseg z0.b, z1.b, z31.b
 // CHECK-INST: histseg z0.b, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0xa0,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 a0 3f 45 <unknown>
+// CHECK-UNKNOWN: 453fa020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ldnt1b.s b/llvm/test/MC/AArch64/SVE2/ldnt1b.s
index a7b9d918076cb..adb21bb06f3a4 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1b.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1b.s
@@ -13,70 +13,70 @@ ldnt1b z0.s, p0/z, [z1.s]
 // CHECK-INST: ldnt1b { z0.s }, p0/z, [z1.s]
 // CHECK-ENCODING: [0x20,0xa0,0x1f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 a0 1f 84 <unknown>
+// CHECK-UNKNOWN: 841fa020 <unknown>
 
 ldnt1b z31.s, p7/z, [z31.s, xzr]
 // CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s]
 // CHECK-ENCODING: [0xff,0xbf,0x1f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff bf 1f 84 <unknown>
+// CHECK-UNKNOWN: 841fbfff <unknown>
 
 ldnt1b z31.s, p7/z, [z31.s, x0]
 // CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0xbf,0x00,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff bf 00 84 <unknown>
+// CHECK-UNKNOWN: 8400bfff <unknown>
 
 ldnt1b z0.d, p0/z, [z1.d]
 // CHECK-INST: ldnt1b { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0xc0,0x1f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 c0 1f c4 <unknown>
+// CHECK-UNKNOWN: c41fc020 <unknown>
 
 ldnt1b z31.d, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0x1f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 1f c4 <unknown>
+// CHECK-UNKNOWN: c41fdfff <unknown>
 
 ldnt1b z31.d, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0xdf,0x00,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 00 c4 <unknown>
+// CHECK-UNKNOWN: c400dfff <unknown>
 
 ldnt1b { z0.s }, p0/z, [z1.s]
 // CHECK-INST: ldnt1b { z0.s }, p0/z, [z1.s]
 // CHECK-ENCODING: [0x20,0xa0,0x1f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 a0 1f 84 <unknown>
+// CHECK-UNKNOWN: 841fa020 <unknown>
 
 ldnt1b { z31.s }, p7/z, [z31.s, xzr]
 // CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s]
 // CHECK-ENCODING: [0xff,0xbf,0x1f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff bf 1f 84 <unknown>
+// CHECK-UNKNOWN: 841fbfff <unknown>
 
 ldnt1b { z31.s }, p7/z, [z31.s, x0]
 // CHECK-INST: ldnt1b { z31.s }, p7/z, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0xbf,0x00,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff bf 00 84 <unknown>
+// CHECK-UNKNOWN: 8400bfff <unknown>
 
 ldnt1b { z0.d }, p0/z, [z1.d]
 // CHECK-INST: ldnt1b { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0xc0,0x1f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 c0 1f c4 <unknown>
+// CHECK-UNKNOWN: c41fc020 <unknown>
 
 ldnt1b { z31.d }, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0x1f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 1f c4 <unknown>
+// CHECK-UNKNOWN: c41fdfff <unknown>
 
 ldnt1b { z31.d }, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1b { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0xdf,0x00,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 00 c4 <unknown>
+// CHECK-UNKNOWN: c400dfff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ldnt1d.s b/llvm/test/MC/AArch64/SVE2/ldnt1d.s
index 9201e83181e82..97324079ed4e5 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1d.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1d.s
@@ -13,34 +13,34 @@ ldnt1d z0.d, p0/z, [z1.d]
 // CHECK-INST: ldnt1d { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0xc0,0x9f,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 c0 9f c5 <unknown>
+// CHECK-UNKNOWN: c59fc020 <unknown>
 
 ldnt1d z31.d, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0x9f,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 9f c5 <unknown>
+// CHECK-UNKNOWN: c59fdfff <unknown>
 
 ldnt1d z31.d, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0xdf,0x80,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 80 c5 <unknown>
+// CHECK-UNKNOWN: c580dfff <unknown>
 
 ldnt1d { z0.d }, p0/z, [z1.d]
 // CHECK-INST: ldnt1d { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0xc0,0x9f,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 c0 9f c5 <unknown>
+// CHECK-UNKNOWN: c59fc020 <unknown>
 
 ldnt1d { z31.d }, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0x9f,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 9f c5 <unknown>
+// CHECK-UNKNOWN: c59fdfff <unknown>
 
 ldnt1d { z31.d }, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1d { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0xdf,0x80,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 80 c5 <unknown>
+// CHECK-UNKNOWN: c580dfff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ldnt1h.s b/llvm/test/MC/AArch64/SVE2/ldnt1h.s
index 18d6772f87dc4..da09b7cbd3b88 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1h.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1h.s
@@ -13,70 +13,70 @@ ldnt1h z0.s, p0/z, [z1.s]
 // CHECK-INST: ldnt1h { z0.s }, p0/z, [z1.s]
 // CHECK-ENCODING: [0x20,0xa0,0x9f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 a0 9f 84 <unknown>
+// CHECK-UNKNOWN: 849fa020 <unknown>
 
 ldnt1h z31.s, p7/z, [z31.s, xzr]
 // CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s]
 // CHECK-ENCODING: [0xff,0xbf,0x9f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff bf 9f 84 <unknown>
+// CHECK-UNKNOWN: 849fbfff <unknown>
 
 ldnt1h z31.s, p7/z, [z31.s, x0]
 // CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0xbf,0x80,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff bf 80 84 <unknown>
+// CHECK-UNKNOWN: 8480bfff <unknown>
 
 ldnt1h z0.d, p0/z, [z1.d]
 // CHECK-INST: ldnt1h { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0xc0,0x9f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 c0 9f c4 <unknown>
+// CHECK-UNKNOWN: c49fc020 <unknown>
 
 ldnt1h z31.d, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0x9f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 9f c4 <unknown>
+// CHECK-UNKNOWN: c49fdfff <unknown>
 
 ldnt1h z31.d, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0xdf,0x80,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 80 c4 <unknown>
+// CHECK-UNKNOWN: c480dfff <unknown>
 
 ldnt1h { z0.s }, p0/z, [z1.s]
 // CHECK-INST: ldnt1h { z0.s }, p0/z, [z1.s]
 // CHECK-ENCODING: [0x20,0xa0,0x9f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 a0 9f 84 <unknown>
+// CHECK-UNKNOWN: 849fa020 <unknown>
 
 ldnt1h { z31.s }, p7/z, [z31.s, xzr]
 // CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s]
 // CHECK-ENCODING: [0xff,0xbf,0x9f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff bf 9f 84 <unknown>
+// CHECK-UNKNOWN: 849fbfff <unknown>
 
 ldnt1h { z31.s }, p7/z, [z31.s, x0]
 // CHECK-INST: ldnt1h { z31.s }, p7/z, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0xbf,0x80,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff bf 80 84 <unknown>
+// CHECK-UNKNOWN: 8480bfff <unknown>
 
 ldnt1h { z0.d }, p0/z, [z1.d]
 // CHECK-INST: ldnt1h { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0xc0,0x9f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 c0 9f c4 <unknown>
+// CHECK-UNKNOWN: c49fc020 <unknown>
 
 ldnt1h { z31.d }, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0x9f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 9f c4 <unknown>
+// CHECK-UNKNOWN: c49fdfff <unknown>
 
 ldnt1h { z31.d }, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1h { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0xdf,0x80,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 80 c4 <unknown>
+// CHECK-UNKNOWN: c480dfff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ldnt1sb.s b/llvm/test/MC/AArch64/SVE2/ldnt1sb.s
index 1dff0d740a2ed..a8cf121e67907 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1sb.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1sb.s
@@ -13,70 +13,70 @@ ldnt1sb z0.s, p0/z, [z1.s]
 // CHECK-INST: ldnt1sb { z0.s }, p0/z, [z1.s]
 // CHECK-ENCODING: [0x20,0x80,0x1f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 80 1f 84 <unknown>
+// CHECK-UNKNOWN: 841f8020 <unknown>
 
 ldnt1sb z31.s, p7/z, [z31.s, xzr]
 // CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s]
 // CHECK-ENCODING: [0xff,0x9f,0x1f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 1f 84 <unknown>
+// CHECK-UNKNOWN: 841f9fff <unknown>
 
 ldnt1sb z31.s, p7/z, [z31.s, x0]
 // CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0x9f,0x00,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 00 84 <unknown>
+// CHECK-UNKNOWN: 84009fff <unknown>
 
 ldnt1sb z0.d, p0/z, [z1.d]
 // CHECK-INST: ldnt1sb { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0x80,0x1f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 80 1f c4 <unknown>
+// CHECK-UNKNOWN: c41f8020 <unknown>
 
 ldnt1sb z31.d, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0x9f,0x1f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 1f c4 <unknown>
+// CHECK-UNKNOWN: c41f9fff <unknown>
 
 ldnt1sb z31.d, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x9f,0x00,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 00 c4 <unknown>
+// CHECK-UNKNOWN: c4009fff <unknown>
 
 ldnt1sb { z0.s }, p0/z, [z1.s]
 // CHECK-INST: ldnt1sb { z0.s }, p0/z, [z1.s]
 // CHECK-ENCODING: [0x20,0x80,0x1f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 80 1f 84 <unknown>
+// CHECK-UNKNOWN: 841f8020 <unknown>
 
 ldnt1sb { z31.s }, p7/z, [z31.s, xzr]
 // CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s]
 // CHECK-ENCODING: [0xff,0x9f,0x1f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 1f 84 <unknown>
+// CHECK-UNKNOWN: 841f9fff <unknown>
 
 ldnt1sb { z31.s }, p7/z, [z31.s, x0]
 // CHECK-INST: ldnt1sb { z31.s }, p7/z, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0x9f,0x00,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 00 84 <unknown>
+// CHECK-UNKNOWN: 84009fff <unknown>
 
 ldnt1sb { z0.d }, p0/z, [z1.d]
 // CHECK-INST: ldnt1sb { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0x80,0x1f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 80 1f c4 <unknown>
+// CHECK-UNKNOWN: c41f8020 <unknown>
 
 ldnt1sb { z31.d }, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0x9f,0x1f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 1f c4 <unknown>
+// CHECK-UNKNOWN: c41f9fff <unknown>
 
 ldnt1sb { z31.d }, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1sb { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x9f,0x00,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 00 c4 <unknown>
+// CHECK-UNKNOWN: c4009fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ldnt1sh.s b/llvm/test/MC/AArch64/SVE2/ldnt1sh.s
index 1a9d5c3c550bf..057c4cfe13a17 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1sh.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1sh.s
@@ -13,70 +13,70 @@ ldnt1sh z0.s, p0/z, [z1.s]
 // CHECK-INST: ldnt1sh { z0.s }, p0/z, [z1.s]
 // CHECK-ENCODING: [0x20,0x80,0x9f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 80 9f 84 <unknown>
+// CHECK-UNKNOWN: 849f8020 <unknown>
 
 ldnt1sh z31.s, p7/z, [z31.s, xzr]
 // CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s]
 // CHECK-ENCODING: [0xff,0x9f,0x9f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 9f 84 <unknown>
+// CHECK-UNKNOWN: 849f9fff <unknown>
 
 ldnt1sh z31.s, p7/z, [z31.s, x0]
 // CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0x9f,0x80,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 80 84 <unknown>
+// CHECK-UNKNOWN: 84809fff <unknown>
 
 ldnt1sh z0.d, p0/z, [z1.d]
 // CHECK-INST: ldnt1sh { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0x80,0x9f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 80 9f c4 <unknown>
+// CHECK-UNKNOWN: c49f8020 <unknown>
 
 ldnt1sh z31.d, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0x9f,0x9f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 9f c4 <unknown>
+// CHECK-UNKNOWN: c49f9fff <unknown>
 
 ldnt1sh z31.d, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x9f,0x80,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 80 c4 <unknown>
+// CHECK-UNKNOWN: c4809fff <unknown>
 
 ldnt1sh { z0.s }, p0/z, [z1.s]
 // CHECK-INST: ldnt1sh { z0.s }, p0/z, [z1.s]
 // CHECK-ENCODING: [0x20,0x80,0x9f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 80 9f 84 <unknown>
+// CHECK-UNKNOWN: 849f8020 <unknown>
 
 ldnt1sh { z31.s }, p7/z, [z31.s, xzr]
 // CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s]
 // CHECK-ENCODING: [0xff,0x9f,0x9f,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 9f 84 <unknown>
+// CHECK-UNKNOWN: 849f9fff <unknown>
 
 ldnt1sh { z31.s }, p7/z, [z31.s, x0]
 // CHECK-INST: ldnt1sh { z31.s }, p7/z, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0x9f,0x80,0x84]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 80 84 <unknown>
+// CHECK-UNKNOWN: 84809fff <unknown>
 
 ldnt1sh { z0.d }, p0/z, [z1.d]
 // CHECK-INST: ldnt1sh { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0x80,0x9f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 80 9f c4 <unknown>
+// CHECK-UNKNOWN: c49f8020 <unknown>
 
 ldnt1sh { z31.d }, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0x9f,0x9f,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 9f c4 <unknown>
+// CHECK-UNKNOWN: c49f9fff <unknown>
 
 ldnt1sh { z31.d }, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1sh { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x9f,0x80,0xc4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 80 c4 <unknown>
+// CHECK-UNKNOWN: c4809fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ldnt1sw.s b/llvm/test/MC/AArch64/SVE2/ldnt1sw.s
index edd0b6cd6015d..694ad67b89ec0 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1sw.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1sw.s
@@ -13,34 +13,34 @@ ldnt1sw z0.d, p0/z, [z1.d]
 // CHECK-INST: ldnt1sw { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0x80,0x1f,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 80 1f c5 <unknown>
+// CHECK-UNKNOWN: c51f8020 <unknown>
 
 ldnt1sw z31.d, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0x9f,0x1f,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 1f c5 <unknown>
+// CHECK-UNKNOWN: c51f9fff <unknown>
 
 ldnt1sw z31.d, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x9f,0x00,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 00 c5 <unknown>
+// CHECK-UNKNOWN: c5009fff <unknown>
 
 ldnt1sw { z0.d }, p0/z, [z1.d]
 // CHECK-INST: ldnt1sw { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0x80,0x1f,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 80 1f c5 <unknown>
+// CHECK-UNKNOWN: c51f8020 <unknown>
 
 ldnt1sw { z31.d }, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0x9f,0x1f,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 1f c5 <unknown>
+// CHECK-UNKNOWN: c51f9fff <unknown>
 
 ldnt1sw { z31.d }, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1sw { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x9f,0x00,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 9f 00 c5 <unknown>
+// CHECK-UNKNOWN: c5009fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ldnt1w.s b/llvm/test/MC/AArch64/SVE2/ldnt1w.s
index ef590b6383cd4..b6dd4b34ee3a7 100644
--- a/llvm/test/MC/AArch64/SVE2/ldnt1w.s
+++ b/llvm/test/MC/AArch64/SVE2/ldnt1w.s
@@ -13,70 +13,70 @@ ldnt1w z0.s, p0/z, [z1.s]
 // CHECK-INST: ldnt1w { z0.s }, p0/z, [z1.s]
 // CHECK-ENCODING: [0x20,0xa0,0x1f,0x85]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 a0 1f 85 <unknown>
+// CHECK-UNKNOWN: 851fa020 <unknown>
 
 ldnt1w z31.s, p7/z, [z31.s, xzr]
 // CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s]
 // CHECK-ENCODING: [0xff,0xbf,0x1f,0x85]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff bf 1f 85 <unknown>
+// CHECK-UNKNOWN: 851fbfff <unknown>
 
 ldnt1w z31.s, p7/z, [z31.s, x0]
 // CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0xbf,0x00,0x85]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff bf 00 85 <unknown>
+// CHECK-UNKNOWN: 8500bfff <unknown>
 
 ldnt1w z0.d, p0/z, [z1.d]
 // CHECK-INST: ldnt1w { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0xc0,0x1f,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 c0 1f c5 <unknown>
+// CHECK-UNKNOWN: c51fc020 <unknown>
 
 ldnt1w z31.d, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0x1f,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 1f c5 <unknown>
+// CHECK-UNKNOWN: c51fdfff <unknown>
 
 ldnt1w z31.d, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0xdf,0x00,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 00 c5 <unknown>
+// CHECK-UNKNOWN: c500dfff <unknown>
 
 ldnt1w { z0.s }, p0/z, [z1.s]
 // CHECK-INST: ldnt1w { z0.s }, p0/z, [z1.s]
 // CHECK-ENCODING: [0x20,0xa0,0x1f,0x85]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 a0 1f 85 <unknown>
+// CHECK-UNKNOWN: 851fa020 <unknown>
 
 ldnt1w { z31.s }, p7/z, [z31.s, xzr]
 // CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s]
 // CHECK-ENCODING: [0xff,0xbf,0x1f,0x85]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff bf 1f 85 <unknown>
+// CHECK-UNKNOWN: 851fbfff <unknown>
 
 ldnt1w { z31.s }, p7/z, [z31.s, x0]
 // CHECK-INST: ldnt1w { z31.s }, p7/z, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0xbf,0x00,0x85]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff bf 00 85 <unknown>
+// CHECK-UNKNOWN: 8500bfff <unknown>
 
 ldnt1w { z0.d }, p0/z, [z1.d]
 // CHECK-INST: ldnt1w { z0.d }, p0/z, [z1.d]
 // CHECK-ENCODING: [0x20,0xc0,0x1f,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 c0 1f c5 <unknown>
+// CHECK-UNKNOWN: c51fc020 <unknown>
 
 ldnt1w { z31.d }, p7/z, [z31.d, xzr]
 // CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d]
 // CHECK-ENCODING: [0xff,0xdf,0x1f,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 1f c5 <unknown>
+// CHECK-UNKNOWN: c51fdfff <unknown>
 
 ldnt1w { z31.d }, p7/z, [z31.d, x0]
 // CHECK-INST: ldnt1w { z31.d }, p7/z, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0xdf,0x00,0xc5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff df 00 c5 <unknown>
+// CHECK-UNKNOWN: c500dfff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/match.s b/llvm/test/MC/AArch64/SVE2/match.s
index 4ae2b3bc70c0a..4f2130ac269e7 100644
--- a/llvm/test/MC/AArch64/SVE2/match.s
+++ b/llvm/test/MC/AArch64/SVE2/match.s
@@ -13,22 +13,22 @@ match p0.b, p0/z, z0.b, z0.b
 // CHECK-INST: match p0.b, p0/z, z0.b, z0.b
 // CHECK-ENCODING: [0x00,0x80,0x20,0x45]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 00 80 20 45 <unknown>
+// CHECK-UNKNOWN: 45208000 <unknown>
 
 match p0.h, p0/z, z0.h, z0.h
 // CHECK-INST: match p0.h, p0/z, z0.h, z0.h
 // CHECK-ENCODING: [0x00,0x80,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 00 80 60 45 <unknown>
+// CHECK-UNKNOWN: 45608000 <unknown>
 
 match p15.b, p7/z, z30.b, z31.b
 // CHECK-INST: match p15.b, p7/z, z30.b, z31.b
 // CHECK-ENCODING: [0xcf,0x9f,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: cf 9f 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f9fcf <unknown>
 
 match p15.h, p7/z, z30.h, z31.h
 // CHECK-INST: match p15.h, p7/z, z30.h, z31.h
 // CHECK-ENCODING: [0xcf,0x9f,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: cf 9f 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f9fcf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/mla.s b/llvm/test/MC/AArch64/SVE2/mla.s
index c62f8b425eeba..8b3a5fbba1aec 100644
--- a/llvm/test/MC/AArch64/SVE2/mla.s
+++ b/llvm/test/MC/AArch64/SVE2/mla.s
@@ -13,19 +13,19 @@ mla z0.h, z1.h, z7.h[7]
 // CHECK-INST: mla	z0.h, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x08,0x7f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 08 7f 44 <unknown>
+// CHECK-UNKNOWN: 447f0820 <unknown>
 
 mla z0.s, z1.s, z7.s[3]
 // CHECK-INST: mla	z0.s, z1.s, z7.s[3]
 // CHECK-ENCODING: [0x20,0x08,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 08 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf0820 <unknown>
 
 mla z0.d, z1.d, z7.d[1]
 // CHECK-INST: mla	z0.d, z1.d, z7.d[1]
 // CHECK-ENCODING: [0x20,0x08,0xf7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 08 f7 44 <unknown>
+// CHECK-UNKNOWN: 44f70820 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,10 +35,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 mla z0.d, z1.d, z7.d[1]
 // CHECK-INST: mla	z0.d, z1.d, z7.d[1]
 // CHECK-ENCODING: [0x20,0x08,0xf7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 08 f7 44 <unknown>
+// CHECK-UNKNOWN: 44f70820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/mls.s b/llvm/test/MC/AArch64/SVE2/mls.s
index 036dffe8e92c5..a2495f4093934 100644
--- a/llvm/test/MC/AArch64/SVE2/mls.s
+++ b/llvm/test/MC/AArch64/SVE2/mls.s
@@ -13,19 +13,19 @@ mls z0.h, z1.h, z7.h[7]
 // CHECK-INST: mls	z0.h, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x0c,0x7f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 0c 7f 44 <unknown>
+// CHECK-UNKNOWN: 447f0c20 <unknown>
 
 mls z0.s, z1.s, z7.s[3]
 // CHECK-INST: mls	z0.s, z1.s, z7.s[3]
 // CHECK-ENCODING: [0x20,0x0c,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 0c bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf0c20 <unknown>
 
 mls z0.d, z1.d, z7.d[1]
 // CHECK-INST: mls	z0.d, z1.d, z7.d[1]
 // CHECK-ENCODING: [0x20,0x0c,0xf7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 0c f7 44 <unknown>
+// CHECK-UNKNOWN: 44f70c20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -35,10 +35,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 mls z0.d, z1.d, z7.d[1]
 // CHECK-INST: mls	z0.d, z1.d, z7.d[1]
 // CHECK-ENCODING: [0x20,0x0c,0xf7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 0c f7 44 <unknown>
+// CHECK-UNKNOWN: 44f70c20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/mul.s b/llvm/test/MC/AArch64/SVE2/mul.s
index 6beab055b8b73..d82836f88b2ff 100644
--- a/llvm/test/MC/AArch64/SVE2/mul.s
+++ b/llvm/test/MC/AArch64/SVE2/mul.s
@@ -13,40 +13,40 @@ mul z0.b, z1.b, z2.b
 // CHECK-INST: mul z0.b, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x60,0x22,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 60 22 04 <unknown>
+// CHECK-UNKNOWN: 04226020 <unknown>
 
 mul z0.h, z1.h, z2.h
 // CHECK-INST: mul z0.h, z1.h, z2.h
 // CHECK-ENCODING: [0x20,0x60,0x62,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 60 62 04 <unknown>
+// CHECK-UNKNOWN: 04626020 <unknown>
 
 mul z29.s, z30.s, z31.s
 // CHECK-INST: mul z29.s, z30.s, z31.s
 // CHECK-ENCODING: [0xdd,0x63,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 63 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf63dd <unknown>
 
 mul z31.d, z31.d, z31.d
 // CHECK-INST: mul z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x63,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 63 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff63ff <unknown>
 
 mul z0.h, z1.h, z7.h[7]
 // CHECK-INST: mul	z0.h, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0xf8,0x7f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f8 7f 44 <unknown>
+// CHECK-UNKNOWN: 447ff820 <unknown>
 
 mul z0.s, z1.s, z7.s[3]
 // CHECK-INST: mul	z0.s, z1.s, z7.s[3]
 // CHECK-ENCODING: [0x20,0xf8,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f8 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bff820 <unknown>
 
 mul z0.d, z1.d, z15.d[1]
 // CHECK-INST: mul	z0.d, z1.d, z15.d[1]
 // CHECK-ENCODING: [0x20,0xf8,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f8 ff 44 <unknown>
+// CHECK-UNKNOWN: 44fff820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/nbsl.s b/llvm/test/MC/AArch64/SVE2/nbsl.s
index 2d2aef8323955..737480c2b8edd 100644
--- a/llvm/test/MC/AArch64/SVE2/nbsl.s
+++ b/llvm/test/MC/AArch64/SVE2/nbsl.s
@@ -13,7 +13,7 @@ nbsl z0.d, z0.d, z1.d, z2.d
 // CHECK-INST: nbsl z0.d, z0.d, z1.d, z2.d
 // CHECK-ENCODING: [0x40,0x3c,0xe1,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 40 3c e1 04 <unknown>
+// CHECK-UNKNOWN: 04e13c40 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -23,10 +23,10 @@ movprfx z31, z7
 // CHECK-INST: movprfx z31, z7
 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcff <unknown>
 
 nbsl z31.d, z31.d, z30.d, z29.d
 // CHECK-INST: nbsl z31.d, z31.d, z30.d, z29.d
 // CHECK-ENCODING: [0xbf,0x3f,0xfe,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: bf 3f fe 04 <unknown>
+// CHECK-UNKNOWN: 04fe3fbf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/nmatch.s b/llvm/test/MC/AArch64/SVE2/nmatch.s
index 68c8a29a02968..1f3d0c816174f 100644
--- a/llvm/test/MC/AArch64/SVE2/nmatch.s
+++ b/llvm/test/MC/AArch64/SVE2/nmatch.s
@@ -13,22 +13,22 @@ nmatch p0.b, p0/z, z0.b, z0.b
 // CHECK-INST: nmatch p0.b, p0/z, z0.b, z0.b
 // CHECK-ENCODING: [0x10,0x80,0x20,0x45]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 10 80 20 45 <unknown>
+// CHECK-UNKNOWN: 45208010 <unknown>
 
 nmatch p0.h, p0/z, z0.h, z0.h
 // CHECK-INST: nmatch p0.h, p0/z, z0.h, z0.h
 // CHECK-ENCODING: [0x10,0x80,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 10 80 60 45 <unknown>
+// CHECK-UNKNOWN: 45608010 <unknown>
 
 nmatch p15.b, p7/z, z30.b, z31.b
 // CHECK-INST: nmatch p15.b, p7/z, z30.b, z31.b
 // CHECK-ENCODING: [0xdf,0x9f,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: df 9f 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f9fdf <unknown>
 
 nmatch p15.h, p7/z, z30.h, z31.h
 // CHECK-INST: nmatch p15.h, p7/z, z30.h, z31.h
 // CHECK-ENCODING: [0xdf,0x9f,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: df 9f 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f9fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/pmul.s b/llvm/test/MC/AArch64/SVE2/pmul.s
index 0ee5dddc9ed80..714db56d36faa 100644
--- a/llvm/test/MC/AArch64/SVE2/pmul.s
+++ b/llvm/test/MC/AArch64/SVE2/pmul.s
@@ -13,10 +13,10 @@ pmul z0.b, z1.b, z2.b
 // CHECK-INST: pmul z0.b, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x64,0x22,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 64 22 04 <unknown>
+// CHECK-UNKNOWN: 04226420 <unknown>
 
 pmul z29.b, z30.b, z31.b
 // CHECK-INST: pmul z29.b, z30.b, z31.b
 // CHECK-ENCODING: [0xdd,0x67,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 67 3f 04 <unknown>
+// CHECK-UNKNOWN: 043f67dd <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/pmullb-128.s b/llvm/test/MC/AArch64/SVE2/pmullb-128.s
index 183a5abcd83dd..d48c75b3d4999 100644
--- a/llvm/test/MC/AArch64/SVE2/pmullb-128.s
+++ b/llvm/test/MC/AArch64/SVE2/pmullb-128.s
@@ -14,4 +14,4 @@ pmullb z29.q, z30.d, z31.d
 // CHECK-INST: pmullb z29.q, z30.d, z31.d
 // CHECK-ENCODING: [0xdd,0x6b,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2-aes
-// CHECK-UNKNOWN: dd 6b 1f 45 <unknown>
+// CHECK-UNKNOWN: 451f6bdd <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/pmullb.s b/llvm/test/MC/AArch64/SVE2/pmullb.s
index b1d9d7d1bb1a9..cbb0c8378d694 100644
--- a/llvm/test/MC/AArch64/SVE2/pmullb.s
+++ b/llvm/test/MC/AArch64/SVE2/pmullb.s
@@ -14,10 +14,10 @@ pmullb z0.h, z1.b, z2.b
 // CHECK-INST: pmullb z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x68,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 68 42 45 <unknown>
+// CHECK-UNKNOWN: 45426820 <unknown>
 
 pmullb z31.d, z31.s, z31.s
 // CHECK-INST: pmullb z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x6b,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 6b df 45 <unknown>
+// CHECK-UNKNOWN: 45df6bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/pmullt-128.s b/llvm/test/MC/AArch64/SVE2/pmullt-128.s
index d0252706122ab..e1eca8d1d89f8 100644
--- a/llvm/test/MC/AArch64/SVE2/pmullt-128.s
+++ b/llvm/test/MC/AArch64/SVE2/pmullt-128.s
@@ -14,4 +14,4 @@ pmullt z29.q, z30.d, z31.d
 // CHECK-INST: pmullt z29.q, z30.d, z31.d
 // CHECK-ENCODING: [0xdd,0x6f,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2-aes
-// CHECK-UNKNOWN: dd 6f 1f 45 <unknown>
+// CHECK-UNKNOWN: 451f6fdd <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/pmullt.s b/llvm/test/MC/AArch64/SVE2/pmullt.s
index a91c3da82de2c..4e67fdafb1700 100644
--- a/llvm/test/MC/AArch64/SVE2/pmullt.s
+++ b/llvm/test/MC/AArch64/SVE2/pmullt.s
@@ -14,10 +14,10 @@ pmullt z0.h, z1.b, z2.b
 // CHECK-INST: pmullt z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x6c,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 6c 42 45 <unknown>
+// CHECK-UNKNOWN: 45426c20 <unknown>
 
 pmullt z31.d, z31.s, z31.s
 // CHECK-INST: pmullt z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x6f,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 6f df 45 <unknown>
+// CHECK-UNKNOWN: 45df6fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/raddhnb.s b/llvm/test/MC/AArch64/SVE2/raddhnb.s
index 70726976e78af..bd7b8f663888a 100644
--- a/llvm/test/MC/AArch64/SVE2/raddhnb.s
+++ b/llvm/test/MC/AArch64/SVE2/raddhnb.s
@@ -14,16 +14,16 @@ raddhnb z0.b, z1.h, z31.h
 // CHECK-INST: raddhnb	z0.b, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x68,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 68 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f6820 <unknown>
 
 raddhnb z0.h, z1.s, z31.s
 // CHECK-INST: raddhnb	z0.h, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x68,0xbf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 68 bf 45 <unknown>
+// CHECK-UNKNOWN: 45bf6820 <unknown>
 
 raddhnb z0.s, z1.d, z31.d
 // CHECK-INST: raddhnb	z0.s, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x68,0xff,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 68 ff 45 <unknown>
+// CHECK-UNKNOWN: 45ff6820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/raddhnt.s b/llvm/test/MC/AArch64/SVE2/raddhnt.s
index 47612de5e8bff..34e9ecdf32ded 100644
--- a/llvm/test/MC/AArch64/SVE2/raddhnt.s
+++ b/llvm/test/MC/AArch64/SVE2/raddhnt.s
@@ -14,16 +14,16 @@ raddhnt z0.b, z1.h, z31.h
 // CHECK-INST: raddhnt	z0.b, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x6c,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 6c 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f6c20 <unknown>
 
 raddhnt z0.h, z1.s, z31.s
 // CHECK-INST: raddhnt	z0.h, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x6c,0xbf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 6c bf 45 <unknown>
+// CHECK-UNKNOWN: 45bf6c20 <unknown>
 
 raddhnt z0.s, z1.d, z31.d
 // CHECK-INST: raddhnt	z0.s, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x6c,0xff,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 6c ff 45 <unknown>
+// CHECK-UNKNOWN: 45ff6c20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/rax1.s b/llvm/test/MC/AArch64/SVE2/rax1.s
index 2ff91f1b8859f..c110d0a83b1c1 100644
--- a/llvm/test/MC/AArch64/SVE2/rax1.s
+++ b/llvm/test/MC/AArch64/SVE2/rax1.s
@@ -14,4 +14,4 @@ rax1 z0.d, z1.d, z31.d
 // CHECK-INST: rax1 z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xf4,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2-sha3
-// CHECK-UNKNOWN: 20 f4 3f 45 <unknown>
+// CHECK-UNKNOWN: 453ff420 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/rshrnb.s b/llvm/test/MC/AArch64/SVE2/rshrnb.s
index 605364e3e369a..0d6b618f7885f 100644
--- a/llvm/test/MC/AArch64/SVE2/rshrnb.s
+++ b/llvm/test/MC/AArch64/SVE2/rshrnb.s
@@ -13,34 +13,34 @@ rshrnb     z0.b, z0.h, #1
 // CHECK-INST: rshrnb	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x18,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 18 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f1800 <unknown>
 
 rshrnb     z31.b, z31.h, #8
 // CHECK-INST: rshrnb	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x1b,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 1b 28 45 <unknown>
+// CHECK-UNKNOWN: 45281bff <unknown>
 
 rshrnb     z0.h, z0.s, #1
 // CHECK-INST: rshrnb	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x18,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 18 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f1800 <unknown>
 
 rshrnb     z31.h, z31.s, #16
 // CHECK-INST: rshrnb	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x1b,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 1b 30 45 <unknown>
+// CHECK-UNKNOWN: 45301bff <unknown>
 
 rshrnb     z0.s, z0.d, #1
 // CHECK-INST: rshrnb	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x18,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 18 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f1800 <unknown>
 
 rshrnb     z31.s, z31.d, #32
 // CHECK-INST: rshrnb	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x1b,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 1b 60 45 <unknown>
+// CHECK-UNKNOWN: 45601bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/rshrnt.s b/llvm/test/MC/AArch64/SVE2/rshrnt.s
index f981a6f612b31..805f17498c084 100644
--- a/llvm/test/MC/AArch64/SVE2/rshrnt.s
+++ b/llvm/test/MC/AArch64/SVE2/rshrnt.s
@@ -13,34 +13,34 @@ rshrnt     z0.b, z0.h, #1
 // CHECK-INST: rshrnt	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x1c,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 1c 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f1c00 <unknown>
 
 rshrnt     z31.b, z31.h, #8
 // CHECK-INST: rshrnt	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x1f,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 1f 28 45 <unknown>
+// CHECK-UNKNOWN: 45281fff <unknown>
 
 rshrnt     z0.h, z0.s, #1
 // CHECK-INST: rshrnt	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x1c,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 1c 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f1c00 <unknown>
 
 rshrnt     z31.h, z31.s, #16
 // CHECK-INST: rshrnt	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x1f,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 1f 30 45 <unknown>
+// CHECK-UNKNOWN: 45301fff <unknown>
 
 rshrnt     z0.s, z0.d, #1
 // CHECK-INST: rshrnt	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x1c,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 1c 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f1c00 <unknown>
 
 rshrnt     z31.s, z31.d, #32
 // CHECK-INST: rshrnt	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x1f,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 1f 60 45 <unknown>
+// CHECK-UNKNOWN: 45601fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/rsubhnb.s b/llvm/test/MC/AArch64/SVE2/rsubhnb.s
index 574c0f2657079..74c181cdfc22f 100644
--- a/llvm/test/MC/AArch64/SVE2/rsubhnb.s
+++ b/llvm/test/MC/AArch64/SVE2/rsubhnb.s
@@ -14,16 +14,16 @@ rsubhnb z0.b, z1.h, z31.h
 // CHECK-INST: rsubhnb	z0.b, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x78,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 78 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f7820 <unknown>
 
 rsubhnb z0.h, z1.s, z31.s
 // CHECK-INST: rsubhnb	z0.h, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x78,0xbf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 78 bf 45 <unknown>
+// CHECK-UNKNOWN: 45bf7820 <unknown>
 
 rsubhnb z0.s, z1.d, z31.d
 // CHECK-INST: rsubhnb	z0.s, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x78,0xff,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 78 ff 45 <unknown>
+// CHECK-UNKNOWN: 45ff7820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/rsubhnt.s b/llvm/test/MC/AArch64/SVE2/rsubhnt.s
index 071382659913a..ece20ad49a7b6 100644
--- a/llvm/test/MC/AArch64/SVE2/rsubhnt.s
+++ b/llvm/test/MC/AArch64/SVE2/rsubhnt.s
@@ -14,16 +14,16 @@ rsubhnt z0.b, z1.h, z31.h
 // CHECK-INST: rsubhnt	z0.b, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x7c,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 7c 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f7c20 <unknown>
 
 rsubhnt z0.h, z1.s, z31.s
 // CHECK-INST: rsubhnt	z0.h, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x7c,0xbf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 7c bf 45 <unknown>
+// CHECK-UNKNOWN: 45bf7c20 <unknown>
 
 rsubhnt z0.s, z1.d, z31.d
 // CHECK-INST: rsubhnt	z0.s, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x7c,0xff,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 7c ff 45 <unknown>
+// CHECK-UNKNOWN: 45ff7c20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/saba.s b/llvm/test/MC/AArch64/SVE2/saba.s
index a2d0442777e1a..f1cb033afa8a4 100644
--- a/llvm/test/MC/AArch64/SVE2/saba.s
+++ b/llvm/test/MC/AArch64/SVE2/saba.s
@@ -13,25 +13,25 @@ saba z0.b, z1.b, z31.b
 // CHECK-INST: saba z0.b, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0xf8,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f8 1f 45 <unknown>
+// CHECK-UNKNOWN: 451ff820 <unknown>
 
 saba z0.h, z1.h, z31.h
 // CHECK-INST: saba z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0xf8,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f8 5f 45 <unknown>
+// CHECK-UNKNOWN: 455ff820 <unknown>
 
 saba z0.s, z1.s, z31.s
 // CHECK-INST: saba z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xf8,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f8 9f 45 <unknown>
+// CHECK-UNKNOWN: 459ff820 <unknown>
 
 saba z0.d, z1.d, z31.d
 // CHECK-INST: saba z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xf8,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f8 df 45 <unknown>
+// CHECK-UNKNOWN: 45dff820 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,10 +41,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 saba z0.d, z1.d, z31.d
 // CHECK-INST: saba z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xf8,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f8 df 45 <unknown>
+// CHECK-UNKNOWN: 45dff820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sabalb.s b/llvm/test/MC/AArch64/SVE2/sabalb.s
index ab49fe16b9e18..15e73d1443c51 100644
--- a/llvm/test/MC/AArch64/SVE2/sabalb.s
+++ b/llvm/test/MC/AArch64/SVE2/sabalb.s
@@ -14,19 +14,19 @@ sabalb z0.h, z1.b, z31.b
 // CHECK-INST: sabalb	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0xc0,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 c0 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fc020 <unknown>
 
 sabalb z0.s, z1.h, z31.h
 // CHECK-INST: sabalb	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0xc0,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 c0 9f 45 <unknown>
+// CHECK-UNKNOWN: 459fc020 <unknown>
 
 sabalb z0.d, z1.s, z31.s
 // CHECK-INST: sabalb	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xc0,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 c0 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfc020 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -36,10 +36,10 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 sabalb z21.d, z1.s, z31.s
 // CHECK-INST: sabalb	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0xc0,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 c0 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfc035 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sabalt.s b/llvm/test/MC/AArch64/SVE2/sabalt.s
index b07f1d9561e7e..42ecd8034b82f 100644
--- a/llvm/test/MC/AArch64/SVE2/sabalt.s
+++ b/llvm/test/MC/AArch64/SVE2/sabalt.s
@@ -14,19 +14,19 @@ sabalt z0.h, z1.b, z31.b
 // CHECK-INST: sabalt	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0xc4,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 c4 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fc420 <unknown>
 
 sabalt z0.s, z1.h, z31.h
 // CHECK-INST: sabalt	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0xc4,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 c4 9f 45 <unknown>
+// CHECK-UNKNOWN: 459fc420 <unknown>
 
 sabalt z0.d, z1.s, z31.s
 // CHECK-INST: sabalt	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xc4,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 c4 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfc420 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -36,10 +36,10 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 sabalt z21.d, z1.s, z31.s
 // CHECK-INST: sabalt	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0xc4,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 c4 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfc435 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sabdlb.s b/llvm/test/MC/AArch64/SVE2/sabdlb.s
index 5dce17db319e7..27190a93072c3 100644
--- a/llvm/test/MC/AArch64/SVE2/sabdlb.s
+++ b/llvm/test/MC/AArch64/SVE2/sabdlb.s
@@ -14,16 +14,16 @@ sabdlb z0.h, z1.b, z2.b
 // CHECK-INST: sabdlb z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x30,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 30 42 45 <unknown>
+// CHECK-UNKNOWN: 45423020 <unknown>
 
 sabdlb z29.s, z30.h, z31.h
 // CHECK-INST: sabdlb z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x33,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 33 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f33dd <unknown>
 
 sabdlb z31.d, z31.s, z31.s
 // CHECK-INST: sabdlb z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x33,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 33 df 45 <unknown>
+// CHECK-UNKNOWN: 45df33ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sabdlt.s b/llvm/test/MC/AArch64/SVE2/sabdlt.s
index e5ddf00d41ae3..9e6c65fac2fd6 100644
--- a/llvm/test/MC/AArch64/SVE2/sabdlt.s
+++ b/llvm/test/MC/AArch64/SVE2/sabdlt.s
@@ -14,16 +14,16 @@ sabdlt z0.h, z1.b, z2.b
 // CHECK-INST: sabdlt z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x34,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 34 42 45 <unknown>
+// CHECK-UNKNOWN: 45423420 <unknown>
 
 sabdlt z29.s, z30.h, z31.h
 // CHECK-INST: sabdlt z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x37,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 37 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f37dd <unknown>
 
 sabdlt z31.d, z31.s, z31.s
 // CHECK-INST: sabdlt z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x37,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 37 df 45 <unknown>
+// CHECK-UNKNOWN: 45df37ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sadalp.s b/llvm/test/MC/AArch64/SVE2/sadalp.s
index 71036e4de257d..95eb17fedb105 100644
--- a/llvm/test/MC/AArch64/SVE2/sadalp.s
+++ b/llvm/test/MC/AArch64/SVE2/sadalp.s
@@ -13,19 +13,19 @@ sadalp z0.h, p0/m, z1.b
 // CHECK-INST: sadalp z0.h, p0/m, z1.b
 // CHECK-ENCODING: [0x20,0xa0,0x44,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 44 44 <unknown>
+// CHECK-UNKNOWN: 4444a020 <unknown>
 
 sadalp z29.s, p0/m, z30.h
 // CHECK-INST: sadalp z29.s, p0/m, z30.h
 // CHECK-ENCODING: [0xdd,0xa3,0x84,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd a3 84 44 <unknown>
+// CHECK-UNKNOWN: 4484a3dd <unknown>
 
 sadalp z30.d, p7/m, z31.s
 // CHECK-INST: sadalp z30.d, p7/m, z31.s
 // CHECK-ENCODING: [0xfe,0xbf,0xc4,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fe bf c4 44 <unknown>
+// CHECK-UNKNOWN: 44c4bffe <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -34,22 +34,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 sadalp z31.d, p0/m, z30.s
 // CHECK-INST: sadalp z31.d, p0/m, z30.s
 // CHECK-ENCODING: [0xdf,0xa3,0xc4,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df a3 c4 44 <unknown>
+// CHECK-UNKNOWN: 44c4a3df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sadalp z31.d, p0/m, z30.s
 // CHECK-INST: sadalp z31.d, p0/m, z30.s
 // CHECK-ENCODING: [0xdf,0xa3,0xc4,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df a3 c4 44 <unknown>
+// CHECK-UNKNOWN: 44c4a3df <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/saddlb.s b/llvm/test/MC/AArch64/SVE2/saddlb.s
index e054612dd3243..00f32b899271b 100644
--- a/llvm/test/MC/AArch64/SVE2/saddlb.s
+++ b/llvm/test/MC/AArch64/SVE2/saddlb.s
@@ -14,16 +14,16 @@ saddlb z0.h, z1.b, z2.b
 // CHECK-INST: saddlb z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x00,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 00 42 45 <unknown>
+// CHECK-UNKNOWN: 45420020 <unknown>
 
 saddlb z29.s, z30.h, z31.h
 // CHECK-INST: saddlb z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x03,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 03 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f03dd <unknown>
 
 saddlb z31.d, z31.s, z31.s
 // CHECK-INST: saddlb z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x03,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 03 df 45 <unknown>
+// CHECK-UNKNOWN: 45df03ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/saddlbt.s b/llvm/test/MC/AArch64/SVE2/saddlbt.s
index f0162effdcfa4..fb58d7e121412 100644
--- a/llvm/test/MC/AArch64/SVE2/saddlbt.s
+++ b/llvm/test/MC/AArch64/SVE2/saddlbt.s
@@ -14,16 +14,16 @@ saddlbt z0.h, z1.b, z31.b
 // CHECK-INST: saddlbt	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x80,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 5f 45 <unknown>
+// CHECK-UNKNOWN: 455f8020 <unknown>
 
 saddlbt z0.s, z1.h, z31.h
 // CHECK-INST: saddlbt	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x80,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f8020 <unknown>
 
 saddlbt z0.d, z1.s, z31.s
 // CHECK-INST: saddlbt	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x80,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 df 45 <unknown>
+// CHECK-UNKNOWN: 45df8020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/saddlt.s b/llvm/test/MC/AArch64/SVE2/saddlt.s
index c353222bd2f88..479ea936f3766 100644
--- a/llvm/test/MC/AArch64/SVE2/saddlt.s
+++ b/llvm/test/MC/AArch64/SVE2/saddlt.s
@@ -14,16 +14,16 @@ saddlt z0.h, z1.b, z2.b
 // CHECK-INST: saddlt z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x04,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 04 42 45 <unknown>
+// CHECK-UNKNOWN: 45420420 <unknown>
 
 saddlt z29.s, z30.h, z31.h
 // CHECK-INST: saddlt z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x07,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 07 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f07dd <unknown>
 
 saddlt z31.d, z31.s, z31.s
 // CHECK-INST: saddlt z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x07,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 07 df 45 <unknown>
+// CHECK-UNKNOWN: 45df07ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/saddwb.s b/llvm/test/MC/AArch64/SVE2/saddwb.s
index 8cf7b8893791d..46ec5b55bf3d5 100644
--- a/llvm/test/MC/AArch64/SVE2/saddwb.s
+++ b/llvm/test/MC/AArch64/SVE2/saddwb.s
@@ -14,16 +14,16 @@ saddwb z0.h, z1.h, z2.b
 // CHECK-INST: saddwb z0.h, z1.h, z2.b
 // CHECK-ENCODING: [0x20,0x40,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 40 42 45 <unknown>
+// CHECK-UNKNOWN: 45424020 <unknown>
 
 saddwb z29.s, z30.s, z31.h
 // CHECK-INST: saddwb z29.s, z30.s, z31.h
 // CHECK-ENCODING: [0xdd,0x43,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 43 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f43dd <unknown>
 
 saddwb z31.d, z31.d, z31.s
 // CHECK-INST: saddwb z31.d, z31.d, z31.s
 // CHECK-ENCODING: [0xff,0x43,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 43 df 45 <unknown>
+// CHECK-UNKNOWN: 45df43ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/saddwt.s b/llvm/test/MC/AArch64/SVE2/saddwt.s
index e99597f257272..f2fc423a651c5 100644
--- a/llvm/test/MC/AArch64/SVE2/saddwt.s
+++ b/llvm/test/MC/AArch64/SVE2/saddwt.s
@@ -14,16 +14,16 @@ saddwt z0.h, z1.h, z2.b
 // CHECK-INST: saddwt z0.h, z1.h, z2.b
 // CHECK-ENCODING: [0x20,0x44,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 44 42 45 <unknown>
+// CHECK-UNKNOWN: 45424420 <unknown>
 
 saddwt z29.s, z30.s, z31.h
 // CHECK-INST: saddwt z29.s, z30.s, z31.h
 // CHECK-ENCODING: [0xdd,0x47,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 47 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f47dd <unknown>
 
 saddwt z31.d, z31.d, z31.s
 // CHECK-INST: saddwt z31.d, z31.d, z31.s
 // CHECK-ENCODING: [0xff,0x47,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 47 df 45 <unknown>
+// CHECK-UNKNOWN: 45df47ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sbclb.s b/llvm/test/MC/AArch64/SVE2/sbclb.s
index 232d8235f094a..1126523bdebdc 100644
--- a/llvm/test/MC/AArch64/SVE2/sbclb.s
+++ b/llvm/test/MC/AArch64/SVE2/sbclb.s
@@ -13,13 +13,13 @@ sbclb z0.s, z1.s, z31.s
 // CHECK-INST: sbclb z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xd0,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d0 9f 45 <unknown>
+// CHECK-UNKNOWN: 459fd020 <unknown>
 
 sbclb z0.d, z1.d, z31.d
 // CHECK-INST: sbclb z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xd0,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d0 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfd020 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -29,10 +29,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sbclb z0.d, z1.d, z31.d
 // CHECK-INST: sbclb z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xd0,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d0 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfd020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sbclt.s b/llvm/test/MC/AArch64/SVE2/sbclt.s
index de3f5478427b9..4593f68e9c7c4 100644
--- a/llvm/test/MC/AArch64/SVE2/sbclt.s
+++ b/llvm/test/MC/AArch64/SVE2/sbclt.s
@@ -13,13 +13,13 @@ sbclt z0.s, z1.s, z31.s
 // CHECK-INST: sbclt z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xd4,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d4 9f 45 <unknown>
+// CHECK-UNKNOWN: 459fd420 <unknown>
 
 sbclt z0.d, z1.d, z31.d
 // CHECK-INST: sbclt z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xd4,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d4 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfd420 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -29,10 +29,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sbclt z0.d, z1.d, z31.d
 // CHECK-INST: sbclt z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xd4,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d4 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfd420 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/shadd.s b/llvm/test/MC/AArch64/SVE2/shadd.s
index 37899c9c01b5a..807bf099d596b 100644
--- a/llvm/test/MC/AArch64/SVE2/shadd.s
+++ b/llvm/test/MC/AArch64/SVE2/shadd.s
@@ -13,25 +13,25 @@ shadd z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: shadd z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x10,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 10 44 <unknown>
+// CHECK-UNKNOWN: 44108020 <unknown>
 
 shadd z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: shadd z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x50,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 50 44 <unknown>
+// CHECK-UNKNOWN: 44508020 <unknown>
 
 shadd z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: shadd z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x90,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 90 44 <unknown>
+// CHECK-UNKNOWN: 44909fdd <unknown>
 
 shadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: shadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd0,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d0 44 <unknown>
+// CHECK-UNKNOWN: 44d09fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 shadd z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: shadd z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd0,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d0 44 <unknown>
+// CHECK-UNKNOWN: 44d083df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 shadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: shadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd0,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d0 44 <unknown>
+// CHECK-UNKNOWN: 44d09fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/shrnb.s b/llvm/test/MC/AArch64/SVE2/shrnb.s
index f40fe37a4ce9b..c20009ab2e6c5 100644
--- a/llvm/test/MC/AArch64/SVE2/shrnb.s
+++ b/llvm/test/MC/AArch64/SVE2/shrnb.s
@@ -13,34 +13,34 @@ shrnb     z0.b, z0.h, #1
 // CHECK-INST: shrnb	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x10,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 10 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f1000 <unknown>
 
 shrnb     z31.b, z31.h, #8
 // CHECK-INST: shrnb	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x13,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 13 28 45 <unknown>
+// CHECK-UNKNOWN: 452813ff <unknown>
 
 shrnb     z0.h, z0.s, #1
 // CHECK-INST: shrnb	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x10,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 10 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f1000 <unknown>
 
 shrnb     z31.h, z31.s, #16
 // CHECK-INST: shrnb	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x13,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 13 30 45 <unknown>
+// CHECK-UNKNOWN: 453013ff <unknown>
 
 shrnb     z0.s, z0.d, #1
 // CHECK-INST: shrnb	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x10,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 10 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f1000 <unknown>
 
 shrnb     z31.s, z31.d, #32
 // CHECK-INST: shrnb	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x13,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 13 60 45 <unknown>
+// CHECK-UNKNOWN: 456013ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/shrnt.s b/llvm/test/MC/AArch64/SVE2/shrnt.s
index 1d83f8445c1e3..af131384a3e6e 100644
--- a/llvm/test/MC/AArch64/SVE2/shrnt.s
+++ b/llvm/test/MC/AArch64/SVE2/shrnt.s
@@ -13,34 +13,34 @@ shrnt     z0.b, z0.h, #1
 // CHECK-INST: shrnt	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x14,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 14 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f1400 <unknown>
 
 shrnt     z31.b, z31.h, #8
 // CHECK-INST: shrnt	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x17,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 17 28 45 <unknown>
+// CHECK-UNKNOWN: 452817ff <unknown>
 
 shrnt     z0.h, z0.s, #1
 // CHECK-INST: shrnt	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x14,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 14 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f1400 <unknown>
 
 shrnt     z31.h, z31.s, #16
 // CHECK-INST: shrnt	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x17,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 17 30 45 <unknown>
+// CHECK-UNKNOWN: 453017ff <unknown>
 
 shrnt     z0.s, z0.d, #1
 // CHECK-INST: shrnt	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x14,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 14 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f1400 <unknown>
 
 shrnt     z31.s, z31.d, #32
 // CHECK-INST: shrnt	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x17,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 17 60 45 <unknown>
+// CHECK-UNKNOWN: 456017ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/shsub.s b/llvm/test/MC/AArch64/SVE2/shsub.s
index f2784fbd9ebe2..49f39d8859b6d 100644
--- a/llvm/test/MC/AArch64/SVE2/shsub.s
+++ b/llvm/test/MC/AArch64/SVE2/shsub.s
@@ -13,25 +13,25 @@ shsub z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: shsub z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x12,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 12 44 <unknown>
+// CHECK-UNKNOWN: 44128020 <unknown>
 
 shsub z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: shsub z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x52,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 52 44 <unknown>
+// CHECK-UNKNOWN: 44528020 <unknown>
 
 shsub z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: shsub z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x92,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 92 44 <unknown>
+// CHECK-UNKNOWN: 44929fdd <unknown>
 
 shsub z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: shsub z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd2,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d2 44 <unknown>
+// CHECK-UNKNOWN: 44d29fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 shsub z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: shsub z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd2,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d2 44 <unknown>
+// CHECK-UNKNOWN: 44d283df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 shsub z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: shsub z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd2,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d2 44 <unknown>
+// CHECK-UNKNOWN: 44d29fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/shsubr.s b/llvm/test/MC/AArch64/SVE2/shsubr.s
index 8c52f9cc8d8d0..04750390418c9 100644
--- a/llvm/test/MC/AArch64/SVE2/shsubr.s
+++ b/llvm/test/MC/AArch64/SVE2/shsubr.s
@@ -13,25 +13,25 @@ shsubr z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: shsubr z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x16,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 16 44 <unknown>
+// CHECK-UNKNOWN: 44168020 <unknown>
 
 shsubr z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: shsubr z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x56,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 56 44 <unknown>
+// CHECK-UNKNOWN: 44568020 <unknown>
 
 shsubr z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: shsubr z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x96,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 96 44 <unknown>
+// CHECK-UNKNOWN: 44969fdd <unknown>
 
 shsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: shsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd6,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d6 44 <unknown>
+// CHECK-UNKNOWN: 44d69fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 shsubr z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: shsubr z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd6,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d6 44 <unknown>
+// CHECK-UNKNOWN: 44d683df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 shsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: shsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd6,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d6 44 <unknown>
+// CHECK-UNKNOWN: 44d69fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sli.s b/llvm/test/MC/AArch64/SVE2/sli.s
index fea4e392ec314..04516e87e0b90 100644
--- a/llvm/test/MC/AArch64/SVE2/sli.s
+++ b/llvm/test/MC/AArch64/SVE2/sli.s
@@ -13,46 +13,46 @@ sli     z0.b, z0.b, #0
 // CHECK-INST: sli	z0.b, z0.b, #0
 // CHECK-ENCODING: [0x00,0xf4,0x08,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 f4 08 45 <unknown>
+// CHECK-UNKNOWN: 4508f400 <unknown>
 
 sli     z31.b, z31.b, #7
 // CHECK-INST: sli	z31.b, z31.b, #7
 // CHECK-ENCODING: [0xff,0xf7,0x0f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff f7 0f 45 <unknown>
+// CHECK-UNKNOWN: 450ff7ff <unknown>
 
 sli     z0.h, z0.h, #0
 // CHECK-INST: sli	z0.h, z0.h, #0
 // CHECK-ENCODING: [0x00,0xf4,0x10,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 f4 10 45 <unknown>
+// CHECK-UNKNOWN: 4510f400 <unknown>
 
 sli     z31.h, z31.h, #15
 // CHECK-INST: sli	z31.h, z31.h, #15
 // CHECK-ENCODING: [0xff,0xf7,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff f7 1f 45 <unknown>
+// CHECK-UNKNOWN: 451ff7ff <unknown>
 
 sli     z0.s, z0.s, #0
 // CHECK-INST: sli	z0.s, z0.s, #0
 // CHECK-ENCODING: [0x00,0xf4,0x40,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 f4 40 45 <unknown>
+// CHECK-UNKNOWN: 4540f400 <unknown>
 
 sli     z31.s, z31.s, #31
 // CHECK-INST: sli	z31.s, z31.s, #31
 // CHECK-ENCODING: [0xff,0xf7,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff f7 5f 45 <unknown>
+// CHECK-UNKNOWN: 455ff7ff <unknown>
 
 sli     z0.d, z0.d, #0
 // CHECK-INST: sli	z0.d, z0.d, #0
 // CHECK-ENCODING: [0x00,0xf4,0x80,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 f4 80 45 <unknown>
+// CHECK-UNKNOWN: 4580f400 <unknown>
 
 sli     z31.d, z31.d, #63
 // CHECK-INST: sli	z31.d, z31.d, #63
 // CHECK-ENCODING: [0xff,0xf7,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff f7 df 45 <unknown>
+// CHECK-UNKNOWN: 45dff7ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sm4e.s b/llvm/test/MC/AArch64/SVE2/sm4e.s
index 36db12de551e6..329484bc4b4a5 100644
--- a/llvm/test/MC/AArch64/SVE2/sm4e.s
+++ b/llvm/test/MC/AArch64/SVE2/sm4e.s
@@ -14,4 +14,4 @@ sm4e z0.s, z0.s, z31.s
 // CHECK-INST: sm4e z0.s, z0.s, z31.s
 // CHECK-ENCODING: [0xe0,0xe3,0x23,0x45]
 // CHECK-ERROR: instruction requires: sve2-sm4
-// CHECK-UNKNOWN: e0 e3 23 45 <unknown>
+// CHECK-UNKNOWN: 4523e3e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sm4ekey.s b/llvm/test/MC/AArch64/SVE2/sm4ekey.s
index c8a206b8cbb3b..c81e39e19167a 100644
--- a/llvm/test/MC/AArch64/SVE2/sm4ekey.s
+++ b/llvm/test/MC/AArch64/SVE2/sm4ekey.s
@@ -14,4 +14,4 @@ sm4ekey z0.s, z1.s, z31.s
 // CHECK-INST: sm4ekey z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xf0,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2-sm4
-// CHECK-UNKNOWN: 20 f0 3f 45 <unknown>
+// CHECK-UNKNOWN: 453ff020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/smaxp.s b/llvm/test/MC/AArch64/SVE2/smaxp.s
index acf90f092f4c3..3a5eebc71de59 100644
--- a/llvm/test/MC/AArch64/SVE2/smaxp.s
+++ b/llvm/test/MC/AArch64/SVE2/smaxp.s
@@ -13,25 +13,25 @@ smaxp z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: smaxp z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0xa0,0x14,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 14 44 <unknown>
+// CHECK-UNKNOWN: 4414a020 <unknown>
 
 smaxp z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: smaxp z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0xa0,0x54,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 54 44 <unknown>
+// CHECK-UNKNOWN: 4454a020 <unknown>
 
 smaxp z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: smaxp z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0xbf,0x94,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd bf 94 44 <unknown>
+// CHECK-UNKNOWN: 4494bfdd <unknown>
 
 smaxp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df bf d4 44 <unknown>
+// CHECK-UNKNOWN: 44d4bfdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 smaxp z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: smaxp z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xa3,0xd4,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df a3 d4 44 <unknown>
+// CHECK-UNKNOWN: 44d4a3df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 smaxp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: smaxp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xbf,0xd4,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df bf d4 44 <unknown>
+// CHECK-UNKNOWN: 44d4bfdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sminp.s b/llvm/test/MC/AArch64/SVE2/sminp.s
index be78cdfd266d0..180cf31fd21f0 100644
--- a/llvm/test/MC/AArch64/SVE2/sminp.s
+++ b/llvm/test/MC/AArch64/SVE2/sminp.s
@@ -13,25 +13,25 @@ sminp z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: sminp z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0xa0,0x16,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 16 44 <unknown>
+// CHECK-UNKNOWN: 4416a020 <unknown>
 
 sminp z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: sminp z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0xa0,0x56,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 56 44 <unknown>
+// CHECK-UNKNOWN: 4456a020 <unknown>
 
 sminp z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: sminp z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0xbf,0x96,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd bf 96 44 <unknown>
+// CHECK-UNKNOWN: 4496bfdd <unknown>
 
 sminp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df bf d6 44 <unknown>
+// CHECK-UNKNOWN: 44d6bfdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 sminp z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: sminp z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xa3,0xd6,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df a3 d6 44 <unknown>
+// CHECK-UNKNOWN: 44d6a3df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sminp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sminp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xbf,0xd6,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df bf d6 44 <unknown>
+// CHECK-UNKNOWN: 44d6bfdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/smlalb.s b/llvm/test/MC/AArch64/SVE2/smlalb.s
index 542110085e81b..5f4868c01fd3f 100644
--- a/llvm/test/MC/AArch64/SVE2/smlalb.s
+++ b/llvm/test/MC/AArch64/SVE2/smlalb.s
@@ -14,31 +14,31 @@ smlalb z0.h, z1.b, z31.b
 // CHECK-INST: smlalb	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x40,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 40 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f4020 <unknown>
 
 smlalb z0.s, z1.h, z31.h
 // CHECK-INST: smlalb	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x40,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 40 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f4020 <unknown>
 
 smlalb z0.d, z1.s, z31.s
 // CHECK-INST: smlalb	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x40,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 40 df 44 <unknown>
+// CHECK-UNKNOWN: 44df4020 <unknown>
 
 smlalb z0.s, z1.h, z7.h[7]
 // CHECK-INST: smlalb	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x88,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 88 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf8820 <unknown>
 
 smlalb z0.d, z1.s, z15.s[1]
 // CHECK-INST: smlalb	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0x88,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 88 ef 44 <unknown>
+// CHECK-UNKNOWN: 44ef8820 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -48,22 +48,22 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 smlalb z21.d, z1.s, z31.s
 // CHECK-INST: smlalb	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x40,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 40 df 44 <unknown>
+// CHECK-UNKNOWN: 44df4035 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 smlalb   z21.d, z10.s, z5.s[1]
 // CHECK-INST: smlalb   z21.d, z10.s, z5.s[1]
 // CHECK-ENCODING: [0x55,0x89,0xe5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 89 e5 44 <unknown>
+// CHECK-UNKNOWN: 44e58955 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/smlalt.s b/llvm/test/MC/AArch64/SVE2/smlalt.s
index 92a51d946c534..2c1ef7e54d051 100644
--- a/llvm/test/MC/AArch64/SVE2/smlalt.s
+++ b/llvm/test/MC/AArch64/SVE2/smlalt.s
@@ -14,31 +14,31 @@ smlalt z0.h, z1.b, z31.b
 // CHECK-INST: smlalt	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x44,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 44 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f4420 <unknown>
 
 smlalt z0.s, z1.h, z31.h
 // CHECK-INST: smlalt	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x44,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 44 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f4420 <unknown>
 
 smlalt z0.d, z1.s, z31.s
 // CHECK-INST: smlalt	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x44,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 44 df 44 <unknown>
+// CHECK-UNKNOWN: 44df4420 <unknown>
 
 smlalt z0.s, z1.h, z7.h[7]
 // CHECK-INST: smlalt	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x8c,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 8c bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf8c20 <unknown>
 
 smlalt z0.d, z1.s, z15.s[1]
 // CHECK-INST: smlalt	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0x8c,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 8c ef 44 <unknown>
+// CHECK-UNKNOWN: 44ef8c20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -48,22 +48,22 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 smlalt z21.d, z1.s, z31.s
 // CHECK-INST: smlalt	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x44,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 44 df 44 <unknown>
+// CHECK-UNKNOWN: 44df4435 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 smlalt   z21.d, z10.s, z5.s[1]
 // CHECK-INST: smlalt   z21.d, z10.s, z5.s[1]
 // CHECK-ENCODING: [0x55,0x8d,0xe5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 8d e5 44 <unknown>
+// CHECK-UNKNOWN: 44e58d55 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/smlslb.s b/llvm/test/MC/AArch64/SVE2/smlslb.s
index fb29cc63eb2cb..7890a43671527 100644
--- a/llvm/test/MC/AArch64/SVE2/smlslb.s
+++ b/llvm/test/MC/AArch64/SVE2/smlslb.s
@@ -14,31 +14,31 @@ smlslb z0.h, z1.b, z31.b
 // CHECK-INST: smlslb	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x50,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 50 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f5020 <unknown>
 
 smlslb z0.s, z1.h, z31.h
 // CHECK-INST: smlslb	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x50,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 50 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f5020 <unknown>
 
 smlslb z0.d, z1.s, z31.s
 // CHECK-INST: smlslb	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x50,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 50 df 44 <unknown>
+// CHECK-UNKNOWN: 44df5020 <unknown>
 
 smlslb z0.s, z1.h, z7.h[7]
 // CHECK-INST: smlslb	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0xa8,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a8 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bfa820 <unknown>
 
 smlslb z0.d, z1.s, z15.s[1]
 // CHECK-INST: smlslb	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0xa8,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a8 ef 44 <unknown>
+// CHECK-UNKNOWN: 44efa820 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -48,22 +48,22 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 smlslb z21.d, z1.s, z31.s
 // CHECK-INST: smlslb	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x50,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 50 df 44 <unknown>
+// CHECK-UNKNOWN: 44df5035 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 smlslb   z21.d, z10.s, z5.s[1]
 // CHECK-INST: smlslb   z21.d, z10.s, z5.s[1]
 // CHECK-ENCODING: [0x55,0xa9,0xe5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 a9 e5 44 <unknown>
+// CHECK-UNKNOWN: 44e5a955 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/smlslt.s b/llvm/test/MC/AArch64/SVE2/smlslt.s
index 2b7038ec1b4a2..7055648ed400d 100644
--- a/llvm/test/MC/AArch64/SVE2/smlslt.s
+++ b/llvm/test/MC/AArch64/SVE2/smlslt.s
@@ -14,31 +14,31 @@ smlslt z0.h, z1.b, z31.b
 // CHECK-INST: smlslt	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x54,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 54 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f5420 <unknown>
 
 smlslt z0.s, z1.h, z31.h
 // CHECK-INST: smlslt	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x54,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 54 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f5420 <unknown>
 
 smlslt z0.d, z1.s, z31.s
 // CHECK-INST: smlslt	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x54,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 54 df 44 <unknown>
+// CHECK-UNKNOWN: 44df5420 <unknown>
 
 smlslt z0.s, z1.h, z7.h[7]
 // CHECK-INST: smlslt	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0xac,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 ac bf 44 <unknown>
+// CHECK-UNKNOWN: 44bfac20 <unknown>
 
 smlslt z0.d, z1.s, z15.s[1]
 // CHECK-INST: smlslt	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0xac,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 ac ef 44 <unknown>
+// CHECK-UNKNOWN: 44efac20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -48,22 +48,22 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 smlslt z21.d, z1.s, z31.s
 // CHECK-INST: smlslt	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x54,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 54 df 44 <unknown>
+// CHECK-UNKNOWN: 44df5435 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 smlslt   z21.d, z10.s, z5.s[1]
 // CHECK-INST: smlslt   z21.d, z10.s, z5.s[1]
 // CHECK-ENCODING: [0x55,0xad,0xe5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 ad e5 44 <unknown>
+// CHECK-UNKNOWN: 44e5ad55 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/smulh.s b/llvm/test/MC/AArch64/SVE2/smulh.s
index 65ae93b41349b..2446d62cb0c11 100644
--- a/llvm/test/MC/AArch64/SVE2/smulh.s
+++ b/llvm/test/MC/AArch64/SVE2/smulh.s
@@ -13,22 +13,22 @@ smulh z0.b, z1.b, z2.b
 // CHECK-INST: smulh z0.b, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x68,0x22,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 68 22 04 <unknown>
+// CHECK-UNKNOWN: 04226820 <unknown>
 
 smulh z0.h, z1.h, z2.h
 // CHECK-INST: smulh z0.h, z1.h, z2.h
 // CHECK-ENCODING: [0x20,0x68,0x62,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 68 62 04 <unknown>
+// CHECK-UNKNOWN: 04626820 <unknown>
 
 smulh z29.s, z30.s, z31.s
 // CHECK-INST: smulh z29.s, z30.s, z31.s
 // CHECK-ENCODING: [0xdd,0x6b,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 6b bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf6bdd <unknown>
 
 smulh z31.d, z31.d, z31.d
 // CHECK-INST: smulh z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x6b,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 6b ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff6bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/smullb.s b/llvm/test/MC/AArch64/SVE2/smullb.s
index fe83e9f7fd169..3a16a20a7580a 100644
--- a/llvm/test/MC/AArch64/SVE2/smullb.s
+++ b/llvm/test/MC/AArch64/SVE2/smullb.s
@@ -14,28 +14,28 @@ smullb z0.h, z1.b, z2.b
 // CHECK-INST: smullb z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x70,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 70 42 45 <unknown>
+// CHECK-UNKNOWN: 45427020 <unknown>
 
 smullb z29.s, z30.h, z31.h
 // CHECK-INST: smullb z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x73,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 73 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f73dd <unknown>
 
 smullb z31.d, z31.s, z31.s
 // CHECK-INST: smullb z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x73,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 73 df 45 <unknown>
+// CHECK-UNKNOWN: 45df73ff <unknown>
 
 smullb z0.s, z1.h, z7.h[7]
 // CHECK-INST: smullb	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0xc8,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 c8 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bfc820 <unknown>
 
 smullb z0.d, z1.s, z15.s[1]
 // CHECK-INST: smullb	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0xc8,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 c8 ef 44 <unknown>
+// CHECK-UNKNOWN: 44efc820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/smullt.s b/llvm/test/MC/AArch64/SVE2/smullt.s
index 74905f85eff2f..a53a9c9297991 100644
--- a/llvm/test/MC/AArch64/SVE2/smullt.s
+++ b/llvm/test/MC/AArch64/SVE2/smullt.s
@@ -14,28 +14,28 @@ smullt z0.h, z1.b, z2.b
 // CHECK-INST: smullt z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x74,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 74 42 45 <unknown>
+// CHECK-UNKNOWN: 45427420 <unknown>
 
 smullt z29.s, z30.h, z31.h
 // CHECK-INST: smullt z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x77,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 77 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f77dd <unknown>
 
 smullt z31.d, z31.s, z31.s
 // CHECK-INST: smullt z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x77,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 77 df 45 <unknown>
+// CHECK-UNKNOWN: 45df77ff <unknown>
 
 smullt z0.s, z1.h, z7.h[7]
 // CHECK-INST: smullt	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0xcc,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 cc bf 44 <unknown>
+// CHECK-UNKNOWN: 44bfcc20 <unknown>
 
 smullt z0.d, z1.s, z15.s[1]
 // CHECK-INST: smullt	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0xcc,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 cc ef 44 <unknown>
+// CHECK-UNKNOWN: 44efcc20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/splice.s b/llvm/test/MC/AArch64/SVE2/splice.s
index b1a396f0f9464..76a1efaba61a6 100644
--- a/llvm/test/MC/AArch64/SVE2/splice.s
+++ b/llvm/test/MC/AArch64/SVE2/splice.s
@@ -13,22 +13,22 @@ splice  z29.b, p7, { z30.b, z31.b }
 // CHECK-INST: splice  z29.b, p7, { z30.b, z31.b }
 // CHECK-ENCODING: [0xdd,0x9f,0x2d,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 2d 05 <unknown>
+// CHECK-UNKNOWN: 052d9fdd <unknown>
 
 splice  z29.h, p7, { z30.h, z31.h }
 // CHECK-INST: splice  z29.h, p7, { z30.h, z31.h }
 // CHECK-ENCODING: [0xdd,0x9f,0x6d,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 6d 05 <unknown>
+// CHECK-UNKNOWN: 056d9fdd <unknown>
 
 splice  z29.s, p7, { z30.s, z31.s }
 // CHECK-INST: splice  z29.s, p7, { z30.s, z31.s }
 // CHECK-ENCODING: [0xdd,0x9f,0xad,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f ad 05 <unknown>
+// CHECK-UNKNOWN: 05ad9fdd <unknown>
 
 splice  z29.d, p7, { z30.d, z31.d }
 // CHECK-INST: splice  z29.d, p7, { z30.d, z31.d }
 // CHECK-ENCODING: [0xdd,0x9f,0xed,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f ed 05 <unknown>
+// CHECK-UNKNOWN: 05ed9fdd <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqabs.s b/llvm/test/MC/AArch64/SVE2/sqabs.s
index d28899221196e..cfaefbb303cac 100644
--- a/llvm/test/MC/AArch64/SVE2/sqabs.s
+++ b/llvm/test/MC/AArch64/SVE2/sqabs.s
@@ -13,25 +13,25 @@ sqabs z31.b, p7/m, z31.b
 // CHECK-INST: sqabs z31.b, p7/m, z31.b
 // CHECK-ENCODING: [0xff,0xbf,0x08,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff bf 08 44 <unknown>
+// CHECK-UNKNOWN: 4408bfff <unknown>
 
 sqabs z31.h, p7/m, z31.h
 // CHECK-INST: sqabs z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x48,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff bf 48 44 <unknown>
+// CHECK-UNKNOWN: 4448bfff <unknown>
 
 sqabs z31.s, p7/m, z31.s
 // CHECK-INST: sqabs z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x88,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff bf 88 44 <unknown>
+// CHECK-UNKNOWN: 4488bfff <unknown>
 
 sqabs z31.d, p7/m, z31.d
 // CHECK-INST: sqabs z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xc8,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff bf c8 44 <unknown>
+// CHECK-UNKNOWN: 44c8bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z4.s, p7/z, z6.s
 // CHECK-INST: movprfx	z4.s, p7/z, z6.s
 // CHECK-ENCODING: [0xc4,0x3c,0x90,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c 90 04 <unknown>
+// CHECK-UNKNOWN: 04903cc4 <unknown>
 
 sqabs z4.s, p7/m, z31.s
 // CHECK-INST: sqabs z4.s, p7/m, z31.s
 // CHECK-ENCODING: [0xe4,0xbf,0x88,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 bf 88 44 <unknown>
+// CHECK-UNKNOWN: 4488bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 sqabs z4.s, p7/m, z31.s
 // CHECK-INST: sqabs z4.s, p7/m, z31.s
 // CHECK-ENCODING: [0xe4,0xbf,0x88,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 bf 88 44 <unknown>
+// CHECK-UNKNOWN: 4488bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqadd.s b/llvm/test/MC/AArch64/SVE2/sqadd.s
index 9ea1a7b7be77d..b53fe8cc35000 100644
--- a/llvm/test/MC/AArch64/SVE2/sqadd.s
+++ b/llvm/test/MC/AArch64/SVE2/sqadd.s
@@ -13,25 +13,25 @@ sqadd z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: sqadd z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x18,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 18 44 <unknown>
+// CHECK-UNKNOWN: 44188020 <unknown>
 
 sqadd z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: sqadd z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x58,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 58 44 <unknown>
+// CHECK-UNKNOWN: 44588020 <unknown>
 
 sqadd z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: sqadd z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x98,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 98 44 <unknown>
+// CHECK-UNKNOWN: 44989fdd <unknown>
 
 sqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd8,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d8 44 <unknown>
+// CHECK-UNKNOWN: 44d89fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 sqadd z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: sqadd z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd8,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d8 44 <unknown>
+// CHECK-UNKNOWN: 44d883df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd8,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d8 44 <unknown>
+// CHECK-UNKNOWN: 44d89fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqcadd.s b/llvm/test/MC/AArch64/SVE2/sqcadd.s
index 505d640f9e67c..4f412b8821241 100644
--- a/llvm/test/MC/AArch64/SVE2/sqcadd.s
+++ b/llvm/test/MC/AArch64/SVE2/sqcadd.s
@@ -13,49 +13,49 @@ sqcadd   z0.b, z0.b, z0.b, #90
 // CHECK-INST: sqcadd   z0.b, z0.b, z0.b, #90
 // CHECK-ENCODING: [0x00,0xd8,0x01,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 d8 01 45 <unknown>
+// CHECK-UNKNOWN: 4501d800 <unknown>
 
 sqcadd   z0.h, z0.h, z0.h, #90
 // CHECK-INST: sqcadd   z0.h, z0.h, z0.h, #90
 // CHECK-ENCODING: [0x00,0xd8,0x41,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 d8 41 45 <unknown>
+// CHECK-UNKNOWN: 4541d800 <unknown>
 
 sqcadd   z0.s, z0.s, z0.s, #90
 // CHECK-INST: sqcadd   z0.s, z0.s, z0.s, #90
 // CHECK-ENCODING: [0x00,0xd8,0x81,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 d8 81 45 <unknown>
+// CHECK-UNKNOWN: 4581d800 <unknown>
 
 sqcadd   z0.d, z0.d, z0.d, #90
 // CHECK-INST: sqcadd   z0.d, z0.d, z0.d, #90
 // CHECK-ENCODING: [0x00,0xd8,0xc1,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 d8 c1 45 <unknown>
+// CHECK-UNKNOWN: 45c1d800 <unknown>
 
 sqcadd   z31.b, z31.b, z31.b, #270
 // CHECK-INST: sqcadd   z31.b, z31.b, z31.b, #270
 // CHECK-ENCODING: [0xff,0xdf,0x01,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff df 01 45 <unknown>
+// CHECK-UNKNOWN: 4501dfff <unknown>
 
 sqcadd   z31.h, z31.h, z31.h, #270
 // CHECK-INST: sqcadd   z31.h, z31.h, z31.h, #270
 // CHECK-ENCODING: [0xff,0xdf,0x41,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff df 41 45 <unknown>
+// CHECK-UNKNOWN: 4541dfff <unknown>
 
 sqcadd   z31.s, z31.s, z31.s, #270
 // CHECK-INST: sqcadd   z31.s, z31.s, z31.s, #270
 // CHECK-ENCODING: [0xff,0xdf,0x81,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff df 81 45 <unknown>
+// CHECK-UNKNOWN: 4581dfff <unknown>
 
 sqcadd   z31.d, z31.d, z31.d, #270
 // CHECK-INST: sqcadd   z31.d, z31.d, z31.d, #270
 // CHECK-ENCODING: [0xff,0xdf,0xc1,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff df c1 45 <unknown>
+// CHECK-UNKNOWN: 45c1dfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -65,10 +65,10 @@ movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 sqcadd   z4.d, z4.d, z31.d, #270
 // CHECK-INST: sqcadd	z4.d, z4.d, z31.d, #270
 // CHECK-ENCODING: [0xe4,0xdf,0xc1,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 df c1 45 <unknown>
+// CHECK-UNKNOWN: 45c1dfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqdmlalb.s b/llvm/test/MC/AArch64/SVE2/sqdmlalb.s
index ce655a1e61d7c..c4f594be31cbd 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmlalb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmlalb.s
@@ -14,31 +14,31 @@ sqdmlalb z0.h, z1.b, z31.b
 // CHECK-INST: sqdmlalb	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x60,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 60 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f6020 <unknown>
 
 sqdmlalb z0.s, z1.h, z31.h
 // CHECK-INST: sqdmlalb	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x60,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 60 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f6020 <unknown>
 
 sqdmlalb z0.d, z1.s, z31.s
 // CHECK-INST: sqdmlalb	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x60,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 60 df 44 <unknown>
+// CHECK-UNKNOWN: 44df6020 <unknown>
 
 sqdmlalb z0.s, z1.h, z7.h[7]
 // CHECK-INST: sqdmlalb	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x28,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 28 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf2820 <unknown>
 
 sqdmlalb z0.d, z1.s, z15.s[3]
 // CHECK-INST: sqdmlalb	z0.d, z1.s, z15.s[3]
 // CHECK-ENCODING: [0x20,0x28,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 28 ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff2820 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -48,22 +48,22 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 sqdmlalb z21.d, z1.s, z31.s
 // CHECK-INST: sqdmlalb	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x60,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 60 df 44 <unknown>
+// CHECK-UNKNOWN: 44df6035 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 sqdmlalb   z21.d, z10.s, z5.s[1]
 // CHECK-INST: sqdmlalb   z21.d, z10.s, z5.s[1]
 // CHECK-ENCODING: [0x55,0x29,0xe5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 29 e5 44 <unknown>
+// CHECK-UNKNOWN: 44e52955 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqdmlalbt.s b/llvm/test/MC/AArch64/SVE2/sqdmlalbt.s
index d830b2c9e9d25..d9cc23017ab26 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmlalbt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmlalbt.s
@@ -14,19 +14,19 @@ sqdmlalbt z0.h, z1.b, z31.b
 // CHECK-INST: sqdmlalbt	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x08,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 08 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f0820 <unknown>
 
 sqdmlalbt z0.s, z1.h, z31.h
 // CHECK-INST: sqdmlalbt	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x08,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 08 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f0820 <unknown>
 
 sqdmlalbt z0.d, z1.s, z31.s
 // CHECK-INST: sqdmlalbt	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x08,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 08 df 44 <unknown>
+// CHECK-UNKNOWN: 44df0820 <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -35,10 +35,10 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 sqdmlalbt z21.d, z1.s, z31.s
 // CHECK-INST: sqdmlalbt	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x08,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 08 df 44 <unknown>
+// CHECK-UNKNOWN: 44df0835 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqdmlalt.s b/llvm/test/MC/AArch64/SVE2/sqdmlalt.s
index 7aba6eaccfbdd..a189940782011 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmlalt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmlalt.s
@@ -14,31 +14,31 @@ sqdmlalt z0.h, z1.b, z31.b
 // CHECK-INST: sqdmlalt	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x64,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 64 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f6420 <unknown>
 
 sqdmlalt z0.s, z1.h, z31.h
 // CHECK-INST: sqdmlalt	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x64,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 64 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f6420 <unknown>
 
 sqdmlalt z0.d, z1.s, z31.s
 // CHECK-INST: sqdmlalt	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x64,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 64 df 44 <unknown>
+// CHECK-UNKNOWN: 44df6420 <unknown>
 
 sqdmlalt z0.s, z1.h, z7.h[7]
 // CHECK-INST: sqdmlalt	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x2c,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 2c bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf2c20 <unknown>
 
 sqdmlalt z0.d, z1.s, z15.s[3]
 // CHECK-INST: sqdmlalt	z0.d, z1.s, z15.s[3]
 // CHECK-ENCODING: [0x20,0x2c,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 2c ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff2c20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -48,22 +48,22 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 sqdmlalt z21.d, z1.s, z31.s
 // CHECK-INST: sqdmlalt	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x64,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 64 df 44 <unknown>
+// CHECK-UNKNOWN: 44df6435 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 sqdmlalt   z21.d, z10.s, z5.s[1]
 // CHECK-INST: sqdmlalt   z21.d, z10.s, z5.s[1]
 // CHECK-ENCODING: [0x55,0x2d,0xe5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 2d e5 44 <unknown>
+// CHECK-UNKNOWN: 44e52d55 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqdmlslb.s b/llvm/test/MC/AArch64/SVE2/sqdmlslb.s
index 106d55fdb42b0..05d45291591e7 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmlslb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmlslb.s
@@ -14,31 +14,31 @@ sqdmlslb z0.h, z1.b, z31.b
 // CHECK-INST: sqdmlslb	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x68,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 68 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f6820 <unknown>
 
 sqdmlslb z0.s, z1.h, z31.h
 // CHECK-INST: sqdmlslb	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x68,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 68 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f6820 <unknown>
 
 sqdmlslb z0.d, z1.s, z31.s
 // CHECK-INST: sqdmlslb	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x68,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 68 df 44 <unknown>
+// CHECK-UNKNOWN: 44df6820 <unknown>
 
 sqdmlslb z0.s, z1.h, z7.h[7]
 // CHECK-INST: sqdmlslb	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x38,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 38 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf3820 <unknown>
 
 sqdmlslb z0.d, z1.s, z15.s[3]
 // CHECK-INST: sqdmlslb	z0.d, z1.s, z15.s[3]
 // CHECK-ENCODING: [0x20,0x38,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 38 ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff3820 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -48,22 +48,22 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 sqdmlslb z21.d, z1.s, z31.s
 // CHECK-INST: sqdmlslb	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x68,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 68 df 44 <unknown>
+// CHECK-UNKNOWN: 44df6835 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 sqdmlslb   z21.d, z10.s, z5.s[1]
 // CHECK-INST: sqdmlslb   z21.d, z10.s, z5.s[1]
 // CHECK-ENCODING: [0x55,0x39,0xe5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 39 e5 44 <unknown>
+// CHECK-UNKNOWN: 44e53955 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqdmlslbt.s b/llvm/test/MC/AArch64/SVE2/sqdmlslbt.s
index a54499523de9c..ea27e715b6d6c 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmlslbt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmlslbt.s
@@ -14,19 +14,19 @@ sqdmlslbt z0.h, z1.b, z31.b
 // CHECK-INST: sqdmlslbt	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x0c,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 0c 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f0c20 <unknown>
 
 sqdmlslbt z0.s, z1.h, z31.h
 // CHECK-INST: sqdmlslbt	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x0c,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 0c 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f0c20 <unknown>
 
 sqdmlslbt z0.d, z1.s, z31.s
 // CHECK-INST: sqdmlslbt	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x0c,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 0c df 44 <unknown>
+// CHECK-UNKNOWN: 44df0c20 <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -35,10 +35,10 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 sqdmlslbt z21.d, z1.s, z31.s
 // CHECK-INST: sqdmlslbt	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x0c,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 0c df 44 <unknown>
+// CHECK-UNKNOWN: 44df0c35 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqdmlslt.s b/llvm/test/MC/AArch64/SVE2/sqdmlslt.s
index 872c4302ac510..3212f9a483371 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmlslt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmlslt.s
@@ -14,31 +14,31 @@ sqdmlslt z0.h, z1.b, z31.b
 // CHECK-INST: sqdmlslt	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x6c,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 6c 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f6c20 <unknown>
 
 sqdmlslt z0.s, z1.h, z31.h
 // CHECK-INST: sqdmlslt	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x6c,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 6c 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f6c20 <unknown>
 
 sqdmlslt z0.d, z1.s, z31.s
 // CHECK-INST: sqdmlslt	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x6c,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 6c df 44 <unknown>
+// CHECK-UNKNOWN: 44df6c20 <unknown>
 
 sqdmlslt z0.s, z1.h, z7.h[7]
 // CHECK-INST: sqdmlslt	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x3c,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 3c bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf3c20 <unknown>
 
 sqdmlslt z0.d, z1.s, z15.s[3]
 // CHECK-INST: sqdmlslt	z0.d, z1.s, z15.s[3]
 // CHECK-ENCODING: [0x20,0x3c,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 3c ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff3c20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -48,22 +48,22 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 sqdmlslt z21.d, z1.s, z31.s
 // CHECK-INST: sqdmlslt	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x6c,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 6c df 44 <unknown>
+// CHECK-UNKNOWN: 44df6c35 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 sqdmlslt   z21.d, z10.s, z5.s[1]
 // CHECK-INST: sqdmlslt   z21.d, z10.s, z5.s[1]
 // CHECK-ENCODING: [0x55,0x3d,0xe5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 3d e5 44 <unknown>
+// CHECK-UNKNOWN: 44e53d55 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqdmulh.s b/llvm/test/MC/AArch64/SVE2/sqdmulh.s
index 58b1c0f834cd8..7b7648e200b39 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmulh.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmulh.s
@@ -13,40 +13,40 @@ sqdmulh z0.b, z1.b, z2.b
 // CHECK-INST: sqdmulh	z0.b, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x70,0x22,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 70 22 04 <unknown>
+// CHECK-UNKNOWN: 04227020 <unknown>
 
 sqdmulh z0.h, z1.h, z2.h
 // CHECK-INST: sqdmulh	z0.h, z1.h, z2.h
 // CHECK-ENCODING: [0x20,0x70,0x62,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 70 62 04 <unknown>
+// CHECK-UNKNOWN: 04627020 <unknown>
 
 sqdmulh z29.s, z30.s, z31.s
 // CHECK-INST: sqdmulh z29.s, z30.s, z31.s
 // CHECK-ENCODING: [0xdd,0x73,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 73 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf73dd <unknown>
 
 sqdmulh z31.d, z31.d, z31.d
 // CHECK-INST: sqdmulh z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x73,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 73 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff73ff <unknown>
 
 sqdmulh z0.h, z1.h, z7.h[7]
 // CHECK-INST: sqdmulh	z0.h, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0xf0,0x7f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f0 7f 44 <unknown>
+// CHECK-UNKNOWN: 447ff020 <unknown>
 
 sqdmulh z0.s, z1.s, z7.s[3]
 // CHECK-INST: sqdmulh	z0.s, z1.s, z7.s[3]
 // CHECK-ENCODING: [0x20,0xf0,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f0 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bff020 <unknown>
 
 sqdmulh z0.d, z1.d, z15.d[1]
 // CHECK-INST: sqdmulh	z0.d, z1.d, z15.d[1]
 // CHECK-ENCODING: [0x20,0xf0,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f0 ff 44 <unknown>
+// CHECK-UNKNOWN: 44fff020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqdmullb.s b/llvm/test/MC/AArch64/SVE2/sqdmullb.s
index d6d55efbec527..623043e2bf815 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmullb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmullb.s
@@ -14,28 +14,28 @@ sqdmullb z0.h, z1.b, z2.b
 // CHECK-INST: sqdmullb z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x60,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 60 42 45 <unknown>
+// CHECK-UNKNOWN: 45426020 <unknown>
 
 sqdmullb z29.s, z30.h, z31.h
 // CHECK-INST: sqdmullb z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x63,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 63 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f63dd <unknown>
 
 sqdmullb z31.d, z31.s, z31.s
 // CHECK-INST: sqdmullb z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x63,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 63 df 45 <unknown>
+// CHECK-UNKNOWN: 45df63ff <unknown>
 
 sqdmullb z0.s, z1.h, z7.h[7]
 // CHECK-INST: sqdmullb	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0xe8,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 e8 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bfe820 <unknown>
 
 sqdmullb z0.d, z1.s, z15.s[1]
 // CHECK-INST: sqdmullb	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0xe8,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 e8 ef 44 <unknown>
+// CHECK-UNKNOWN: 44efe820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqdmullt.s b/llvm/test/MC/AArch64/SVE2/sqdmullt.s
index 8755a2127fdd3..9739ae2cf71ff 100644
--- a/llvm/test/MC/AArch64/SVE2/sqdmullt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqdmullt.s
@@ -14,28 +14,28 @@ sqdmullt z0.h, z1.b, z2.b
 // CHECK-INST: sqdmullt z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x64,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 64 42 45 <unknown>
+// CHECK-UNKNOWN: 45426420 <unknown>
 
 sqdmullt z29.s, z30.h, z31.h
 // CHECK-INST: sqdmullt z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x67,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 67 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f67dd <unknown>
 
 sqdmullt z31.d, z31.s, z31.s
 // CHECK-INST: sqdmullt z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x67,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 67 df 45 <unknown>
+// CHECK-UNKNOWN: 45df67ff <unknown>
 
 sqdmullt z0.s, z1.h, z7.h[7]
 // CHECK-INST: sqdmullt	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0xec,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 ec bf 44 <unknown>
+// CHECK-UNKNOWN: 44bfec20 <unknown>
 
 sqdmullt z0.d, z1.s, z15.s[1]
 // CHECK-INST: sqdmullt	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0xec,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 ec ef 44 <unknown>
+// CHECK-UNKNOWN: 44efec20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqneg.s b/llvm/test/MC/AArch64/SVE2/sqneg.s
index 95457a20d0650..d3b525b64970b 100644
--- a/llvm/test/MC/AArch64/SVE2/sqneg.s
+++ b/llvm/test/MC/AArch64/SVE2/sqneg.s
@@ -13,25 +13,25 @@ sqneg z31.b, p7/m, z31.b
 // CHECK-INST: sqneg z31.b, p7/m, z31.b
 // CHECK-ENCODING: [0xff,0xbf,0x09,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff bf 09 44 <unknown>
+// CHECK-UNKNOWN: 4409bfff <unknown>
 
 sqneg z31.h, p7/m, z31.h
 // CHECK-INST: sqneg z31.h, p7/m, z31.h
 // CHECK-ENCODING: [0xff,0xbf,0x49,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff bf 49 44 <unknown>
+// CHECK-UNKNOWN: 4449bfff <unknown>
 
 sqneg z31.s, p7/m, z31.s
 // CHECK-INST: sqneg z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x89,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff bf 89 44 <unknown>
+// CHECK-UNKNOWN: 4489bfff <unknown>
 
 sqneg z31.d, p7/m, z31.d
 // CHECK-INST: sqneg z31.d, p7/m, z31.d
 // CHECK-ENCODING: [0xff,0xbf,0xc9,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff bf c9 44 <unknown>
+// CHECK-UNKNOWN: 44c9bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,22 +41,22 @@ movprfx z4.s, p7/z, z6.s
 // CHECK-INST: movprfx	z4.s, p7/z, z6.s
 // CHECK-ENCODING: [0xc4,0x3c,0x90,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c 90 04 <unknown>
+// CHECK-UNKNOWN: 04903cc4 <unknown>
 
 sqneg z4.s, p7/m, z31.s
 // CHECK-INST: sqneg z4.s, p7/m, z31.s
 // CHECK-ENCODING: [0xe4,0xbf,0x89,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 bf 89 44 <unknown>
+// CHECK-UNKNOWN: 4489bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 sqneg z4.s, p7/m, z31.s
 // CHECK-INST: sqneg z4.s, p7/m, z31.s
 // CHECK-ENCODING: [0xe4,0xbf,0x89,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 bf 89 44 <unknown>
+// CHECK-UNKNOWN: 4489bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqrdcmlah.s b/llvm/test/MC/AArch64/SVE2/sqrdcmlah.s
index 6dd1d8861a8a7..7f067913c3ce6 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrdcmlah.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrdcmlah.s
@@ -13,121 +13,121 @@ sqrdcmlah   z0.b, z1.b, z2.b, #0
 // CHECK-INST: sqrdcmlah   z0.b, z1.b, z2.b, #0
 // CHECK-ENCODING: [0x20,0x30,0x02,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 30 02 44 <unknown>
+// CHECK-UNKNOWN: 44023020 <unknown>
 
 sqrdcmlah   z0.h, z1.h, z2.h, #0
 // CHECK-INST: sqrdcmlah   z0.h, z1.h, z2.h, #0
 // CHECK-ENCODING: [0x20,0x30,0x42,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 30 42 44 <unknown>
+// CHECK-UNKNOWN: 44423020 <unknown>
 
 sqrdcmlah   z0.s, z1.s, z2.s, #0
 // CHECK-INST: sqrdcmlah   z0.s, z1.s, z2.s, #0
 // CHECK-ENCODING: [0x20,0x30,0x82,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 30 82 44 <unknown>
+// CHECK-UNKNOWN: 44823020 <unknown>
 
 sqrdcmlah   z0.d, z1.d, z2.d, #0
 // CHECK-INST: sqrdcmlah   z0.d, z1.d, z2.d, #0
 // CHECK-ENCODING: [0x20,0x30,0xc2,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 30 c2 44 <unknown>
+// CHECK-UNKNOWN: 44c23020 <unknown>
 
 sqrdcmlah   z29.b, z30.b, z31.b, #90
 // CHECK-INST: sqrdcmlah   z29.b, z30.b, z31.b, #90
 // CHECK-ENCODING: [0xdd,0x37,0x1f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 37 1f 44 <unknown>
+// CHECK-UNKNOWN: 441f37dd <unknown>
 
 sqrdcmlah   z29.h, z30.h, z31.h, #90
 // CHECK-INST: sqrdcmlah   z29.h, z30.h, z31.h, #90
 // CHECK-ENCODING: [0xdd,0x37,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 37 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f37dd <unknown>
 
 sqrdcmlah   z29.s, z30.s, z31.s, #90
 // CHECK-INST: sqrdcmlah   z29.s, z30.s, z31.s, #90
 // CHECK-ENCODING: [0xdd,0x37,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 37 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f37dd <unknown>
 
 sqrdcmlah   z29.d, z30.d, z31.d, #90
 // CHECK-INST: sqrdcmlah   z29.d, z30.d, z31.d, #90
 // CHECK-ENCODING: [0xdd,0x37,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 37 df 44 <unknown>
+// CHECK-UNKNOWN: 44df37dd <unknown>
 
 sqrdcmlah   z31.b, z31.b, z31.b, #180
 // CHECK-INST: sqrdcmlah   z31.b, z31.b, z31.b, #180
 // CHECK-ENCODING: [0xff,0x3b,0x1f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 3b 1f 44 <unknown>
+// CHECK-UNKNOWN: 441f3bff <unknown>
 
 sqrdcmlah   z31.h, z31.h, z31.h, #180
 // CHECK-INST: sqrdcmlah   z31.h, z31.h, z31.h, #180
 // CHECK-ENCODING: [0xff,0x3b,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 3b 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f3bff <unknown>
 
 sqrdcmlah   z31.s, z31.s, z31.s, #180
 // CHECK-INST: sqrdcmlah   z31.s, z31.s, z31.s, #180
 // CHECK-ENCODING: [0xff,0x3b,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 3b 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f3bff <unknown>
 
 sqrdcmlah   z31.d, z31.d, z31.d, #180
 // CHECK-INST: sqrdcmlah   z31.d, z31.d, z31.d, #180
 // CHECK-ENCODING: [0xff,0x3b,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 3b df 44 <unknown>
+// CHECK-UNKNOWN: 44df3bff <unknown>
 
 sqrdcmlah   z15.b, z16.b, z17.b, #270
 // CHECK-INST: sqrdcmlah   z15.b, z16.b, z17.b, #270
 // CHECK-ENCODING: [0x0f,0x3e,0x11,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 3e 11 44 <unknown>
+// CHECK-UNKNOWN: 44113e0f <unknown>
 
 sqrdcmlah   z15.h, z16.h, z17.h, #270
 // CHECK-INST: sqrdcmlah   z15.h, z16.h, z17.h, #270
 // CHECK-ENCODING: [0x0f,0x3e,0x51,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 3e 51 44 <unknown>
+// CHECK-UNKNOWN: 44513e0f <unknown>
 
 sqrdcmlah   z15.s, z16.s, z17.s, #270
 // CHECK-INST: sqrdcmlah   z15.s, z16.s, z17.s, #270
 // CHECK-ENCODING: [0x0f,0x3e,0x91,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 3e 91 44 <unknown>
+// CHECK-UNKNOWN: 44913e0f <unknown>
 
 sqrdcmlah   z15.d, z16.d, z17.d, #270
 // CHECK-INST: sqrdcmlah   z15.d, z16.d, z17.d, #270
 // CHECK-ENCODING: [0x0f,0x3e,0xd1,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 3e d1 44 <unknown>
+// CHECK-UNKNOWN: 44d13e0f <unknown>
 
 sqrdcmlah   z0.h, z1.h, z2.h[0], #0
 // CHECK-INST: sqrdcmlah   z0.h, z1.h, z2.h[0], #0
 // CHECK-ENCODING: [0x20,0x70,0xa2,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 70 a2 44 <unknown>
+// CHECK-UNKNOWN: 44a27020 <unknown>
 
 sqrdcmlah   z0.s, z1.s, z2.s[0], #0
 // CHECK-INST: sqrdcmlah   z0.s, z1.s, z2.s[0], #0
 // CHECK-ENCODING: [0x20,0x70,0xe2,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 70 e2 44 <unknown>
+// CHECK-UNKNOWN: 44e27020 <unknown>
 
 sqrdcmlah   z31.h, z30.h, z7.h[0], #180
 // CHECK-INST: sqrdcmlah   z31.h, z30.h, z7.h[0], #180
 // CHECK-ENCODING: [0xdf,0x7b,0xa7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 7b a7 44 <unknown>
+// CHECK-UNKNOWN: 44a77bdf <unknown>
 
 sqrdcmlah   z31.s, z30.s, z7.s[0], #180
 // CHECK-INST: sqrdcmlah   z31.s, z30.s, z7.s[0], #180
 // CHECK-ENCODING: [0xdf,0x7b,0xe7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 7b e7 44 <unknown>
+// CHECK-UNKNOWN: 44e77bdf <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -137,22 +137,22 @@ movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 sqrdcmlah   z4.d, z31.d, z31.d, #270
 // CHECK-INST: sqrdcmlah   z4.d, z31.d, z31.d, #270
 // CHECK-ENCODING: [0xe4,0x3f,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 3f df 44 <unknown>
+// CHECK-UNKNOWN: 44df3fe4 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 sqrdcmlah   z21.s, z10.s, z5.s[1], #90
 // CHECK-INST: sqrdcmlah	z21.s, z10.s, z5.s[1], #90
 // CHECK-ENCODING: [0x55,0x75,0xf5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 75 f5 44 <unknown>
+// CHECK-UNKNOWN: 44f57555 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqrdmlah.s b/llvm/test/MC/AArch64/SVE2/sqrdmlah.s
index 0addb6cb16295..9e65e6815c69a 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrdmlah.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrdmlah.s
@@ -14,43 +14,43 @@ sqrdmlah z0.b, z1.b, z31.b
 // CHECK-INST: sqrdmlah z0.b, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x70,0x1f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 70 1f 44 <unknown>
+// CHECK-UNKNOWN: 441f7020 <unknown>
 
 sqrdmlah z0.h, z1.h, z31.h
 // CHECK-INST: sqrdmlah z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x70,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 70 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f7020 <unknown>
 
 sqrdmlah z0.s, z1.s, z31.s
 // CHECK-INST: sqrdmlah z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x70,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 70 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f7020 <unknown>
 
 sqrdmlah z0.d, z1.d, z31.d
 // CHECK-INST: sqrdmlah z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x70,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 70 df 44 <unknown>
+// CHECK-UNKNOWN: 44df7020 <unknown>
 
 sqrdmlah z0.h, z1.h, z7.h[7]
 // CHECK-INST: sqrdmlah	z0.h, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x10,0x7f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 10 7f 44 <unknown>
+// CHECK-UNKNOWN: 447f1020 <unknown>
 
 sqrdmlah z0.s, z1.s, z7.s[3]
 // CHECK-INST: sqrdmlah	z0.s, z1.s, z7.s[3]
 // CHECK-ENCODING: [0x20,0x10,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 10 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf1020 <unknown>
 
 sqrdmlah z0.d, z1.d, z15.d[1]
 // CHECK-INST: sqrdmlah	z0.d, z1.d, z15.d[1]
 // CHECK-ENCODING: [0x20,0x10,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 10 ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff1020 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -60,22 +60,22 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqrdmlah z0.d, z1.d, z31.d
 // CHECK-INST: sqrdmlah z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x70,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 70 df 44 <unknown>
+// CHECK-UNKNOWN: 44df7020 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqrdmlah z0.d, z1.d, z15.d[1]
 // CHECK-INST: sqrdmlah	z0.d, z1.d, z15.d[1]
 // CHECK-ENCODING: [0x20,0x10,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 10 ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff1020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqrdmlsh.s b/llvm/test/MC/AArch64/SVE2/sqrdmlsh.s
index c75aa96208e09..bd901e1530590 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrdmlsh.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrdmlsh.s
@@ -13,43 +13,43 @@ sqrdmlsh z0.b, z1.b, z31.b
 // CHECK-INST: sqrdmlsh z0.b, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x74,0x1f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 74 1f 44 <unknown>
+// CHECK-UNKNOWN: 441f7420 <unknown>
 
 sqrdmlsh z0.h, z1.h, z31.h
 // CHECK-INST: sqrdmlsh z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x74,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 74 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f7420 <unknown>
 
 sqrdmlsh z0.s, z1.s, z31.s
 // CHECK-INST: sqrdmlsh z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x74,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 74 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f7420 <unknown>
 
 sqrdmlsh z0.d, z1.d, z31.d
 // CHECK-INST: sqrdmlsh z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x74,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 74 df 44 <unknown>
+// CHECK-UNKNOWN: 44df7420 <unknown>
 
 sqrdmlsh z0.h, z1.h, z7.h[7]
 // CHECK-INST: sqrdmlsh	z0.h, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x14,0x7f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 14 7f 44 <unknown>
+// CHECK-UNKNOWN: 447f1420 <unknown>
 
 sqrdmlsh z0.s, z1.s, z7.s[3]
 // CHECK-INST: sqrdmlsh	z0.s, z1.s, z7.s[3]
 // CHECK-ENCODING: [0x20,0x14,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 14 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf1420 <unknown>
 
 sqrdmlsh z0.d, z1.d, z15.d[1]
 // CHECK-INST: sqrdmlsh	z0.d, z1.d, z15.d[1]
 // CHECK-ENCODING: [0x20,0x14,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 14 ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff1420 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -59,22 +59,22 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqrdmlsh z0.d, z1.d, z31.d
 // CHECK-INST: sqrdmlsh z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x74,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 74 df 44 <unknown>
+// CHECK-UNKNOWN: 44df7420 <unknown>
 
 movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 sqrdmlsh z0.d, z1.d, z15.d[1]
 // CHECK-INST: sqrdmlsh	z0.d, z1.d, z15.d[1]
 // CHECK-ENCODING: [0x20,0x14,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 14 ff 44 <unknown>
+// CHECK-UNKNOWN: 44ff1420 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqrdmulh.s b/llvm/test/MC/AArch64/SVE2/sqrdmulh.s
index 1da631b07d26e..7be08191cf60f 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrdmulh.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrdmulh.s
@@ -13,40 +13,40 @@ sqrdmulh z0.b, z1.b, z2.b
 // CHECK-INST: sqrdmulh	z0.b, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x74,0x22,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 74 22 04 <unknown>
+// CHECK-UNKNOWN: 04227420 <unknown>
 
 sqrdmulh z0.h, z1.h, z2.h
 // CHECK-INST: sqrdmulh	z0.h, z1.h, z2.h
 // CHECK-ENCODING: [0x20,0x74,0x62,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 74 62 04 <unknown>
+// CHECK-UNKNOWN: 04627420 <unknown>
 
 sqrdmulh z29.s, z30.s, z31.s
 // CHECK-INST: sqrdmulh z29.s, z30.s, z31.s
 // CHECK-ENCODING: [0xdd,0x77,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 77 bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf77dd <unknown>
 
 sqrdmulh z31.d, z31.d, z31.d
 // CHECK-INST: sqrdmulh z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x77,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 77 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff77ff <unknown>
 
 sqrdmulh z0.h, z1.h, z7.h[7]
 // CHECK-INST: sqrdmulh	z0.h, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0xf4,0x7f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f4 7f 44 <unknown>
+// CHECK-UNKNOWN: 447ff420 <unknown>
 
 sqrdmulh z0.s, z1.s, z7.s[3]
 // CHECK-INST: sqrdmulh	z0.s, z1.s, z7.s[3]
 // CHECK-ENCODING: [0x20,0xf4,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f4 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bff420 <unknown>
 
 sqrdmulh z0.d, z1.d, z15.d[1]
 // CHECK-INST: sqrdmulh	z0.d, z1.d, z15.d[1]
 // CHECK-ENCODING: [0x20,0xf4,0xff,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 f4 ff 44 <unknown>
+// CHECK-UNKNOWN: 44fff420 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqrshl.s b/llvm/test/MC/AArch64/SVE2/sqrshl.s
index 72905896007b6..60c315248e553 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrshl.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrshl.s
@@ -13,25 +13,25 @@ sqrshl z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: sqrshl z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x0a,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 0a 44 <unknown>
+// CHECK-UNKNOWN: 440a8020 <unknown>
 
 sqrshl z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: sqrshl z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x4a,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 4a 44 <unknown>
+// CHECK-UNKNOWN: 444a8020 <unknown>
 
 sqrshl z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: sqrshl z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x8a,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 8a 44 <unknown>
+// CHECK-UNKNOWN: 448a9fdd <unknown>
 
 sqrshl z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqrshl z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xca,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f ca 44 <unknown>
+// CHECK-UNKNOWN: 44ca9fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 sqrshl z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: sqrshl z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xca,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 ca 44 <unknown>
+// CHECK-UNKNOWN: 44ca83df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sqrshl z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqrshl z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xca,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f ca 44 <unknown>
+// CHECK-UNKNOWN: 44ca9fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqrshlr.s b/llvm/test/MC/AArch64/SVE2/sqrshlr.s
index a09e0ea0e5727..dbeedfbfb1ac0 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrshlr.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrshlr.s
@@ -13,25 +13,25 @@ sqrshlr z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: sqrshlr z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x0e,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 0e 44 <unknown>
+// CHECK-UNKNOWN: 440e8020 <unknown>
 
 sqrshlr z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: sqrshlr z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x4e,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 4e 44 <unknown>
+// CHECK-UNKNOWN: 444e8020 <unknown>
 
 sqrshlr z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: sqrshlr z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x8e,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 8e 44 <unknown>
+// CHECK-UNKNOWN: 448e9fdd <unknown>
 
 sqrshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqrshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xce,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f ce 44 <unknown>
+// CHECK-UNKNOWN: 44ce9fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 sqrshlr z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: sqrshlr z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xce,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 ce 44 <unknown>
+// CHECK-UNKNOWN: 44ce83df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sqrshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqrshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xce,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f ce 44 <unknown>
+// CHECK-UNKNOWN: 44ce9fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqrshrnb.s b/llvm/test/MC/AArch64/SVE2/sqrshrnb.s
index 83719834789bf..265cb9d897ab1 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrshrnb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrshrnb.s
@@ -13,34 +13,34 @@ sqrshrnb     z0.b, z0.h, #1
 // CHECK-INST: sqrshrnb	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x28,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 28 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f2800 <unknown>
 
 sqrshrnb     z31.b, z31.h, #8
 // CHECK-INST: sqrshrnb	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x2b,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2b 28 45 <unknown>
+// CHECK-UNKNOWN: 45282bff <unknown>
 
 sqrshrnb     z0.h, z0.s, #1
 // CHECK-INST: sqrshrnb	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x28,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 28 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f2800 <unknown>
 
 sqrshrnb     z31.h, z31.s, #16
 // CHECK-INST: sqrshrnb	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x2b,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2b 30 45 <unknown>
+// CHECK-UNKNOWN: 45302bff <unknown>
 
 sqrshrnb     z0.s, z0.d, #1
 // CHECK-INST: sqrshrnb	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x28,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 28 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f2800 <unknown>
 
 sqrshrnb     z31.s, z31.d, #32
 // CHECK-INST: sqrshrnb	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x2b,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2b 60 45 <unknown>
+// CHECK-UNKNOWN: 45602bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqrshrnt.s b/llvm/test/MC/AArch64/SVE2/sqrshrnt.s
index 598c4c05f6355..c167595baabae 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrshrnt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrshrnt.s
@@ -13,34 +13,34 @@ sqrshrnt     z0.b, z0.h, #1
 // CHECK-INST: sqrshrnt	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x2c,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 2c 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f2c00 <unknown>
 
 sqrshrnt     z31.b, z31.h, #8
 // CHECK-INST: sqrshrnt	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x2f,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2f 28 45 <unknown>
+// CHECK-UNKNOWN: 45282fff <unknown>
 
 sqrshrnt     z0.h, z0.s, #1
 // CHECK-INST: sqrshrnt	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x2c,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 2c 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f2c00 <unknown>
 
 sqrshrnt     z31.h, z31.s, #16
 // CHECK-INST: sqrshrnt	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x2f,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2f 30 45 <unknown>
+// CHECK-UNKNOWN: 45302fff <unknown>
 
 sqrshrnt     z0.s, z0.d, #1
 // CHECK-INST: sqrshrnt	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x2c,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 2c 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f2c00 <unknown>
 
 sqrshrnt     z31.s, z31.d, #32
 // CHECK-INST: sqrshrnt	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x2f,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2f 60 45 <unknown>
+// CHECK-UNKNOWN: 45602fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqrshrunb.s b/llvm/test/MC/AArch64/SVE2/sqrshrunb.s
index 69cb47d2e374f..ac7a5ff445315 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrshrunb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrshrunb.s
@@ -13,34 +13,34 @@ sqrshrunb     z0.b, z0.h, #1
 // CHECK-INST: sqrshrunb	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x08,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 08 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f0800 <unknown>
 
 sqrshrunb     z31.b, z31.h, #8
 // CHECK-INST: sqrshrunb	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x0b,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 0b 28 45 <unknown>
+// CHECK-UNKNOWN: 45280bff <unknown>
 
 sqrshrunb     z0.h, z0.s, #1
 // CHECK-INST: sqrshrunb	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x08,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 08 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f0800 <unknown>
 
 sqrshrunb     z31.h, z31.s, #16
 // CHECK-INST: sqrshrunb	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x0b,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 0b 30 45 <unknown>
+// CHECK-UNKNOWN: 45300bff <unknown>
 
 sqrshrunb     z0.s, z0.d, #1
 // CHECK-INST: sqrshrunb	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x08,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 08 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f0800 <unknown>
 
 sqrshrunb     z31.s, z31.d, #32
 // CHECK-INST: sqrshrunb	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x0b,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 0b 60 45 <unknown>
+// CHECK-UNKNOWN: 45600bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqrshrunt.s b/llvm/test/MC/AArch64/SVE2/sqrshrunt.s
index 377f960454261..cbf377eeb37b8 100644
--- a/llvm/test/MC/AArch64/SVE2/sqrshrunt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqrshrunt.s
@@ -13,34 +13,34 @@ sqrshrunt     z0.b, z0.h, #1
 // CHECK-INST: sqrshrunt	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x0c,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 0c 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f0c00 <unknown>
 
 sqrshrunt     z31.b, z31.h, #8
 // CHECK-INST: sqrshrunt	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x0f,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 0f 28 45 <unknown>
+// CHECK-UNKNOWN: 45280fff <unknown>
 
 sqrshrunt     z0.h, z0.s, #1
 // CHECK-INST: sqrshrunt	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x0c,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 0c 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f0c00 <unknown>
 
 sqrshrunt     z31.h, z31.s, #16
 // CHECK-INST: sqrshrunt	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x0f,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 0f 30 45 <unknown>
+// CHECK-UNKNOWN: 45300fff <unknown>
 
 sqrshrunt     z0.s, z0.d, #1
 // CHECK-INST: sqrshrunt	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x0c,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 0c 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f0c00 <unknown>
 
 sqrshrunt     z31.s, z31.d, #32
 // CHECK-INST: sqrshrunt	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x0f,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 0f 60 45 <unknown>
+// CHECK-UNKNOWN: 45600fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqshl.s b/llvm/test/MC/AArch64/SVE2/sqshl.s
index f5b224211f93b..cfeb7f16181a1 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshl.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshl.s
@@ -13,73 +13,73 @@ sqshl z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: sqshl z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x08,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 08 44 <unknown>
+// CHECK-UNKNOWN: 44088020 <unknown>
 
 sqshl z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: sqshl z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x48,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 48 44 <unknown>
+// CHECK-UNKNOWN: 44488020 <unknown>
 
 sqshl z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: sqshl z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x88,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 88 44 <unknown>
+// CHECK-UNKNOWN: 44889fdd <unknown>
 
 sqshl z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqshl z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xc8,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f c8 44 <unknown>
+// CHECK-UNKNOWN: 44c89fdf <unknown>
 
 sqshl z0.b, p0/m, z0.b, #0
 // CHECK-INST: sqshl z0.b, p0/m, z0.b, #0
 // CHECK-ENCODING: [0x00,0x81,0x06,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 81 06 04 <unknown>
+// CHECK-UNKNOWN: 04068100 <unknown>
 
 sqshl z31.b, p0/m, z31.b, #7
 // CHECK-INST: sqshl z31.b, p0/m, z31.b, #7
 // CHECK-ENCODING: [0xff,0x81,0x06,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 81 06 04 <unknown>
+// CHECK-UNKNOWN: 040681ff <unknown>
 
 sqshl z0.h, p0/m, z0.h, #0
 // CHECK-INST: sqshl z0.h, p0/m, z0.h, #0
 // CHECK-ENCODING: [0x00,0x82,0x06,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 82 06 04 <unknown>
+// CHECK-UNKNOWN: 04068200 <unknown>
 
 sqshl z31.h, p0/m, z31.h, #15
 // CHECK-INST: sqshl z31.h, p0/m, z31.h, #15
 // CHECK-ENCODING: [0xff,0x83,0x06,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 06 04 <unknown>
+// CHECK-UNKNOWN: 040683ff <unknown>
 
 sqshl z0.s, p0/m, z0.s, #0
 // CHECK-INST: sqshl z0.s, p0/m, z0.s, #0
 // CHECK-ENCODING: [0x00,0x80,0x46,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 80 46 04 <unknown>
+// CHECK-UNKNOWN: 04468000 <unknown>
 
 sqshl z31.s, p0/m, z31.s, #31
 // CHECK-INST: sqshl z31.s, p0/m, z31.s, #31
 // CHECK-ENCODING: [0xff,0x83,0x46,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 46 04 <unknown>
+// CHECK-UNKNOWN: 044683ff <unknown>
 
 sqshl z0.d, p0/m, z0.d, #0
 // CHECK-INST: sqshl z0.d, p0/m, z0.d, #0
 // CHECK-ENCODING: [0x00,0x80,0x86,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 80 86 04 <unknown>
+// CHECK-UNKNOWN: 04868000 <unknown>
 
 sqshl z31.d, p0/m, z31.d, #63
 // CHECK-INST: sqshl z31.d, p0/m, z31.d, #63
 // CHECK-ENCODING: [0xff,0x83,0xc6,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 c6 04 <unknown>
+// CHECK-UNKNOWN: 04c683ff <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -88,46 +88,46 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 sqshl z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: sqshl z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xc8,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 c8 44 <unknown>
+// CHECK-UNKNOWN: 44c883df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sqshl z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqshl z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xc8,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f c8 44 <unknown>
+// CHECK-UNKNOWN: 44c89fdf <unknown>
 
 movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 sqshl z31.d, p0/m, z31.d, #63
 // CHECK-INST: sqshl z31.d, p0/m, z31.d, #63
 // CHECK-ENCODING: [0xff,0x83,0xc6,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 c6 04 <unknown>
+// CHECK-UNKNOWN: 04c683ff <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sqshl z31.d, p0/m, z31.d, #63
 // CHECK-INST: sqshl z31.d, p0/m, z31.d, #63
 // CHECK-ENCODING: [0xff,0x83,0xc6,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 c6 04 <unknown>
+// CHECK-UNKNOWN: 04c683ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqshlr.s b/llvm/test/MC/AArch64/SVE2/sqshlr.s
index 224a5506fbe32..c2c1f2cec207f 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshlr.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshlr.s
@@ -13,25 +13,25 @@ sqshlr z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: sqshlr z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x0c,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 0c 44 <unknown>
+// CHECK-UNKNOWN: 440c8020 <unknown>
 
 sqshlr z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: sqshlr z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x4c,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 4c 44 <unknown>
+// CHECK-UNKNOWN: 444c8020 <unknown>
 
 sqshlr z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: sqshlr z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x8c,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 8c 44 <unknown>
+// CHECK-UNKNOWN: 448c9fdd <unknown>
 
 sqshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xcc,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f cc 44 <unknown>
+// CHECK-UNKNOWN: 44cc9fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 sqshlr z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: sqshlr z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xcc,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 cc 44 <unknown>
+// CHECK-UNKNOWN: 44cc83df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sqshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xcc,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f cc 44 <unknown>
+// CHECK-UNKNOWN: 44cc9fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqshlu.s b/llvm/test/MC/AArch64/SVE2/sqshlu.s
index ea5fc98a40255..f3e1a3a13af71 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshlu.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshlu.s
@@ -13,49 +13,49 @@ sqshlu z0.b, p0/m, z0.b, #0
 // CHECK-INST: sqshlu z0.b, p0/m, z0.b, #0
 // CHECK-ENCODING: [0x00,0x81,0x0f,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 81 0f 04 <unknown>
+// CHECK-UNKNOWN: 040f8100 <unknown>
 
 sqshlu z31.b, p0/m, z31.b, #7
 // CHECK-INST: sqshlu z31.b, p0/m, z31.b, #7
 // CHECK-ENCODING: [0xff,0x81,0x0f,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 81 0f 04 <unknown>
+// CHECK-UNKNOWN: 040f81ff <unknown>
 
 sqshlu z0.h, p0/m, z0.h, #0
 // CHECK-INST: sqshlu z0.h, p0/m, z0.h, #0
 // CHECK-ENCODING: [0x00,0x82,0x0f,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 82 0f 04 <unknown>
+// CHECK-UNKNOWN: 040f8200 <unknown>
 
 sqshlu z31.h, p0/m, z31.h, #15
 // CHECK-INST: sqshlu z31.h, p0/m, z31.h, #15
 // CHECK-ENCODING: [0xff,0x83,0x0f,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 0f 04 <unknown>
+// CHECK-UNKNOWN: 040f83ff <unknown>
 
 sqshlu z0.s, p0/m, z0.s, #0
 // CHECK-INST: sqshlu z0.s, p0/m, z0.s, #0
 // CHECK-ENCODING: [0x00,0x80,0x4f,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 80 4f 04 <unknown>
+// CHECK-UNKNOWN: 044f8000 <unknown>
 
 sqshlu z31.s, p0/m, z31.s, #31
 // CHECK-INST: sqshlu z31.s, p0/m, z31.s, #31
 // CHECK-ENCODING: [0xff,0x83,0x4f,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 4f 04 <unknown>
+// CHECK-UNKNOWN: 044f83ff <unknown>
 
 sqshlu z0.d, p0/m, z0.d, #0
 // CHECK-INST: sqshlu z0.d, p0/m, z0.d, #0
 // CHECK-ENCODING: [0x00,0x80,0x8f,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 80 8f 04 <unknown>
+// CHECK-UNKNOWN: 048f8000 <unknown>
 
 sqshlu z31.d, p0/m, z31.d, #63
 // CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63
 // CHECK-ENCODING: [0xff,0x83,0xcf,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 cf 04 <unknown>
+// CHECK-UNKNOWN: 04cf83ff <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -64,22 +64,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 sqshlu z31.d, p0/m, z31.d, #63
 // CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63
 // CHECK-ENCODING: [0xff,0x83,0xcf,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 cf 04 <unknown>
+// CHECK-UNKNOWN: 04cf83ff <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sqshlu z31.d, p0/m, z31.d, #63
 // CHECK-INST: sqshlu z31.d, p0/m, z31.d, #63
 // CHECK-ENCODING: [0xff,0x83,0xcf,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 cf 04 <unknown>
+// CHECK-UNKNOWN: 04cf83ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqshrnb.s b/llvm/test/MC/AArch64/SVE2/sqshrnb.s
index 836b69e5d5ad9..5f3670c2880fd 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshrnb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshrnb.s
@@ -13,34 +13,34 @@ sqshrnb     z0.b, z0.h, #1
 // CHECK-INST: sqshrnb	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x20,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 20 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f2000 <unknown>
 
 sqshrnb     z31.b, z31.h, #8
 // CHECK-INST: sqshrnb	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x23,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 23 28 45 <unknown>
+// CHECK-UNKNOWN: 452823ff <unknown>
 
 sqshrnb     z0.h, z0.s, #1
 // CHECK-INST: sqshrnb	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x20,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 20 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f2000 <unknown>
 
 sqshrnb     z31.h, z31.s, #16
 // CHECK-INST: sqshrnb	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x23,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 23 30 45 <unknown>
+// CHECK-UNKNOWN: 453023ff <unknown>
 
 sqshrnb     z0.s, z0.d, #1
 // CHECK-INST: sqshrnb	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x20,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 20 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f2000 <unknown>
 
 sqshrnb     z31.s, z31.d, #32
 // CHECK-INST: sqshrnb	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x23,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 23 60 45 <unknown>
+// CHECK-UNKNOWN: 456023ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqshrnt.s b/llvm/test/MC/AArch64/SVE2/sqshrnt.s
index 97f546847a08c..b7aea1a4a412c 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshrnt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshrnt.s
@@ -13,34 +13,34 @@ sqshrnt     z0.b, z0.h, #1
 // CHECK-INST: sqshrnt	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x24,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 24 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f2400 <unknown>
 
 sqshrnt     z31.b, z31.h, #8
 // CHECK-INST: sqshrnt	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x27,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 27 28 45 <unknown>
+// CHECK-UNKNOWN: 452827ff <unknown>
 
 sqshrnt     z0.h, z0.s, #1
 // CHECK-INST: sqshrnt	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x24,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 24 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f2400 <unknown>
 
 sqshrnt     z31.h, z31.s, #16
 // CHECK-INST: sqshrnt	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x27,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 27 30 45 <unknown>
+// CHECK-UNKNOWN: 453027ff <unknown>
 
 sqshrnt     z0.s, z0.d, #1
 // CHECK-INST: sqshrnt	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x24,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 24 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f2400 <unknown>
 
 sqshrnt     z31.s, z31.d, #32
 // CHECK-INST: sqshrnt	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x27,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 27 60 45 <unknown>
+// CHECK-UNKNOWN: 456027ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqshrunb.s b/llvm/test/MC/AArch64/SVE2/sqshrunb.s
index c3636f5a1f7e5..1dac60216eedb 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshrunb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshrunb.s
@@ -13,34 +13,34 @@ sqshrunb     z0.b, z0.h, #1
 // CHECK-INST: sqshrunb	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x00,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 00 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f0000 <unknown>
 
 sqshrunb     z31.b, z31.h, #8
 // CHECK-INST: sqshrunb	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x03,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 03 28 45 <unknown>
+// CHECK-UNKNOWN: 452803ff <unknown>
 
 sqshrunb     z0.h, z0.s, #1
 // CHECK-INST: sqshrunb	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x00,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 00 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f0000 <unknown>
 
 sqshrunb     z31.h, z31.s, #16
 // CHECK-INST: sqshrunb	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x03,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 03 30 45 <unknown>
+// CHECK-UNKNOWN: 453003ff <unknown>
 
 sqshrunb     z0.s, z0.d, #1
 // CHECK-INST: sqshrunb	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x00,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 00 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f0000 <unknown>
 
 sqshrunb     z31.s, z31.d, #32
 // CHECK-INST: sqshrunb	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x03,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 03 60 45 <unknown>
+// CHECK-UNKNOWN: 456003ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqshrunt.s b/llvm/test/MC/AArch64/SVE2/sqshrunt.s
index 26222587860a8..b166b58890676 100644
--- a/llvm/test/MC/AArch64/SVE2/sqshrunt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqshrunt.s
@@ -13,34 +13,34 @@ sqshrunt     z0.b, z0.h, #1
 // CHECK-INST: sqshrunt	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x04,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 04 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f0400 <unknown>
 
 sqshrunt     z31.b, z31.h, #8
 // CHECK-INST: sqshrunt	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x07,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 07 28 45 <unknown>
+// CHECK-UNKNOWN: 452807ff <unknown>
 
 sqshrunt     z0.h, z0.s, #1
 // CHECK-INST: sqshrunt	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x04,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 04 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f0400 <unknown>
 
 sqshrunt     z31.h, z31.s, #16
 // CHECK-INST: sqshrunt	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x07,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 07 30 45 <unknown>
+// CHECK-UNKNOWN: 453007ff <unknown>
 
 sqshrunt     z0.s, z0.d, #1
 // CHECK-INST: sqshrunt	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x04,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 04 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f0400 <unknown>
 
 sqshrunt     z31.s, z31.d, #32
 // CHECK-INST: sqshrunt	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x07,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 07 60 45 <unknown>
+// CHECK-UNKNOWN: 456007ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqsub.s b/llvm/test/MC/AArch64/SVE2/sqsub.s
index b192fb3b8a517..7b949554205e0 100644
--- a/llvm/test/MC/AArch64/SVE2/sqsub.s
+++ b/llvm/test/MC/AArch64/SVE2/sqsub.s
@@ -13,25 +13,25 @@ sqsub z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: sqsub z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x1a,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 1a 44 <unknown>
+// CHECK-UNKNOWN: 441a8020 <unknown>
 
 sqsub z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: sqsub z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x5a,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 5a 44 <unknown>
+// CHECK-UNKNOWN: 445a8020 <unknown>
 
 sqsub z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: sqsub z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x9a,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 9a 44 <unknown>
+// CHECK-UNKNOWN: 449a9fdd <unknown>
 
 sqsub z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqsub z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xda,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f da 44 <unknown>
+// CHECK-UNKNOWN: 44da9fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 sqsub z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: sqsub z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xda,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 da 44 <unknown>
+// CHECK-UNKNOWN: 44da83df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sqsub z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqsub z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xda,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f da 44 <unknown>
+// CHECK-UNKNOWN: 44da9fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqsubr.s b/llvm/test/MC/AArch64/SVE2/sqsubr.s
index 903521ae2739b..0030ea64d4da5 100644
--- a/llvm/test/MC/AArch64/SVE2/sqsubr.s
+++ b/llvm/test/MC/AArch64/SVE2/sqsubr.s
@@ -13,25 +13,25 @@ sqsubr z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: sqsubr z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x1e,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 1e 44 <unknown>
+// CHECK-UNKNOWN: 441e8020 <unknown>
 
 sqsubr z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: sqsubr z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x5e,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 5e 44 <unknown>
+// CHECK-UNKNOWN: 445e8020 <unknown>
 
 sqsubr z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: sqsubr z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x9e,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 9e 44 <unknown>
+// CHECK-UNKNOWN: 449e9fdd <unknown>
 
 sqsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xde,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f de 44 <unknown>
+// CHECK-UNKNOWN: 44de9fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 sqsubr z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: sqsubr z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xde,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 de 44 <unknown>
+// CHECK-UNKNOWN: 44de83df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 sqsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: sqsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xde,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f de 44 <unknown>
+// CHECK-UNKNOWN: 44de9fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqxtnb.s b/llvm/test/MC/AArch64/SVE2/sqxtnb.s
index 2ccd27d97f23f..00fc8ea31388f 100644
--- a/llvm/test/MC/AArch64/SVE2/sqxtnb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqxtnb.s
@@ -14,16 +14,16 @@ sqxtnb z0.b, z31.h
 // CHECK-INST: sqxtnb	z0.b, z31.h
 // CHECK-ENCODING: [0xe0,0x43,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 43 28 45 <unknown>
+// CHECK-UNKNOWN: 452843e0 <unknown>
 
 sqxtnb z0.h, z31.s
 // CHECK-INST: sqxtnb	z0.h, z31.s
 // CHECK-ENCODING: [0xe0,0x43,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 43 30 45 <unknown>
+// CHECK-UNKNOWN: 453043e0 <unknown>
 
 sqxtnb z0.s, z31.d
 // CHECK-INST: sqxtnb	z0.s, z31.d
 // CHECK-ENCODING: [0xe0,0x43,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 43 60 45 <unknown>
+// CHECK-UNKNOWN: 456043e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqxtnt.s b/llvm/test/MC/AArch64/SVE2/sqxtnt.s
index a3d9f6160c28a..380a80db07475 100644
--- a/llvm/test/MC/AArch64/SVE2/sqxtnt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqxtnt.s
@@ -14,16 +14,16 @@ sqxtnt z0.b, z31.h
 // CHECK-INST: sqxtnt	z0.b, z31.h
 // CHECK-ENCODING: [0xe0,0x47,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 47 28 45 <unknown>
+// CHECK-UNKNOWN: 452847e0 <unknown>
 
 sqxtnt z0.h, z31.s
 // CHECK-INST: sqxtnt	z0.h, z31.s
 // CHECK-ENCODING: [0xe0,0x47,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 47 30 45 <unknown>
+// CHECK-UNKNOWN: 453047e0 <unknown>
 
 sqxtnt z0.s, z31.d
 // CHECK-INST: sqxtnt	z0.s, z31.d
 // CHECK-ENCODING: [0xe0,0x47,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 47 60 45 <unknown>
+// CHECK-UNKNOWN: 456047e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqxtunb.s b/llvm/test/MC/AArch64/SVE2/sqxtunb.s
index 71e9d4ec2c22a..c273ac9882bc8 100644
--- a/llvm/test/MC/AArch64/SVE2/sqxtunb.s
+++ b/llvm/test/MC/AArch64/SVE2/sqxtunb.s
@@ -14,16 +14,16 @@ sqxtunb z0.b, z31.h
 // CHECK-INST: sqxtunb	z0.b, z31.h
 // CHECK-ENCODING: [0xe0,0x53,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 53 28 45 <unknown>
+// CHECK-UNKNOWN: 452853e0 <unknown>
 
 sqxtunb z0.h, z31.s
 // CHECK-INST: sqxtunb	z0.h, z31.s
 // CHECK-ENCODING: [0xe0,0x53,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 53 30 45 <unknown>
+// CHECK-UNKNOWN: 453053e0 <unknown>
 
 sqxtunb z0.s, z31.d
 // CHECK-INST: sqxtunb	z0.s, z31.d
 // CHECK-ENCODING: [0xe0,0x53,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 53 60 45 <unknown>
+// CHECK-UNKNOWN: 456053e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sqxtunt.s b/llvm/test/MC/AArch64/SVE2/sqxtunt.s
index 99422a430bfe6..9691b15ae5bb5 100644
--- a/llvm/test/MC/AArch64/SVE2/sqxtunt.s
+++ b/llvm/test/MC/AArch64/SVE2/sqxtunt.s
@@ -14,16 +14,16 @@ sqxtunt z0.b, z31.h
 // CHECK-INST: sqxtunt	z0.b, z31.h
 // CHECK-ENCODING: [0xe0,0x57,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 57 28 45 <unknown>
+// CHECK-UNKNOWN: 452857e0 <unknown>
 
 sqxtunt z0.h, z31.s
 // CHECK-INST: sqxtunt	z0.h, z31.s
 // CHECK-ENCODING: [0xe0,0x57,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 57 30 45 <unknown>
+// CHECK-UNKNOWN: 453057e0 <unknown>
 
 sqxtunt z0.s, z31.d
 // CHECK-INST: sqxtunt	z0.s, z31.d
 // CHECK-ENCODING: [0xe0,0x57,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 57 60 45 <unknown>
+// CHECK-UNKNOWN: 456057e0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/srhadd.s b/llvm/test/MC/AArch64/SVE2/srhadd.s
index 84b66ce6ec322..34a329c2e393c 100644
--- a/llvm/test/MC/AArch64/SVE2/srhadd.s
+++ b/llvm/test/MC/AArch64/SVE2/srhadd.s
@@ -13,25 +13,25 @@ srhadd z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: srhadd z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x14,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 14 44 <unknown>
+// CHECK-UNKNOWN: 44148020 <unknown>
 
 srhadd z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: srhadd z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x54,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 54 44 <unknown>
+// CHECK-UNKNOWN: 44548020 <unknown>
 
 srhadd z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: srhadd z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x94,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 94 44 <unknown>
+// CHECK-UNKNOWN: 44949fdd <unknown>
 
 srhadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: srhadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd4,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d4 44 <unknown>
+// CHECK-UNKNOWN: 44d49fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 srhadd z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: srhadd z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd4,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d4 44 <unknown>
+// CHECK-UNKNOWN: 44d483df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 srhadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: srhadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd4,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d4 44 <unknown>
+// CHECK-UNKNOWN: 44d49fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sri.s b/llvm/test/MC/AArch64/SVE2/sri.s
index 5a0681e643b3b..00572dcab9d06 100644
--- a/llvm/test/MC/AArch64/SVE2/sri.s
+++ b/llvm/test/MC/AArch64/SVE2/sri.s
@@ -13,46 +13,46 @@ sri     z0.b, z0.b, #1
 // CHECK-INST: sri	z0.b, z0.b, #1
 // CHECK-ENCODING: [0x00,0xf0,0x0f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 f0 0f 45 <unknown>
+// CHECK-UNKNOWN: 450ff000 <unknown>
 
 sri     z31.b, z31.b, #8
 // CHECK-INST: sri	z31.b, z31.b, #8
 // CHECK-ENCODING: [0xff,0xf3,0x08,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff f3 08 45 <unknown>
+// CHECK-UNKNOWN: 4508f3ff <unknown>
 
 sri     z0.h, z0.h, #1
 // CHECK-INST: sri	z0.h, z0.h, #1
 // CHECK-ENCODING: [0x00,0xf0,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 f0 1f 45 <unknown>
+// CHECK-UNKNOWN: 451ff000 <unknown>
 
 sri     z31.h, z31.h, #16
 // CHECK-INST: sri	z31.h, z31.h, #16
 // CHECK-ENCODING: [0xff,0xf3,0x10,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff f3 10 45 <unknown>
+// CHECK-UNKNOWN: 4510f3ff <unknown>
 
 sri     z0.s, z0.s, #1
 // CHECK-INST: sri	z0.s, z0.s, #1
 // CHECK-ENCODING: [0x00,0xf0,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 f0 5f 45 <unknown>
+// CHECK-UNKNOWN: 455ff000 <unknown>
 
 sri     z31.s, z31.s, #32
 // CHECK-INST: sri	z31.s, z31.s, #32
 // CHECK-ENCODING: [0xff,0xf3,0x40,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff f3 40 45 <unknown>
+// CHECK-UNKNOWN: 4540f3ff <unknown>
 
 sri     z0.d, z0.d, #1
 // CHECK-INST: sri	z0.d, z0.d, #1
 // CHECK-ENCODING: [0x00,0xf0,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 f0 df 45 <unknown>
+// CHECK-UNKNOWN: 45dff000 <unknown>
 
 sri     z31.d, z31.d, #64
 // CHECK-INST: sri	z31.d, z31.d, #64
 // CHECK-ENCODING: [0xff,0xf3,0x80,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff f3 80 45 <unknown>
+// CHECK-UNKNOWN: 4580f3ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/srshl.s b/llvm/test/MC/AArch64/SVE2/srshl.s
index 87188ce1c36ef..bb60301395471 100644
--- a/llvm/test/MC/AArch64/SVE2/srshl.s
+++ b/llvm/test/MC/AArch64/SVE2/srshl.s
@@ -13,25 +13,25 @@ srshl z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: srshl z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x02,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 02 44 <unknown>
+// CHECK-UNKNOWN: 44028020 <unknown>
 
 srshl z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: srshl z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x42,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 42 44 <unknown>
+// CHECK-UNKNOWN: 44428020 <unknown>
 
 srshl z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: srshl z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x82,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 82 44 <unknown>
+// CHECK-UNKNOWN: 44829fdd <unknown>
 
 srshl z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: srshl z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xc2,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f c2 44 <unknown>
+// CHECK-UNKNOWN: 44c29fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 srshl z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: srshl z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xc2,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 c2 44 <unknown>
+// CHECK-UNKNOWN: 44c283df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 srshl z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: srshl z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xc2,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f c2 44 <unknown>
+// CHECK-UNKNOWN: 44c29fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/srshlr.s b/llvm/test/MC/AArch64/SVE2/srshlr.s
index 562ce752c5426..649f03afe0680 100644
--- a/llvm/test/MC/AArch64/SVE2/srshlr.s
+++ b/llvm/test/MC/AArch64/SVE2/srshlr.s
@@ -13,25 +13,25 @@ srshlr z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: srshlr z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x06,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 06 44 <unknown>
+// CHECK-UNKNOWN: 44068020 <unknown>
 
 srshlr z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: srshlr z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x46,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 46 44 <unknown>
+// CHECK-UNKNOWN: 44468020 <unknown>
 
 srshlr z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: srshlr z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x86,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 86 44 <unknown>
+// CHECK-UNKNOWN: 44869fdd <unknown>
 
 srshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: srshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xc6,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f c6 44 <unknown>
+// CHECK-UNKNOWN: 44c69fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 srshlr z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: srshlr z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xc6,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 c6 44 <unknown>
+// CHECK-UNKNOWN: 44c683df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 srshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: srshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xc6,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f c6 44 <unknown>
+// CHECK-UNKNOWN: 44c69fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/srshr.s b/llvm/test/MC/AArch64/SVE2/srshr.s
index ea93a440b6922..ce4236c534c8e 100644
--- a/llvm/test/MC/AArch64/SVE2/srshr.s
+++ b/llvm/test/MC/AArch64/SVE2/srshr.s
@@ -13,49 +13,49 @@ srshr    z0.b, p0/m, z0.b, #1
 // CHECK-INST: srshr	z0.b, p0/m, z0.b, #1
 // CHECK-ENCODING: [0xe0,0x81,0x0c,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 81 0c 04 <unknown>
+// CHECK-UNKNOWN: 040c81e0 <unknown>
 
 srshr    z31.b, p0/m, z31.b, #8
 // CHECK-INST: srshr	z31.b, p0/m, z31.b, #8
 // CHECK-ENCODING: [0x1f,0x81,0x0c,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 81 0c 04 <unknown>
+// CHECK-UNKNOWN: 040c811f <unknown>
 
 srshr    z0.h, p0/m, z0.h, #1
 // CHECK-INST: srshr	z0.h, p0/m, z0.h, #1
 // CHECK-ENCODING: [0xe0,0x83,0x0c,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 83 0c 04 <unknown>
+// CHECK-UNKNOWN: 040c83e0 <unknown>
 
 srshr    z31.h, p0/m, z31.h, #16
 // CHECK-INST: srshr	z31.h, p0/m, z31.h, #16
 // CHECK-ENCODING: [0x1f,0x82,0x0c,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 82 0c 04 <unknown>
+// CHECK-UNKNOWN: 040c821f <unknown>
 
 srshr    z0.s, p0/m, z0.s, #1
 // CHECK-INST: srshr	z0.s, p0/m, z0.s, #1
 // CHECK-ENCODING: [0xe0,0x83,0x4c,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 83 4c 04 <unknown>
+// CHECK-UNKNOWN: 044c83e0 <unknown>
 
 srshr    z31.s, p0/m, z31.s, #32
 // CHECK-INST: srshr	z31.s, p0/m, z31.s, #32
 // CHECK-ENCODING: [0x1f,0x80,0x4c,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 80 4c 04 <unknown>
+// CHECK-UNKNOWN: 044c801f <unknown>
 
 srshr    z0.d, p0/m, z0.d, #1
 // CHECK-INST: srshr	z0.d, p0/m, z0.d, #1
 // CHECK-ENCODING: [0xe0,0x83,0xcc,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 83 cc 04 <unknown>
+// CHECK-UNKNOWN: 04cc83e0 <unknown>
 
 srshr    z31.d, p0/m, z31.d, #64
 // CHECK-INST: srshr	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x8c,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 80 8c 04 <unknown>
+// CHECK-UNKNOWN: 048c801f <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -65,22 +65,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx	z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 srshr    z31.d, p0/m, z31.d, #64
 // CHECK-INST: srshr	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x8c,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 80 8c 04 <unknown>
+// CHECK-UNKNOWN: 048c801f <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 srshr    z31.d, p0/m, z31.d, #64
 // CHECK-INST: srshr	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x8c,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 80 8c 04 <unknown>
+// CHECK-UNKNOWN: 048c801f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/srsra.s b/llvm/test/MC/AArch64/SVE2/srsra.s
index 90fe1ef426ffd..ccb7d891eebb8 100644
--- a/llvm/test/MC/AArch64/SVE2/srsra.s
+++ b/llvm/test/MC/AArch64/SVE2/srsra.s
@@ -13,49 +13,49 @@ srsra     z0.b, z0.b, #1
 // CHECK-INST: srsra	z0.b, z0.b, #1
 // CHECK-ENCODING: [0x00,0xe8,0x0f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 e8 0f 45 <unknown>
+// CHECK-UNKNOWN: 450fe800 <unknown>
 
 srsra     z31.b, z31.b, #8
 // CHECK-INST: srsra	z31.b, z31.b, #8
 // CHECK-ENCODING: [0xff,0xeb,0x08,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff eb 08 45 <unknown>
+// CHECK-UNKNOWN: 4508ebff <unknown>
 
 srsra     z0.h, z0.h, #1
 // CHECK-INST: srsra	z0.h, z0.h, #1
 // CHECK-ENCODING: [0x00,0xe8,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 e8 1f 45 <unknown>
+// CHECK-UNKNOWN: 451fe800 <unknown>
 
 srsra     z31.h, z31.h, #16
 // CHECK-INST: srsra	z31.h, z31.h, #16
 // CHECK-ENCODING: [0xff,0xeb,0x10,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff eb 10 45 <unknown>
+// CHECK-UNKNOWN: 4510ebff <unknown>
 
 srsra     z0.s, z0.s, #1
 // CHECK-INST: srsra	z0.s, z0.s, #1
 // CHECK-ENCODING: [0x00,0xe8,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 e8 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fe800 <unknown>
 
 srsra     z31.s, z31.s, #32
 // CHECK-INST: srsra	z31.s, z31.s, #32
 // CHECK-ENCODING: [0xff,0xeb,0x40,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff eb 40 45 <unknown>
+// CHECK-UNKNOWN: 4540ebff <unknown>
 
 srsra     z0.d, z0.d, #1
 // CHECK-INST: srsra	z0.d, z0.d, #1
 // CHECK-ENCODING: [0x00,0xe8,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 e8 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfe800 <unknown>
 
 srsra     z31.d, z31.d, #64
 // CHECK-INST: srsra	z31.d, z31.d, #64
 // CHECK-ENCODING: [0xff,0xeb,0x80,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff eb 80 45 <unknown>
+// CHECK-UNKNOWN: 4580ebff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -65,10 +65,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 srsra     z0.d, z1.d, #1
 // CHECK-INST: srsra	z0.d, z1.d, #1
 // CHECK-ENCODING: [0x20,0xe8,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 e8 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfe820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sshllb.s b/llvm/test/MC/AArch64/SVE2/sshllb.s
index 54aee28b90090..3e1d24c4983fb 100644
--- a/llvm/test/MC/AArch64/SVE2/sshllb.s
+++ b/llvm/test/MC/AArch64/SVE2/sshllb.s
@@ -13,34 +13,34 @@ sshllb     z0.h, z0.b, #0
 // CHECK-INST: sshllb	z0.h, z0.b, #0
 // CHECK-ENCODING: [0x00,0xa0,0x08,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 a0 08 45 <unknown>
+// CHECK-UNKNOWN: 4508a000 <unknown>
 
 sshllb     z31.h, z31.b, #7
 // CHECK-INST: sshllb	z31.h, z31.b, #7
 // CHECK-ENCODING: [0xff,0xa3,0x0f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff a3 0f 45 <unknown>
+// CHECK-UNKNOWN: 450fa3ff <unknown>
 
 sshllb     z0.s, z0.h, #0
 // CHECK-INST: sshllb	z0.s, z0.h, #0
 // CHECK-ENCODING: [0x00,0xa0,0x10,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 a0 10 45 <unknown>
+// CHECK-UNKNOWN: 4510a000 <unknown>
 
 sshllb     z31.s, z31.h, #15
 // CHECK-INST: sshllb	z31.s, z31.h, #15
 // CHECK-ENCODING: [0xff,0xa3,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff a3 1f 45 <unknown>
+// CHECK-UNKNOWN: 451fa3ff <unknown>
 
 sshllb     z0.d, z0.s, #0
 // CHECK-INST: sshllb	z0.d, z0.s, #0
 // CHECK-ENCODING: [0x00,0xa0,0x40,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 a0 40 45 <unknown>
+// CHECK-UNKNOWN: 4540a000 <unknown>
 
 sshllb     z31.d, z31.s, #31
 // CHECK-INST: sshllb	z31.d, z31.s, #31
 // CHECK-ENCODING: [0xff,0xa3,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff a3 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fa3ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/sshllt.s b/llvm/test/MC/AArch64/SVE2/sshllt.s
index 6dfc8cca61f35..a889bbbf4c4c2 100644
--- a/llvm/test/MC/AArch64/SVE2/sshllt.s
+++ b/llvm/test/MC/AArch64/SVE2/sshllt.s
@@ -13,34 +13,34 @@ sshllt     z0.h, z0.b, #0
 // CHECK-INST: sshllt	z0.h, z0.b, #0
 // CHECK-ENCODING: [0x00,0xa4,0x08,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 a4 08 45 <unknown>
+// CHECK-UNKNOWN: 4508a400 <unknown>
 
 sshllt     z31.h, z31.b, #7
 // CHECK-INST: sshllt	z31.h, z31.b, #7
 // CHECK-ENCODING: [0xff,0xa7,0x0f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff a7 0f 45 <unknown>
+// CHECK-UNKNOWN: 450fa7ff <unknown>
 
 sshllt     z0.s, z0.h, #0
 // CHECK-INST: sshllt	z0.s, z0.h, #0
 // CHECK-ENCODING: [0x00,0xa4,0x10,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 a4 10 45 <unknown>
+// CHECK-UNKNOWN: 4510a400 <unknown>
 
 sshllt     z31.s, z31.h, #15
 // CHECK-INST: sshllt	z31.s, z31.h, #15
 // CHECK-ENCODING: [0xff,0xa7,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff a7 1f 45 <unknown>
+// CHECK-UNKNOWN: 451fa7ff <unknown>
 
 sshllt     z0.d, z0.s, #0
 // CHECK-INST: sshllt	z0.d, z0.s, #0
 // CHECK-ENCODING: [0x00,0xa4,0x40,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 a4 40 45 <unknown>
+// CHECK-UNKNOWN: 4540a400 <unknown>
 
 sshllt     z31.d, z31.s, #31
 // CHECK-INST: sshllt	z31.d, z31.s, #31
 // CHECK-ENCODING: [0xff,0xa7,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff a7 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fa7ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ssra.s b/llvm/test/MC/AArch64/SVE2/ssra.s
index a208dc31e7b92..8e8a7c9e67003 100644
--- a/llvm/test/MC/AArch64/SVE2/ssra.s
+++ b/llvm/test/MC/AArch64/SVE2/ssra.s
@@ -13,49 +13,49 @@ ssra     z0.b, z0.b, #1
 // CHECK-INST: ssra	z0.b, z0.b, #1
 // CHECK-ENCODING: [0x00,0xe0,0x0f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 e0 0f 45 <unknown>
+// CHECK-UNKNOWN: 450fe000 <unknown>
 
 ssra     z31.b, z31.b, #8
 // CHECK-INST: ssra	z31.b, z31.b, #8
 // CHECK-ENCODING: [0xff,0xe3,0x08,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff e3 08 45 <unknown>
+// CHECK-UNKNOWN: 4508e3ff <unknown>
 
 ssra     z0.h, z0.h, #1
 // CHECK-INST: ssra	z0.h, z0.h, #1
 // CHECK-ENCODING: [0x00,0xe0,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 e0 1f 45 <unknown>
+// CHECK-UNKNOWN: 451fe000 <unknown>
 
 ssra     z31.h, z31.h, #16
 // CHECK-INST: ssra	z31.h, z31.h, #16
 // CHECK-ENCODING: [0xff,0xe3,0x10,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff e3 10 45 <unknown>
+// CHECK-UNKNOWN: 4510e3ff <unknown>
 
 ssra     z0.s, z0.s, #1
 // CHECK-INST: ssra	z0.s, z0.s, #1
 // CHECK-ENCODING: [0x00,0xe0,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 e0 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fe000 <unknown>
 
 ssra     z31.s, z31.s, #32
 // CHECK-INST: ssra	z31.s, z31.s, #32
 // CHECK-ENCODING: [0xff,0xe3,0x40,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff e3 40 45 <unknown>
+// CHECK-UNKNOWN: 4540e3ff <unknown>
 
 ssra     z0.d, z0.d, #1
 // CHECK-INST: ssra	z0.d, z0.d, #1
 // CHECK-ENCODING: [0x00,0xe0,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 e0 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfe000 <unknown>
 
 ssra     z31.d, z31.d, #64
 // CHECK-INST: ssra	z31.d, z31.d, #64
 // CHECK-ENCODING: [0xff,0xe3,0x80,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff e3 80 45 <unknown>
+// CHECK-UNKNOWN: 4580e3ff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -65,10 +65,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 ssra     z0.d, z1.d, #1
 // CHECK-INST: ssra	z0.d, z1.d, #1
 // CHECK-ENCODING: [0x20,0xe0,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 e0 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfe020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ssublb.s b/llvm/test/MC/AArch64/SVE2/ssublb.s
index 6e92d5c9ecbdf..937699e6b1787 100644
--- a/llvm/test/MC/AArch64/SVE2/ssublb.s
+++ b/llvm/test/MC/AArch64/SVE2/ssublb.s
@@ -14,16 +14,16 @@ ssublb z0.h, z1.b, z2.b
 // CHECK-INST: ssublb z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x10,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 10 42 45 <unknown>
+// CHECK-UNKNOWN: 45421020 <unknown>
 
 ssublb z29.s, z30.h, z31.h
 // CHECK-INST: ssublb z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x13,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 13 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f13dd <unknown>
 
 ssublb z31.d, z31.s, z31.s
 // CHECK-INST: ssublb z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x13,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 13 df 45 <unknown>
+// CHECK-UNKNOWN: 45df13ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ssublbt.s b/llvm/test/MC/AArch64/SVE2/ssublbt.s
index 6ac6e86a5e914..ab6a52db7434e 100644
--- a/llvm/test/MC/AArch64/SVE2/ssublbt.s
+++ b/llvm/test/MC/AArch64/SVE2/ssublbt.s
@@ -14,16 +14,16 @@ ssublbt z0.h, z1.b, z31.b
 // CHECK-INST: ssublbt	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x88,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 88 5f 45 <unknown>
+// CHECK-UNKNOWN: 455f8820 <unknown>
 
 ssublbt z0.s, z1.h, z31.h
 // CHECK-INST: ssublbt	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x88,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 88 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f8820 <unknown>
 
 ssublbt z0.d, z1.s, z31.s
 // CHECK-INST: ssublbt	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x88,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 88 df 45 <unknown>
+// CHECK-UNKNOWN: 45df8820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ssublt.s b/llvm/test/MC/AArch64/SVE2/ssublt.s
index adb1c8783a59d..262a68dea361f 100644
--- a/llvm/test/MC/AArch64/SVE2/ssublt.s
+++ b/llvm/test/MC/AArch64/SVE2/ssublt.s
@@ -14,16 +14,16 @@ ssublt z0.h, z1.b, z2.b
 // CHECK-INST: ssublt z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x14,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 14 42 45 <unknown>
+// CHECK-UNKNOWN: 45421420 <unknown>
 
 ssublt z29.s, z30.h, z31.h
 // CHECK-INST: ssublt z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x17,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 17 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f17dd <unknown>
 
 ssublt z31.d, z31.s, z31.s
 // CHECK-INST: ssublt z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x17,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 17 df 45 <unknown>
+// CHECK-UNKNOWN: 45df17ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ssubltb.s b/llvm/test/MC/AArch64/SVE2/ssubltb.s
index 9c0fdb494aae5..5fe1437bb345e 100644
--- a/llvm/test/MC/AArch64/SVE2/ssubltb.s
+++ b/llvm/test/MC/AArch64/SVE2/ssubltb.s
@@ -14,16 +14,16 @@ ssubltb z0.h, z1.b, z31.b
 // CHECK-INST: ssubltb	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x8c,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 8c 5f 45 <unknown>
+// CHECK-UNKNOWN: 455f8c20 <unknown>
 
 ssubltb z0.s, z1.h, z31.h
 // CHECK-INST: ssubltb	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x8c,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 8c 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f8c20 <unknown>
 
 ssubltb z0.d, z1.s, z31.s
 // CHECK-INST: ssubltb	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x8c,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 8c df 45 <unknown>
+// CHECK-UNKNOWN: 45df8c20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ssubwb.s b/llvm/test/MC/AArch64/SVE2/ssubwb.s
index fc62aa814e77e..4e8f8761d8e05 100644
--- a/llvm/test/MC/AArch64/SVE2/ssubwb.s
+++ b/llvm/test/MC/AArch64/SVE2/ssubwb.s
@@ -14,16 +14,16 @@ ssubwb z0.h, z1.h, z2.b
 // CHECK-INST: ssubwb z0.h, z1.h, z2.b
 // CHECK-ENCODING: [0x20,0x50,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 50 42 45 <unknown>
+// CHECK-UNKNOWN: 45425020 <unknown>
 
 ssubwb z29.s, z30.s, z31.h
 // CHECK-INST: ssubwb z29.s, z30.s, z31.h
 // CHECK-ENCODING: [0xdd,0x53,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 53 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f53dd <unknown>
 
 ssubwb z31.d, z31.d, z31.s
 // CHECK-INST: ssubwb z31.d, z31.d, z31.s
 // CHECK-ENCODING: [0xff,0x53,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 53 df 45 <unknown>
+// CHECK-UNKNOWN: 45df53ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ssubwt.s b/llvm/test/MC/AArch64/SVE2/ssubwt.s
index de0eec38c40cf..3b6c28900d756 100644
--- a/llvm/test/MC/AArch64/SVE2/ssubwt.s
+++ b/llvm/test/MC/AArch64/SVE2/ssubwt.s
@@ -14,16 +14,16 @@ ssubwt z0.h, z1.h, z2.b
 // CHECK-INST: ssubwt z0.h, z1.h, z2.b
 // CHECK-ENCODING: [0x20,0x54,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 54 42 45 <unknown>
+// CHECK-UNKNOWN: 45425420 <unknown>
 
 ssubwt z29.s, z30.s, z31.h
 // CHECK-INST: ssubwt z29.s, z30.s, z31.h
 // CHECK-ENCODING: [0xdd,0x57,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 57 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f57dd <unknown>
 
 ssubwt z31.d, z31.d, z31.s
 // CHECK-INST: ssubwt z31.d, z31.d, z31.s
 // CHECK-ENCODING: [0xff,0x57,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 57 df 45 <unknown>
+// CHECK-UNKNOWN: 45df57ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/stnt1b.s b/llvm/test/MC/AArch64/SVE2/stnt1b.s
index fb89f5a96e897..c3c0e86b529a1 100644
--- a/llvm/test/MC/AArch64/SVE2/stnt1b.s
+++ b/llvm/test/MC/AArch64/SVE2/stnt1b.s
@@ -13,70 +13,70 @@ stnt1b z0.s, p0, [z1.s]
 // CHECK-INST: stnt1b { z0.s }, p0, [z1.s]
 // CHECK-ENCODING: [0x20,0x20,0x5f,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 5f e4 <unknown>
+// CHECK-UNKNOWN: e45f2020 <unknown>
 
 stnt1b z31.s, p7, [z31.s, xzr]
 // CHECK-INST: stnt1b { z31.s }, p7, [z31.s]
 // CHECK-ENCODING: [0xff,0x3f,0x5f,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 5f e4 <unknown>
+// CHECK-UNKNOWN: e45f3fff <unknown>
 
 stnt1b z31.s, p7, [z31.s, x0]
 // CHECK-INST: stnt1b { z31.s }, p7, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0x3f,0x40,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 40 e4 <unknown>
+// CHECK-UNKNOWN: e4403fff <unknown>
 
 stnt1b z0.d, p0, [z1.d]
 // CHECK-INST: stnt1b { z0.d }, p0, [z1.d]
 // CHECK-ENCODING: [0x20,0x20,0x1f,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 1f e4 <unknown>
+// CHECK-UNKNOWN: e41f2020 <unknown>
 
 stnt1b z31.d, p7, [z31.d, xzr]
 // CHECK-INST: stnt1b { z31.d }, p7, [z31.d]
 // CHECK-ENCODING: [0xff,0x3f,0x1f,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 1f e4 <unknown>
+// CHECK-UNKNOWN: e41f3fff <unknown>
 
 stnt1b z31.d, p7, [z31.d, x0]
 // CHECK-INST: stnt1b { z31.d }, p7, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x3f,0x00,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 00 e4 <unknown>
+// CHECK-UNKNOWN: e4003fff <unknown>
 
 stnt1b { z0.s }, p0, [z1.s]
 // CHECK-INST: stnt1b { z0.s }, p0, [z1.s]
 // CHECK-ENCODING: [0x20,0x20,0x5f,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 5f e4 <unknown>
+// CHECK-UNKNOWN: e45f2020 <unknown>
 
 stnt1b { z31.s }, p7, [z31.s, xzr]
 // CHECK-INST: stnt1b { z31.s }, p7, [z31.s]
 // CHECK-ENCODING: [0xff,0x3f,0x5f,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 5f e4 <unknown>
+// CHECK-UNKNOWN: e45f3fff <unknown>
 
 stnt1b { z31.s }, p7, [z31.s, x0]
 // CHECK-INST: stnt1b { z31.s }, p7, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0x3f,0x40,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 40 e4 <unknown>
+// CHECK-UNKNOWN: e4403fff <unknown>
 
 stnt1b { z0.d }, p0, [z1.d]
 // CHECK-INST: stnt1b { z0.d }, p0, [z1.d]
 // CHECK-ENCODING: [0x20,0x20,0x1f,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 1f e4 <unknown>
+// CHECK-UNKNOWN: e41f2020 <unknown>
 
 stnt1b { z31.d }, p7, [z31.d, xzr]
 // CHECK-INST: stnt1b { z31.d }, p7, [z31.d]
 // CHECK-ENCODING: [0xff,0x3f,0x1f,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 1f e4 <unknown>
+// CHECK-UNKNOWN: e41f3fff <unknown>
 
 stnt1b { z31.d }, p7, [z31.d, x0]
 // CHECK-INST: stnt1b { z31.d }, p7, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x3f,0x00,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 00 e4 <unknown>
+// CHECK-UNKNOWN: e4003fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/stnt1d.s b/llvm/test/MC/AArch64/SVE2/stnt1d.s
index 966c2d8aea5e9..85458ea797a9d 100644
--- a/llvm/test/MC/AArch64/SVE2/stnt1d.s
+++ b/llvm/test/MC/AArch64/SVE2/stnt1d.s
@@ -13,34 +13,34 @@ stnt1d z0.d, p0, [z1.d]
 // CHECK-INST: stnt1d { z0.d }, p0, [z1.d]
 // CHECK-ENCODING: [0x20,0x20,0x9f,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 9f e5 <unknown>
+// CHECK-UNKNOWN: e59f2020 <unknown>
 
 stnt1d z31.d, p7, [z31.d, xzr]
 // CHECK-INST: stnt1d { z31.d }, p7, [z31.d]
 // CHECK-ENCODING: [0xff,0x3f,0x9f,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 9f e5 <unknown>
+// CHECK-UNKNOWN: e59f3fff <unknown>
 
 stnt1d z31.d, p7, [z31.d, x0]
 // CHECK-INST: stnt1d { z31.d }, p7, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x3f,0x80,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 80 e5 <unknown>
+// CHECK-UNKNOWN: e5803fff <unknown>
 
 stnt1d { z0.d }, p0, [z1.d]
 // CHECK-INST: stnt1d { z0.d }, p0, [z1.d]
 // CHECK-ENCODING: [0x20,0x20,0x9f,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 9f e5 <unknown>
+// CHECK-UNKNOWN: e59f2020 <unknown>
 
 stnt1d { z31.d }, p7, [z31.d, xzr]
 // CHECK-INST: stnt1d { z31.d }, p7, [z31.d]
 // CHECK-ENCODING: [0xff,0x3f,0x9f,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 9f e5 <unknown>
+// CHECK-UNKNOWN: e59f3fff <unknown>
 
 stnt1d { z31.d }, p7, [z31.d, x0]
 // CHECK-INST: stnt1d { z31.d }, p7, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x3f,0x80,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 80 e5 <unknown>
+// CHECK-UNKNOWN: e5803fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/stnt1h.s b/llvm/test/MC/AArch64/SVE2/stnt1h.s
index 0bd106662d3ee..1a8d8450fb23b 100644
--- a/llvm/test/MC/AArch64/SVE2/stnt1h.s
+++ b/llvm/test/MC/AArch64/SVE2/stnt1h.s
@@ -13,70 +13,70 @@ stnt1h z0.s, p0, [z1.s]
 // CHECK-INST: stnt1h { z0.s }, p0, [z1.s]
 // CHECK-ENCODING: [0x20,0x20,0xdf,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 df e4 <unknown>
+// CHECK-UNKNOWN: e4df2020 <unknown>
 
 stnt1h z31.s, p7, [z31.s, xzr]
 // CHECK-INST: stnt1h { z31.s }, p7, [z31.s]
 // CHECK-ENCODING: [0xff,0x3f,0xdf,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f df e4 <unknown>
+// CHECK-UNKNOWN: e4df3fff <unknown>
 
 stnt1h z31.s, p7, [z31.s, x0]
 // CHECK-INST: stnt1h { z31.s }, p7, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0x3f,0xc0,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f c0 e4 <unknown>
+// CHECK-UNKNOWN: e4c03fff <unknown>
 
 stnt1h z0.d, p0, [z1.d]
 // CHECK-INST: stnt1h { z0.d }, p0, [z1.d]
 // CHECK-ENCODING: [0x20,0x20,0x9f,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 9f e4 <unknown>
+// CHECK-UNKNOWN: e49f2020 <unknown>
 
 stnt1h z31.d, p7, [z31.d, xzr]
 // CHECK-INST: stnt1h { z31.d }, p7, [z31.d]
 // CHECK-ENCODING: [0xff,0x3f,0x9f,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 9f e4 <unknown>
+// CHECK-UNKNOWN: e49f3fff <unknown>
 
 stnt1h z31.d, p7, [z31.d, x0]
 // CHECK-INST: stnt1h { z31.d }, p7, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x3f,0x80,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 80 e4 <unknown>
+// CHECK-UNKNOWN: e4803fff <unknown>
 
 stnt1h { z0.s }, p0, [z1.s]
 // CHECK-INST: stnt1h { z0.s }, p0, [z1.s]
 // CHECK-ENCODING: [0x20,0x20,0xdf,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 df e4 <unknown>
+// CHECK-UNKNOWN: e4df2020 <unknown>
 
 stnt1h { z31.s }, p7, [z31.s, xzr]
 // CHECK-INST: stnt1h { z31.s }, p7, [z31.s]
 // CHECK-ENCODING: [0xff,0x3f,0xdf,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f df e4 <unknown>
+// CHECK-UNKNOWN: e4df3fff <unknown>
 
 stnt1h { z31.s }, p7, [z31.s, x0]
 // CHECK-INST: stnt1h { z31.s }, p7, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0x3f,0xc0,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f c0 e4 <unknown>
+// CHECK-UNKNOWN: e4c03fff <unknown>
 
 stnt1h { z0.d }, p0, [z1.d]
 // CHECK-INST: stnt1h { z0.d }, p0, [z1.d]
 // CHECK-ENCODING: [0x20,0x20,0x9f,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 9f e4 <unknown>
+// CHECK-UNKNOWN: e49f2020 <unknown>
 
 stnt1h { z31.d }, p7, [z31.d, xzr]
 // CHECK-INST: stnt1h { z31.d }, p7, [z31.d]
 // CHECK-ENCODING: [0xff,0x3f,0x9f,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 9f e4 <unknown>
+// CHECK-UNKNOWN: e49f3fff <unknown>
 
 stnt1h { z31.d }, p7, [z31.d, x0]
 // CHECK-INST: stnt1h { z31.d }, p7, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x3f,0x80,0xe4]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 80 e4 <unknown>
+// CHECK-UNKNOWN: e4803fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/stnt1w.s b/llvm/test/MC/AArch64/SVE2/stnt1w.s
index 3b083fb6e453d..90d824035fb1d 100644
--- a/llvm/test/MC/AArch64/SVE2/stnt1w.s
+++ b/llvm/test/MC/AArch64/SVE2/stnt1w.s
@@ -13,70 +13,70 @@ stnt1w z0.s, p0, [z1.s]
 // CHECK-INST: stnt1w { z0.s }, p0, [z1.s]
 // CHECK-ENCODING: [0x20,0x20,0x5f,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 5f e5 <unknown>
+// CHECK-UNKNOWN: e55f2020 <unknown>
 
 stnt1w z31.s, p7, [z31.s, xzr]
 // CHECK-INST: stnt1w { z31.s }, p7, [z31.s]
 // CHECK-ENCODING: [0xff,0x3f,0x5f,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 5f e5 <unknown>
+// CHECK-UNKNOWN: e55f3fff <unknown>
 
 stnt1w z31.s, p7, [z31.s, x0]
 // CHECK-INST: stnt1w { z31.s }, p7, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0x3f,0x40,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 40 e5 <unknown>
+// CHECK-UNKNOWN: e5403fff <unknown>
 
 stnt1w z0.d, p0, [z1.d]
 // CHECK-INST: stnt1w { z0.d }, p0, [z1.d]
 // CHECK-ENCODING: [0x20,0x20,0x1f,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 1f e5 <unknown>
+// CHECK-UNKNOWN: e51f2020 <unknown>
 
 stnt1w z31.d, p7, [z31.d, xzr]
 // CHECK-INST: stnt1w { z31.d }, p7, [z31.d]
 // CHECK-ENCODING: [0xff,0x3f,0x1f,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 1f e5 <unknown>
+// CHECK-UNKNOWN: e51f3fff <unknown>
 
 stnt1w z31.d, p7, [z31.d, x0]
 // CHECK-INST: stnt1w { z31.d }, p7, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x3f,0x00,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 00 e5 <unknown>
+// CHECK-UNKNOWN: e5003fff <unknown>
 
 stnt1w { z0.s }, p0, [z1.s]
 // CHECK-INST: stnt1w { z0.s }, p0, [z1.s]
 // CHECK-ENCODING: [0x20,0x20,0x5f,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 5f e5 <unknown>
+// CHECK-UNKNOWN: e55f2020 <unknown>
 
 stnt1w { z31.s }, p7, [z31.s, xzr]
 // CHECK-INST: stnt1w { z31.s }, p7, [z31.s]
 // CHECK-ENCODING: [0xff,0x3f,0x5f,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 5f e5 <unknown>
+// CHECK-UNKNOWN: e55f3fff <unknown>
 
 stnt1w { z31.s }, p7, [z31.s, x0]
 // CHECK-INST: stnt1w { z31.s }, p7, [z31.s, x0]
 // CHECK-ENCODING: [0xff,0x3f,0x40,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 40 e5 <unknown>
+// CHECK-UNKNOWN: e5403fff <unknown>
 
 stnt1w { z0.d }, p0, [z1.d]
 // CHECK-INST: stnt1w { z0.d }, p0, [z1.d]
 // CHECK-ENCODING: [0x20,0x20,0x1f,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: 20 20 1f e5 <unknown>
+// CHECK-UNKNOWN: e51f2020 <unknown>
 
 stnt1w { z31.d }, p7, [z31.d, xzr]
 // CHECK-INST: stnt1w { z31.d }, p7, [z31.d]
 // CHECK-ENCODING: [0xff,0x3f,0x1f,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 1f e5 <unknown>
+// CHECK-UNKNOWN: e51f3fff <unknown>
 
 stnt1w { z31.d }, p7, [z31.d, x0]
 // CHECK-INST: stnt1w { z31.d }, p7, [z31.d, x0]
 // CHECK-ENCODING: [0xff,0x3f,0x00,0xe5]
 // CHECK-ERROR: instruction requires: sve2
-// CHECK-UNKNOWN: ff 3f 00 e5 <unknown>
+// CHECK-UNKNOWN: e5003fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/subhnb.s b/llvm/test/MC/AArch64/SVE2/subhnb.s
index 785814c66b5df..85dcb6163b9cf 100644
--- a/llvm/test/MC/AArch64/SVE2/subhnb.s
+++ b/llvm/test/MC/AArch64/SVE2/subhnb.s
@@ -14,16 +14,16 @@ subhnb z0.b, z1.h, z31.h
 // CHECK-INST: subhnb	z0.b, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x70,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 70 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f7020 <unknown>
 
 subhnb z0.h, z1.s, z31.s
 // CHECK-INST: subhnb	z0.h, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x70,0xbf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 70 bf 45 <unknown>
+// CHECK-UNKNOWN: 45bf7020 <unknown>
 
 subhnb z0.s, z1.d, z31.d
 // CHECK-INST: subhnb	z0.s, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x70,0xff,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 70 ff 45 <unknown>
+// CHECK-UNKNOWN: 45ff7020 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/subhnt.s b/llvm/test/MC/AArch64/SVE2/subhnt.s
index e22515715c26b..e125257b3169f 100644
--- a/llvm/test/MC/AArch64/SVE2/subhnt.s
+++ b/llvm/test/MC/AArch64/SVE2/subhnt.s
@@ -14,16 +14,16 @@ subhnt z0.b, z1.h, z31.h
 // CHECK-INST: subhnt	z0.b, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x74,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 74 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f7420 <unknown>
 
 subhnt z0.h, z1.s, z31.s
 // CHECK-INST: subhnt	z0.h, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x74,0xbf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 74 bf 45 <unknown>
+// CHECK-UNKNOWN: 45bf7420 <unknown>
 
 subhnt z0.s, z1.d, z31.d
 // CHECK-INST: subhnt	z0.s, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0x74,0xff,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 74 ff 45 <unknown>
+// CHECK-UNKNOWN: 45ff7420 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/suqadd.s b/llvm/test/MC/AArch64/SVE2/suqadd.s
index 1c1b2e458f03d..20c6da459d220 100644
--- a/llvm/test/MC/AArch64/SVE2/suqadd.s
+++ b/llvm/test/MC/AArch64/SVE2/suqadd.s
@@ -13,25 +13,25 @@ suqadd z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: suqadd z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x1c,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 1c 44 <unknown>
+// CHECK-UNKNOWN: 441c8020 <unknown>
 
 suqadd z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: suqadd z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x5c,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 5c 44 <unknown>
+// CHECK-UNKNOWN: 445c8020 <unknown>
 
 suqadd z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: suqadd z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x9c,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 9c 44 <unknown>
+// CHECK-UNKNOWN: 449c9fdd <unknown>
 
 suqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: suqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xdc,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f dc 44 <unknown>
+// CHECK-UNKNOWN: 44dc9fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 suqadd z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: suqadd z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xdc,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 dc 44 <unknown>
+// CHECK-UNKNOWN: 44dc83df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 suqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: suqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xdc,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f dc 44 <unknown>
+// CHECK-UNKNOWN: 44dc9fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/tbl.s b/llvm/test/MC/AArch64/SVE2/tbl.s
index 781263f15e335..f436e63294593 100644
--- a/llvm/test/MC/AArch64/SVE2/tbl.s
+++ b/llvm/test/MC/AArch64/SVE2/tbl.s
@@ -13,22 +13,22 @@ tbl  z28.b, { z29.b, z30.b }, z31.b
 // CHECK-INST: tbl  z28.b, { z29.b, z30.b }, z31.b
 // CHECK-ENCODING: [0xbc,0x2b,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: bc 2b 3f 05 <unknown>
+// CHECK-UNKNOWN: 053f2bbc <unknown>
 
 tbl  z28.h, { z29.h, z30.h }, z31.h
 // CHECK-INST: tbl  z28.h, { z29.h, z30.h }, z31.h
 // CHECK-ENCODING: [0xbc,0x2b,0x7f,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: bc 2b 7f 05 <unknown>
+// CHECK-UNKNOWN: 057f2bbc <unknown>
 
 tbl  z28.s, { z29.s, z30.s }, z31.s
 // CHECK-INST: tbl  z28.s, { z29.s, z30.s }, z31.s
 // CHECK-ENCODING: [0xbc,0x2b,0xbf,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: bc 2b bf 05 <unknown>
+// CHECK-UNKNOWN: 05bf2bbc <unknown>
 
 tbl  z28.d, { z29.d, z30.d }, z31.d
 // CHECK-INST: tbl  z28.d, { z29.d, z30.d }, z31.d
 // CHECK-ENCODING: [0xbc,0x2b,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: bc 2b ff 05 <unknown>
+// CHECK-UNKNOWN: 05ff2bbc <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/tbx.s b/llvm/test/MC/AArch64/SVE2/tbx.s
index b65d13679d3c1..01f6cbcddd2d3 100644
--- a/llvm/test/MC/AArch64/SVE2/tbx.s
+++ b/llvm/test/MC/AArch64/SVE2/tbx.s
@@ -13,22 +13,22 @@ tbx  z31.b, z31.b, z31.b
 // CHECK-INST: tbx	z31.b, z31.b, z31.b
 // CHECK-ENCODING: [0xff,0x2f,0x3f,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2f 3f 05 <unknown>
+// CHECK-UNKNOWN: 053f2fff <unknown>
 
 tbx  z31.h, z31.h, z31.h
 // CHECK-INST: tbx	z31.h, z31.h, z31.h
 // CHECK-ENCODING: [0xff,0x2f,0x7f,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2f 7f 05 <unknown>
+// CHECK-UNKNOWN: 057f2fff <unknown>
 
 tbx  z31.s, z31.s, z31.s
 // CHECK-INST: tbx	z31.s, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x2f,0xbf,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2f bf 05 <unknown>
+// CHECK-UNKNOWN: 05bf2fff <unknown>
 
 tbx  z31.d, z31.d, z31.d
 // CHECK-INST: tbx	z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x2f,0xff,0x05]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 2f ff 05 <unknown>
+// CHECK-UNKNOWN: 05ff2fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uaba.s b/llvm/test/MC/AArch64/SVE2/uaba.s
index 54769b357bbfa..ea7c8795bd766 100644
--- a/llvm/test/MC/AArch64/SVE2/uaba.s
+++ b/llvm/test/MC/AArch64/SVE2/uaba.s
@@ -13,25 +13,25 @@ uaba z0.b, z1.b, z31.b
 // CHECK-INST: uaba z0.b, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0xfc,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 fc 1f 45 <unknown>
+// CHECK-UNKNOWN: 451ffc20 <unknown>
 
 uaba z0.h, z1.h, z31.h
 // CHECK-INST: uaba z0.h, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0xfc,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 fc 5f 45 <unknown>
+// CHECK-UNKNOWN: 455ffc20 <unknown>
 
 uaba z0.s, z1.s, z31.s
 // CHECK-INST: uaba z0.s, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xfc,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 fc 9f 45 <unknown>
+// CHECK-UNKNOWN: 459ffc20 <unknown>
 
 uaba z0.d, z1.d, z31.d
 // CHECK-INST: uaba z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xfc,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 fc df 45 <unknown>
+// CHECK-UNKNOWN: 45dffc20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -41,10 +41,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 uaba z0.d, z1.d, z31.d
 // CHECK-INST: uaba z0.d, z1.d, z31.d
 // CHECK-ENCODING: [0x20,0xfc,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 fc df 45 <unknown>
+// CHECK-UNKNOWN: 45dffc20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uabalb.s b/llvm/test/MC/AArch64/SVE2/uabalb.s
index 76beb81cf47d9..a2c4ba9464336 100644
--- a/llvm/test/MC/AArch64/SVE2/uabalb.s
+++ b/llvm/test/MC/AArch64/SVE2/uabalb.s
@@ -14,19 +14,19 @@ uabalb z0.h, z1.b, z31.b
 // CHECK-INST: uabalb	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0xc8,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 c8 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fc820 <unknown>
 
 uabalb z0.s, z1.h, z31.h
 // CHECK-INST: uabalb	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0xc8,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 c8 9f 45 <unknown>
+// CHECK-UNKNOWN: 459fc820 <unknown>
 
 uabalb z0.d, z1.s, z31.s
 // CHECK-INST: uabalb	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xc8,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 c8 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfc820 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -36,10 +36,10 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 uabalb z21.d, z1.s, z31.s
 // CHECK-INST: uabalb	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0xc8,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 c8 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfc835 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uabalt.s b/llvm/test/MC/AArch64/SVE2/uabalt.s
index 9805ca0f7021e..a69770e6f52a7 100644
--- a/llvm/test/MC/AArch64/SVE2/uabalt.s
+++ b/llvm/test/MC/AArch64/SVE2/uabalt.s
@@ -14,19 +14,19 @@ uabalt z0.h, z1.b, z31.b
 // CHECK-INST: uabalt	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0xcc,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 cc 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fcc20 <unknown>
 
 uabalt z0.s, z1.h, z31.h
 // CHECK-INST: uabalt	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0xcc,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 cc 9f 45 <unknown>
+// CHECK-UNKNOWN: 459fcc20 <unknown>
 
 uabalt z0.d, z1.s, z31.s
 // CHECK-INST: uabalt	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0xcc,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 cc df 45 <unknown>
+// CHECK-UNKNOWN: 45dfcc20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -36,10 +36,10 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 uabalt z21.d, z1.s, z31.s
 // CHECK-INST: uabalt	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0xcc,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 cc df 45 <unknown>
+// CHECK-UNKNOWN: 45dfcc35 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uabdlb.s b/llvm/test/MC/AArch64/SVE2/uabdlb.s
index c733baf2931e3..2fef6127645b7 100644
--- a/llvm/test/MC/AArch64/SVE2/uabdlb.s
+++ b/llvm/test/MC/AArch64/SVE2/uabdlb.s
@@ -14,16 +14,16 @@ uabdlb z0.h, z1.b, z2.b
 // CHECK-INST: uabdlb z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x38,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 38 42 45 <unknown>
+// CHECK-UNKNOWN: 45423820 <unknown>
 
 uabdlb z29.s, z30.h, z31.h
 // CHECK-INST: uabdlb z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x3b,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 3b 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f3bdd <unknown>
 
 uabdlb z31.d, z31.s, z31.s
 // CHECK-INST: uabdlb z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x3b,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 3b df 45 <unknown>
+// CHECK-UNKNOWN: 45df3bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uabdlt.s b/llvm/test/MC/AArch64/SVE2/uabdlt.s
index 97c273b510f57..949bd31c84d6f 100644
--- a/llvm/test/MC/AArch64/SVE2/uabdlt.s
+++ b/llvm/test/MC/AArch64/SVE2/uabdlt.s
@@ -14,16 +14,16 @@ uabdlt z0.h, z1.b, z2.b
 // CHECK-INST: uabdlt z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x3c,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 3c 42 45 <unknown>
+// CHECK-UNKNOWN: 45423c20 <unknown>
 
 uabdlt z29.s, z30.h, z31.h
 // CHECK-INST: uabdlt z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x3f,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 3f 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f3fdd <unknown>
 
 uabdlt z31.d, z31.s, z31.s
 // CHECK-INST: uabdlt z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x3f,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 3f df 45 <unknown>
+// CHECK-UNKNOWN: 45df3fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uadalp.s b/llvm/test/MC/AArch64/SVE2/uadalp.s
index fe3d737955f33..562ef50cf7482 100644
--- a/llvm/test/MC/AArch64/SVE2/uadalp.s
+++ b/llvm/test/MC/AArch64/SVE2/uadalp.s
@@ -13,19 +13,19 @@ uadalp z0.h, p0/m, z1.b
 // CHECK-INST: uadalp z0.h, p0/m, z1.b
 // CHECK-ENCODING: [0x20,0xa0,0x45,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 45 44 <unknown>
+// CHECK-UNKNOWN: 4445a020 <unknown>
 
 uadalp z29.s, p0/m, z30.h
 // CHECK-INST: uadalp z29.s, p0/m, z30.h
 // CHECK-ENCODING: [0xdd,0xa3,0x85,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd a3 85 44 <unknown>
+// CHECK-UNKNOWN: 4485a3dd <unknown>
 
 uadalp z30.d, p7/m, z31.s
 // CHECK-INST: uadalp z30.d, p7/m, z31.s
 // CHECK-ENCODING: [0xfe,0xbf,0xc5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: fe bf c5 44 <unknown>
+// CHECK-UNKNOWN: 44c5bffe <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -34,22 +34,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 uadalp z31.d, p0/m, z30.s
 // CHECK-INST: uadalp z31.d, p0/m, z30.s
 // CHECK-ENCODING: [0xdf,0xa3,0xc5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df a3 c5 44 <unknown>
+// CHECK-UNKNOWN: 44c5a3df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uadalp z31.d, p0/m, z30.s
 // CHECK-INST: uadalp z31.d, p0/m, z30.s
 // CHECK-ENCODING: [0xdf,0xa3,0xc5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df a3 c5 44 <unknown>
+// CHECK-UNKNOWN: 44c5a3df <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uaddlb.s b/llvm/test/MC/AArch64/SVE2/uaddlb.s
index 056ffb3fc708f..c4f37a37c30da 100644
--- a/llvm/test/MC/AArch64/SVE2/uaddlb.s
+++ b/llvm/test/MC/AArch64/SVE2/uaddlb.s
@@ -14,16 +14,16 @@ uaddlb z0.h, z1.b, z2.b
 // CHECK-INST: uaddlb z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x08,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 08 42 45 <unknown>
+// CHECK-UNKNOWN: 45420820 <unknown>
 
 uaddlb z29.s, z30.h, z31.h
 // CHECK-INST: uaddlb z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x0b,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 0b 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f0bdd <unknown>
 
 uaddlb z31.d, z31.s, z31.s
 // CHECK-INST: uaddlb z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x0b,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 0b df 45 <unknown>
+// CHECK-UNKNOWN: 45df0bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uaddlt.s b/llvm/test/MC/AArch64/SVE2/uaddlt.s
index f25e3952c95e9..6ff64fe41ed58 100644
--- a/llvm/test/MC/AArch64/SVE2/uaddlt.s
+++ b/llvm/test/MC/AArch64/SVE2/uaddlt.s
@@ -14,16 +14,16 @@ uaddlt z0.h, z1.b, z2.b
 // CHECK-INST: uaddlt z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x0c,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 0c 42 45 <unknown>
+// CHECK-UNKNOWN: 45420c20 <unknown>
 
 uaddlt z29.s, z30.h, z31.h
 // CHECK-INST: uaddlt z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x0f,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 0f 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f0fdd <unknown>
 
 uaddlt z31.d, z31.s, z31.s
 // CHECK-INST: uaddlt z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x0f,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 0f df 45 <unknown>
+// CHECK-UNKNOWN: 45df0fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uaddwb.s b/llvm/test/MC/AArch64/SVE2/uaddwb.s
index c66bd821499b5..40248012355b6 100644
--- a/llvm/test/MC/AArch64/SVE2/uaddwb.s
+++ b/llvm/test/MC/AArch64/SVE2/uaddwb.s
@@ -14,16 +14,16 @@ uaddwb z0.h, z1.h, z2.b
 // CHECK-INST: uaddwb z0.h, z1.h, z2.b
 // CHECK-ENCODING: [0x20,0x48,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 48 42 45 <unknown>
+// CHECK-UNKNOWN: 45424820 <unknown>
 
 uaddwb z29.s, z30.s, z31.h
 // CHECK-INST: uaddwb z29.s, z30.s, z31.h
 // CHECK-ENCODING: [0xdd,0x4b,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 4b 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f4bdd <unknown>
 
 uaddwb z31.d, z31.d, z31.s
 // CHECK-INST: uaddwb z31.d, z31.d, z31.s
 // CHECK-ENCODING: [0xff,0x4b,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 4b df 45 <unknown>
+// CHECK-UNKNOWN: 45df4bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uaddwt.s b/llvm/test/MC/AArch64/SVE2/uaddwt.s
index 0624d37edbb34..55b4d15e9c102 100644
--- a/llvm/test/MC/AArch64/SVE2/uaddwt.s
+++ b/llvm/test/MC/AArch64/SVE2/uaddwt.s
@@ -14,16 +14,16 @@ uaddwt z0.h, z1.h, z2.b
 // CHECK-INST: uaddwt z0.h, z1.h, z2.b
 // CHECK-ENCODING: [0x20,0x4c,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 4c 42 45 <unknown>
+// CHECK-UNKNOWN: 45424c20 <unknown>
 
 uaddwt z29.s, z30.s, z31.h
 // CHECK-INST: uaddwt z29.s, z30.s, z31.h
 // CHECK-ENCODING: [0xdd,0x4f,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 4f 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f4fdd <unknown>
 
 uaddwt z31.d, z31.d, z31.s
 // CHECK-INST: uaddwt z31.d, z31.d, z31.s
 // CHECK-ENCODING: [0xff,0x4f,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 4f df 45 <unknown>
+// CHECK-UNKNOWN: 45df4fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uhadd.s b/llvm/test/MC/AArch64/SVE2/uhadd.s
index 8312c32e6fe2b..99a2be0b5d363 100644
--- a/llvm/test/MC/AArch64/SVE2/uhadd.s
+++ b/llvm/test/MC/AArch64/SVE2/uhadd.s
@@ -13,25 +13,25 @@ uhadd z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: uhadd z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x11,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 11 44 <unknown>
+// CHECK-UNKNOWN: 44118020 <unknown>
 
 uhadd z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: uhadd z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x51,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 51 44 <unknown>
+// CHECK-UNKNOWN: 44518020 <unknown>
 
 uhadd z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: uhadd z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x91,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 91 44 <unknown>
+// CHECK-UNKNOWN: 44919fdd <unknown>
 
 uhadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uhadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd1,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d1 44 <unknown>
+// CHECK-UNKNOWN: 44d19fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 uhadd z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: uhadd z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd1,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d1 44 <unknown>
+// CHECK-UNKNOWN: 44d183df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uhadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uhadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd1,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d1 44 <unknown>
+// CHECK-UNKNOWN: 44d19fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uhsub.s b/llvm/test/MC/AArch64/SVE2/uhsub.s
index f261d26c8046f..6c52ae04900ee 100644
--- a/llvm/test/MC/AArch64/SVE2/uhsub.s
+++ b/llvm/test/MC/AArch64/SVE2/uhsub.s
@@ -13,25 +13,25 @@ uhsub z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: uhsub z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x13,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 13 44 <unknown>
+// CHECK-UNKNOWN: 44138020 <unknown>
 
 uhsub z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: uhsub z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x53,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 53 44 <unknown>
+// CHECK-UNKNOWN: 44538020 <unknown>
 
 uhsub z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: uhsub z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x93,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 93 44 <unknown>
+// CHECK-UNKNOWN: 44939fdd <unknown>
 
 uhsub z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uhsub z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd3,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d3 44 <unknown>
+// CHECK-UNKNOWN: 44d39fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 uhsub z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: uhsub z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd3,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d3 44 <unknown>
+// CHECK-UNKNOWN: 44d383df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uhsub z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uhsub z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd3,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d3 44 <unknown>
+// CHECK-UNKNOWN: 44d39fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uhsubr.s b/llvm/test/MC/AArch64/SVE2/uhsubr.s
index c5def46591153..b9a9fb9d66877 100644
--- a/llvm/test/MC/AArch64/SVE2/uhsubr.s
+++ b/llvm/test/MC/AArch64/SVE2/uhsubr.s
@@ -13,25 +13,25 @@ uhsubr z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: uhsubr z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x17,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 17 44 <unknown>
+// CHECK-UNKNOWN: 44178020 <unknown>
 
 uhsubr z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: uhsubr z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x57,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 57 44 <unknown>
+// CHECK-UNKNOWN: 44578020 <unknown>
 
 uhsubr z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: uhsubr z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x97,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 97 44 <unknown>
+// CHECK-UNKNOWN: 44979fdd <unknown>
 
 uhsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uhsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d7 44 <unknown>
+// CHECK-UNKNOWN: 44d79fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 uhsubr z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: uhsubr z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d7 44 <unknown>
+// CHECK-UNKNOWN: 44d783df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uhsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uhsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d7 44 <unknown>
+// CHECK-UNKNOWN: 44d79fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/umaxp.s b/llvm/test/MC/AArch64/SVE2/umaxp.s
index d08bd5b3d8445..47c152d05f4f1 100644
--- a/llvm/test/MC/AArch64/SVE2/umaxp.s
+++ b/llvm/test/MC/AArch64/SVE2/umaxp.s
@@ -13,25 +13,25 @@ umaxp z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: umaxp z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0xa0,0x15,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 15 44 <unknown>
+// CHECK-UNKNOWN: 4415a020 <unknown>
 
 umaxp z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: umaxp z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0xa0,0x55,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 55 44 <unknown>
+// CHECK-UNKNOWN: 4455a020 <unknown>
 
 umaxp z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: umaxp z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0xbf,0x95,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd bf 95 44 <unknown>
+// CHECK-UNKNOWN: 4495bfdd <unknown>
 
 umaxp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: umaxp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xbf,0xd5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df bf d5 44 <unknown>
+// CHECK-UNKNOWN: 44d5bfdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 umaxp z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: umaxp z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xa3,0xd5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df a3 d5 44 <unknown>
+// CHECK-UNKNOWN: 44d5a3df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 umaxp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: umaxp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xbf,0xd5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df bf d5 44 <unknown>
+// CHECK-UNKNOWN: 44d5bfdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uminp.s b/llvm/test/MC/AArch64/SVE2/uminp.s
index 193eed95bf3e8..58545aeab87af 100644
--- a/llvm/test/MC/AArch64/SVE2/uminp.s
+++ b/llvm/test/MC/AArch64/SVE2/uminp.s
@@ -13,25 +13,25 @@ uminp z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: uminp z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0xa0,0x17,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 17 44 <unknown>
+// CHECK-UNKNOWN: 4417a020 <unknown>
 
 uminp z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: uminp z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0xa0,0x57,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 a0 57 44 <unknown>
+// CHECK-UNKNOWN: 4457a020 <unknown>
 
 uminp z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: uminp z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0xbf,0x97,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd bf 97 44 <unknown>
+// CHECK-UNKNOWN: 4497bfdd <unknown>
 
 uminp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uminp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xbf,0xd7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df bf d7 44 <unknown>
+// CHECK-UNKNOWN: 44d7bfdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 uminp z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: uminp z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xa3,0xd7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df a3 d7 44 <unknown>
+// CHECK-UNKNOWN: 44d7a3df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uminp z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uminp z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0xbf,0xd7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df bf d7 44 <unknown>
+// CHECK-UNKNOWN: 44d7bfdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/umlalb.s b/llvm/test/MC/AArch64/SVE2/umlalb.s
index 173165e6a73db..f9e97357b32c4 100644
--- a/llvm/test/MC/AArch64/SVE2/umlalb.s
+++ b/llvm/test/MC/AArch64/SVE2/umlalb.s
@@ -14,31 +14,31 @@ umlalb z0.h, z1.b, z31.b
 // CHECK-INST: umlalb	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x48,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 48 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f4820 <unknown>
 
 umlalb z0.s, z1.h, z31.h
 // CHECK-INST: umlalb	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x48,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 48 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f4820 <unknown>
 
 umlalb z0.d, z1.s, z31.s
 // CHECK-INST: umlalb	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x48,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 48 df 44 <unknown>
+// CHECK-UNKNOWN: 44df4820 <unknown>
 
 umlalb z0.s, z1.h, z7.h[7]
 // CHECK-INST: umlalb	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x98,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 98 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf9820 <unknown>
 
 umlalb z0.d, z1.s, z15.s[1]
 // CHECK-INST: umlalb	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0x98,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 98 ef 44 <unknown>
+// CHECK-UNKNOWN: 44ef9820 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -48,22 +48,22 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 umlalb z21.d, z1.s, z31.s
 // CHECK-INST: umlalb	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x48,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 48 df 44 <unknown>
+// CHECK-UNKNOWN: 44df4835 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 umlalb   z21.d, z10.s, z5.s[1]
 // CHECK-INST: umlalb   z21.d, z10.s, z5.s[1]
 // CHECK-ENCODING: [0x55,0x99,0xe5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 99 e5 44 <unknown>
+// CHECK-UNKNOWN: 44e59955 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/umlalt.s b/llvm/test/MC/AArch64/SVE2/umlalt.s
index e95293b0b27c3..139f3bf96b27e 100644
--- a/llvm/test/MC/AArch64/SVE2/umlalt.s
+++ b/llvm/test/MC/AArch64/SVE2/umlalt.s
@@ -14,31 +14,31 @@ umlalt z0.h, z1.b, z31.b
 // CHECK-INST: umlalt	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x4c,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 4c 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f4c20 <unknown>
 
 umlalt z0.s, z1.h, z31.h
 // CHECK-INST: umlalt	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x4c,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 4c 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f4c20 <unknown>
 
 umlalt z0.d, z1.s, z31.s
 // CHECK-INST: umlalt	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x4c,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 4c df 44 <unknown>
+// CHECK-UNKNOWN: 44df4c20 <unknown>
 
 umlalt z0.s, z1.h, z7.h[7]
 // CHECK-INST: umlalt	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0x9c,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 9c bf 44 <unknown>
+// CHECK-UNKNOWN: 44bf9c20 <unknown>
 
 umlalt z0.d, z1.s, z15.s[1]
 // CHECK-INST: umlalt	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0x9c,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 9c ef 44 <unknown>
+// CHECK-UNKNOWN: 44ef9c20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -48,22 +48,22 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 umlalt z21.d, z1.s, z31.s
 // CHECK-INST: umlalt	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x4c,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 4c df 44 <unknown>
+// CHECK-UNKNOWN: 44df4c35 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 umlalt   z21.d, z10.s, z5.s[1]
 // CHECK-INST: umlalt   z21.d, z10.s, z5.s[1]
 // CHECK-ENCODING: [0x55,0x9d,0xe5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 9d e5 44 <unknown>
+// CHECK-UNKNOWN: 44e59d55 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/umlslb.s b/llvm/test/MC/AArch64/SVE2/umlslb.s
index 69d2fbb667df9..2d36fdb586c7a 100644
--- a/llvm/test/MC/AArch64/SVE2/umlslb.s
+++ b/llvm/test/MC/AArch64/SVE2/umlslb.s
@@ -14,31 +14,31 @@ umlslb z0.h, z1.b, z31.b
 // CHECK-INST: umlslb	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x58,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 58 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f5820 <unknown>
 
 umlslb z0.s, z1.h, z31.h
 // CHECK-INST: umlslb	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x58,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 58 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f5820 <unknown>
 
 umlslb z0.d, z1.s, z31.s
 // CHECK-INST: umlslb	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x58,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 58 df 44 <unknown>
+// CHECK-UNKNOWN: 44df5820 <unknown>
 
 umlslb z0.s, z1.h, z7.h[7]
 // CHECK-INST: umlslb	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0xb8,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 b8 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bfb820 <unknown>
 
 umlslb z0.d, z1.s, z15.s[1]
 // CHECK-INST: umlslb	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0xb8,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 b8 ef 44 <unknown>
+// CHECK-UNKNOWN: 44efb820 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -48,22 +48,22 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 umlslb z21.d, z1.s, z31.s
 // CHECK-INST: umlslb	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x58,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 58 df 44 <unknown>
+// CHECK-UNKNOWN: 44df5835 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 umlslb   z21.d, z10.s, z5.s[1]
 // CHECK-INST: umlslb   z21.d, z10.s, z5.s[1]
 // CHECK-ENCODING: [0x55,0xb9,0xe5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 b9 e5 44 <unknown>
+// CHECK-UNKNOWN: 44e5b955 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/umlslt.s b/llvm/test/MC/AArch64/SVE2/umlslt.s
index 96b05cfa906fa..1751b52220024 100644
--- a/llvm/test/MC/AArch64/SVE2/umlslt.s
+++ b/llvm/test/MC/AArch64/SVE2/umlslt.s
@@ -14,31 +14,31 @@ umlslt z0.h, z1.b, z31.b
 // CHECK-INST: umlslt	z0.h, z1.b, z31.b
 // CHECK-ENCODING: [0x20,0x5c,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 5c 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f5c20 <unknown>
 
 umlslt z0.s, z1.h, z31.h
 // CHECK-INST: umlslt	z0.s, z1.h, z31.h
 // CHECK-ENCODING: [0x20,0x5c,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 5c 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f5c20 <unknown>
 
 umlslt z0.d, z1.s, z31.s
 // CHECK-INST: umlslt	z0.d, z1.s, z31.s
 // CHECK-ENCODING: [0x20,0x5c,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 5c df 44 <unknown>
+// CHECK-UNKNOWN: 44df5c20 <unknown>
 
 umlslt z0.s, z1.h, z7.h[7]
 // CHECK-INST: umlslt	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0xbc,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 bc bf 44 <unknown>
+// CHECK-UNKNOWN: 44bfbc20 <unknown>
 
 umlslt z0.d, z1.s, z15.s[1]
 // CHECK-INST: umlslt	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0xbc,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 bc ef 44 <unknown>
+// CHECK-UNKNOWN: 44efbc20 <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -48,22 +48,22 @@ movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 umlslt z21.d, z1.s, z31.s
 // CHECK-INST: umlslt	z21.d, z1.s, z31.s
 // CHECK-ENCODING: [0x35,0x5c,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 35 5c df 44 <unknown>
+// CHECK-UNKNOWN: 44df5c35 <unknown>
 
 movprfx z21, z28
 // CHECK-INST: movprfx	z21, z28
 // CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bf95 <unknown>
 
 umlslt   z21.d, z10.s, z5.s[1]
 // CHECK-INST: umlslt   z21.d, z10.s, z5.s[1]
 // CHECK-ENCODING: [0x55,0xbd,0xe5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 55 bd e5 44 <unknown>
+// CHECK-UNKNOWN: 44e5bd55 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/umulh.s b/llvm/test/MC/AArch64/SVE2/umulh.s
index 4fef346b10d8e..e13a4d7b8bf7e 100644
--- a/llvm/test/MC/AArch64/SVE2/umulh.s
+++ b/llvm/test/MC/AArch64/SVE2/umulh.s
@@ -13,22 +13,22 @@ umulh z0.b, z1.b, z2.b
 // CHECK-INST: umulh z0.b, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x6c,0x22,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 6c 22 04 <unknown>
+// CHECK-UNKNOWN: 04226c20 <unknown>
 
 umulh z0.h, z1.h, z2.h
 // CHECK-INST: umulh z0.h, z1.h, z2.h
 // CHECK-ENCODING: [0x20,0x6c,0x62,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 6c 62 04 <unknown>
+// CHECK-UNKNOWN: 04626c20 <unknown>
 
 umulh z29.s, z30.s, z31.s
 // CHECK-INST: umulh z29.s, z30.s, z31.s
 // CHECK-ENCODING: [0xdd,0x6f,0xbf,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 6f bf 04 <unknown>
+// CHECK-UNKNOWN: 04bf6fdd <unknown>
 
 umulh z31.d, z31.d, z31.d
 // CHECK-INST: umulh z31.d, z31.d, z31.d
 // CHECK-ENCODING: [0xff,0x6f,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 6f ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff6fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/umullb.s b/llvm/test/MC/AArch64/SVE2/umullb.s
index 4594682227966..8cf81dbd2b634 100644
--- a/llvm/test/MC/AArch64/SVE2/umullb.s
+++ b/llvm/test/MC/AArch64/SVE2/umullb.s
@@ -14,28 +14,28 @@ umullb z0.h, z1.b, z2.b
 // CHECK-INST: umullb z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x78,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 78 42 45 <unknown>
+// CHECK-UNKNOWN: 45427820 <unknown>
 
 umullb z29.s, z30.h, z31.h
 // CHECK-INST: umullb z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x7b,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 7b 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f7bdd <unknown>
 
 umullb z31.d, z31.s, z31.s
 // CHECK-INST: umullb z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x7b,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 7b df 45 <unknown>
+// CHECK-UNKNOWN: 45df7bff <unknown>
 
 umullb z0.s, z1.h, z7.h[7]
 // CHECK-INST: umullb	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0xd8,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d8 bf 44 <unknown>
+// CHECK-UNKNOWN: 44bfd820 <unknown>
 
 umullb z0.d, z1.s, z15.s[1]
 // CHECK-INST: umullb	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0xd8,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 d8 ef 44 <unknown>
+// CHECK-UNKNOWN: 44efd820 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/umullt.s b/llvm/test/MC/AArch64/SVE2/umullt.s
index eba65077549cb..a8a222101cd7b 100644
--- a/llvm/test/MC/AArch64/SVE2/umullt.s
+++ b/llvm/test/MC/AArch64/SVE2/umullt.s
@@ -14,28 +14,28 @@ umullt z0.h, z1.b, z2.b
 // CHECK-INST: umullt z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x7c,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 7c 42 45 <unknown>
+// CHECK-UNKNOWN: 45427c20 <unknown>
 
 umullt z29.s, z30.h, z31.h
 // CHECK-INST: umullt z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x7f,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 7f 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f7fdd <unknown>
 
 umullt z31.d, z31.s, z31.s
 // CHECK-INST: umullt z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x7f,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 7f df 45 <unknown>
+// CHECK-UNKNOWN: 45df7fff <unknown>
 
 umullt z0.s, z1.h, z7.h[7]
 // CHECK-INST: umullt	z0.s, z1.h, z7.h[7]
 // CHECK-ENCODING: [0x20,0xdc,0xbf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 dc bf 44 <unknown>
+// CHECK-UNKNOWN: 44bfdc20 <unknown>
 
 umullt z0.d, z1.s, z15.s[1]
 // CHECK-INST: umullt	z0.d, z1.s, z15.s[1]
 // CHECK-ENCODING: [0x20,0xdc,0xef,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 dc ef 44 <unknown>
+// CHECK-UNKNOWN: 44efdc20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uqadd.s b/llvm/test/MC/AArch64/SVE2/uqadd.s
index e5ca9da0231f4..ff8be706aa96d 100644
--- a/llvm/test/MC/AArch64/SVE2/uqadd.s
+++ b/llvm/test/MC/AArch64/SVE2/uqadd.s
@@ -13,25 +13,25 @@ uqadd z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: uqadd z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x19,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 19 44 <unknown>
+// CHECK-UNKNOWN: 44198020 <unknown>
 
 uqadd z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: uqadd z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x59,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 59 44 <unknown>
+// CHECK-UNKNOWN: 44598020 <unknown>
 
 uqadd z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: uqadd z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x99,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 99 44 <unknown>
+// CHECK-UNKNOWN: 44999fdd <unknown>
 
 uqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd9,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d9 44 <unknown>
+// CHECK-UNKNOWN: 44d99fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 uqadd z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: uqadd z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd9,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d9 44 <unknown>
+// CHECK-UNKNOWN: 44d983df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd9,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d9 44 <unknown>
+// CHECK-UNKNOWN: 44d99fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uqrshl.s b/llvm/test/MC/AArch64/SVE2/uqrshl.s
index 651efd6570ca0..0c4e190c24536 100644
--- a/llvm/test/MC/AArch64/SVE2/uqrshl.s
+++ b/llvm/test/MC/AArch64/SVE2/uqrshl.s
@@ -13,25 +13,25 @@ uqrshl z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: uqrshl z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x0b,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 0b 44 <unknown>
+// CHECK-UNKNOWN: 440b8020 <unknown>
 
 uqrshl z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: uqrshl z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x4b,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 4b 44 <unknown>
+// CHECK-UNKNOWN: 444b8020 <unknown>
 
 uqrshl z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: uqrshl z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x8b,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 8b 44 <unknown>
+// CHECK-UNKNOWN: 448b9fdd <unknown>
 
 uqrshl z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqrshl z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xcb,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f cb 44 <unknown>
+// CHECK-UNKNOWN: 44cb9fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 uqrshl z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: uqrshl z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xcb,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 cb 44 <unknown>
+// CHECK-UNKNOWN: 44cb83df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uqrshl z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqrshl z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xcb,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f cb 44 <unknown>
+// CHECK-UNKNOWN: 44cb9fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uqrshlr.s b/llvm/test/MC/AArch64/SVE2/uqrshlr.s
index f5ee0c1a230a7..5e64334d6d2d6 100644
--- a/llvm/test/MC/AArch64/SVE2/uqrshlr.s
+++ b/llvm/test/MC/AArch64/SVE2/uqrshlr.s
@@ -13,25 +13,25 @@ uqrshlr z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: uqrshlr z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x0f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 0f 44 <unknown>
+// CHECK-UNKNOWN: 440f8020 <unknown>
 
 uqrshlr z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: uqrshlr z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x4f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 4f 44 <unknown>
+// CHECK-UNKNOWN: 444f8020 <unknown>
 
 uqrshlr z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: uqrshlr z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x8f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 8f 44 <unknown>
+// CHECK-UNKNOWN: 448f9fdd <unknown>
 
 uqrshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqrshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xcf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f cf 44 <unknown>
+// CHECK-UNKNOWN: 44cf9fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 uqrshlr z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: uqrshlr z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xcf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 cf 44 <unknown>
+// CHECK-UNKNOWN: 44cf83df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uqrshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqrshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xcf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f cf 44 <unknown>
+// CHECK-UNKNOWN: 44cf9fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uqrshrnb.s b/llvm/test/MC/AArch64/SVE2/uqrshrnb.s
index c239980f811bd..7c3682c7f2bf3 100644
--- a/llvm/test/MC/AArch64/SVE2/uqrshrnb.s
+++ b/llvm/test/MC/AArch64/SVE2/uqrshrnb.s
@@ -13,34 +13,34 @@ uqrshrnb     z0.b, z0.h, #1
 // CHECK-INST: uqrshrnb	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x38,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 38 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f3800 <unknown>
 
 uqrshrnb     z31.b, z31.h, #8
 // CHECK-INST: uqrshrnb	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x3b,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 3b 28 45 <unknown>
+// CHECK-UNKNOWN: 45283bff <unknown>
 
 uqrshrnb     z0.h, z0.s, #1
 // CHECK-INST: uqrshrnb	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x38,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 38 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f3800 <unknown>
 
 uqrshrnb     z31.h, z31.s, #16
 // CHECK-INST: uqrshrnb	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x3b,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 3b 30 45 <unknown>
+// CHECK-UNKNOWN: 45303bff <unknown>
 
 uqrshrnb     z0.s, z0.d, #1
 // CHECK-INST: uqrshrnb	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x38,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 38 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f3800 <unknown>
 
 uqrshrnb     z31.s, z31.d, #32
 // CHECK-INST: uqrshrnb	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x3b,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 3b 60 45 <unknown>
+// CHECK-UNKNOWN: 45603bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uqrshrnt.s b/llvm/test/MC/AArch64/SVE2/uqrshrnt.s
index c87b7a168ca7d..3fda2c6d5b28b 100644
--- a/llvm/test/MC/AArch64/SVE2/uqrshrnt.s
+++ b/llvm/test/MC/AArch64/SVE2/uqrshrnt.s
@@ -13,34 +13,34 @@ uqrshrnt     z0.b, z0.h, #1
 // CHECK-INST: uqrshrnt	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x3c,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 3c 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f3c00 <unknown>
 
 uqrshrnt     z31.b, z31.h, #8
 // CHECK-INST: uqrshrnt	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x3f,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 3f 28 45 <unknown>
+// CHECK-UNKNOWN: 45283fff <unknown>
 
 uqrshrnt     z0.h, z0.s, #1
 // CHECK-INST: uqrshrnt	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x3c,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 3c 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f3c00 <unknown>
 
 uqrshrnt     z31.h, z31.s, #16
 // CHECK-INST: uqrshrnt	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x3f,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 3f 30 45 <unknown>
+// CHECK-UNKNOWN: 45303fff <unknown>
 
 uqrshrnt     z0.s, z0.d, #1
 // CHECK-INST: uqrshrnt	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x3c,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 3c 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f3c00 <unknown>
 
 uqrshrnt     z31.s, z31.d, #32
 // CHECK-INST: uqrshrnt	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x3f,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 3f 60 45 <unknown>
+// CHECK-UNKNOWN: 45603fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uqshl.s b/llvm/test/MC/AArch64/SVE2/uqshl.s
index 4301db8a70957..ec7d1c04621f1 100644
--- a/llvm/test/MC/AArch64/SVE2/uqshl.s
+++ b/llvm/test/MC/AArch64/SVE2/uqshl.s
@@ -13,73 +13,73 @@ uqshl z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: uqshl z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x09,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 09 44 <unknown>
+// CHECK-UNKNOWN: 44098020 <unknown>
 
 uqshl z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: uqshl z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x49,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 49 44 <unknown>
+// CHECK-UNKNOWN: 44498020 <unknown>
 
 uqshl z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: uqshl z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x89,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 89 44 <unknown>
+// CHECK-UNKNOWN: 44899fdd <unknown>
 
 uqshl z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqshl z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xc9,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f c9 44 <unknown>
+// CHECK-UNKNOWN: 44c99fdf <unknown>
 
 uqshl z0.b, p0/m, z0.b, #0
 // CHECK-INST: uqshl z0.b, p0/m, z0.b, #0
 // CHECK-ENCODING: [0x00,0x81,0x07,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 81 07 04 <unknown>
+// CHECK-UNKNOWN: 04078100 <unknown>
 
 uqshl z31.b, p0/m, z31.b, #7
 // CHECK-INST: uqshl z31.b, p0/m, z31.b, #7
 // CHECK-ENCODING: [0xff,0x81,0x07,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 81 07 04 <unknown>
+// CHECK-UNKNOWN: 040781ff <unknown>
 
 uqshl z0.h, p0/m, z0.h, #0
 // CHECK-INST: uqshl z0.h, p0/m, z0.h, #0
 // CHECK-ENCODING: [0x00,0x82,0x07,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 82 07 04 <unknown>
+// CHECK-UNKNOWN: 04078200 <unknown>
 
 uqshl z31.h, p0/m, z31.h, #15
 // CHECK-INST: uqshl z31.h, p0/m, z31.h, #15
 // CHECK-ENCODING: [0xff,0x83,0x07,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 07 04 <unknown>
+// CHECK-UNKNOWN: 040783ff <unknown>
 
 uqshl z0.s, p0/m, z0.s, #0
 // CHECK-INST: uqshl z0.s, p0/m, z0.s, #0
 // CHECK-ENCODING: [0x00,0x80,0x47,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 80 47 04 <unknown>
+// CHECK-UNKNOWN: 04478000 <unknown>
 
 uqshl z31.s, p0/m, z31.s, #31
 // CHECK-INST: uqshl z31.s, p0/m, z31.s, #31
 // CHECK-ENCODING: [0xff,0x83,0x47,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 47 04 <unknown>
+// CHECK-UNKNOWN: 044783ff <unknown>
 
 uqshl z0.d, p0/m, z0.d, #0
 // CHECK-INST: uqshl z0.d, p0/m, z0.d, #0
 // CHECK-ENCODING: [0x00,0x80,0x87,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 80 87 04 <unknown>
+// CHECK-UNKNOWN: 04878000 <unknown>
 
 uqshl z31.d, p0/m, z31.d, #63
 // CHECK-INST: uqshl z31.d, p0/m, z31.d, #63
 // CHECK-ENCODING: [0xff,0x83,0xc7,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 c7 04 <unknown>
+// CHECK-UNKNOWN: 04c783ff <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -88,46 +88,46 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 uqshl z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: uqshl z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xc9,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 c9 44 <unknown>
+// CHECK-UNKNOWN: 44c983df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uqshl z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqshl z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xc9,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f c9 44 <unknown>
+// CHECK-UNKNOWN: 44c99fdf <unknown>
 
 movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 uqshl z31.d, p0/m, z31.d, #63
 // CHECK-INST: uqshl z31.d, p0/m, z31.d, #63
 // CHECK-ENCODING: [0xff,0x83,0xc7,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 c7 04 <unknown>
+// CHECK-UNKNOWN: 04c783ff <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uqshl z31.d, p0/m, z31.d, #63
 // CHECK-INST: uqshl z31.d, p0/m, z31.d, #63
 // CHECK-ENCODING: [0xff,0x83,0xc7,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 83 c7 04 <unknown>
+// CHECK-UNKNOWN: 04c783ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uqshlr.s b/llvm/test/MC/AArch64/SVE2/uqshlr.s
index 270b0c8ac1038..1d0b121e411cf 100644
--- a/llvm/test/MC/AArch64/SVE2/uqshlr.s
+++ b/llvm/test/MC/AArch64/SVE2/uqshlr.s
@@ -13,25 +13,25 @@ uqshlr z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: uqshlr z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x0d,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 0d 44 <unknown>
+// CHECK-UNKNOWN: 440d8020 <unknown>
 
 uqshlr z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: uqshlr z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x4d,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 4d 44 <unknown>
+// CHECK-UNKNOWN: 444d8020 <unknown>
 
 uqshlr z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: uqshlr z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x8d,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 8d 44 <unknown>
+// CHECK-UNKNOWN: 448d9fdd <unknown>
 
 uqshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xcd,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f cd 44 <unknown>
+// CHECK-UNKNOWN: 44cd9fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 uqshlr z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: uqshlr z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xcd,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 cd 44 <unknown>
+// CHECK-UNKNOWN: 44cd83df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uqshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xcd,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f cd 44 <unknown>
+// CHECK-UNKNOWN: 44cd9fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uqshrnb.s b/llvm/test/MC/AArch64/SVE2/uqshrnb.s
index 032e7f40bea07..cc6ee1db6a196 100644
--- a/llvm/test/MC/AArch64/SVE2/uqshrnb.s
+++ b/llvm/test/MC/AArch64/SVE2/uqshrnb.s
@@ -13,34 +13,34 @@ uqshrnb     z0.b, z0.h, #1
 // CHECK-INST: uqshrnb	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x30,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 30 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f3000 <unknown>
 
 uqshrnb     z31.b, z31.h, #8
 // CHECK-INST: uqshrnb	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x33,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 33 28 45 <unknown>
+// CHECK-UNKNOWN: 452833ff <unknown>
 
 uqshrnb     z0.h, z0.s, #1
 // CHECK-INST: uqshrnb	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x30,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 30 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f3000 <unknown>
 
 uqshrnb     z31.h, z31.s, #16
 // CHECK-INST: uqshrnb	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x33,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 33 30 45 <unknown>
+// CHECK-UNKNOWN: 453033ff <unknown>
 
 uqshrnb     z0.s, z0.d, #1
 // CHECK-INST: uqshrnb	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x30,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 30 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f3000 <unknown>
 
 uqshrnb     z31.s, z31.d, #32
 // CHECK-INST: uqshrnb	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x33,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 33 60 45 <unknown>
+// CHECK-UNKNOWN: 456033ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uqshrnt.s b/llvm/test/MC/AArch64/SVE2/uqshrnt.s
index 4a07a7c02fdd2..0c3ad8bc1f6ab 100644
--- a/llvm/test/MC/AArch64/SVE2/uqshrnt.s
+++ b/llvm/test/MC/AArch64/SVE2/uqshrnt.s
@@ -13,34 +13,34 @@ uqshrnt     z0.b, z0.h, #1
 // CHECK-INST: uqshrnt	z0.b, z0.h, #1
 // CHECK-ENCODING: [0x00,0x34,0x2f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 34 2f 45 <unknown>
+// CHECK-UNKNOWN: 452f3400 <unknown>
 
 uqshrnt     z31.b, z31.h, #8
 // CHECK-INST: uqshrnt	z31.b, z31.h, #8
 // CHECK-ENCODING: [0xff,0x37,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 37 28 45 <unknown>
+// CHECK-UNKNOWN: 452837ff <unknown>
 
 uqshrnt     z0.h, z0.s, #1
 // CHECK-INST: uqshrnt	z0.h, z0.s, #1
 // CHECK-ENCODING: [0x00,0x34,0x3f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 34 3f 45 <unknown>
+// CHECK-UNKNOWN: 453f3400 <unknown>
 
 uqshrnt     z31.h, z31.s, #16
 // CHECK-INST: uqshrnt	z31.h, z31.s, #16
 // CHECK-ENCODING: [0xff,0x37,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 37 30 45 <unknown>
+// CHECK-UNKNOWN: 453037ff <unknown>
 
 uqshrnt     z0.s, z0.d, #1
 // CHECK-INST: uqshrnt	z0.s, z0.d, #1
 // CHECK-ENCODING: [0x00,0x34,0x7f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 34 7f 45 <unknown>
+// CHECK-UNKNOWN: 457f3400 <unknown>
 
 uqshrnt     z31.s, z31.d, #32
 // CHECK-INST: uqshrnt	z31.s, z31.d, #32
 // CHECK-ENCODING: [0xff,0x37,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 37 60 45 <unknown>
+// CHECK-UNKNOWN: 456037ff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uqsub.s b/llvm/test/MC/AArch64/SVE2/uqsub.s
index 7855e0c871e6d..9c95ac07c2058 100644
--- a/llvm/test/MC/AArch64/SVE2/uqsub.s
+++ b/llvm/test/MC/AArch64/SVE2/uqsub.s
@@ -13,25 +13,25 @@ uqsub z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: uqsub z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x1b,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 1b 44 <unknown>
+// CHECK-UNKNOWN: 441b8020 <unknown>
 
 uqsub z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: uqsub z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x5b,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 5b 44 <unknown>
+// CHECK-UNKNOWN: 445b8020 <unknown>
 
 uqsub z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: uqsub z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x9b,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 9b 44 <unknown>
+// CHECK-UNKNOWN: 449b9fdd <unknown>
 
 uqsub z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqsub z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xdb,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f db 44 <unknown>
+// CHECK-UNKNOWN: 44db9fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 uqsub z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: uqsub z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xdb,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 db 44 <unknown>
+// CHECK-UNKNOWN: 44db83df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uqsub z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqsub z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xdb,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f db 44 <unknown>
+// CHECK-UNKNOWN: 44db9fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uqsubr.s b/llvm/test/MC/AArch64/SVE2/uqsubr.s
index 051989e3476da..604d0f29361bc 100644
--- a/llvm/test/MC/AArch64/SVE2/uqsubr.s
+++ b/llvm/test/MC/AArch64/SVE2/uqsubr.s
@@ -13,25 +13,25 @@ uqsubr z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: uqsubr z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x1f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 1f 44 <unknown>
+// CHECK-UNKNOWN: 441f8020 <unknown>
 
 uqsubr z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: uqsubr z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x5f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 5f 44 <unknown>
+// CHECK-UNKNOWN: 445f8020 <unknown>
 
 uqsubr z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: uqsubr z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x9f,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 9f 44 <unknown>
+// CHECK-UNKNOWN: 449f9fdd <unknown>
 
 uqsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f df 44 <unknown>
+// CHECK-UNKNOWN: 44df9fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 uqsubr z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: uqsubr z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 df 44 <unknown>
+// CHECK-UNKNOWN: 44df83df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 uqsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: uqsubr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xdf,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f df 44 <unknown>
+// CHECK-UNKNOWN: 44df9fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uqxtnb.s b/llvm/test/MC/AArch64/SVE2/uqxtnb.s
index 4f7b3e55505f3..c0e03709ca264 100644
--- a/llvm/test/MC/AArch64/SVE2/uqxtnb.s
+++ b/llvm/test/MC/AArch64/SVE2/uqxtnb.s
@@ -14,16 +14,16 @@ uqxtnb z0.b, z31.h
 // CHECK-INST: uqxtnb	z0.b, z31.h
 // CHECK-ENCODING: [0xe0,0x4b,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 4b 28 45 <unknown>
+// CHECK-UNKNOWN: 45284be0 <unknown>
 
 uqxtnb z0.h, z31.s
 // CHECK-INST: uqxtnb	z0.h, z31.s
 // CHECK-ENCODING: [0xe0,0x4b,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 4b 30 45 <unknown>
+// CHECK-UNKNOWN: 45304be0 <unknown>
 
 uqxtnb z0.s, z31.d
 // CHECK-INST: uqxtnb	z0.s, z31.d
 // CHECK-ENCODING: [0xe0,0x4b,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 4b 60 45 <unknown>
+// CHECK-UNKNOWN: 45604be0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/uqxtnt.s b/llvm/test/MC/AArch64/SVE2/uqxtnt.s
index 8f8ed690140dc..ab83a129b0c18 100644
--- a/llvm/test/MC/AArch64/SVE2/uqxtnt.s
+++ b/llvm/test/MC/AArch64/SVE2/uqxtnt.s
@@ -14,16 +14,16 @@ uqxtnt z0.b, z31.h
 // CHECK-INST: uqxtnt	z0.b, z31.h
 // CHECK-ENCODING: [0xe0,0x4f,0x28,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 4f 28 45 <unknown>
+// CHECK-UNKNOWN: 45284fe0 <unknown>
 
 uqxtnt z0.h, z31.s
 // CHECK-INST: uqxtnt	z0.h, z31.s
 // CHECK-ENCODING: [0xe0,0x4f,0x30,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 4f 30 45 <unknown>
+// CHECK-UNKNOWN: 45304fe0 <unknown>
 
 uqxtnt z0.s, z31.d
 // CHECK-INST: uqxtnt	z0.s, z31.d
 // CHECK-ENCODING: [0xe0,0x4f,0x60,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 4f 60 45 <unknown>
+// CHECK-UNKNOWN: 45604fe0 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/urecpe.s b/llvm/test/MC/AArch64/SVE2/urecpe.s
index bb5631410de10..a93cc7078a1af 100644
--- a/llvm/test/MC/AArch64/SVE2/urecpe.s
+++ b/llvm/test/MC/AArch64/SVE2/urecpe.s
@@ -13,7 +13,7 @@ urecpe z31.s, p7/m, z31.s
 // CHECK-INST: urecpe z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x80,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff bf 80 44 <unknown>
+// CHECK-UNKNOWN: 4480bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -23,22 +23,22 @@ movprfx z4.s, p7/z, z6.s
 // CHECK-INST: movprfx	z4.s, p7/z, z6.s
 // CHECK-ENCODING: [0xc4,0x3c,0x90,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c 90 04 <unknown>
+// CHECK-UNKNOWN: 04903cc4 <unknown>
 
 urecpe z4.s, p7/m, z31.s
 // CHECK-INST: urecpe z4.s, p7/m, z31.s
 // CHECK-ENCODING: [0xe4,0xbf,0x80,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 bf 80 44 <unknown>
+// CHECK-UNKNOWN: 4480bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 urecpe z4.s, p7/m, z31.s
 // CHECK-INST: urecpe z4.s, p7/m, z31.s
 // CHECK-ENCODING: [0xe4,0xbf,0x80,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 bf 80 44 <unknown>
+// CHECK-UNKNOWN: 4480bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/urhadd.s b/llvm/test/MC/AArch64/SVE2/urhadd.s
index f4530bc20d22e..59417ae489b1b 100644
--- a/llvm/test/MC/AArch64/SVE2/urhadd.s
+++ b/llvm/test/MC/AArch64/SVE2/urhadd.s
@@ -13,25 +13,25 @@ urhadd z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: urhadd z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x15,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 15 44 <unknown>
+// CHECK-UNKNOWN: 44158020 <unknown>
 
 urhadd z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: urhadd z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x55,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 55 44 <unknown>
+// CHECK-UNKNOWN: 44558020 <unknown>
 
 urhadd z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: urhadd z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x95,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 95 44 <unknown>
+// CHECK-UNKNOWN: 44959fdd <unknown>
 
 urhadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: urhadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d5 44 <unknown>
+// CHECK-UNKNOWN: 44d59fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 urhadd z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: urhadd z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xd5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 d5 44 <unknown>
+// CHECK-UNKNOWN: 44d583df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 urhadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: urhadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xd5,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f d5 44 <unknown>
+// CHECK-UNKNOWN: 44d59fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/urshl.s b/llvm/test/MC/AArch64/SVE2/urshl.s
index ad3b4584ce1e3..c4a791cb938d6 100644
--- a/llvm/test/MC/AArch64/SVE2/urshl.s
+++ b/llvm/test/MC/AArch64/SVE2/urshl.s
@@ -13,25 +13,25 @@ urshl z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: urshl z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x03,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 03 44 <unknown>
+// CHECK-UNKNOWN: 44038020 <unknown>
 
 urshl z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: urshl z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x43,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 43 44 <unknown>
+// CHECK-UNKNOWN: 44438020 <unknown>
 
 urshl z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: urshl z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x83,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 83 44 <unknown>
+// CHECK-UNKNOWN: 44839fdd <unknown>
 
 urshl z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: urshl z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xc3,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f c3 44 <unknown>
+// CHECK-UNKNOWN: 44c39fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 urshl z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: urshl z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xc3,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 c3 44 <unknown>
+// CHECK-UNKNOWN: 44c383df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 urshl z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: urshl z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xc3,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f c3 44 <unknown>
+// CHECK-UNKNOWN: 44c39fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/urshlr.s b/llvm/test/MC/AArch64/SVE2/urshlr.s
index 0abd7da5e6903..28211ce8f63eb 100644
--- a/llvm/test/MC/AArch64/SVE2/urshlr.s
+++ b/llvm/test/MC/AArch64/SVE2/urshlr.s
@@ -13,25 +13,25 @@ urshlr z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: urshlr z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x07,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 07 44 <unknown>
+// CHECK-UNKNOWN: 44078020 <unknown>
 
 urshlr z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: urshlr z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x47,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 47 44 <unknown>
+// CHECK-UNKNOWN: 44478020 <unknown>
 
 urshlr z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: urshlr z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x87,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 87 44 <unknown>
+// CHECK-UNKNOWN: 44879fdd <unknown>
 
 urshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: urshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xc7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f c7 44 <unknown>
+// CHECK-UNKNOWN: 44c79fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 urshlr z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: urshlr z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xc7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 c7 44 <unknown>
+// CHECK-UNKNOWN: 44c783df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 urshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: urshlr z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xc7,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f c7 44 <unknown>
+// CHECK-UNKNOWN: 44c79fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/urshr.s b/llvm/test/MC/AArch64/SVE2/urshr.s
index 03e100164a6c8..b8501b856ecdb 100644
--- a/llvm/test/MC/AArch64/SVE2/urshr.s
+++ b/llvm/test/MC/AArch64/SVE2/urshr.s
@@ -13,49 +13,49 @@ urshr    z0.b, p0/m, z0.b, #1
 // CHECK-INST: urshr	z0.b, p0/m, z0.b, #1
 // CHECK-ENCODING: [0xe0,0x81,0x0d,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 81 0d 04 <unknown>
+// CHECK-UNKNOWN: 040d81e0 <unknown>
 
 urshr    z31.b, p0/m, z31.b, #8
 // CHECK-INST: urshr	z31.b, p0/m, z31.b, #8
 // CHECK-ENCODING: [0x1f,0x81,0x0d,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 81 0d 04 <unknown>
+// CHECK-UNKNOWN: 040d811f <unknown>
 
 urshr    z0.h, p0/m, z0.h, #1
 // CHECK-INST: urshr	z0.h, p0/m, z0.h, #1
 // CHECK-ENCODING: [0xe0,0x83,0x0d,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 83 0d 04 <unknown>
+// CHECK-UNKNOWN: 040d83e0 <unknown>
 
 urshr    z31.h, p0/m, z31.h, #16
 // CHECK-INST: urshr	z31.h, p0/m, z31.h, #16
 // CHECK-ENCODING: [0x1f,0x82,0x0d,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 82 0d 04 <unknown>
+// CHECK-UNKNOWN: 040d821f <unknown>
 
 urshr    z0.s, p0/m, z0.s, #1
 // CHECK-INST: urshr	z0.s, p0/m, z0.s, #1
 // CHECK-ENCODING: [0xe0,0x83,0x4d,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 83 4d 04 <unknown>
+// CHECK-UNKNOWN: 044d83e0 <unknown>
 
 urshr    z31.s, p0/m, z31.s, #32
 // CHECK-INST: urshr	z31.s, p0/m, z31.s, #32
 // CHECK-ENCODING: [0x1f,0x80,0x4d,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 80 4d 04 <unknown>
+// CHECK-UNKNOWN: 044d801f <unknown>
 
 urshr    z0.d, p0/m, z0.d, #1
 // CHECK-INST: urshr	z0.d, p0/m, z0.d, #1
 // CHECK-ENCODING: [0xe0,0x83,0xcd,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e0 83 cd 04 <unknown>
+// CHECK-UNKNOWN: 04cd83e0 <unknown>
 
 urshr    z31.d, p0/m, z31.d, #64
 // CHECK-INST: urshr	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x8d,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 80 8d 04 <unknown>
+// CHECK-UNKNOWN: 048d801f <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -65,22 +65,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx	z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 urshr    z31.d, p0/m, z31.d, #64
 // CHECK-INST: urshr	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x8d,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 80 8d 04 <unknown>
+// CHECK-UNKNOWN: 048d801f <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx	z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 urshr    z31.d, p0/m, z31.d, #64
 // CHECK-INST: urshr	z31.d, p0/m, z31.d, #64
 // CHECK-ENCODING: [0x1f,0x80,0x8d,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 80 8d 04 <unknown>
+// CHECK-UNKNOWN: 048d801f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ursqrte.s b/llvm/test/MC/AArch64/SVE2/ursqrte.s
index 4e4fd60513b69..ae7c2521977b3 100644
--- a/llvm/test/MC/AArch64/SVE2/ursqrte.s
+++ b/llvm/test/MC/AArch64/SVE2/ursqrte.s
@@ -13,7 +13,7 @@ ursqrte z31.s, p7/m, z31.s
 // CHECK-INST: ursqrte z31.s, p7/m, z31.s
 // CHECK-ENCODING: [0xff,0xbf,0x81,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff bf 81 44 <unknown>
+// CHECK-UNKNOWN: 4481bfff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -23,22 +23,22 @@ movprfx z4.s, p7/z, z6.s
 // CHECK-INST: movprfx	z4.s, p7/z, z6.s
 // CHECK-ENCODING: [0xc4,0x3c,0x90,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 3c 90 04 <unknown>
+// CHECK-UNKNOWN: 04903cc4 <unknown>
 
 ursqrte z4.s, p7/m, z31.s
 // CHECK-INST: ursqrte z4.s, p7/m, z31.s
 // CHECK-ENCODING: [0xe4,0xbf,0x81,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 bf 81 44 <unknown>
+// CHECK-UNKNOWN: 4481bfe4 <unknown>
 
 movprfx z4, z6
 // CHECK-INST: movprfx	z4, z6
 // CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcc4 <unknown>
 
 ursqrte z4.s, p7/m, z31.s
 // CHECK-INST: ursqrte z4.s, p7/m, z31.s
 // CHECK-ENCODING: [0xe4,0xbf,0x81,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: e4 bf 81 44 <unknown>
+// CHECK-UNKNOWN: 4481bfe4 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ursra.s b/llvm/test/MC/AArch64/SVE2/ursra.s
index 975a876135d92..5de5196fdda40 100644
--- a/llvm/test/MC/AArch64/SVE2/ursra.s
+++ b/llvm/test/MC/AArch64/SVE2/ursra.s
@@ -13,49 +13,49 @@ ursra     z0.b, z0.b, #1
 // CHECK-INST: ursra	z0.b, z0.b, #1
 // CHECK-ENCODING: [0x00,0xec,0x0f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 ec 0f 45 <unknown>
+// CHECK-UNKNOWN: 450fec00 <unknown>
 
 ursra     z31.b, z31.b, #8
 // CHECK-INST: ursra	z31.b, z31.b, #8
 // CHECK-ENCODING: [0xff,0xef,0x08,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff ef 08 45 <unknown>
+// CHECK-UNKNOWN: 4508efff <unknown>
 
 ursra     z0.h, z0.h, #1
 // CHECK-INST: ursra	z0.h, z0.h, #1
 // CHECK-ENCODING: [0x00,0xec,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 ec 1f 45 <unknown>
+// CHECK-UNKNOWN: 451fec00 <unknown>
 
 ursra     z31.h, z31.h, #16
 // CHECK-INST: ursra	z31.h, z31.h, #16
 // CHECK-ENCODING: [0xff,0xef,0x10,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff ef 10 45 <unknown>
+// CHECK-UNKNOWN: 4510efff <unknown>
 
 ursra     z0.s, z0.s, #1
 // CHECK-INST: ursra	z0.s, z0.s, #1
 // CHECK-ENCODING: [0x00,0xec,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 ec 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fec00 <unknown>
 
 ursra     z31.s, z31.s, #32
 // CHECK-INST: ursra	z31.s, z31.s, #32
 // CHECK-ENCODING: [0xff,0xef,0x40,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff ef 40 45 <unknown>
+// CHECK-UNKNOWN: 4540efff <unknown>
 
 ursra     z0.d, z0.d, #1
 // CHECK-INST: ursra	z0.d, z0.d, #1
 // CHECK-ENCODING: [0x00,0xec,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 ec df 45 <unknown>
+// CHECK-UNKNOWN: 45dfec00 <unknown>
 
 ursra     z31.d, z31.d, #64
 // CHECK-INST: ursra	z31.d, z31.d, #64
 // CHECK-ENCODING: [0xff,0xef,0x80,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff ef 80 45 <unknown>
+// CHECK-UNKNOWN: 4580efff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -65,10 +65,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 ursra     z0.d, z1.d, #1
 // CHECK-INST: ursra	z0.d, z1.d, #1
 // CHECK-ENCODING: [0x20,0xec,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 ec df 45 <unknown>
+// CHECK-UNKNOWN: 45dfec20 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ushllb.s b/llvm/test/MC/AArch64/SVE2/ushllb.s
index 3ab875df9038c..8791b144a0eba 100644
--- a/llvm/test/MC/AArch64/SVE2/ushllb.s
+++ b/llvm/test/MC/AArch64/SVE2/ushllb.s
@@ -13,34 +13,34 @@ ushllb     z0.h, z0.b, #0
 // CHECK-INST: ushllb	z0.h, z0.b, #0
 // CHECK-ENCODING: [0x00,0xa8,0x08,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 a8 08 45 <unknown>
+// CHECK-UNKNOWN: 4508a800 <unknown>
 
 ushllb     z31.h, z31.b, #7
 // CHECK-INST: ushllb	z31.h, z31.b, #7
 // CHECK-ENCODING: [0xff,0xab,0x0f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff ab 0f 45 <unknown>
+// CHECK-UNKNOWN: 450fabff <unknown>
 
 ushllb     z0.s, z0.h, #0
 // CHECK-INST: ushllb	z0.s, z0.h, #0
 // CHECK-ENCODING: [0x00,0xa8,0x10,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 a8 10 45 <unknown>
+// CHECK-UNKNOWN: 4510a800 <unknown>
 
 ushllb     z31.s, z31.h, #15
 // CHECK-INST: ushllb	z31.s, z31.h, #15
 // CHECK-ENCODING: [0xff,0xab,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff ab 1f 45 <unknown>
+// CHECK-UNKNOWN: 451fabff <unknown>
 
 ushllb     z0.d, z0.s, #0
 // CHECK-INST: ushllb	z0.d, z0.s, #0
 // CHECK-ENCODING: [0x00,0xa8,0x40,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 a8 40 45 <unknown>
+// CHECK-UNKNOWN: 4540a800 <unknown>
 
 ushllb     z31.d, z31.s, #31
 // CHECK-INST: ushllb	z31.d, z31.s, #31
 // CHECK-ENCODING: [0xff,0xab,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff ab 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fabff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/ushllt.s b/llvm/test/MC/AArch64/SVE2/ushllt.s
index 4d0d928c62356..a955d3f7dc272 100644
--- a/llvm/test/MC/AArch64/SVE2/ushllt.s
+++ b/llvm/test/MC/AArch64/SVE2/ushllt.s
@@ -13,34 +13,34 @@ ushllt     z0.h, z0.b, #0
 // CHECK-INST: ushllt	z0.h, z0.b, #0
 // CHECK-ENCODING: [0x00,0xac,0x08,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 ac 08 45 <unknown>
+// CHECK-UNKNOWN: 4508ac00 <unknown>
 
 ushllt     z31.h, z31.b, #7
 // CHECK-INST: ushllt	z31.h, z31.b, #7
 // CHECK-ENCODING: [0xff,0xaf,0x0f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff af 0f 45 <unknown>
+// CHECK-UNKNOWN: 450fafff <unknown>
 
 ushllt     z0.s, z0.h, #0
 // CHECK-INST: ushllt	z0.s, z0.h, #0
 // CHECK-ENCODING: [0x00,0xac,0x10,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 ac 10 45 <unknown>
+// CHECK-UNKNOWN: 4510ac00 <unknown>
 
 ushllt     z31.s, z31.h, #15
 // CHECK-INST: ushllt	z31.s, z31.h, #15
 // CHECK-ENCODING: [0xff,0xaf,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff af 1f 45 <unknown>
+// CHECK-UNKNOWN: 451fafff <unknown>
 
 ushllt     z0.d, z0.s, #0
 // CHECK-INST: ushllt	z0.d, z0.s, #0
 // CHECK-ENCODING: [0x00,0xac,0x40,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 ac 40 45 <unknown>
+// CHECK-UNKNOWN: 4540ac00 <unknown>
 
 ushllt     z31.d, z31.s, #31
 // CHECK-INST: ushllt	z31.d, z31.s, #31
 // CHECK-ENCODING: [0xff,0xaf,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff af 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fafff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/usqadd.s b/llvm/test/MC/AArch64/SVE2/usqadd.s
index 0bc8c9bffa5cf..c12aa0e5844ee 100644
--- a/llvm/test/MC/AArch64/SVE2/usqadd.s
+++ b/llvm/test/MC/AArch64/SVE2/usqadd.s
@@ -13,25 +13,25 @@ usqadd z0.b, p0/m, z0.b, z1.b
 // CHECK-INST: usqadd z0.b, p0/m, z0.b, z1.b
 // CHECK-ENCODING: [0x20,0x80,0x1d,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 1d 44 <unknown>
+// CHECK-UNKNOWN: 441d8020 <unknown>
 
 usqadd z0.h, p0/m, z0.h, z1.h
 // CHECK-INST: usqadd z0.h, p0/m, z0.h, z1.h
 // CHECK-ENCODING: [0x20,0x80,0x5d,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 80 5d 44 <unknown>
+// CHECK-UNKNOWN: 445d8020 <unknown>
 
 usqadd z29.s, p7/m, z29.s, z30.s
 // CHECK-INST: usqadd z29.s, p7/m, z29.s, z30.s
 // CHECK-ENCODING: [0xdd,0x9f,0x9d,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 9f 9d 44 <unknown>
+// CHECK-UNKNOWN: 449d9fdd <unknown>
 
 usqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: usqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xdd,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f dd 44 <unknown>
+// CHECK-UNKNOWN: 44dd9fdf <unknown>
 
 // --------------------------------------------------------------------------//
 // Test compatibility with MOVPRFX instruction.
@@ -40,22 +40,22 @@ movprfx z31.d, p0/z, z6.d
 // CHECK-INST: movprfx z31.d, p0/z, z6.d
 // CHECK-ENCODING: [0xdf,0x20,0xd0,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df 20 d0 04 <unknown>
+// CHECK-UNKNOWN: 04d020df <unknown>
 
 usqadd z31.d, p0/m, z31.d, z30.d
 // CHECK-INST: usqadd z31.d, p0/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x83,0xdd,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 83 dd 44 <unknown>
+// CHECK-UNKNOWN: 44dd83df <unknown>
 
 movprfx z31, z6
 // CHECK-INST: movprfx z31, z6
 // CHECK-ENCODING: [0xdf,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: df bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcdf <unknown>
 
 usqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-INST: usqadd z31.d, p7/m, z31.d, z30.d
 // CHECK-ENCODING: [0xdf,0x9f,0xdd,0x44]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 9f dd 44 <unknown>
+// CHECK-UNKNOWN: 44dd9fdf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/usra.s b/llvm/test/MC/AArch64/SVE2/usra.s
index 13cf7dd99805c..fdc49ef8c3a04 100644
--- a/llvm/test/MC/AArch64/SVE2/usra.s
+++ b/llvm/test/MC/AArch64/SVE2/usra.s
@@ -13,49 +13,49 @@ usra     z0.b, z0.b, #1
 // CHECK-INST: usra	z0.b, z0.b, #1
 // CHECK-ENCODING: [0x00,0xe4,0x0f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 e4 0f 45 <unknown>
+// CHECK-UNKNOWN: 450fe400 <unknown>
 
 usra     z31.b, z31.b, #8
 // CHECK-INST: usra	z31.b, z31.b, #8
 // CHECK-ENCODING: [0xff,0xe7,0x08,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff e7 08 45 <unknown>
+// CHECK-UNKNOWN: 4508e7ff <unknown>
 
 usra     z0.h, z0.h, #1
 // CHECK-INST: usra	z0.h, z0.h, #1
 // CHECK-ENCODING: [0x00,0xe4,0x1f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 e4 1f 45 <unknown>
+// CHECK-UNKNOWN: 451fe400 <unknown>
 
 usra     z31.h, z31.h, #16
 // CHECK-INST: usra	z31.h, z31.h, #16
 // CHECK-ENCODING: [0xff,0xe7,0x10,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff e7 10 45 <unknown>
+// CHECK-UNKNOWN: 4510e7ff <unknown>
 
 usra     z0.s, z0.s, #1
 // CHECK-INST: usra	z0.s, z0.s, #1
 // CHECK-ENCODING: [0x00,0xe4,0x5f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 e4 5f 45 <unknown>
+// CHECK-UNKNOWN: 455fe400 <unknown>
 
 usra     z31.s, z31.s, #32
 // CHECK-INST: usra	z31.s, z31.s, #32
 // CHECK-ENCODING: [0xff,0xe7,0x40,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff e7 40 45 <unknown>
+// CHECK-UNKNOWN: 4540e7ff <unknown>
 
 usra     z0.d, z0.d, #1
 // CHECK-INST: usra	z0.d, z0.d, #1
 // CHECK-ENCODING: [0x00,0xe4,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 00 e4 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfe400 <unknown>
 
 usra     z31.d, z31.d, #64
 // CHECK-INST: usra	z31.d, z31.d, #64
 // CHECK-ENCODING: [0xff,0xe7,0x80,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff e7 80 45 <unknown>
+// CHECK-UNKNOWN: 4580e7ff <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -65,10 +65,10 @@ movprfx z0, z7
 // CHECK-INST: movprfx	z0, z7
 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bce0 <unknown>
 
 usra     z0.d, z1.d, #1
 // CHECK-INST: usra	z0.d, z1.d, #1
 // CHECK-ENCODING: [0x20,0xe4,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 e4 df 45 <unknown>
+// CHECK-UNKNOWN: 45dfe420 <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/usublb.s b/llvm/test/MC/AArch64/SVE2/usublb.s
index ce6134c44df79..41f84aaf1852c 100644
--- a/llvm/test/MC/AArch64/SVE2/usublb.s
+++ b/llvm/test/MC/AArch64/SVE2/usublb.s
@@ -14,16 +14,16 @@ usublb z0.h, z1.b, z2.b
 // CHECK-INST: usublb z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x18,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 18 42 45 <unknown>
+// CHECK-UNKNOWN: 45421820 <unknown>
 
 usublb z29.s, z30.h, z31.h
 // CHECK-INST: usublb z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x1b,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 1b 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f1bdd <unknown>
 
 usublb z31.d, z31.s, z31.s
 // CHECK-INST: usublb z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1b,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 1b df 45 <unknown>
+// CHECK-UNKNOWN: 45df1bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/usublt.s b/llvm/test/MC/AArch64/SVE2/usublt.s
index bde7736ba29cc..0420356878cdf 100644
--- a/llvm/test/MC/AArch64/SVE2/usublt.s
+++ b/llvm/test/MC/AArch64/SVE2/usublt.s
@@ -14,16 +14,16 @@ usublt z0.h, z1.b, z2.b
 // CHECK-INST: usublt z0.h, z1.b, z2.b
 // CHECK-ENCODING: [0x20,0x1c,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 1c 42 45 <unknown>
+// CHECK-UNKNOWN: 45421c20 <unknown>
 
 usublt z29.s, z30.h, z31.h
 // CHECK-INST: usublt z29.s, z30.h, z31.h
 // CHECK-ENCODING: [0xdd,0x1f,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 1f 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f1fdd <unknown>
 
 usublt z31.d, z31.s, z31.s
 // CHECK-INST: usublt z31.d, z31.s, z31.s
 // CHECK-ENCODING: [0xff,0x1f,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 1f df 45 <unknown>
+// CHECK-UNKNOWN: 45df1fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/usubwb.s b/llvm/test/MC/AArch64/SVE2/usubwb.s
index 37b6f951b214c..1bdd132f7c7ff 100644
--- a/llvm/test/MC/AArch64/SVE2/usubwb.s
+++ b/llvm/test/MC/AArch64/SVE2/usubwb.s
@@ -14,16 +14,16 @@ usubwb z0.h, z1.h, z2.b
 // CHECK-INST: usubwb z0.h, z1.h, z2.b
 // CHECK-ENCODING: [0x20,0x58,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 58 42 45 <unknown>
+// CHECK-UNKNOWN: 45425820 <unknown>
 
 usubwb z29.s, z30.s, z31.h
 // CHECK-INST: usubwb z29.s, z30.s, z31.h
 // CHECK-ENCODING: [0xdd,0x5b,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 5b 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f5bdd <unknown>
 
 usubwb z31.d, z31.d, z31.s
 // CHECK-INST: usubwb z31.d, z31.d, z31.s
 // CHECK-ENCODING: [0xff,0x5b,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 5b df 45 <unknown>
+// CHECK-UNKNOWN: 45df5bff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/usubwt.s b/llvm/test/MC/AArch64/SVE2/usubwt.s
index 2c8fb84b7ce72..3bd5abeb44da4 100644
--- a/llvm/test/MC/AArch64/SVE2/usubwt.s
+++ b/llvm/test/MC/AArch64/SVE2/usubwt.s
@@ -14,16 +14,16 @@ usubwt z0.h, z1.h, z2.b
 // CHECK-INST: usubwt z0.h, z1.h, z2.b
 // CHECK-ENCODING: [0x20,0x5c,0x42,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 5c 42 45 <unknown>
+// CHECK-UNKNOWN: 45425c20 <unknown>
 
 usubwt z29.s, z30.s, z31.h
 // CHECK-INST: usubwt z29.s, z30.s, z31.h
 // CHECK-ENCODING: [0xdd,0x5f,0x9f,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: dd 5f 9f 45 <unknown>
+// CHECK-UNKNOWN: 459f5fdd <unknown>
 
 usubwt z31.d, z31.d, z31.s
 // CHECK-INST: usubwt z31.d, z31.d, z31.s
 // CHECK-ENCODING: [0xff,0x5f,0xdf,0x45]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 5f df 45 <unknown>
+// CHECK-UNKNOWN: 45df5fff <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/whilege.s b/llvm/test/MC/AArch64/SVE2/whilege.s
index d145da2ae366b..cec9aff723887 100644
--- a/llvm/test/MC/AArch64/SVE2/whilege.s
+++ b/llvm/test/MC/AArch64/SVE2/whilege.s
@@ -13,58 +13,58 @@ whilege  p15.b, xzr, x0
 // CHECK-INST: whilege	p15.b, xzr, x0
 // CHECK-ENCODING: [0xef,0x13,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ef 13 20 25 <unknown>
+// CHECK-UNKNOWN: 252013ef <unknown>
 
 whilege  p15.b, x0, xzr
 // CHECK-INST: whilege	p15.b, x0, xzr
 // CHECK-ENCODING: [0x0f,0x10,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 10 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f100f <unknown>
 
 whilege  p15.b, wzr, w0
 // CHECK-INST: whilege	p15.b, wzr, w0
 // CHECK-ENCODING: [0xef,0x03,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ef 03 20 25 <unknown>
+// CHECK-UNKNOWN: 252003ef <unknown>
 
 whilege  p15.b, w0, wzr
 // CHECK-INST: whilege	p15.b, w0, wzr
 // CHECK-ENCODING: [0x0f,0x00,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 00 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f000f <unknown>
 
 whilege  p15.h, x0, xzr
 // CHECK-INST: whilege	p15.h, x0, xzr
 // CHECK-ENCODING: [0x0f,0x10,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 10 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f100f <unknown>
 
 whilege  p15.h, w0, wzr
 // CHECK-INST: whilege	p15.h, w0, wzr
 // CHECK-ENCODING: [0x0f,0x00,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 00 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f000f <unknown>
 
 whilege  p15.s, x0, xzr
 // CHECK-INST: whilege	p15.s, x0, xzr
 // CHECK-ENCODING: [0x0f,0x10,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 10 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf100f <unknown>
 
 whilege  p15.s, w0, wzr
 // CHECK-INST: whilege	p15.s, w0, wzr
 // CHECK-ENCODING: [0x0f,0x00,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 00 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf000f <unknown>
 
 whilege  p15.d, w0, wzr
 // CHECK-INST: whilege	p15.d, w0, wzr
 // CHECK-ENCODING: [0x0f,0x00,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 00 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff000f <unknown>
 
 whilege  p15.d, x0, xzr
 // CHECK-INST: whilege	p15.d, x0, xzr
 // CHECK-ENCODING: [0x0f,0x10,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 10 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff100f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/whilegt.s b/llvm/test/MC/AArch64/SVE2/whilegt.s
index 8effd64d14193..7526d1d72ac30 100644
--- a/llvm/test/MC/AArch64/SVE2/whilegt.s
+++ b/llvm/test/MC/AArch64/SVE2/whilegt.s
@@ -13,58 +13,58 @@ whilegt  p15.b, xzr, x0
 // CHECK-INST: whilegt	p15.b, xzr, x0
 // CHECK-ENCODING: [0xff,0x13,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 13 20 25 <unknown>
+// CHECK-UNKNOWN: 252013ff <unknown>
 
 whilegt  p15.b, x0, xzr
 // CHECK-INST: whilegt	p15.b, x0, xzr
 // CHECK-ENCODING: [0x1f,0x10,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 10 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f101f <unknown>
 
 whilegt  p15.b, wzr, w0
 // CHECK-INST: whilegt	p15.b, wzr, w0
 // CHECK-ENCODING: [0xff,0x03,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 03 20 25 <unknown>
+// CHECK-UNKNOWN: 252003ff <unknown>
 
 whilegt  p15.b, w0, wzr
 // CHECK-INST: whilegt	p15.b, w0, wzr
 // CHECK-ENCODING: [0x1f,0x00,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 00 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f001f <unknown>
 
 whilegt  p15.h, x0, xzr
 // CHECK-INST: whilegt	p15.h, x0, xzr
 // CHECK-ENCODING: [0x1f,0x10,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 10 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f101f <unknown>
 
 whilegt  p15.h, w0, wzr
 // CHECK-INST: whilegt	p15.h, w0, wzr
 // CHECK-ENCODING: [0x1f,0x00,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 00 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f001f <unknown>
 
 whilegt  p15.s, x0, xzr
 // CHECK-INST: whilegt	p15.s, x0, xzr
 // CHECK-ENCODING: [0x1f,0x10,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 10 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf101f <unknown>
 
 whilegt  p15.s, w0, wzr
 // CHECK-INST: whilegt	p15.s, w0, wzr
 // CHECK-ENCODING: [0x1f,0x00,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 00 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf001f <unknown>
 
 whilegt  p15.d, w0, wzr
 // CHECK-INST: whilegt	p15.d, w0, wzr
 // CHECK-ENCODING: [0x1f,0x00,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 00 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff001f <unknown>
 
 whilegt  p15.d, x0, xzr
 // CHECK-INST: whilegt	p15.d, x0, xzr
 // CHECK-ENCODING: [0x1f,0x10,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 10 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff101f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/whilehi.s b/llvm/test/MC/AArch64/SVE2/whilehi.s
index 18588d4f37084..52d0d1eb00740 100644
--- a/llvm/test/MC/AArch64/SVE2/whilehi.s
+++ b/llvm/test/MC/AArch64/SVE2/whilehi.s
@@ -13,58 +13,58 @@ whilehi  p15.b, xzr, x0
 // CHECK-INST: whilehi	p15.b, xzr, x0
 // CHECK-ENCODING: [0xff,0x1b,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 1b 20 25 <unknown>
+// CHECK-UNKNOWN: 25201bff <unknown>
 
 whilehi  p15.b, x0, xzr
 // CHECK-INST: whilehi	p15.b, x0, xzr
 // CHECK-ENCODING: [0x1f,0x18,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 18 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f181f <unknown>
 
 whilehi  p15.b, wzr, w0
 // CHECK-INST: whilehi	p15.b, wzr, w0
 // CHECK-ENCODING: [0xff,0x0b,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ff 0b 20 25 <unknown>
+// CHECK-UNKNOWN: 25200bff <unknown>
 
 whilehi  p15.b, w0, wzr
 // CHECK-INST: whilehi	p15.b, w0, wzr
 // CHECK-ENCODING: [0x1f,0x08,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 08 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f081f <unknown>
 
 whilehi  p15.h, x0, xzr
 // CHECK-INST: whilehi	p15.h, x0, xzr
 // CHECK-ENCODING: [0x1f,0x18,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 18 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f181f <unknown>
 
 whilehi  p15.h, w0, wzr
 // CHECK-INST: whilehi	p15.h, w0, wzr
 // CHECK-ENCODING: [0x1f,0x08,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 08 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f081f <unknown>
 
 whilehi  p15.s, x0, xzr
 // CHECK-INST: whilehi	p15.s, x0, xzr
 // CHECK-ENCODING: [0x1f,0x18,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 18 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf181f <unknown>
 
 whilehi  p15.s, w0, wzr
 // CHECK-INST: whilehi	p15.s, w0, wzr
 // CHECK-ENCODING: [0x1f,0x08,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 08 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf081f <unknown>
 
 whilehi  p15.d, w0, wzr
 // CHECK-INST: whilehi	p15.d, w0, wzr
 // CHECK-ENCODING: [0x1f,0x08,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 08 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff081f <unknown>
 
 whilehi  p15.d, x0, xzr
 // CHECK-INST: whilehi	p15.d, x0, xzr
 // CHECK-ENCODING: [0x1f,0x18,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 1f 18 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff181f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/whilehs.s b/llvm/test/MC/AArch64/SVE2/whilehs.s
index 855cbbb112b48..46a4591587279 100644
--- a/llvm/test/MC/AArch64/SVE2/whilehs.s
+++ b/llvm/test/MC/AArch64/SVE2/whilehs.s
@@ -13,58 +13,58 @@ whilehs  p15.b, xzr, x0
 // CHECK-INST: whilehs	p15.b, xzr, x0
 // CHECK-ENCODING: [0xef,0x1b,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ef 1b 20 25 <unknown>
+// CHECK-UNKNOWN: 25201bef <unknown>
 
 whilehs  p15.b, x0, xzr
 // CHECK-INST: whilehs	p15.b, x0, xzr
 // CHECK-ENCODING: [0x0f,0x18,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 18 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f180f <unknown>
 
 whilehs  p15.b, wzr, w0
 // CHECK-INST: whilehs	p15.b, wzr, w0
 // CHECK-ENCODING: [0xef,0x0b,0x20,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: ef 0b 20 25 <unknown>
+// CHECK-UNKNOWN: 25200bef <unknown>
 
 whilehs  p15.b, w0, wzr
 // CHECK-INST: whilehs	p15.b, w0, wzr
 // CHECK-ENCODING: [0x0f,0x08,0x3f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 08 3f 25 <unknown>
+// CHECK-UNKNOWN: 253f080f <unknown>
 
 whilehs  p15.h, x0, xzr
 // CHECK-INST: whilehs	p15.h, x0, xzr
 // CHECK-ENCODING: [0x0f,0x18,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 18 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f180f <unknown>
 
 whilehs  p15.h, w0, wzr
 // CHECK-INST: whilehs	p15.h, w0, wzr
 // CHECK-ENCODING: [0x0f,0x08,0x7f,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 08 7f 25 <unknown>
+// CHECK-UNKNOWN: 257f080f <unknown>
 
 whilehs  p15.s, x0, xzr
 // CHECK-INST: whilehs	p15.s, x0, xzr
 // CHECK-ENCODING: [0x0f,0x18,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 18 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf180f <unknown>
 
 whilehs  p15.s, w0, wzr
 // CHECK-INST: whilehs	p15.s, w0, wzr
 // CHECK-ENCODING: [0x0f,0x08,0xbf,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 08 bf 25 <unknown>
+// CHECK-UNKNOWN: 25bf080f <unknown>
 
 whilehs  p15.d, w0, wzr
 // CHECK-INST: whilehs	p15.d, w0, wzr
 // CHECK-ENCODING: [0x0f,0x08,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 08 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff080f <unknown>
 
 whilehs  p15.d, x0, xzr
 // CHECK-INST: whilehs	p15.d, x0, xzr
 // CHECK-ENCODING: [0x0f,0x18,0xff,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 0f 18 ff 25 <unknown>
+// CHECK-UNKNOWN: 25ff180f <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/whilerw.s b/llvm/test/MC/AArch64/SVE2/whilerw.s
index a3255b77316eb..0fb8364ccd9c5 100644
--- a/llvm/test/MC/AArch64/SVE2/whilerw.s
+++ b/llvm/test/MC/AArch64/SVE2/whilerw.s
@@ -13,22 +13,22 @@ whilerw  p15.b, x30, x30
 // CHECK-INST: whilerw  p15.b, x30, x30
 // CHECK-ENCODING: [0xdf,0x33,0x3e,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 33 3e 25 <unknown>
+// CHECK-UNKNOWN: 253e33df <unknown>
 
 whilerw  p15.h, x30, x30
 // CHECK-INST: whilerw  p15.h, x30, x30
 // CHECK-ENCODING: [0xdf,0x33,0x7e,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 33 7e 25 <unknown>
+// CHECK-UNKNOWN: 257e33df <unknown>
 
 whilerw  p15.s, x30, x30
 // CHECK-INST: whilerw  p15.s, x30, x30
 // CHECK-ENCODING: [0xdf,0x33,0xbe,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 33 be 25 <unknown>
+// CHECK-UNKNOWN: 25be33df <unknown>
 
 whilerw  p15.d, x30, x30
 // CHECK-INST: whilerw  p15.d, x30, x30
 // CHECK-ENCODING: [0xdf,0x33,0xfe,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 33 fe 25 <unknown>
+// CHECK-UNKNOWN: 25fe33df <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/whilewr.s b/llvm/test/MC/AArch64/SVE2/whilewr.s
index f5fbbd11059a4..f2808171bab58 100644
--- a/llvm/test/MC/AArch64/SVE2/whilewr.s
+++ b/llvm/test/MC/AArch64/SVE2/whilewr.s
@@ -13,22 +13,22 @@ whilewr  p15.b, x30, x30
 // CHECK-INST: whilewr  p15.b, x30, x30
 // CHECK-ENCODING: [0xcf,0x33,0x3e,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: cf 33 3e 25 <unknown>
+// CHECK-UNKNOWN: 253e33cf <unknown>
 
 whilewr  p15.h, x30, x30
 // CHECK-INST: whilewr  p15.h, x30, x30
 // CHECK-ENCODING: [0xcf,0x33,0x7e,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: cf 33 7e 25 <unknown>
+// CHECK-UNKNOWN: 257e33cf <unknown>
 
 whilewr  p15.s, x30, x30
 // CHECK-INST: whilewr  p15.s, x30, x30
 // CHECK-ENCODING: [0xcf,0x33,0xbe,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: cf 33 be 25 <unknown>
+// CHECK-UNKNOWN: 25be33cf <unknown>
 
 whilewr  p15.d, x30, x30
 // CHECK-INST: whilewr  p15.d, x30, x30
 // CHECK-ENCODING: [0xcf,0x33,0xfe,0x25]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: cf 33 fe 25 <unknown>
+// CHECK-UNKNOWN: 25fe33cf <unknown>

diff  --git a/llvm/test/MC/AArch64/SVE2/xar.s b/llvm/test/MC/AArch64/SVE2/xar.s
index a8cb8eea74c43..e225cdd22b4d5 100644
--- a/llvm/test/MC/AArch64/SVE2/xar.s
+++ b/llvm/test/MC/AArch64/SVE2/xar.s
@@ -13,49 +13,49 @@ xar     z0.b, z0.b, z1.b, #1
 // CHECK-INST: xar	z0.b, z0.b, z1.b, #1
 // CHECK-ENCODING: [0x20,0x34,0x2f,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 34 2f 04 <unknown>
+// CHECK-UNKNOWN: 042f3420 <unknown>
 
 xar     z31.b, z31.b, z30.b, #8
 // CHECK-INST: xar	z31.b, z31.b, z30.b, #8
 // CHECK-ENCODING: [0xdf,0x37,0x28,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 37 28 04 <unknown>
+// CHECK-UNKNOWN: 042837df <unknown>
 
 xar     z0.h, z0.h, z1.h, #1
 // CHECK-INST: xar	z0.h, z0.h, z1.h, #1
 // CHECK-ENCODING: [0x20,0x34,0x3f,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 34 3f 04 <unknown>
+// CHECK-UNKNOWN: 043f3420 <unknown>
 
 xar     z31.h, z31.h, z30.h, #16
 // CHECK-INST: xar	z31.h, z31.h, z30.h, #16
 // CHECK-ENCODING: [0xdf,0x37,0x30,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 37 30 04 <unknown>
+// CHECK-UNKNOWN: 043037df <unknown>
 
 xar     z0.s, z0.s, z1.s, #1
 // CHECK-INST: xar	z0.s, z0.s, z1.s, #1
 // CHECK-ENCODING: [0x20,0x34,0x7f,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 34 7f 04 <unknown>
+// CHECK-UNKNOWN: 047f3420 <unknown>
 
 xar     z31.s, z31.s, z30.s, #32
 // CHECK-INST: xar	z31.s, z31.s, z30.s, #32
 // CHECK-ENCODING: [0xdf,0x37,0x60,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 37 60 04 <unknown>
+// CHECK-UNKNOWN: 046037df <unknown>
 
 xar     z0.d, z0.d, z1.d, #1
 // CHECK-INST: xar	z0.d, z0.d, z1.d, #1
 // CHECK-ENCODING: [0x20,0x34,0xff,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: 20 34 ff 04 <unknown>
+// CHECK-UNKNOWN: 04ff3420 <unknown>
 
 xar     z31.d, z31.d, z30.d, #64
 // CHECK-INST: xar	z31.d, z31.d, z30.d, #64
 // CHECK-ENCODING: [0xdf,0x37,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 37 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a037df <unknown>
 
 
 // --------------------------------------------------------------------------//
@@ -65,10 +65,10 @@ movprfx z31, z7
 // CHECK-INST: movprfx z31, z7
 // CHECK-ENCODING: [0xff,0xbc,0x20,0x04]
 // CHECK-ERROR: instruction requires: sve or sme
-// CHECK-UNKNOWN: ff bc 20 04 <unknown>
+// CHECK-UNKNOWN: 0420bcff <unknown>
 
 xar     z31.d, z31.d, z30.d, #64
 // CHECK-INST: xar     z31.d, z31.d, z30.d, #64
 // CHECK-ENCODING: [0xdf,0x37,0xa0,0x04]
 // CHECK-ERROR: instruction requires: sve2 or sme
-// CHECK-UNKNOWN: df 37 a0 04 <unknown>
+// CHECK-UNKNOWN: 04a037df <unknown>

diff  --git a/llvm/test/MC/AArch64/align.s b/llvm/test/MC/AArch64/align.s
index fa9950f987754..e1841c05ce791 100644
--- a/llvm/test/MC/AArch64/align.s
+++ b/llvm/test/MC/AArch64/align.s
@@ -1,11 +1,11 @@
 // RUN: llvm-mc -filetype=obj -triple aarch64-none-eabi %s | llvm-objdump -d - | FileCheck %s
 // RUN: llvm-mc -filetype=obj -triple aarch64_be-none-eabi %s | llvm-objdump -d - | FileCheck %s
 
-// CHECK:   0: 00 00 80 d2   mov     x0, #0
-// CHECK:   4: 00 00 80 d2   mov     x0, #0
-// CHECK:   8: 1f 20 03 d5   nop
-// CHECK:   c: 1f 20 03 d5   nop
-// CHECK:  10: 00 00 80 d2   mov     x0, #0
+// CHECK:   0: d2800000   mov     x0, #0
+// CHECK:   4: d2800000   mov     x0, #0
+// CHECK:   8: d503201f   nop
+// CHECK:   c: d503201f   nop
+// CHECK:  10: d2800000   mov     x0, #0
 
        .text
        mov x0, #0

diff  --git a/llvm/test/MC/AArch64/coff-relocations-offset.s b/llvm/test/MC/AArch64/coff-relocations-offset.s
index c16b445e9006a..1408ba826dea7 100644
--- a/llvm/test/MC/AArch64/coff-relocations-offset.s
+++ b/llvm/test/MC/AArch64/coff-relocations-offset.s
@@ -22,11 +22,11 @@ main:
     // .Ltmp2+8 points here
     .word 5
 
-// CHECK:      0: 20 00 00 90   adrp    x0, 0x4000
+// CHECK:      0: 90000020   adrp    x0, 0x4000
 // CHECK-NEXT:          0000000000000000:  IMAGE_REL_ARM64_PAGEBASE_REL21       .rdata
-// CHECK-NEXT: 4: 40 00 00 90   adrp    x0, 0x8000
+// CHECK-NEXT: 4: 90000040   adrp    x0, 0x8000
 // CHECK-NEXT:          0000000000000004:  IMAGE_REL_ARM64_PAGEBASE_REL21       $L.rdata_1
-// CHECK-NEXT: 8: 20 00 00 90   adrp    x0, 0x4000
+// CHECK-NEXT: 8: 90000020   adrp    x0, 0x4000
 // CHECK-NEXT:          0000000000000008:  IMAGE_REL_ARM64_PAGEBASE_REL21       $L.rdata_2
 
 // SYMBOLS:      Symbol {

diff  --git a/llvm/test/MC/AArch64/coff-relocations.s b/llvm/test/MC/AArch64/coff-relocations.s
index cfe1070b3a6d3..ae8209ecdd4ce 100644
--- a/llvm/test/MC/AArch64/coff-relocations.s
+++ b/llvm/test/MC/AArch64/coff-relocations.s
@@ -104,14 +104,14 @@ tbz x0, #0, target
 // CHECK:   }
 // CHECK: ]
 
-// DISASM: 30:       20 1a 09 b0     adrp    x0, 0x12345000
-// DISASM: 34:       00 14 0d 91     add     x0, x0, #837
-// DISASM: 38:       00 14 4d 39     ldrb    w0, [x0, #837]
-// DISASM: 3c:       00 a4 41 f9     ldr     x0, [x0, #840]
-// DISASM: 40:       00 00 00 91     add     x0, x0, #0
-// DISASM: 44:       00 00 40 91     add     x0, x0, #0, lsl #12
-// DISASM: 48:       00 00 40 f9     ldr     x0, [x0]
-// DISASM: 4c:       20 1a 09 30     adr     x0, #74565
+// DISASM: 30:       b0091a20     adrp    x0, 0x12345000
+// DISASM: 34:       910d1400     add     x0, x0, #837
+// DISASM: 38:       394d1400     ldrb    w0, [x0, #837]
+// DISASM: 3c:       f941a400     ldr     x0, [x0, #840]
+// DISASM: 40:       91000000     add     x0, x0, #0
+// DISASM: 44:       91400000     add     x0, x0, #0, lsl #12
+// DISASM: 48:       f9400000     ldr     x0, [x0]
+// DISASM: 4c:       30091a20     adr     x0, #74565
 
 // DATA: Contents of section .rdata:
 // DATA-NEXT:  0000 30000000 08000000

diff  --git a/llvm/test/MC/AArch64/coff-separator.s b/llvm/test/MC/AArch64/coff-separator.s
index 7535cf0571b94..64e8b92a98872 100644
--- a/llvm/test/MC/AArch64/coff-separator.s
+++ b/llvm/test/MC/AArch64/coff-separator.s
@@ -8,6 +8,6 @@ func:
 nop; nop
 add x0, x0, #42
 
-// CHECK:  0:       1f 20 03 d5     nop
-// CHECK:  4:       1f 20 03 d5     nop
-// CHECK:  8:       00 a8 00 91     add x0, x0, #42
+// CHECK:  0:       d503201f     nop
+// CHECK:  4:       d503201f     nop
+// CHECK:  8:       9100a800     add x0, x0, #42

diff  --git a/llvm/test/MC/AArch64/darwin-reloc-addsubimm.s b/llvm/test/MC/AArch64/darwin-reloc-addsubimm.s
index f3e31b224c21c..788658cd88379 100644
--- a/llvm/test/MC/AArch64/darwin-reloc-addsubimm.s
+++ b/llvm/test/MC/AArch64/darwin-reloc-addsubimm.s
@@ -4,9 +4,9 @@
 // OBJ-LABEL: Disassembly of section __TEXT,__text:
 
   add x2, x3, _data at pageoff
-// OBJ: [[addr:[0-9a-f]+]]: 62 00 00 91 add x2, x3, #0
+// OBJ: [[addr:[0-9a-f]+]]: 91000062 add x2, x3, #0
 // OBJ-NEXT: [[addr]]: ARM64_RELOC_PAGEOFF12	_data
 
   add x2, x3, #_data at pageoff, lsl #12
-// OBJ: [[addr:[0-9a-f]+]]: 62 00 40 91 add x2, x3, #0, lsl #12
+// OBJ: [[addr:[0-9a-f]+]]: 91400062 add x2, x3, #0, lsl #12
 // OBJ-NEXT: [[addr]]: ARM64_RELOC_PAGEOFF12	_data

diff  --git a/llvm/test/MC/AArch64/elf-reloc-addsubimm.s b/llvm/test/MC/AArch64/elf-reloc-addsubimm.s
index deecd20d59a87..b515ca9d7a446 100644
--- a/llvm/test/MC/AArch64/elf-reloc-addsubimm.s
+++ b/llvm/test/MC/AArch64/elf-reloc-addsubimm.s
@@ -4,10 +4,10 @@
 // OBJ-LABEL: Disassembly of section .text:
 
         add x2, x3, #:lo12:some_label
-// OBJ: [[addr:[0-9a-f]+]]: 62 00 00 91 add x2, x3, #0
+// OBJ: [[addr:[0-9a-f]+]]: 91000062 add x2, x3, #0
 // OBJ-NEXT: [[addr]]: R_AARCH64_ADD_ABS_LO12_NC	some_label
 
         add x2, x3, #:lo12:some_label, lsl #12
-// OBJ: [[addr:[0-9a-f]+]]: 62 00 40 91 add x2, x3, #0, lsl #12
+// OBJ: [[addr:[0-9a-f]+]]: 91400062 add x2, x3, #0, lsl #12
 // OBJ-NEXT: [[addr]]: R_AARCH64_ADD_ABS_LO12_NC	some_label
 

diff  --git a/llvm/test/MC/AArch64/inst-directive-other.s b/llvm/test/MC/AArch64/inst-directive-other.s
index 02f21c13d2959..02e51003d73ca 100644
--- a/llvm/test/MC/AArch64/inst-directive-other.s
+++ b/llvm/test/MC/AArch64/inst-directive-other.s
@@ -35,8 +35,8 @@ _func:
 // CHECK-ASM:        .{{long|word}}   3573751839
 // CHECK-ASM:        .inst   0xd503201f
 
-// CHECK-OBJ:        0:       1f 20 03 d5     nop
-// CHECK-OBJ-CODE:   4:       1f 20 03 d5     nop
+// CHECK-OBJ:        0:       d503201f     nop
+// CHECK-OBJ-CODE:   4:       d503201f     nop
 // CHECK-OBJ-DATA:   4:       1f 20 03 d5     .word 0xd503201f
 // CHECK-OBJ-BE:     4:       d5 03 20 1f     .word 0xd503201f
-// CHECK-OBJ:        8:       1f 20 03 d5     nop
+// CHECK-OBJ:        8:       d503201f     nop

diff  --git a/llvm/test/MC/ARM/Windows/literals-comments.s b/llvm/test/MC/ARM/Windows/literals-comments.s
index 031fa9750cb05..ebb92f9934622 100644
--- a/llvm/test/MC/ARM/Windows/literals-comments.s
+++ b/llvm/test/MC/ARM/Windows/literals-comments.s
@@ -16,7 +16,7 @@ function:
   nop; nop @ This retains both instructions
   bx lr
 
-@ CHECK:  0: 4f f0 2a 00   mov.w   r0, #42
-@ CHECK:  4: 00 bf         nop
-@ CHECK:  6: 00 bf         nop
-@ CHECK:  8: 70 47         bx      lr
+@ CHECK:  0: f04f 002a     mov.w   r0, #42
+@ CHECK:  4: bf00          nop
+@ CHECK:  6: bf00          nop
+@ CHECK:  8: 4770          bx      lr

diff  --git a/llvm/test/MC/ARM/Windows/mov32t-range.s b/llvm/test/MC/ARM/Windows/mov32t-range.s
index 5b29e75b53d33..7e16105cddc6f 100644
--- a/llvm/test/MC/ARM/Windows/mov32t-range.s
+++ b/llvm/test/MC/ARM/Windows/mov32t-range.s
@@ -32,6 +32,6 @@ truncation:
 @ CHECK-RELOCATIONS:   }
 @ CHECK-RELOCATIONS: ]
 
-@ CHECK-ENCODING:      0: 40 f2 00 00
-@ CHECK-ENCODING-NEXT: 4: c0 f2 01 00
+@ CHECK-ENCODING:      0: f240 0000
+@ CHECK-ENCODING-NEXT: 4: f2c0 0001
 

diff  --git a/llvm/test/MC/ARM/align_arm_2_thumb.s b/llvm/test/MC/ARM/align_arm_2_thumb.s
index 553dc89f2a360..7c1b77b32fd4b 100644
--- a/llvm/test/MC/ARM/align_arm_2_thumb.s
+++ b/llvm/test/MC/ARM/align_arm_2_thumb.s
@@ -10,6 +10,6 @@
 foo:
   add r0, r0
 .align 3
-@ ARM_2_THUMB: 2: 00 bf     nop
+@ ARM_2_THUMB: 2: bf00      nop
   add r0, r0
 

diff  --git a/llvm/test/MC/ARM/align_thumb_2_arm.s b/llvm/test/MC/ARM/align_thumb_2_arm.s
index 693a3ab5d6c91..546a392743f76 100644
--- a/llvm/test/MC/ARM/align_thumb_2_arm.s
+++ b/llvm/test/MC/ARM/align_thumb_2_arm.s
@@ -10,6 +10,6 @@
 foo:
   add r0, r0
 .align 3
-@ THUMB_2_ARM: 4: 00 f0 20 e3    nop
+@ THUMB_2_ARM: 4: e320f000       nop
   add r0, r0
 

diff  --git a/llvm/test/MC/ARM/elf-movt.s b/llvm/test/MC/ARM/elf-movt.s
index 0478a233b23cf..40227421eb784 100644
--- a/llvm/test/MC/ARM/elf-movt.s
+++ b/llvm/test/MC/ARM/elf-movt.s
@@ -32,27 +32,27 @@ bar:
 @OBJ:      Disassembly of section .text:
 @OBJ-EMPTY:
 @OBJ-NEXT: <barf>:
- at OBJ-NEXT: 0:             f0 0f 0f e3     movw    r0, #65520
+ at OBJ-NEXT: 0:             e30f0ff0        movw    r0, #65520
 @OBJ-NEXT: 00000000:         R_ARM_MOVW_PREL_NC   GOT
- at OBJ-NEXT: 4:             f4 0f 4f e3     movt    r0, #65524
+ at OBJ-NEXT: 4:             e34f0ff4        movt    r0, #65524
 @OBJ-NEXT: 00000004:         R_ARM_MOVT_PREL      GOT
- at OBJ-NEXT: 8:             d2 04 00 e3     movw    r0, #1234
+ at OBJ-NEXT: 8:             e30004d2        movw    r0, #1234
 @OBJ-NEXT: 00000008:         R_ARM_MOVW_ABS_NC    extern_symbol
- at OBJ-NEXT: c:             d2 04 40 e3     movt    r0, #1234
+ at OBJ-NEXT: c:             e34004d2        movt    r0, #1234
 @OBJ-NEXT: 0000000c:         R_ARM_MOVT_ABS       extern_symbol
- at OBJ-NEXT: 10:            d2 04 00 e3     movw    r0, #1234
- at OBJ-NEXT: 14:            00 00 40 e3     movt    r0, #0
+ at OBJ-NEXT: 10:            e30004d2        movw    r0, #1234
+ at OBJ-NEXT: 14:            e3400000        movt    r0, #0
 
 @THUMB:      Disassembly of section .text:
 @THUMB-EMPTY:
 @THUMB-NEXT: <barf>:
- at THUMB-NEXT: 0:             4f f6 f0 70     movw    r0, #65520
+ at THUMB-NEXT: 0:             f64f 70f0       movw    r0, #65520
 @THUMB-NEXT: 00000000:         R_ARM_THM_MOVW_PREL_NC GOT
- at THUMB-NEXT: 4:             cf f6 f4 70     movt    r0, #65524
+ at THUMB-NEXT: 4:             f6cf 70f4       movt    r0, #65524
 @THUMB-NEXT: 00000004:         R_ARM_THM_MOVT_PREL    GOT
- at THUMB-NEXT: 8:             40 f2 d2 40     movw    r0, #1234
+ at THUMB-NEXT: 8:             f240 40d2       movw    r0, #1234
 @THUMB-NEXT: 00000008:         R_ARM_THM_MOVW_ABS_NC  extern_symbol
- at THUMB-NEXT: c:             c0 f2 d2 40     movt    r0, #1234
+ at THUMB-NEXT: c:             f2c0 40d2       movt    r0, #1234
 @THUMB-NEXT: 0000000c:         R_ARM_THM_MOVT_ABS     extern_symbol
- at THUMB-NEXT: 10:            40 f2 d2 40     movw    r0, #1234
- at THUMB-NEXT: 14:            c0 f2 00 00     movt    r0, #0
+ at THUMB-NEXT: 10:            f240 40d2       movw    r0, #1234
+ at THUMB-NEXT: 14:            f2c0 0000       movt    r0, #0

diff  --git a/llvm/test/MC/ARM/inst-directive-other.s b/llvm/test/MC/ARM/inst-directive-other.s
index 06c89f5333ee0..e5914ec02aa46 100644
--- a/llvm/test/MC/ARM/inst-directive-other.s
+++ b/llvm/test/MC/ARM/inst-directive-other.s
@@ -37,11 +37,11 @@ _func:
 // CHECK-ASM:        .short  42
 // CHECK-ASM:        .inst.w 0xf04f002a
 
-// CHECK-OBJ:        0:       70 47           bx lr
-// CHECK-OBJ-CODE:   2:       70 47           bx lr
+// CHECK-OBJ:        0:       4770            bx lr
+// CHECK-OBJ-CODE:   2:       4770            bx lr
 // CHECK-OBJ-DATA:   2:       70 47           .short 0x4770
-// CHECK-OBJ:        4:       70 47           bx lr
-// CHECK-OBJ:        6:       4f f0 2a 00     mov.w   r0, #42
-// CHECK-OBJ-CODE:   a:       4f f0 2a 00     mov.w   r0, #42
+// CHECK-OBJ:        4:       4770            bx lr
+// CHECK-OBJ:        6:       f04f 002a       mov.w   r0, #42
+// CHECK-OBJ-CODE:   a:       f04f 002a       mov.w   r0, #42
 // CHECK-OBJ-DATA:   a:       4f f0 2a 00     .word 0x002af04f
-// CHECK-OBJ:        e:       4f f0 2a 00     mov.w   r0, #42
+// CHECK-OBJ:        e:       f04f 002a       mov.w   r0, #42

diff  --git a/llvm/test/MC/ARM/thumb1-relax-bcc.s b/llvm/test/MC/ARM/thumb1-relax-bcc.s
index 1b853991754fc..e3ba256ff6a7d 100644
--- a/llvm/test/MC/ARM/thumb1-relax-bcc.s
+++ b/llvm/test/MC/ARM/thumb1-relax-bcc.s
@@ -8,5 +8,5 @@ _func1:
 @ CHECK-ERROR: :[[#@LINE+1]]:9: error: unsupported relocation on symbol
         bne _func2
 
-@ CHECK-ELF: 7f f4 fe af        bne.w {{.+}} @ imm = #-4
+@ CHECK-ELF: f47f affe          bne.w {{.+}} @ imm = #-4
 @ CHECK-ELF-NEXT: R_ARM_THM_JUMP19 _func2

diff  --git a/llvm/test/MC/ARM/thumb1-relax-br.s b/llvm/test/MC/ARM/thumb1-relax-br.s
index 4c0ecb33ff33a..fba0aab4186ab 100644
--- a/llvm/test/MC/ARM/thumb1-relax-br.s
+++ b/llvm/test/MC/ARM/thumb1-relax-br.s
@@ -12,8 +12,8 @@ _func1:
 
 @ CHECK-ERROR: unsupported relocation on symbol
 
-@ CHECK-MACHO: ff f7 fe bf        b.w {{.+}} @ imm = #-4
+@ CHECK-MACHO: f7ff bffe          b.w {{.+}} @ imm = #-4
 @ CHECK-MACHO-NEXT: ARM_THUMB_RELOC_BR22
 
-@ CHECK-ELF: ff f7 fe bf        b.w {{.+}} @ imm = #-4
+@ CHECK-ELF: f7ff bffe          b.w {{.+}} @ imm = #-4
 @ CHECK-ELF-NEXT: R_ARM_THM_JUMP24 _func2

diff  --git a/llvm/test/MC/ARM/thumb2-cbn-to-next-inst.s b/llvm/test/MC/ARM/thumb2-cbn-to-next-inst.s
index 12b6b57aac22c..e6a34c74029ea 100644
--- a/llvm/test/MC/ARM/thumb2-cbn-to-next-inst.s
+++ b/llvm/test/MC/ARM/thumb2-cbn-to-next-inst.s
@@ -20,14 +20,14 @@ L3:
 L4:
 	add	r3, r4, r5
 
-@ CHECK: 0:	02 eb 03 01	add.w	r1, r2, r3
-@ CHECK: 4:	00 bf		nop
-@ CHECK: 6:	05 eb 06 04	add.w	r4, r5, r6
-@ CHECK: a:	0a b9		cbnz	r2, 0x10 <start+0x10> @ imm = #2
-@ CHECK: c:	a8 eb 09 07	sub.w	r7, r8, r9
-@ CHECK: 10:	08 eb 09 07	add.w	r7, r8, r9
-@ CHECK: 14:	00 bf		nop
-@ CHECK: 16:	0b eb 0c 0a	add.w	r10, r11, r12
-@ CHECK: 1a:	0a b1		cbz	r2, 0x20 <start+0x20> @ imm = #2
-@ CHECK: 1c:	a8 eb 09 07	sub.w	r7, r8, r9
-@ CHECK: 20:	04 eb 05 03	add.w	r3, r4, r5
+@ CHECK: 0:	eb02 0103  	add.w	r1, r2, r3
+@ CHECK: 4:	bf00		nop
+@ CHECK: 6:	eb05 0406  	add.w	r4, r5, r6
+@ CHECK: a:	b90a 		cbnz	r2, 0x10 <start+0x10> @ imm = #2
+@ CHECK: c:	eba8 0709  	sub.w	r7, r8, r9
+@ CHECK: 10:	eb08 0709  	add.w	r7, r8, r9
+@ CHECK: 14:	bf00 		nop
+@ CHECK: 16:	eb0b 0a0c  	add.w	r10, r11, r12
+@ CHECK: 1a:	b10a 		cbz	r2, 0x20 <start+0x20> @ imm = #2
+@ CHECK: 1c:	eba8 0709  	sub.w	r7, r8, r9
+@ CHECK: 20:	eb04 0305  	add.w	r3, r4, r5

diff  --git a/llvm/test/MC/Disassembler/AArch64/udf.txt b/llvm/test/MC/Disassembler/AArch64/udf.txt
index 445803ebe7104..e3d506d85118b 100644
--- a/llvm/test/MC/Disassembler/AArch64/udf.txt
+++ b/llvm/test/MC/Disassembler/AArch64/udf.txt
@@ -11,6 +11,6 @@
 # CHECK-NEXT: udf #513
 # CHECK-NEXT: udf #65535
 
-#OBJ:             0:	00 00 00 00 	udf	#0
-#OBJ-NEXT:        4:	01 02 00 00 	udf	#513
-#OBJ-NEXT:        8:	ff ff 00 00 	udf	#65535
+#OBJ:             0:	00000000    	udf	#0
+#OBJ-NEXT:        4:	00000201    	udf	#513
+#OBJ-NEXT:        8:	0000ffff    	udf	#65535


        
