[llvm] f04ae43 - [RISCV] Add more test cases for select with (setge X, C) condition.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 25 11:57:13 PDT 2022
Author: Craig Topper
Date: 2022-07-25T11:55:21-07:00
New Revision: f04ae43752a014fde8d6db6dc248044b0d02976a
URL: https://github.com/llvm/llvm-project/commit/f04ae43752a014fde8d6db6dc248044b0d02976a
DIFF: https://github.com/llvm/llvm-project/commit/f04ae43752a014fde8d6db6dc248044b0d02976a.diff
LOG: [RISCV] Add more test cases for select with (setge X, C) condition.
InstCombine and SelectionDAG will tend to canonicalize these conditions
to (setgt X, C-1). C-1 might be more costly to materialize than C would
have been.
Added:
Modified:
llvm/test/CodeGen/RISCV/select-cc.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll
index a1ab5f80ea72..34656428aeff 100644
--- a/llvm/test/CodeGen/RISCV/select-cc.ll
+++ b/llvm/test/CodeGen/RISCV/select-cc.ll
@@ -1,8 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
+; RUN: | FileCheck -check-prefixes=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -disable-block-placement -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32IBT %s
+; RUN: | FileCheck -check-prefixes=RV32ZBT %s
+; RUN: llc -mtriple=riscv64 -disable-block-placement -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64I %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -disable-block-placement -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefixes=RV64ZBT %s
define signext i32 @foo(i32 signext %a, i32 *%b) nounwind {
; RV32I-LABEL: foo:
@@ -81,51 +85,183 @@ define signext i32 @foo(i32 signext %a, i32 *%b) nounwind {
; RV32I-NEXT: .LBB0_28:
; RV32I-NEXT: ret
;
-; RV32IBT-LABEL: foo:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: lw a3, 0(a1)
-; RV32IBT-NEXT: xor a4, a0, a2
-; RV32IBT-NEXT: cmov a0, a4, a2, a0
-; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: xor a4, a0, a3
-; RV32IBT-NEXT: cmov a0, a4, a0, a3
-; RV32IBT-NEXT: lw a3, 0(a1)
-; RV32IBT-NEXT: sltu a4, a2, a0
-; RV32IBT-NEXT: cmov a0, a4, a0, a2
-; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: sltu a4, a0, a3
-; RV32IBT-NEXT: cmov a0, a4, a3, a0
-; RV32IBT-NEXT: lw a3, 0(a1)
-; RV32IBT-NEXT: sltu a4, a0, a2
-; RV32IBT-NEXT: cmov a0, a4, a0, a2
-; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: sltu a4, a3, a0
-; RV32IBT-NEXT: cmov a0, a4, a3, a0
-; RV32IBT-NEXT: lw a3, 0(a1)
-; RV32IBT-NEXT: slt a4, a2, a0
-; RV32IBT-NEXT: cmov a0, a4, a0, a2
-; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: slt a4, a0, a3
-; RV32IBT-NEXT: cmov a0, a4, a3, a0
-; RV32IBT-NEXT: lw a3, 0(a1)
-; RV32IBT-NEXT: slt a4, a0, a2
-; RV32IBT-NEXT: lw a5, 0(a1)
-; RV32IBT-NEXT: cmov a0, a4, a0, a2
-; RV32IBT-NEXT: slt a2, a3, a0
-; RV32IBT-NEXT: cmov a0, a2, a3, a0
-; RV32IBT-NEXT: slti a2, a5, 1
-; RV32IBT-NEXT: lw a3, 0(a1)
-; RV32IBT-NEXT: cmov a0, a2, a0, a5
-; RV32IBT-NEXT: lw a2, 0(a1)
-; RV32IBT-NEXT: slti a4, a5, 0
-; RV32IBT-NEXT: cmov a0, a4, a3, a0
-; RV32IBT-NEXT: lw a1, 0(a1)
-; RV32IBT-NEXT: slti a3, a2, 1025
-; RV32IBT-NEXT: cmov a0, a3, a2, a0
-; RV32IBT-NEXT: sltiu a2, a5, 2047
-; RV32IBT-NEXT: cmov a0, a2, a1, a0
-; RV32IBT-NEXT: ret
+; RV32ZBT-LABEL: foo:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: lw a2, 0(a1)
+; RV32ZBT-NEXT: lw a3, 0(a1)
+; RV32ZBT-NEXT: xor a4, a0, a2
+; RV32ZBT-NEXT: cmov a0, a4, a2, a0
+; RV32ZBT-NEXT: lw a2, 0(a1)
+; RV32ZBT-NEXT: xor a4, a0, a3
+; RV32ZBT-NEXT: cmov a0, a4, a0, a3
+; RV32ZBT-NEXT: lw a3, 0(a1)
+; RV32ZBT-NEXT: sltu a4, a2, a0
+; RV32ZBT-NEXT: cmov a0, a4, a0, a2
+; RV32ZBT-NEXT: lw a2, 0(a1)
+; RV32ZBT-NEXT: sltu a4, a0, a3
+; RV32ZBT-NEXT: cmov a0, a4, a3, a0
+; RV32ZBT-NEXT: lw a3, 0(a1)
+; RV32ZBT-NEXT: sltu a4, a0, a2
+; RV32ZBT-NEXT: cmov a0, a4, a0, a2
+; RV32ZBT-NEXT: lw a2, 0(a1)
+; RV32ZBT-NEXT: sltu a4, a3, a0
+; RV32ZBT-NEXT: cmov a0, a4, a3, a0
+; RV32ZBT-NEXT: lw a3, 0(a1)
+; RV32ZBT-NEXT: slt a4, a2, a0
+; RV32ZBT-NEXT: cmov a0, a4, a0, a2
+; RV32ZBT-NEXT: lw a2, 0(a1)
+; RV32ZBT-NEXT: slt a4, a0, a3
+; RV32ZBT-NEXT: cmov a0, a4, a3, a0
+; RV32ZBT-NEXT: lw a3, 0(a1)
+; RV32ZBT-NEXT: slt a4, a0, a2
+; RV32ZBT-NEXT: lw a5, 0(a1)
+; RV32ZBT-NEXT: cmov a0, a4, a0, a2
+; RV32ZBT-NEXT: slt a2, a3, a0
+; RV32ZBT-NEXT: cmov a0, a2, a3, a0
+; RV32ZBT-NEXT: slti a2, a5, 1
+; RV32ZBT-NEXT: lw a3, 0(a1)
+; RV32ZBT-NEXT: cmov a0, a2, a0, a5
+; RV32ZBT-NEXT: lw a2, 0(a1)
+; RV32ZBT-NEXT: slti a4, a5, 0
+; RV32ZBT-NEXT: cmov a0, a4, a3, a0
+; RV32ZBT-NEXT: lw a1, 0(a1)
+; RV32ZBT-NEXT: slti a3, a2, 1025
+; RV32ZBT-NEXT: cmov a0, a3, a2, a0
+; RV32ZBT-NEXT: sltiu a2, a5, 2047
+; RV32ZBT-NEXT: cmov a0, a2, a1, a0
+; RV32ZBT-NEXT: ret
+;
+; RV64I-LABEL: foo:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: beq a0, a2, .LBB0_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB0_2:
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: bne a0, a2, .LBB0_4
+; RV64I-NEXT: # %bb.3:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB0_4:
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: bltu a2, a0, .LBB0_6
+; RV64I-NEXT: # %bb.5:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB0_6:
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: bgeu a0, a2, .LBB0_8
+; RV64I-NEXT: # %bb.7:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB0_8:
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: bltu a0, a2, .LBB0_10
+; RV64I-NEXT: # %bb.9:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB0_10:
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: bgeu a2, a0, .LBB0_12
+; RV64I-NEXT: # %bb.11:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB0_12:
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: sext.w a3, a0
+; RV64I-NEXT: blt a2, a3, .LBB0_14
+; RV64I-NEXT: # %bb.13:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB0_14:
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: sext.w a3, a0
+; RV64I-NEXT: bge a3, a2, .LBB0_16
+; RV64I-NEXT: # %bb.15:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB0_16:
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: sext.w a3, a0
+; RV64I-NEXT: blt a3, a2, .LBB0_18
+; RV64I-NEXT: # %bb.17:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB0_18:
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: sext.w a3, a0
+; RV64I-NEXT: bge a2, a3, .LBB0_20
+; RV64I-NEXT: # %bb.19:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB0_20:
+; RV64I-NEXT: lw a2, 0(a1)
+; RV64I-NEXT: blez a2, .LBB0_22
+; RV64I-NEXT: # %bb.21:
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: .LBB0_22:
+; RV64I-NEXT: lw a3, 0(a1)
+; RV64I-NEXT: bgez a2, .LBB0_24
+; RV64I-NEXT: # %bb.23:
+; RV64I-NEXT: mv a0, a3
+; RV64I-NEXT: .LBB0_24:
+; RV64I-NEXT: lw a3, 0(a1)
+; RV64I-NEXT: li a4, 1024
+; RV64I-NEXT: blt a4, a3, .LBB0_26
+; RV64I-NEXT: # %bb.25:
+; RV64I-NEXT: mv a0, a3
+; RV64I-NEXT: .LBB0_26:
+; RV64I-NEXT: lw a1, 0(a1)
+; RV64I-NEXT: li a3, 2046
+; RV64I-NEXT: bltu a3, a2, .LBB0_28
+; RV64I-NEXT: # %bb.27:
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: .LBB0_28:
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: foo:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: lw a2, 0(a1)
+; RV64ZBT-NEXT: lw a3, 0(a1)
+; RV64ZBT-NEXT: xor a4, a0, a2
+; RV64ZBT-NEXT: cmov a0, a4, a2, a0
+; RV64ZBT-NEXT: lw a2, 0(a1)
+; RV64ZBT-NEXT: xor a4, a0, a3
+; RV64ZBT-NEXT: cmov a0, a4, a0, a3
+; RV64ZBT-NEXT: lw a3, 0(a1)
+; RV64ZBT-NEXT: sltu a4, a2, a0
+; RV64ZBT-NEXT: cmov a0, a4, a0, a2
+; RV64ZBT-NEXT: lw a2, 0(a1)
+; RV64ZBT-NEXT: sltu a4, a0, a3
+; RV64ZBT-NEXT: cmov a0, a4, a3, a0
+; RV64ZBT-NEXT: lw a3, 0(a1)
+; RV64ZBT-NEXT: sltu a4, a0, a2
+; RV64ZBT-NEXT: cmov a0, a4, a0, a2
+; RV64ZBT-NEXT: lw a2, 0(a1)
+; RV64ZBT-NEXT: sltu a4, a3, a0
+; RV64ZBT-NEXT: cmov a0, a4, a3, a0
+; RV64ZBT-NEXT: sext.w a3, a0
+; RV64ZBT-NEXT: slt a3, a2, a3
+; RV64ZBT-NEXT: lw a4, 0(a1)
+; RV64ZBT-NEXT: cmov a0, a3, a0, a2
+; RV64ZBT-NEXT: sext.w a2, a0
+; RV64ZBT-NEXT: lw a3, 0(a1)
+; RV64ZBT-NEXT: slt a2, a2, a4
+; RV64ZBT-NEXT: cmov a0, a2, a4, a0
+; RV64ZBT-NEXT: sext.w a2, a0
+; RV64ZBT-NEXT: slt a2, a2, a3
+; RV64ZBT-NEXT: lw a4, 0(a1)
+; RV64ZBT-NEXT: cmov a0, a2, a0, a3
+; RV64ZBT-NEXT: lw a2, 0(a1)
+; RV64ZBT-NEXT: sext.w a3, a0
+; RV64ZBT-NEXT: slt a3, a4, a3
+; RV64ZBT-NEXT: cmov a0, a3, a4, a0
+; RV64ZBT-NEXT: slti a3, a2, 1
+; RV64ZBT-NEXT: lw a4, 0(a1)
+; RV64ZBT-NEXT: cmov a0, a3, a0, a2
+; RV64ZBT-NEXT: lw a3, 0(a1)
+; RV64ZBT-NEXT: slti a5, a2, 0
+; RV64ZBT-NEXT: cmov a0, a5, a4, a0
+; RV64ZBT-NEXT: lw a1, 0(a1)
+; RV64ZBT-NEXT: slti a4, a3, 1025
+; RV64ZBT-NEXT: cmov a0, a4, a3, a0
+; RV64ZBT-NEXT: sltiu a2, a2, 2047
+; RV64ZBT-NEXT: cmov a0, a2, a1, a0
+; RV64ZBT-NEXT: sext.w a0, a0
+; RV64ZBT-NEXT: ret
%val1 = load volatile i32, i32* %b
%tst1 = icmp eq i32 %a, %val1
%val2 = select i1 %tst1, i32 %a, i32 %val1
@@ -208,22 +344,60 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IBT-LABEL: numsignbits:
-; RV32IBT: # %bb.0:
-; RV32IBT-NEXT: addi sp, sp, -16
-; RV32IBT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IBT-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IBT-NEXT: cmov s0, a0, a2, a3
-; RV32IBT-NEXT: beqz a1, .LBB1_2
-; RV32IBT-NEXT: # %bb.1:
-; RV32IBT-NEXT: mv a0, s0
-; RV32IBT-NEXT: call bar at plt
-; RV32IBT-NEXT: .LBB1_2:
-; RV32IBT-NEXT: mv a0, s0
-; RV32IBT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IBT-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IBT-NEXT: addi sp, sp, 16
-; RV32IBT-NEXT: ret
+; RV32ZBT-LABEL: numsignbits:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: addi sp, sp, -16
+; RV32ZBT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32ZBT-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32ZBT-NEXT: cmov s0, a0, a2, a3
+; RV32ZBT-NEXT: beqz a1, .LBB1_2
+; RV32ZBT-NEXT: # %bb.1:
+; RV32ZBT-NEXT: mv a0, s0
+; RV32ZBT-NEXT: call bar at plt
+; RV32ZBT-NEXT: .LBB1_2:
+; RV32ZBT-NEXT: mv a0, s0
+; RV32ZBT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32ZBT-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32ZBT-NEXT: addi sp, sp, 16
+; RV32ZBT-NEXT: ret
+;
+; RV64I-LABEL: numsignbits:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a3
+; RV64I-NEXT: beqz a0, .LBB1_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv s0, a2
+; RV64I-NEXT: .LBB1_2:
+; RV64I-NEXT: beqz a1, .LBB1_4
+; RV64I-NEXT: # %bb.3:
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call bar at plt
+; RV64I-NEXT: .LBB1_4:
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: numsignbits:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: addi sp, sp, -16
+; RV64ZBT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64ZBT-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
+; RV64ZBT-NEXT: cmov s0, a0, a2, a3
+; RV64ZBT-NEXT: beqz a1, .LBB1_2
+; RV64ZBT-NEXT: # %bb.1:
+; RV64ZBT-NEXT: mv a0, s0
+; RV64ZBT-NEXT: call bar at plt
+; RV64ZBT-NEXT: .LBB1_2:
+; RV64ZBT-NEXT: mv a0, s0
+; RV64ZBT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64ZBT-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
+; RV64ZBT-NEXT: addi sp, sp, 16
+; RV64ZBT-NEXT: ret
%5 = icmp eq i16 %0, 0
%6 = select i1 %5, i16 %3, i16 %2
%7 = icmp eq i16 %1, 0
@@ -238,3 +412,100 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
}
declare void @bar(i16 signext)
+
+define i32 @select_sge_int16min(i32 signext %x, i32 signext %y, i32 signext %z) {
+; RV32I-LABEL: select_sge_int16min:
+; RV32I: # %bb.0:
+; RV32I-NEXT: lui a3, 1048560
+; RV32I-NEXT: addi a3, a3, -1
+; RV32I-NEXT: blt a3, a0, .LBB2_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: mv a1, a2
+; RV32I-NEXT: .LBB2_2:
+; RV32I-NEXT: mv a0, a1
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: select_sge_int16min:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: lui a3, 1048560
+; RV32ZBT-NEXT: addi a3, a3, -1
+; RV32ZBT-NEXT: slt a0, a3, a0
+; RV32ZBT-NEXT: cmov a0, a0, a1, a2
+; RV32ZBT-NEXT: ret
+;
+; RV64I-LABEL: select_sge_int16min:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a3, 1048560
+; RV64I-NEXT: addiw a3, a3, -1
+; RV64I-NEXT: blt a3, a0, .LBB2_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a1, a2
+; RV64I-NEXT: .LBB2_2:
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: select_sge_int16min:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: lui a3, 1048560
+; RV64ZBT-NEXT: addiw a3, a3, -1
+; RV64ZBT-NEXT: slt a0, a3, a0
+; RV64ZBT-NEXT: cmov a0, a0, a1, a2
+; RV64ZBT-NEXT: ret
+ %a = icmp sge i32 %x, -65536
+ %b = select i1 %a, i32 %y, i32 %z
+ ret i32 %b
+}
+
+define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) {
+; RV32I-LABEL: select_sge_int32min:
+; RV32I: # %bb.0:
+; RV32I-NEXT: li a6, -1
+; RV32I-NEXT: bne a1, a6, .LBB3_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slti a0, a0, 0
+; RV32I-NEXT: j .LBB3_3
+; RV32I-NEXT: .LBB3_2:
+; RV32I-NEXT: slt a0, a6, a1
+; RV32I-NEXT: .LBB3_3:
+; RV32I-NEXT: bnez a0, .LBB3_5
+; RV32I-NEXT: # %bb.4:
+; RV32I-NEXT: mv a2, a4
+; RV32I-NEXT: mv a3, a5
+; RV32I-NEXT: .LBB3_5:
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: mv a1, a3
+; RV32I-NEXT: ret
+;
+; RV32ZBT-LABEL: select_sge_int32min:
+; RV32ZBT: # %bb.0:
+; RV32ZBT-NEXT: slti a0, a0, 0
+; RV32ZBT-NEXT: addi a6, a1, 1
+; RV32ZBT-NEXT: slti a1, a1, 0
+; RV32ZBT-NEXT: xori a1, a1, 1
+; RV32ZBT-NEXT: cmov a1, a6, a1, a0
+; RV32ZBT-NEXT: cmov a0, a1, a2, a4
+; RV32ZBT-NEXT: cmov a1, a1, a3, a5
+; RV32ZBT-NEXT: ret
+;
+; RV64I-LABEL: select_sge_int32min:
+; RV64I: # %bb.0:
+; RV64I-NEXT: lui a3, 524288
+; RV64I-NEXT: addi a3, a3, -1
+; RV64I-NEXT: blt a3, a0, .LBB3_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: mv a1, a2
+; RV64I-NEXT: .LBB3_2:
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: ret
+;
+; RV64ZBT-LABEL: select_sge_int32min:
+; RV64ZBT: # %bb.0:
+; RV64ZBT-NEXT: lui a3, 524288
+; RV64ZBT-NEXT: addi a3, a3, -1
+; RV64ZBT-NEXT: slt a0, a3, a0
+; RV64ZBT-NEXT: cmov a0, a0, a1, a2
+; RV64ZBT-NEXT: ret
+ %a = icmp sge i64 %x, -2147483648
+ %b = select i1 %a, i64 %y, i64 %z
+ ret i64 %b
+}
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