[PATCH] D130500: Change long to int64_t (which is always 64 bit or 8 bytes )

[Umesh Kalappa via Phabricator via llvm-commits]

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The changes fix the issue 
https://github.com/llvm/llvm-project/issues/55911

We can't guarantee the long always 64 bits like WINDOWS or LLP64 data model (rare  but should consider).

So use int64_t from inttypes.h and safe in this case.


Repository:
  rL LLVM

https://reviews.llvm.org/D130500

Files:
  llvm/lib/Target/PowerPC/PPCFastISel.cpp
  llvm/test/CodeGen/PowerPC/pr55911.ll


Index: llvm/test/CodeGen/PowerPC/pr55911.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/pr55911.ll
@@ -0,0 +1,39 @@
+; ModuleID = 'test.c'
+source_filename = "test.c"
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "ppc64"
+
+ at .str = private unnamed_addr constant [9 x i8] c"correct\0A\00", align 1
+ at .str.1 = private unnamed_addr constant [11 x i8] c"incorrect\0A\00", align 1
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local signext i32 @myTest() #0 {
+  %1 = alloca i64, align 8
+  %2 = alloca i64, align 8
+  store i64 4660, ptr %1, align 8
+  store i64 140737488355328, ptr %2, align 8
+  %3 = load i64, ptr %1, align 8
+  %4 = icmp ult i64 %3, 140737488355328
+  br i1 %4, label %5, label %7
+
+5:                                                ; preds = %0
+  %6 = call signext i32 (ptr, ...) @printf(ptr noundef @.str)
+  br label %9
+
+7:                                                ; preds = %0
+  %8 = call signext i32 (ptr, ...) @printf(ptr noundef @.str.1)
+  br label %9
+
+9:                                                ; preds = %7, %5
+  ret i32 0
+}
+
+declare signext i32 @printf(ptr noundef, ...) #1
+
+; CHECK-LABEL: myTest:
+; CHECK:       # %bb.0:
+; CHECK:       mflr 0
+; CHECK:       li 3, 1
+; CHECK:       sldi 3, 3, 47
+; CHECK:       ld 4, 120(1)
+; CHECK:       cmpld   4, 3
Index: llvm/lib/Target/PowerPC/PPCFastISel.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -831,7 +831,7 @@
   // FIXME: Operands are not in canonical order at -O0, so an immediate
   // operand in position 1 is a lost opportunity for now.  We are
   // similar to ARM in this regard.
-  long Imm = 0;
+  int64_t Imm = 0;
   bool UseImm = false;
   const bool HasSPE = Subtarget->hasSPE();
 
@@ -841,7 +841,7 @@
     if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
         SrcVT == MVT::i8 || SrcVT == MVT::i1) {
       const APInt &CIVal = ConstInt->getValue();
-      Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
+      Imm = (IsZExt) ? (int64_t)CIVal.getZExtValue() : (int64_t)CIVal.getSExtValue();
       if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
         UseImm = true;
     }


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