[PATCH] D130496: [RISCV] Set rematerializable = 1 on PseudoReadVLENB

[luxufan via Phabricator via llvm-commits]

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Set rematerializable = 1 on PseudoReadVLENB since VLENB is a constant
register that represents the length of a RVV vector register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130496

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -4330,7 +4330,7 @@
   def PseudoVMV8R_V : VPseudo<VMV8R_V, V_M8, (outs VRM8:$vd), (ins VRM8:$vs2)>;
 }
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1 in {
+let hasSideEffects = 0, isReMaterializable = 1, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1 in {
   def PseudoReadVLENB : Pseudo<(outs GPR:$rd), (ins),
                                [(set GPR:$rd, (riscv_read_vlenb))]>;
 }


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