[PATCH] D130412: [RISCV] Teach RISCVCodeGenPrepare to optimize (zext (abs(i32 X, i1 1))).

[Philip Reames via Phabricator via llvm-commits]

reames accepted this revision.
reames added a comment.
This revision is now accepted and ready to land.

LGTM



================
Comment at: llvm/test/CodeGen/RISCV/iabs.ll:697
 
+define i64 @zext_abs32(i32 %x) {
+; RV32I-LABEL: zext_abs32:
----------------
Please, in general, just precommit tests without separate review.  It makes it much easier to understand the code change being proposed.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130412/new/

https://reviews.llvm.org/D130412