[PATCH] D130486: [AMDGPU][MC][GFX11] Correct src0 for VOP3_DPP variants of v_cmp*class* opcodes

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

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Disable `SGPRs` for src0 of these opcodes.
See bug 56708 <https://github.com/llvm/llvm-project/issues/56708> for more information.


https://reviews.llvm.org/D130486

Files:
  llvm/lib/Target/AMDGPU/VOPCInstructions.td
  llvm/test/MC/AMDGPU/gfx11_err.s


Index: llvm/test/MC/AMDGPU/gfx11_err.s
===================================================================
--- llvm/test/MC/AMDGPU/gfx11_err.s
+++ llvm/test/MC/AMDGPU/gfx11_err.s
@@ -77,3 +77,9 @@
 
 v_dot4c_i32_i8 v0, v1, v2
 // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+v_cmp_class_f16_e64_dpp s105, s2, v2 row_ror:15
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmpx_class_f32_e64_dpp s1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
+// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
Index: llvm/lib/Target/AMDGPU/VOPCInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -718,7 +718,7 @@
   // DPP8 forbids modifiers and can inherit from VOPC_Profile
 
   let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
-  dag InsPartVOP3DPP = (ins Src0Mod:$src0_modifiers, VGPRSrc_32:$src0, VGPRSrc_32:$src1);
+  dag InsPartVOP3DPP = (ins FPVRegInputMods:$src0_modifiers, VGPRSrc_32:$src0, VGPRSrc_32:$src1);
   let InsVOP3Base = !con(InsPartVOP3DPP, !if(HasOpSel, (ins op_sel0:$op_sel),
                                                        (ins)));
   let Asm64 = "$sdst, $src0_modifiers, $src1";


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