[PATCH] D130163: [AArch64] Combine setcc (iN (bitcast (vNi1 X))) with vecreduce_or

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added a comment.
This revision is now accepted and ready to land.

One minor precommit change plus a suggested improvement which I think is best done as part of this patch but am accepting anyway in case you prefer to create a separate patch.  If you decide to add the improvement to this patch then I'll re-review.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18249
+      LHS = DAG.getNode(ISD::ZERO_EXTEND, DL, ToVT, LHS);
+      return DAG.getSetCC(DL, VT, LHS, DAG.getConstant(0, DL, ToVT),
+                          ISD::SETEQ);
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Can you use `RHS` here? It should already be the zero you need.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18250
+      return DAG.getSetCC(DL, VT, LHS, DAG.getConstant(0, DL, ToVT),
+                          ISD::SETEQ);
+    }
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By making this `Cond` and updating the entry condition, the combine should just work for the `SETNE` case as well?  If so, I think this is worth doing just in case the IR gets inverted.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130163/new/

https://reviews.llvm.org/D130163