[PATCH] D120026: [ARM] Fix ARM backend to correctly use atomic expansion routines.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

I see two possible approaches to restore the functionality you want.

One, you could add a target feature that says "I have 32-bit (or 64-bit) atomics".  That would override the normal rule for setMaxAtomicSizeInBitsSupported.  The target environment would be expected to provide whatever `__sync_*` functions are necessary.  If you don't actually use any atomic operations that require CAS, you won't see any calls, so everything works even if the functions don't actually exist.  (Or it's possible to write an operating system that implements lock-free CAS on Cortex-M0, the same way the Linux kernel implements atomics on old ARM cores.)

Two, you could relax the constraint that atomic load/store are required to be atomic with respect to cmpxchg.  We can add a value to syncscope to represent this.  This would allow mixing code that uses load-store atomics with code that requires "real" atomics.

That said, I'm not sure how you use load-store atomics in practice. I mean, I guess you can use Dekker's alogorithm, or some kinds of lock-free queues, but that seems a bit exotic.  Or do you use some sort of lock implemented by disabling interrupts?


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https://reviews.llvm.org/D120026