[llvm] 162ec61 - [X86] Autogenerate cfguard-x86-64-vectorcall.ll. NFC

[Amaury Séchet via llvm-commits]

Author: Amaury Séchet
Date: 2022-07-24T15:45:51Z
New Revision: 162ec611e92bad0053924f7032037824ad77109c

URL: https://github.com/llvm/llvm-project/commit/162ec611e92bad0053924f7032037824ad77109c
DIFF: https://github.com/llvm/llvm-project/commit/162ec611e92bad0053924f7032037824ad77109c.diff

LOG: [X86] Autogenerate cfguard-x86-64-vectorcall.ll. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/cfguard-x86-64-vectorcall.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/cfguard-x86-64-vectorcall.ll b/llvm/test/CodeGen/X86/cfguard-x86-64-vectorcall.ll
index c2af59785f85..a2a24ba01832 100644
--- a/llvm/test/CodeGen/X86/cfguard-x86-64-vectorcall.ll
+++ b/llvm/test/CodeGen/X86/cfguard-x86-64-vectorcall.ll
@@ -1,9 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc | FileCheck %s -check-prefix=X64
 ; Control Flow Guard is currently only available on Windows
 
 
 ; Test that Control Flow Guard checks are correctly added for x86_64 vector calls.
 define void @func_cf_vector_x64(ptr %0, ptr %1) #0 {
+; X64-LABEL: func_cf_vector_x64:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    subq $72, %rsp
+; X64-NEXT:    .seh_stackalloc 72
+; X64-NEXT:    .seh_endprologue
+; X64-NEXT:    movq %rcx, %rax
+; X64-NEXT:    movups (%rdx), %xmm0
+; X64-NEXT:    movups 16(%rdx), %xmm1
+; X64-NEXT:    movaps %xmm0, {{[0-9]+}}(%rsp)
+; X64-NEXT:    movaps %xmm1, {{[0-9]+}}(%rsp)
+; X64-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; X64-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
+; X64-NEXT:    movsd {{.*#+}} xmm2 = mem[0],zero
+; X64-NEXT:    movsd {{.*#+}} xmm3 = mem[0],zero
+; X64-NEXT:    callq *__guard_dispatch_icall_fptr(%rip)
+; X64-NEXT:    nop
+; X64-NEXT:    addq $72, %rsp
+; X64-NEXT:    retq
+; X64-NEXT:    .seh_endproc
 entry:
   %2 = alloca %struct.HVA, align 8
   call void @llvm.memcpy.p0.p0.i64(ptr align 8 %2, ptr align 8 %1, i64 32, i1 false)
@@ -11,18 +31,6 @@ entry:
   call x86_vectorcallcc void %0(%struct.HVA inreg %3)
   ret void
 
-  ; X64-LABEL: func_cf_vector_x64
-  ; X64:       movq	%rcx, %rax
-  ; X64:       movups (%rdx), %xmm0
-  ; X64:       movups 16(%rdx), %xmm1
-  ; X64:       movaps %xmm0, 32(%rsp)
-  ; X64:       movaps %xmm1, 48(%rsp)
-  ; X64:       movsd 32(%rsp), %xmm0         # xmm0 = mem[0],zero
-  ; X64:       movsd 40(%rsp), %xmm1         # xmm1 = mem[0],zero
-  ; X64:       movsd 48(%rsp), %xmm2         # xmm2 = mem[0],zero
-  ; X64:       movsd 56(%rsp), %xmm3         # xmm3 = mem[0],zero
-  ; X64:       callq *__guard_dispatch_icall_fptr(%rip)
-  ; X64-NOT:   callq
 }
 attributes #0 = { "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" }