[llvm] 428c0f2 - [DAG] getNode - assert that SMUL_LOHI/UMUL_LOHI nodes have the correct ops + types
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 24 07:31:16 PDT 2022
Author: Simon Pilgrim
Date: 2022-07-24T15:30:57+01:00
New Revision: 428c0f2adc522830c54742d8be0d377d8b0fa0e8
URL: https://github.com/llvm/llvm-project/commit/428c0f2adc522830c54742d8be0d377d8b0fa0e8
DIFF: https://github.com/llvm/llvm-project/commit/428c0f2adc522830c54742d8be0d377d8b0fa0e8.diff
LOG: [DAG] getNode - assert that SMUL_LOHI/UMUL_LOHI nodes have the correct ops + types
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 84e1ade1ca1a..478282ab9ee6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -9088,6 +9088,15 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
}
break;
}
+ case ISD::SMUL_LOHI:
+ case ISD::UMUL_LOHI: {
+ assert(VTList.NumVTs == 2 && Ops.size() == 2 && "Invalid mul lo/hi op!");
+ assert(VTList.VTs[0].isInteger() && VTList.VTs[0] == VTList.VTs[1] &&
+ VTList.VTs[0] == Ops[0].getValueType() &&
+ VTList.VTs[0] == Ops[1].getValueType() &&
+ "Binary operator types must match!");
+ break;
+ }
case ISD::STRICT_FP_EXTEND:
assert(VTList.NumVTs == 2 && Ops.size() == 2 &&
"Invalid STRICT_FP_EXTEND!");
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