[llvm] 0708771 - [DAG] MaskedVectorIsZero - don't bother with (-1).isSubsetOf mask check. NFC.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 24 05:12:43 PDT 2022
Author: Simon Pilgrim
Date: 2022-07-24T13:12:21+01:00
New Revision: 0708771cce056c3bf9b89793ebb5aa5305b194b5
URL: https://github.com/llvm/llvm-project/commit/0708771cce056c3bf9b89793ebb5aa5305b194b5
DIFF: https://github.com/llvm/llvm-project/commit/0708771cce056c3bf9b89793ebb5aa5305b194b5.diff
LOG: [DAG] MaskedVectorIsZero - don't bother with (-1).isSubsetOf mask check. NFC.
Just use KnownBits::isZero() to ensure all the bits are known zero.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 441437351852..84e1ade1ca1a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2529,8 +2529,7 @@ bool SelectionDAG::MaskedValueIsZero(SDValue V, const APInt &Mask,
/// DemandedElts. We use this predicate to simplify operations downstream.
bool SelectionDAG::MaskedVectorIsZero(SDValue V, const APInt &DemandedElts,
unsigned Depth /* = 0 */) const {
- APInt Mask = APInt::getAllOnes(V.getScalarValueSizeInBits());
- return Mask.isSubsetOf(computeKnownBits(V, DemandedElts, Depth).Zero);
+ return computeKnownBits(V, DemandedElts, Depth).isZero();
}
/// MaskedValueIsAllOnes - Return true if '(Op & Mask) == Mask'.
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 5a4533c4bac4..6071e3b3a639 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -37522,8 +37522,8 @@ static bool matchBinaryShuffle(MVT MaskVT, ArrayRef<int> Mask,
break;
}
if (IsBlend) {
- if (DAG.computeKnownBits(V1, DemandedZeroV1).isZero() &&
- DAG.computeKnownBits(V2, DemandedZeroV2).isZero()) {
+ if (DAG.MaskedVectorIsZero(V1, DemandedZeroV1) &&
+ DAG.MaskedVectorIsZero(V2, DemandedZeroV2)) {
Shuffle = ISD::OR;
SrcVT = DstVT = MaskVT.changeTypeToInteger();
return true;
@@ -41191,7 +41191,7 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
SDValue Src = Op.getOperand(0);
APInt DemandedUpperElts = DemandedElts;
DemandedUpperElts.clearLowBits(1);
- if (TLO.DAG.computeKnownBits(Src, DemandedUpperElts, Depth + 1).isZero())
+ if (TLO.DAG.MaskedVectorIsZero(Src, DemandedUpperElts, Depth + 1))
return TLO.CombineTo(Op, Src);
break;
}
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