[PATCH] D120026: [ARM] Fix ARM backend to correctly use atomic expansion routines.

Sat Jul 23 15:27:52 PDT 2022

nikic added inline comments.

================
Comment at: llvm/test/CodeGen/ARM/atomic-op.ll:413
+; CHECK-T1-M0: __atomic_load_4
 ; CHECK-T1-M0: dmb
+; CHECK-T1-M0: __atomic_store_4
----------------
efriedma wrote:
> nikic wrote:
> > Is the dmb still needed if we're going through `__atomic`?
> __atomic_load_4 is just supposed to be a sequentially consistent load, and a sequentially consistent load doesn't imply a full fence, even if the load is sequentially consistent.  So there isn't any obvious rule that would allow that transform.
> 
> See also https://github.com/llvm/llvm-project/issues/29472, https://github.com/llvm/llvm-project/issues/56450 .
Uh sorry, I missed that there was an explicit IR fence instruction in this test. The preceding two functions don't have an IR fence, and also no longer emit dmb, so everything is good here.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120026/new/

https://reviews.llvm.org/D120026