[PATCH] D130248: [LoongArch] Offset folding for frameindex

[Sergei Barannikov via Phabricator via llvm-commits]

barannikov88 added a comment.

In D130248#3674127 <https://reviews.llvm.org/D130248#3674127>, @MaskRay wrote:

> Do you know why csky/hexagon need `isOrEquivalentToAdd` while other targets can produce efficient code without `isOrEquivalentToAdd` ?

Other targets just do that in manually in *ISelDAGToDAG.cpp file. E.g. X86:

  case ISD::OR:
    // We want to look through a transform in InstCombine and DAGCombiner that
    // turns 'add' into 'or', so we can treat this 'or' exactly like an 'add'.
    // Example: (or (and x, 1), (shl y, 3)) --> (add (and x, 1), (shl y, 3))
    // An 'lea' can then be used to match the shift (multiply) and add:
    // and $1, %esi
    // lea (%rsi, %rdi, 8), %rax
    if (CurDAG->haveNoCommonBitsSet(N.getOperand(0), N.getOperand(1)) &&
        !matchAdd(N, AM, Depth))
      return false;
    break;

ARM:

  // Determine whether an ISD::OR's operands are suitable to turn the operation
  // into an addition, which often has more compact encodings.
  bool ARMDAGToDAGISel::SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out) {
    assert(Parent->getOpcode() == ISD::OR && "unexpected parent");
    Out = N;
    return CurDAG->haveNoCommonBitsSet(N, Parent->getOperand(1));
  }


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