[PATCH] D130424: AMDGPU: Adjust register allocation priority values down

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
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Set the priorities consistently to number of registers in the tuple -

1. Previously we started at 1, and also tried to give SGPR higher

values than VGPRs. There's no point in assigning SGPRs higher values
now that those are allocated in a separate regalloc run.

      

This avoids overflowing the 5 bits used for the class priority in the
allocation heuristic for 32 element tuples. This avoids some cases
where smaller registers unexpectedly get prioritized over larger.


https://reviews.llvm.org/D130424

Files:
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
  llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
  llvm/test/CodeGen/AMDGPU/extend-phi-subrange-not-in-parent.mir
  llvm/test/CodeGen/AMDGPU/indirect-call.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll
  llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
  llvm/test/CodeGen/AMDGPU/srem64.ll
  llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
  llvm/test/CodeGen/AMDGPU/urem64.ll

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