[PATCH] D130258: [AMDGPU] Remove IR SpeculativeExecution pass from codegen pipeline

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

In D130258#3671596 <https://reviews.llvm.org/D130258#3671596>, @nhaehnle wrote:

> The test diff looks surprisingly small. Intuitively speaking, the most interesting instructions for speculative execution are loads. You wouldn't necessarily see a change in the instruction frequency there...

Maybe I should have said up front that the SpeculativeExecution pass does not actually do any speculative execution! All it does is "hoists instructions to enable speculative execution", and most of that hoisting is undone by the code sinking pass that we run later.

If I remove CodeSinking but don't remove SpeculativeExecution then I see bad effects where we start with:

  bb:
    %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 1
    %load1 = load volatile i32, i32 addrspace(5)* %gep1, align 4

and then SpeculativeExecution hoists the gep:

    %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 1
    br i1 %cmp, label %bb, label %ret
  bb:
    %load1 = load volatile i32, i32 addrspace(5)* %gep1, align 4

and then isel can no longer match the base-plus-constant addressing mode for the load.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130258/new/

https://reviews.llvm.org/D130258