[llvm] 798fa7e - [AMDGPU] Add a test where regClassPriorityTrumpsGlobalness uses more vgprs

Jay Foad via llvm-commits llvm-commits at lists.llvm.org
Fri Jul 22 04:10:57 PDT 2022


Author: Jay Foad
Date: 2022-07-22T12:08:47+01:00
New Revision: 798fa7e9d6973c7ecb736eea41755ef86220cda1

URL: https://github.com/llvm/llvm-project/commit/798fa7e9d6973c7ecb736eea41755ef86220cda1
DIFF: https://github.com/llvm/llvm-project/commit/798fa7e9d6973c7ecb736eea41755ef86220cda1.diff

LOG: [AMDGPU] Add a test where regClassPriorityTrumpsGlobalness uses more vgprs

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir b/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
index 01cda7118716..9c2b5ac92eb8 100644
--- a/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
+++ b/llvm/test/CodeGen/AMDGPU/greedy-liverange-priority.mir
@@ -1,15 +1,15 @@
-# RUN: llc -march=amdgcn -mcpu=gfx1030 -greedy-regclass-priority-trumps-globalness=0 -start-before greedy -o - %s | FileCheck %s -check-prefix=OLD
-# RUN: llc -march=amdgcn -mcpu=gfx1030 -greedy-regclass-priority-trumps-globalness=1 -start-before greedy -o - %s | FileCheck %s -check-prefix=NEW
+# RUN: llc -march=amdgcn -mcpu=gfx1030 -greedy-regclass-priority-trumps-globalness=0 -start-before greedy -o - %s | FileCheck %s -check-prefixes=GCN,OLD
+# RUN: llc -march=amdgcn -mcpu=gfx1030 -greedy-regclass-priority-trumps-globalness=1 -start-before greedy -o - %s | FileCheck %s -check-prefixes=GCN,NEW
 
 # At the time of writing -greedy-regclass-priority-trumps-globalness makes a
 # significant improvement in the total number of vgprs needed to compile this
 # test, from 11 down to 7.
 
+# GCN-LABEL: test1:
 # OLD: NumVgprs: 11{{$}}
 # NEW: NumVgprs: 7{{$}}
-
 ---
-name: _amdgpu_cs_main
+name: test1
 tracksRegLiveness: true
 body: |
   bb.0:
@@ -46,3 +46,59 @@ body: |
   bb.2:
     S_ENDPGM 0
 ...
+
+# GCN-LABEL: test2:
+# OLD: NumVgprs: 7{{$}}
+# NEW: NumVgprs: 11{{$}}
+---
+name: test2
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr2
+
+    %8:vgpr_32 = COPY $vgpr2
+    %6:vgpr_32 = COPY $vgpr0
+
+  bb.1:
+    successors: %bb.2, %bb.3
+
+    undef %25.sub0:sgpr_256 = S_MOV_B32 0
+    %10:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %25.sub1:sgpr_256 = COPY %25.sub0
+    %25.sub2:sgpr_256 = COPY %25.sub0
+    %25.sub3:sgpr_256 = COPY %25.sub0
+    %19:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN %10, %25.sub0_sub1_sub2_sub3, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s32))
+    %36:vreg_64 = DS_READ2_B32_gfx9 %10, 0, 2, 0, implicit $exec :: (load (s32)), (load (s32))
+    %30:vgpr_32 = V_LSHLREV_B32_e32 2, %36.sub0, implicit $exec
+    %3:vgpr_32 = V_ADD_U32_e32 %30, %6, implicit $exec
+    %4:vgpr_32 = V_ADD_U32_e32 %36.sub1, %8, implicit $exec
+    %15:vgpr_32 = V_OR_B32_e32 %4, %3, implicit $exec
+    %21:sreg_32 = V_READFIRSTLANE_B32 %19, implicit $exec
+    %17:sreg_32 = V_CMP_EQ_U32_e64 0, %15, implicit $exec
+    S_CMP_LG_U32 %21, 0, implicit-def $scc
+    %31:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed $scc
+    %23:sreg_32 = S_AND_B32 %31, %17, implicit-def dead $scc
+    %5:sreg_32 = COPY $exec_lo, implicit-def $exec_lo
+    %37:sreg_32 = S_AND_B32 %5, %23, implicit-def dead $scc
+    $exec_lo = S_MOV_B32_term %37
+    S_CBRANCH_EXECZ %bb.3, implicit $exec
+    S_BRANCH %bb.2
+
+  bb.2:
+    undef %28.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
+    %25.sub1:sgpr_256 = COPY %25.sub0
+    %25.sub2:sgpr_256 = COPY %25.sub0
+    %25.sub3:sgpr_256 = COPY %25.sub0
+    %25.sub4:sgpr_256 = COPY %25.sub0
+    %28.sub1:vreg_128 = COPY %28.sub0
+    %28.sub2:vreg_128 = COPY %28.sub0
+    %28.sub3:vreg_128 = COPY %28.sub0
+    %25.sub5:sgpr_256 = COPY %25.sub0
+    %25.sub6:sgpr_256 = COPY %25.sub0
+    %25.sub7:sgpr_256 = COPY %25.sub0
+    IMAGE_STORE_V4_V3_nsa_gfx10 %28, %3, %30, %4, %25, 0, 2, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable store (s32))
+
+  bb.3:
+    S_ENDPGM 0
+...


        


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