[PATCH] D130163: [AArch64] Combine setcc (iN (bitcast (vNi1 X))) with vecreduce_or

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes marked an inline comment as done.
c-rhodes added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:18204
+                          DAG.getConstant(0, DL, OrigVT), N->getOperand(2));
+    return DAG.getNode(ISD::VECREDUCE_OR, DL, MVT::i1, SetCC);
+  }
----------------
paulwalker-arm wrote:
> The result type of `SETCC` doesn't have to be `i1` so you either need to extend the result based on `getBooleanContents()` or restrict the combine to cases where `VT==i1`. My preference is the former.
> The result type of `SETCC` doesn't have to be `i1` so you either need to extend the result based on `getBooleanContents()` or restrict the combine to cases where `VT==i1`. My preference is the former.

Updated to use `getBooleanContents`, I think this is fixed now?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130163/new/

https://reviews.llvm.org/D130163