[PATCH] D130333: [DAGCombiner] Simplify code around call to reduceLoadWidth in visitAND. NFC
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 21 23:48:08 PDT 2022
craig.topper updated this revision to Diff 446725.
craig.topper added a comment.
Remove stale comment
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D130333/new/
https://reviews.llvm.org/D130333
Files:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6363,18 +6363,9 @@
// fold (and (load x), 255) -> (zextload x, i8)
// fold (and (extload x, i16), 255) -> (zextload x, i8)
- // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
- if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD ||
- (N0.getOpcode() == ISD::ANY_EXTEND &&
- N0.getOperand(0).getOpcode() == ISD::LOAD))) {
- if (SDValue Res = reduceLoadWidth(N)) {
- LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND
- ? cast<LoadSDNode>(N0.getOperand(0)) : cast<LoadSDNode>(N0);
- AddToWorklist(N);
- DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 0), Res);
- return SDValue(N, 0);
- }
- }
+ if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD))
+ if (SDValue Res = reduceLoadWidth(N))
+ return Res;
if (LegalTypes) {
// Attempt to propagate the AND back up to the leaves which, if they're
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