[PATCH] D130100: [AArch64] Combine a load into GPR followed by a copy to FPR to a load into FPR directly through MIPeepholeOpt

[Mingming Liu via Phabricator via llvm-commits]

mingmingl updated this revision to Diff 446722.
mingmingl added a comment.

Implementation-wise, use `MachineRegisterInfo::replaceRegWith` to replace all uses of Reg; in this way, debug uses of the register will be updated as well.

Besides, add a dedicated MIR test for this optimization, so that machine instruction update (including `MachineInstr::memoperands`, etc) are visible.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130100/new/

https://reviews.llvm.org/D130100

Files:
  llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
  llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
  llvm/test/CodeGen/AArch64/arm64-vmul.ll
  llvm/test/CodeGen/AArch64/dp1.ll
  llvm/test/CodeGen/AArch64/neon-dotpattern.ll
  llvm/test/CodeGen/AArch64/neon-extadd.ll
  llvm/test/CodeGen/AArch64/peephole-ldr.mir

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