[PATCH] D129084: [AMDGPU] gfx11 Fix VOP3 dot instructions

Joe Nash via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 21 08:53:36 PDT 2022


Joe_Nash accepted this revision.
Joe_Nash added inline comments.


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Comment at: llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8.txt:5287
+# op_sel[1:0] are ignored
+# GFX11: v_dot2_bf16_bf16_e64_dpp v0, v1, v2, v3 op_sel:[0,0,1,1] dpp8:[0,1,2,3,4,4,4,4] ; encoding: [0x00,0x60,0x67,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92]
+0x00,0x78,0x67,0xd6,0xe9,0x04,0x0e,0x04,0x01,0x88,0x46,0x92
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Ok, I was confused because the AsmPrinter prints what the hardware will do with that instruction, not what the bits actually disassemble to. This matches sp3 and there are plenty of warnings how those bits are treated. I think this is good.


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