[llvm] 75950be - [AMDGPU][NFC] Validate G_MERGE_VALUES as we match zero-extended 32-bit scalars.

[Ivan Kosarev via llvm-commits]

Author: Ivan Kosarev
Date: 2022-07-21T14:49:57+01:00
New Revision: 75950be836c9ad962a8aaf51ef664127d7b144b4

URL: https://github.com/llvm/llvm-project/commit/75950be836c9ad962a8aaf51ef664127d7b144b4
DIFF: https://github.com/llvm/llvm-project/commit/75950be836c9ad962a8aaf51ef664127d7b144b4.diff

LOG: [AMDGPU][NFC] Validate G_MERGE_VALUES as we match zero-extended 32-bit scalars.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D130001

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 18fadf036faf..f2e5c2fe00e8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -3245,6 +3245,8 @@ static Register matchZeroExtendFromS32(MachineRegisterInfo &MRI, Register Reg) {
   if (Def->getOpcode() != AMDGPU::G_MERGE_VALUES)
     return Register();
 
+  assert(Def->getNumOperands() == 3 &&
+         MRI.getType(Def->getOperand(0).getReg()) == LLT::scalar(64));
   if (mi_match(Def->getOperand(2).getReg(), MRI, m_ZeroInt())) {
     return Def->getOperand(1).getReg();
   }