[PATCH] D130251: [DAGCombine] Mask don't have to be (EltSize - 1) exactly when combining rotation

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead marked an inline comment as done.
pcwang-thead added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7316
   if (IsRotate && Neg.getOpcode() == ISD::AND && isPowerOf2_64(EltSize)) {
     if (ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(1))) {
       KnownBits Known = DAG.computeKnownBits(Neg.getOperand(0));
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RKSimon wrote:
> It might be worthwhile to replace the ISD::AND case with SimplifyMultipleUseDemandedBits:
> ```
> if (IsRotate && isPowerOf2_64(EltSize)) {
>   unsigned Bits = Log2_64(EltSize);
>   APInt DemandedBits = APInt::getLowBitsSet(EltSize, Bits);
>   if (SDValue Inner = SimplifyMultipleUseDemandedBits(Neg, DemandedBits, DAG)) {
>     Neg = Inner;
>     MaskLoBits = Bits;
>   }
> }
> ```
Thanks! I think it makes sense!


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D130251/new/

https://reviews.llvm.org/D130251