[PATCH] D130251: [DAGCombine] Mask don't have to be (EltSize - 1) exactly when combining rotation

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7316
   if (IsRotate && Neg.getOpcode() == ISD::AND && isPowerOf2_64(EltSize)) {
     if (ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(1))) {
       KnownBits Known = DAG.computeKnownBits(Neg.getOperand(0));
----------------
It might be worthwhile to replace the ISD::AND case with SimplifyMultipleUseDemandedBits:
```
if (IsRotate && isPowerOf2_64(EltSize)) {
  unsigned Bits = Log2_64(EltSize);
  APInt DemandedBits = APInt::getLowBitsSet(EltSize, Bits);
  if (SDValue Inner = SimplifyMultipleUseDemandedBits(Neg, DemandedBits, DAG)) {
    Neg = Inner;
    MaskLoBits = Bits;
  }
}
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130251/new/

https://reviews.llvm.org/D130251