[PATCH] D130246: [AArch64] Use neon instructions for i64/i128 ISD::PARITY calculation

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
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As noticed on D129765 <https://reviews.llvm.org/D129765> and reported on Issue #56531 - aarch64 targets can use the neon ctpop + padd instructions to speed up scalar ctpop instructions, but we fail to doe this for parity calculations.

I'm not sure where the cutoff should be, but i64 (+ i128 special case) shows a definite reduction in instruction count. i32 is about the same (not sure if scalar <-> neon transfers are particularly costly?), and sub-i32 promotion looks to be a definite regression compared to parity expansion optimized for those widths.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130246

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/parity.ll

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