[PATCH] D130222: [RISCV] Add scheduling class for vector pseudo segment instructions.

[Monk Chiang via Phabricator via llvm-commits]

monkchiang created this revision.
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Add scheduling resource for vector segment load/store instructions in D128886 <https://reviews.llvm.org/D128886>.
I miss to add scheduling resource for pseudo segment instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130222

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

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