[PATCH] D130206: CodeGen: use address form for DW_AT_high_pc on RISCV

[Saleem Abdulrasool via Phabricator via llvm-commits]

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This adjusts the DWARF emission on RISCV to use the address form for the
`DW_AT_high_pc` entry in `.debug_info`.  When fission is enabled, this
will be emitted into the `.debug_info.dwo` section which may not contain
relocations.  However, we leave the relocation to the linker to resolve
even without relaxation enabled, which prevents the use of fission on
this target.  Change the emitted form to the address form under all
versions of DWARF if the target is RISCV to accommodate the expectations
for DWARF.

Fixes: #56642


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D130206

Files:
  llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
  llvm/test/CodeGen/RISCV/fixups-diff.ll
  llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll


Index: llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
===================================================================
--- llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
+++ llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll
@@ -6,8 +6,7 @@

 ; Check that we actually have relocations, otherwise this is kind of pointless.
 ; READOBJ-RELOCS:  Section ({{.*}}) .rela.debug_info {
-; READOBJ-RELOCS:    0x1B R_RISCV_ADD32 - 0x0
-; READOBJ-RELOCS-NEXT:    0x1B R_RISCV_SUB32 - 0x0
+; READOBJ-RELOCS:    0x11 R_RISCV_32 - 0x0
 ; READOBJ-RELOCS:  Section ({{.*}}) .rela.debug_frame {
 ; READOBJ-RELOCS:    0x20 R_RISCV_ADD32 - 0x0
 ; READOBJ-RELOCS-NEXT:    0x20 R_RISCV_SUB32 - 0x0
@@ -28,7 +27,7 @@
 ; DWARF-DUMP: DW_AT_name      ("main")
 ; DWARF-DUMP: DW_AT_decl_file ("{{.*}}dwarf-riscv-relocs.c")
 ; DWARF-DUMP: DW_AT_decl_line (1)
-; DWARF-DUMP: DW_AT_type      (0x00000032 "int")
+; DWARF-DUMP: DW_AT_type      (0x0000002c "int")
 ; DWARF-DUMP: DW_AT_name      ("int")
 ; DWARF-DUMP: DW_AT_encoding  (DW_ATE_signed)
 ; DWARF-DUMP: DW_AT_byte_size (0x04)
Index: llvm/test/CodeGen/RISCV/fixups-diff.ll
===================================================================
--- llvm/test/CodeGen/RISCV/fixups-diff.ll
+++ llvm/test/CodeGen/RISCV/fixups-diff.ll
@@ -23,10 +23,8 @@
 }

 ; CHECK:      Section {{.*}} .rela.debug_info {
-; CHECK:        0x22 R_RISCV_ADD32 - 0x0
-; CHECK-NEXT:   0x22 R_RISCV_SUB32 - 0x0
-; CHECK:        0x2B R_RISCV_ADD32 - 0x0
-; CHECK-NEXT:   0x2B R_RISCV_SUB32 - 0x0
+; CHECK:        0x22 R_RISCV_32 - 0x0
+; CHECK:        0x2B R_RISCV_32 - 0x0
 ; CHECK:      }

 ; CHECK:      Section {{.*}} .rela.eh_frame {
Index: llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
===================================================================
--- llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
+++ llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
@@ -434,7 +434,7 @@
   assert(End->isDefined() && "Invalid end label");

   addLabelAddress(D, dwarf::DW_AT_low_pc, Begin);
-  if (DD->getDwarfVersion() < 4)
+  if (DD->getDwarfVersion() < 4 || Asm->TM.getTargetTriple().isRISCV())
     addLabelAddress(D, dwarf::DW_AT_high_pc, End);
   else
     addLabelDelta(D, dwarf::DW_AT_high_pc, End, Begin);


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