[PATCH] D130170: [AMDGPU] Stop running IR code sinking pass

Wed Jul 20 07:05:04 PDT 2022

foad added a comment.

Frontends might need to start running CodeSinking as part of their optimization pass pipelines to avoid code quality regressions. For LLPC this is being done here: https://github.com/GPUOpen-Drivers/llpc/pull/1902
@mareko does Mesa need something similar?

Most of the codegen diffs come from the fact that CodeSinking modified IR that was generated by CodeGenPrepare.

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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll:34
+; GCN-NEXT:    v_mbcnt_hi_u32_b32_e32 v0, exec_hi, v0
+; GCN-NEXT:    s_bcnt1_i32_b64 s4, exec
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
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This is an improvement - //not// sinking the popcnt that uses the result of a ballot means that this instruction can read from exec directly, instead of having to copy it to another sgpr.

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Comment at: llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll:97
 bb.1:
   ; Use the alloca outside of the defining block.
   store i32 0, i32 addrspace(5)* %gep0
----------------
I don't think this test was testing the right thing. CodeSinking moved the alloca into bb.1 so the use was no longer "outside of the defining block".

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130170/new/

https://reviews.llvm.org/D130170