[PATCH] D130075: [InstCombine] Try not to demand low order bits for Add

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


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Comment at: llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll:302
+; AUTO_VEC-NEXT:    [[TMP1:%.*]] = add nsw i64 [[SMAX]], -16
+; AUTO_VEC-NEXT:    [[TMP2:%.*]] = lshr i64 [[TMP1]], 4
 ; AUTO_VEC-NEXT:    [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
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Is dropping `exact` here intentional? 

It looks like we are missing a dedicated instcombine test for this scenario?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130075/new/

https://reviews.llvm.org/D130075