[PATCH] D123265: [RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I think calling setOffset on the pcrel_lo offset is incorrect. That always points to the auipc it shouldn't have an offset.



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Comment at: llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll:365
+; RV32I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(ga+4)
+; RV32I-MEDIUM-NEXT:    lw a0, %pcrel_lo(.Lpcrel_hi9+4)(a0)
 ; RV32I-MEDIUM-NEXT:    ret
----------------
This is incorrect. There shouldn't be a +4 on the pcrel_lo relocation.


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Comment at: llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll:378
+; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(ga+4)
+; RV64I-MEDIUM-NEXT:    lw a0, %pcrel_lo(.Lpcrel_hi9+4)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
----------------
Here too


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Comment at: llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll:417
+; RV64I-MEDIUM-NEXT:    auipc a0, %pcrel_hi(ga_8+8)
+; RV64I-MEDIUM-NEXT:    ld a0, %pcrel_lo(.Lpcrel_hi10+8)(a0)
 ; RV64I-MEDIUM-NEXT:    ret
----------------
And here


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123265/new/

https://reviews.llvm.org/D123265