[PATCH] D123366: [PowerPC] map hardware loop intrinsics to PowerPC pseudo instructions.

Tue Jul 19 01:45:24 PDT 2022

shchenz added a comment.

> Some llc LLVM IR tests are expected to be added and better run with -stop-after=finalize-isel so that we can observe how PPCCTR pseudos are generated.

Thanks for review.

I added some cases to show the change after ISEL with/without this patch. However I think for this patch, the best way to verify the functionality is that there is no ctr loop regression after this patch. Before the change, if we generate `MTCTRloop`, we know that it must be a CTR loop. But after the patch, it is not the case, we may revert the CTR loop pseudos to normal cmp+branch loop.

In the coming change related to Hardware Loop pass(in PPCTargetTransformInfo.cpp), I assume we should be able to generate more CTR loops as now we have more accurate info about CTR clobbers after ISEL.

================
Comment at: llvm/lib/Target/PowerPC/PPCCTRLoops.cpp:10
 // This pass generates machine instructions for the CTR loops related pseudos:
-// 1: MTCTRPseudo/DecreaseCTRPseudo
-// 2: MTCTR8Pseudo/DecreaseCTR8Pseudo
----------------
lkail wrote:
> Can we make it in another NFC patch?
Hmm, for this case, we can not rename the pseudo instruction in another NFC patch. `MTCTRloop` can be selected in ISEL and if we recognize `MTCTRloop` instead of `MTCTRPseudo` here, we have to also make ISEL generate `DecreaseCTRPseudo` too. Otherwise this is not a valid CTR loop.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D123366/new/

https://reviews.llvm.org/D123366