[PATCH] D130059: [X86] Promote v32f16's fadd into v32f32's fadd when it is avx512 without avx512fp16
Bing Yu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 18 22:37:22 PDT 2022
yubing created this revision.
Herald added subscribers: jsji, pengfei, hiraditya.
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yubing requested review of this revision.
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Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D130059
Files:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/avx512-skx-v32f16-fadd.ll
Index: llvm/test/CodeGen/X86/avx512-skx-v32f16-fadd.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/avx512-skx-v32f16-fadd.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512f| FileCheck %s --check-prefixes=CHECK
+
+define <32 x half> @foo(<32 x half> %a, <32 x half> %b) {
+; CHECK-LABEL: foo:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset %rbp, -16
+; CHECK-NEXT: movq %rsp, %rbp
+; CHECK-NEXT: .cfi_def_cfa_register %rbp
+; CHECK-NEXT: andq $-64, %rsp
+; CHECK-NEXT: subq $192, %rsp
+; CHECK-NEXT: vmovaps %zmm1, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: vmovaps %zmm0, (%rsp)
+; CHECK-NEXT: vcvtph2ps {{[0-9]+}}(%rsp), %zmm0
+; CHECK-NEXT: vcvtph2ps (%rsp), %zmm1
+; CHECK-NEXT: vaddps %zmm0, %zmm1, %zmm0
+; CHECK-NEXT: vcvtps2ph $4, %zmm0, %ymm0
+; CHECK-NEXT: vcvtph2ps {{[0-9]+}}(%rsp), %zmm1
+; CHECK-NEXT: vcvtph2ps {{[0-9]+}}(%rsp), %zmm2
+; CHECK-NEXT: vaddps %zmm1, %zmm2, %zmm1
+; CHECK-NEXT: vcvtps2ph $4, %zmm1, %ymm1
+; CHECK-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; CHECK-NEXT: movq %rbp, %rsp
+; CHECK-NEXT: popq %rbp
+; CHECK-NEXT: .cfi_def_cfa %rsp, 8
+; CHECK-NEXT: retq
+ %1 = fadd <32 x half> %a, %b
+ ret <32 x half> %1
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1875,8 +1875,10 @@
setOperationAction(ISD::STRICT_FP_ROUND, MVT::v16f16, Custom);
setOperationAction(ISD::FP_EXTEND, MVT::v16f32, Legal);
setOperationAction(ISD::STRICT_FP_EXTEND, MVT::v16f32, Legal);
- for (unsigned Opc : { ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FDIV })
+ for (unsigned Opc : {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FDIV}) {
setOperationPromotedToType(Opc, MVT::v16f16, MVT::v16f32);
+ setOperationPromotedToType(Opc, MVT::v32f16, MVT::v32f32);
+ }
for (auto VT : { MVT::v16i32, MVT::v8i64, MVT::v16f32, MVT::v8f64 }) {
setOperationAction(ISD::MLOAD, VT, Legal);
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