[PATCH] D130056: [RISCV] Optimize (SRLI (SLLI GPR:$rs1, 32), 32)
Shao-Ce SUN via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 18 19:26:52 PDT 2022
sunshaoce created this revision.
sunshaoce added reviewers: craig.topper, jrtc27, frasercrmck, luismarques, reames.
Herald added subscribers: VincentWu, luke957, StephenFan, vkmr, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
Herald added a project: All.
sunshaoce requested review of this revision.
Herald added subscribers: llvm-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D130056
Files:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/aext-to-sext.ll
llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
llvm/test/CodeGen/RISCV/div.ll
llvm/test/CodeGen/RISCV/frame-info.ll
llvm/test/CodeGen/RISCV/half-convert.ll
llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
llvm/test/CodeGen/RISCV/mul.ll
llvm/test/CodeGen/RISCV/rem.ll
llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
llvm/test/CodeGen/RISCV/rv64i-tricky-shifts.ll
llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
llvm/test/CodeGen/RISCV/rv64zba.ll
llvm/test/CodeGen/RISCV/rv64zbp-zbkb.ll
llvm/test/CodeGen/RISCV/rv64zbt.ll
llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll
llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
llvm/test/CodeGen/RISCV/shrinkwrap.ll
llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
llvm/test/CodeGen/RISCV/urem-lkk.ll
llvm/test/CodeGen/RISCV/vararg.ll
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