[PATCH] D129161: [MachinePipeliner] Consider only direct path successors when calculating circuit latency

[James Nagurne via Phabricator via llvm-commits]

JamesNagurne added a comment.

In D129161#3660660 <https://reviews.llvm.org/D129161#3660660>, @hgreving wrote:

>> 1 -> 2, 1 -> 3, 2 -> 3, and 3 -> 1
>> Assume edges are all weighted 1.
>> Circuit 1 -> 3 correctly calculated as Latency = 1
>
> 1 -> 3 -> 1 should be recurrence length 2, or is the backedge latency 0?

My understanding was that the upstream doesn't properly figure out latencies of backedges in some cases. It'll return getInstrLatency, which is wrong in our downstream implementation.
If it does skip the PHI and instead calculate the latency along the true back edge, then my mistake. I thought that was something I had to implement downstream as part of a DAG mutation.

Regardless, the RecMII error still applies. The compiler will calculate 1 -> 3 -> 1 as 2, and 1 -> 2 -> 3 -> 1 as 4


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