[llvm] 464b3a9 - [RISCV] Pre-commit tests for D129980. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-07-18T10:54:45-07:00
New Revision: 464b3a9d8a1a86b53278c2ecc59db78dcaf0593f

URL: https://github.com/llvm/llvm-project/commit/464b3a9d8a1a86b53278c2ecc59db78dcaf0593f
DIFF: https://github.com/llvm/llvm-project/commit/464b3a9d8a1a86b53278c2ecc59db78dcaf0593f.diff

LOG: [RISCV] Pre-commit tests for D129980. NFC

Differential Revision: https://reviews.llvm.org/D129981

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/i64-icmp.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/i64-icmp.ll b/llvm/test/CodeGen/RISCV/i64-icmp.ll
index db8404b03d2a..2e5b44e8ec94 100644
--- a/llvm/test/CodeGen/RISCV/i64-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/i64-icmp.ll
@@ -685,3 +685,65 @@ define i64 @icmp_sle_constant_neg_2050(i64 %a) nounwind {
   %2 = zext i1 %1 to i64
   ret i64 %2
 }
+
+define i64 @icmp_eq_zext_inreg_small_constant(i64 %a) nounwind {
+; RV64I-LABEL: icmp_eq_zext_inreg_small_constant:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    addi a0, a0, -123
+; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    ret
+  %1 = and i64 %a, 4294967295
+  %2 = icmp eq i64 %1, 123
+  %3 = zext i1 %2 to i64
+  ret i64 %3
+}
+
+define i64 @icmp_eq_zext_inreg_large_constant(i64 %a) nounwind {
+; RV64I-LABEL: icmp_eq_zext_inreg_large_constant:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    lui a1, 138
+; RV64I-NEXT:    addiw a1, a1, -1347
+; RV64I-NEXT:    slli a1, a1, 12
+; RV64I-NEXT:    addi a1, a1, -529
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    seqz a0, a0
+; RV64I-NEXT:    ret
+  %1 = and i64 %a, 4294967295
+  %2 = icmp eq i64 %1, 2309737967
+  %3 = zext i1 %2 to i64
+  ret i64 %3
+}
+
+define i64 @icmp_ne_zext_inreg_small_constant(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ne_zext_inreg_small_constant:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    snez a0, a0
+; RV64I-NEXT:    ret
+  %1 = and i64 %a, 4294967295
+  %2 = icmp ne i64 %1, 0
+  %3 = zext i1 %2 to i64
+  ret i64 %3
+}
+
+define i64 @icmp_ne_zext_inreg_large_constant(i64 %a) nounwind {
+; RV64I-LABEL: icmp_ne_zext_inreg_large_constant:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    li a1, 1
+; RV64I-NEXT:    slli a1, a1, 32
+; RV64I-NEXT:    addi a1, a1, -2
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    snez a0, a0
+; RV64I-NEXT:    ret
+  %1 = and i64 %a, 4294967295
+  %2 = icmp ne i64 %1, 4294967294
+  %3 = zext i1 %2 to i64
+  ret i64 %3
+}