[PATCH] D127392: [AggressiveInstCombine] Combine consecutive loads which are being merged to form a wider load.

Biplob Mishra via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 18 09:08:44 PDT 2022


bipmis added a comment.

In D127392#3654734 <https://reviews.llvm.org/D127392#3654734>, @spatel wrote:

> In D127392#3654507 <https://reviews.llvm.org/D127392#3654507>, @bipmis wrote:
>
>> I should have mentioned. This being the base version have not enabled the same. Just targeting simple load scenarios in this patch. This was enabled in the the InstCombine patch.  The same will be enabled in the subsequent patches to handle memory access b/w loads.
>
> I don't understand the comment. Does the posted patch miscompile the example with a store? If so, then the patch can't be committed in this form. 
> If there are planned changes to the posted patch before it is ready for review, please note that in the patch status (or add "WIP" to the title).

Yes it should have been enabled to handle the store scenarios. I have updates the tests and added few more tests. Can add more as needed.
Also to keep it simple have handled forward load sequences.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127392/new/

https://reviews.llvm.org/D127392



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