[llvm] 9234a7c - [X86][FP16] Don't crash when lowering SELECT on fp16 vectors

[Benjamin Kramer via llvm-commits]

Author: Benjamin Kramer
Date: 2022-07-18T13:41:00+02:00
New Revision: 9234a7c0dfa38bd3855a11a57a9a645fcef7ef79

URL: https://github.com/llvm/llvm-project/commit/9234a7c0dfa38bd3855a11a57a9a645fcef7ef79
DIFF: https://github.com/llvm/llvm-project/commit/9234a7c0dfa38bd3855a11a57a9a645fcef7ef79.diff

LOG: [X86][FP16] Don't crash when lowering SELECT on fp16 vectors

This is a regression from f18794816270244f9942e9217b96e23a94a7f32c

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/half.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 901289b0f6dba..205d35cd499c5 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -24994,10 +24994,12 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
   MVT VT = Op1.getSimpleValueType();
   SDValue CC;
 
-  if (isSoftFP16(VT))
-    return DAG.getBitcast(MVT::f16, DAG.getNode(ISD::SELECT, DL, MVT::i16, Cond,
-                                                DAG.getBitcast(MVT::i16, Op1),
-                                                DAG.getBitcast(MVT::i16, Op2)));
+  if (isSoftFP16(VT)) {
+    MVT NVT = VT.changeTypeToInteger();
+    return DAG.getBitcast(VT, DAG.getNode(ISD::SELECT, DL, NVT, Cond,
+                                          DAG.getBitcast(NVT, Op1),
+                                          DAG.getBitcast(NVT, Op2)));
+  }
 
   // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
   // are available or VBLENDV if AVX is available.

diff  --git a/llvm/test/CodeGen/X86/half.ll b/llvm/test/CodeGen/X86/half.ll
index 895359a06bbd4..d2b9e51bba09b 100644
--- a/llvm/test/CodeGen/X86/half.ll
+++ b/llvm/test/CodeGen/X86/half.ll
@@ -1238,4 +1238,35 @@ define half @fcopysign(half %x, half %y) {
 declare half @llvm.fabs.f16(half)
 declare half @llvm.copysign.f16(half, half)
 
+define <8 x half> @select(i1 %c, <8 x half> %x, <8 x half> %y) {
+; CHECK-LIBCALL-LABEL: select:
+; CHECK-LIBCALL:       # %bb.0:
+; CHECK-LIBCALL-NEXT:    testb $1, %dil
+; CHECK-LIBCALL-NEXT:    jne .LBB23_2
+; CHECK-LIBCALL-NEXT:  # %bb.1:
+; CHECK-LIBCALL-NEXT:    movaps %xmm1, %xmm0
+; CHECK-LIBCALL-NEXT:  .LBB23_2:
+; CHECK-LIBCALL-NEXT:    retq
+;
+; BWON-F16C-LABEL: select:
+; BWON-F16C:       # %bb.0:
+; BWON-F16C-NEXT:    testb $1, %dil
+; BWON-F16C-NEXT:    jne .LBB23_2
+; BWON-F16C-NEXT:  # %bb.1:
+; BWON-F16C-NEXT:    vmovaps %xmm1, %xmm0
+; BWON-F16C-NEXT:  .LBB23_2:
+; BWON-F16C-NEXT:    retq
+;
+; CHECK-I686-LABEL: select:
+; CHECK-I686:       # %bb.0:
+; CHECK-I686-NEXT:    testb $1, {{[0-9]+}}(%esp)
+; CHECK-I686-NEXT:    jne .LBB23_2
+; CHECK-I686-NEXT:  # %bb.1:
+; CHECK-I686-NEXT:    movaps %xmm1, %xmm0
+; CHECK-I686-NEXT:  .LBB23_2:
+; CHECK-I686-NEXT:    retl
+  %s = select i1 %c, <8 x half> %x, <8 x half> %y
+  ret <8 x half> %s
+}
+
 attributes #0 = { nounwind }