[PATCH] D129999: [TableGen] Mark incomplete MachineInstr as not compressible

[Piggy via Phabricator via llvm-commits]

piggynl created this revision.
piggynl added reviewers: sabuasal, zixuan-wu, luismarques, jrtc27.
Herald added a project: All.
piggynl requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

If a MachineInstr is incomplete (e.g. an operand should be Reg but is currently FrameIndex), isCompressibleInst() will terminate at MachineOperandType::getReg().

With this patch, isCompressibleInst() will now return false if an operand's type doesn't match, allowing TargetInstrInfo::getInstSizeInBytes() to return a value and EstimateFunctionSizeInBytes() to work correctly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129999

Files:
  llvm/utils/TableGen/CompressInstEmitter.cpp


Index: llvm/utils/TableGen/CompressInstEmitter.cpp
===================================================================
--- llvm/utils/TableGen/CompressInstEmitter.cpp
+++ llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -716,7 +716,10 @@
       if (SourceOperandMap[OpNo].TiedOpIdx != -1) {
         if (Source.Operands[OpNo].Rec->isSubClassOf("RegisterClass"))
           CondStream.indent(6)
-              << "(MI.getOperand(" << OpNo << ").getReg() ==  MI.getOperand("
+              << "(MI.getOperand(" << OpNo << ").isReg()) && (MI.getOperand("
+              << SourceOperandMap[OpNo].TiedOpIdx << ").isReg()) &&\n"
+              << "      (MI.getOperand(" << OpNo
+              << ").getReg() ==  MI.getOperand("
               << SourceOperandMap[OpNo].TiedOpIdx << ").getReg()) &&\n";
         else
           PrintFatalError("Unexpected tied operand types!\n");
@@ -735,7 +738,8 @@
       case OpData::Reg: {
         Record *Reg = SourceOperandMap[OpNo].Data.Reg;
         CondStream.indent(6)
-            << "(MI.getOperand(" << OpNo << ").getReg() == " << TargetName
+            << "(MI.getOperand(" << OpNo << ").isReg()) &&\n"
+            << "      (MI.getOperand(" << OpNo << ").getReg() == " << TargetName
             << "::" << Reg->getName() << ") &&\n";
         break;
       }
@@ -759,10 +763,12 @@
           // Don't check register class if this is a tied operand, it was done
           // for the operand its tied to.
           if (DestOperand.getTiedRegister() == -1)
-            CondStream.indent(6) << "(MRI.getRegClass(" << TargetName
-                                 << "::" << DestOperand.Rec->getName()
-                                 << "RegClassID).contains(MI.getOperand("
-                                 << OpIdx << ").getReg())) &&\n";
+            CondStream.indent(6)
+                << "(MI.getOperand(" << OpIdx << ").isReg()) &&\n"
+                << "      (MRI.getRegClass(" << TargetName
+                << "::" << DestOperand.Rec->getName()
+                << "RegClassID).contains(MI.getOperand(" << OpIdx
+                << ").getReg())) &&\n";
 
           if (CompressOrUncompress)
             CodeStream.indent(6)


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D129999.445444.patch
Type: text/x-patch
Size: 2185 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220718/be89ae72/attachment.bin>