[PATCH] D129957: [RISCV] Add isel patterns for ineg+setge/le/uge/ule.

Alex Bradbury via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Jul 17 08:04:00 PDT 2022


asb added a comment.

This LGTM if an explanatory comment is added.



================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1280
           (XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>;
 
+def : Pat<(ineg (setuge GPR:$rs1, GPR:$rs2)), (ADDI (SLTU GPR:$rs1, GPR:$rs2), -1)>;
----------------
It would be good to add a comment here that expresses some of the same information used in the patch description, explaining why this pattern is valid.


================
Comment at: llvm/test/CodeGen/RISCV/select-const.ll:870
+}
+
----------------
Nit: Unwanted additional blank line


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129957/new/

https://reviews.llvm.org/D129957



More information about the llvm-commits mailing list