[llvm] 5ec47c6 - [DAG] Add MERGE_VALUE computeKnownBits/ComputeNumSignBits handling.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 17 04:03:32 PDT 2022
Author: Simon Pilgrim
Date: 2022-07-17T11:58:08+01:00
New Revision: 5ec47c6dc5e2954c02319e7609c17acd39684ad0
URL: https://github.com/llvm/llvm-project/commit/5ec47c6dc5e2954c02319e7609c17acd39684ad0
DIFF: https://github.com/llvm/llvm-project/commit/5ec47c6dc5e2954c02319e7609c17acd39684ad0.diff
LOG: [DAG] Add MERGE_VALUE computeKnownBits/ComputeNumSignBits handling.
Just forward the value tracking to the operand specified by the ResNo
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/AMDGPU/sdiv.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index bfaaba054319..be56cc5cbe03 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2947,6 +2947,9 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
unsigned Opcode = Op.getOpcode();
switch (Opcode) {
+ case ISD::MERGE_VALUES:
+ return computeKnownBits(Op.getOperand(Op.getResNo()), DemandedElts,
+ Depth + 1);
case ISD::BUILD_VECTOR:
// Collect the known bits that are shared by every demanded vector element.
Known.Zero.setAllBits(); Known.One.setAllBits();
@@ -3925,7 +3928,9 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
case ISD::AssertZext:
Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
return VTBits-Tmp;
-
+ case ISD::MERGE_VALUES:
+ return ComputeNumSignBits(Op.getOperand(Op.getResNo()), DemandedElts,
+ Depth + 1);
case ISD::BUILD_VECTOR:
Tmp = VTBits;
for (unsigned i = 0, e = Op.getNumOperands(); (i < e) && (Tmp > 1); ++i) {
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv.ll b/llvm/test/CodeGen/AMDGPU/sdiv.ll
index 5c83eeaadd0a..5df7470f65f2 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv.ll
@@ -1915,53 +1915,43 @@ define amdgpu_kernel void @v_sdiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)*
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 3 @6
-; EG-NEXT: ALU 39, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 29, @15, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 6:
; EG-NEXT: VTX_READ_8 T1.X, T0.X, 6, #1
; EG-NEXT: VTX_READ_16 T2.X, T0.X, 0, #1
-; EG-NEXT: VTX_READ_8 T3.X, T0.X, 2, #1
-; EG-NEXT: VTX_READ_16 T0.X, T0.X, 4, #1
+; EG-NEXT: VTX_READ_16 T3.X, T0.X, 4, #1
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 2, #1
; EG-NEXT: ALU clause starting at 14:
; EG-NEXT: MOV * T0.X, KC0[2].Z,
; EG-NEXT: ALU clause starting at 15:
; EG-NEXT: BFE_INT * T0.W, T1.X, 0.0, literal.x,
; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
-; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: LSHL * T1.W, PV.W, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
-; EG-NEXT: OR_INT * T0.W, T0.X, PV.W,
-; EG-NEXT: SETGT_INT * T1.W, 0.0, PV.W,
-; EG-NEXT: BFE_INT T2.W, T3.X, 0.0, literal.x,
-; EG-NEXT: ADD_INT * T0.W, T0.W, PV.W,
+; EG-NEXT: BFE_INT T2.W, T0.X, 0.0, literal.x,
+; EG-NEXT: OR_INT * T1.W, T3.X, PV.W,
; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
-; EG-NEXT: LSHL T2.W, PV.W, literal.x,
-; EG-NEXT: XOR_INT * T0.W, PS, T1.W,
+; EG-NEXT: LSHL T3.W, PV.W, literal.x,
+; EG-NEXT: INT_TO_FLT * T0.X, PS,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
-; EG-NEXT: SUB_INT T0.Z, 0.0, PS,
-; EG-NEXT: OR_INT T2.W, T2.X, PV.W,
-; EG-NEXT: RECIP_UINT * T0.X, PS,
-; EG-NEXT: SETGT_INT T3.W, 0.0, PV.W,
-; EG-NEXT: MULLO_INT * T0.Y, PV.Z, PS,
-; EG-NEXT: ADD_INT T2.W, T2.W, PV.W,
-; EG-NEXT: MULHI * T0.Y, T0.X, PS,
-; EG-NEXT: ADD_INT T4.W, T0.X, PS,
-; EG-NEXT: XOR_INT * T2.W, PV.W, T3.W,
-; EG-NEXT: MULHI * T0.X, PS, PV.W,
-; EG-NEXT: MULLO_INT * T0.Y, PS, T0.W,
-; EG-NEXT: SUB_INT * T2.W, T2.W, PS,
-; EG-NEXT: ADD_INT T0.Z, T0.X, 1,
-; EG-NEXT: SETGE_UINT T4.W, PV.W, T0.W,
-; EG-NEXT: SUB_INT * T5.W, PV.W, T0.W,
-; EG-NEXT: CNDE_INT T2.W, PV.W, T2.W, PS,
-; EG-NEXT: CNDE_INT * T4.W, PV.W, T0.X, PV.Z,
-; EG-NEXT: ADD_INT T5.W, PS, 1,
-; EG-NEXT: SETGE_UINT * T0.W, PV.W, T0.W,
-; EG-NEXT: CNDE_INT T0.W, PS, T4.W, PV.W, BS:VEC_102/SCL_221
-; EG-NEXT: XOR_INT * T1.W, T3.W, T1.W,
-; EG-NEXT: XOR_INT * T0.W, PV.W, PS,
-; EG-NEXT: SUB_INT * T0.W, PV.W, T1.W,
+; EG-NEXT: OR_INT T1.W, T2.X, PV.W,
+; EG-NEXT: RECIP_IEEE * T0.Y, PS,
+; EG-NEXT: INT_TO_FLT * T0.Z, PV.W,
+; EG-NEXT: MUL_IEEE * T1.W, PS, T0.Y,
+; EG-NEXT: TRUNC T1.W, PV.W,
+; EG-NEXT: XOR_INT * T0.W, T2.W, T0.W,
+; EG-NEXT: ASHR T0.W, PS, literal.x,
+; EG-NEXT: MULADD_IEEE * T2.W, -PV.W, T0.X, T0.Z,
+; EG-NEXT: 30(4.203895e-44), 0(0.000000e+00)
+; EG-NEXT: TRUNC T0.Z, T1.W,
+; EG-NEXT: SETGE T1.W, |PS|, |T0.X|,
+; EG-NEXT: OR_INT * T0.W, PV.W, 1,
+; EG-NEXT: CNDE T0.W, PV.W, 0.0, PS,
+; EG-NEXT: FLT_TO_INT * T1.W, PV.Z,
+; EG-NEXT: ADD_INT * T0.W, PS, PV.W,
; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT: ASHR T0.X, PV.W, literal.x,
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