[PATCH] D129890: [SDAG] narrow truncated sign_extend_inreg
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 16 06:33:55 PDT 2022
arsenm accepted this revision.
arsenm added inline comments.
This revision is now accepted and ready to land.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:13138
+ // trunc (sign_ext_inreg X, iM) to iN --> sign_ext_inreg (trunc X to iN), iM
+ if (!LegalTypes && N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
+ N0.hasOneUse()) {
----------------
Shouldn't really require legal types, but the DAG is lacking in adequate legality checks for sext_inreg
================
Comment at: llvm/test/CodeGen/AMDGPU/mul_int24.ll:184-186
+; SI-NEXT: v_mul_i32_i24_e32 v3, v0, v2
+; SI-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v2
+; SI-NEXT: v_mov_b32_e32 v0, v3
----------------
This is a pretty big improvement
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D129890/new/
https://reviews.llvm.org/D129890
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