[PATCH] D129727: [ARM64EC 11/?] Add support for lowering variadic indirect calls.

Sat Jul 16 05:41:27 PDT 2022

bcl5980 added inline comments.

================
Comment at: llvm/test/CodeGen/AArch64/arm64ec-cfg.ll:491-492
+; CHECK-NEXT:    sub sp, sp, #40
+; CHECK-NEXT:    sub x10, x29, #48
+; CHECK-NEXT:    sub x0, x29, #48
+; CHECK-NEXT:    mov x9, x25
----------------
efriedma wrote:
> bcl5980 wrote:
> > Can be TODO also.
> > `sub x0, x29, #48` rematerialize from copy x10
> > and `fmov d0, x10` can't rematerialize so `sub x10, x29, #48` remain.
> > How could we improve the reMaterializeTrivialDef to improve the code?
> Not sure how we're ending up with two separate operations in the first place; I'd normally expect SelectionDAG CSE to kick in.
It happen in the pass RegisterCoalescer, after the DAG CSE, even after machine CSE.
The machine IR is:

```
  %15:gpr64sp = ADDXri %stack.0, 0, 0
  $x0 = COPY %15:gpr64sp
  $d0 = COPY %15:gpr64sp
```
x0 can rematerialize to `ADDXri %stack.0, 0, 0`, but d0 can not.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129727/new/

https://reviews.llvm.org/D129727