[llvm] 2bb6b03 - Fix signed/unsigned mismatch

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Sat Jul 16 03:49:02 PDT 2022


Author: Simon Pilgrim
Date: 2022-07-16T11:48:41+01:00
New Revision: 2bb6b03d713ba91d2c1efdfbc06982598568a52c

URL: https://github.com/llvm/llvm-project/commit/2bb6b03d713ba91d2c1efdfbc06982598568a52c
DIFF: https://github.com/llvm/llvm-project/commit/2bb6b03d713ba91d2c1efdfbc06982598568a52c.diff

LOG: Fix signed/unsigned mismatch

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index ed1dc3e8b1db..13b22bf1796c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -22654,7 +22654,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
       if (M < 0)
         continue;
       ClearMask[I] = M == I ? I : (I + NumElts);
-      IsInLaneMask &= (M == I) || (M == (I + NumElts));
+      IsInLaneMask &= (M == I) || (M == (int)(I + NumElts));
       if (M != I) {
         APInt &Demanded = M < (int)NumElts ? DemandedLHS : DemandedRHS;
         Demanded.setBit(M % NumElts);


        


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