[PATCH] D129927: [MachineScheduler] Try to issue the load instruction preferentially
Allen zhong via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 16 01:54:51 PDT 2022
Allen created this revision.
Allen added reviewers: dmgreen, fhahn, nhaehnle, avieira.
Herald added subscribers: javed.absar, hiraditya, MatzeB.
Herald added a project: All.
Allen requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
Based on the discussion, it is preferable to hoist the loads as much as possible after register allocation.
https://discourse.llvm.org/t/insn-schedule-is-it-reasonable-to-issue-the-load-instruction-preferentially/63674
https://reviews.llvm.org/D129927
Files:
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64MachineScheduler.cpp
llvm/test/CodeGen/AArch64/aarch64-sched-load.ll
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