[PATCH] D129853: Reland "[SystemZ][z/OS] Fix f32 variadic argument assertion"
Mubariz Afzal via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 15 06:49:26 PDT 2022
mubarizafzal updated this revision to Diff 444966.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D129853/new/
https://reviews.llvm.org/D129853
Files:
llvm/lib/Target/SystemZ/SystemZCallingConv.td
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
Index: llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
===================================================================
--- llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
+++ llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
@@ -189,6 +189,28 @@
ret i64 %retval
}
+; CHECK-LABEL: call_vararg_float0
+; CHECK: lghi 1, 1
+; CHECK: llihf 2, 1073692672
+define i64 @call_vararg_float0() {
+entry:
+ %retval = call i64 (i64, ...) @pass_vararg2(i64 1, float 1.953125)
+ ret i64 %retval
+}
+
+; CHECK-LABEL: call_vararg_float1
+; CHECK: larl 1, @CPI17_0
+; CHECK: le 0, 0(1)
+; CHECK: llihf 0, 1073692672
+; CHECK: llihh 2, 16384
+; CHECK: llihh 3, 16392
+; CHECK: stg 0, 2200(4)
+define i64 @call_vararg_float1() {
+entry:
+ %retval = call i64 (float, ...) @pass_vararg4(float 1.0, float 2.0, float 3.0, float 1.953125)
+ ret i64 %retval
+}
+
; Derived from C source:
; #define _VARARG_EXT_
; #include <stdarg.h>
@@ -227,3 +249,4 @@
declare i64 @pass_vararg1(fp128 %arg0, ...)
declare i64 @pass_vararg2(i64 %arg0, ...)
declare i64 @pass_vararg3(...)
+declare i64 @pass_vararg4(float, ...)
Index: llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
===================================================================
--- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -1404,8 +1404,12 @@
return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
case CCValAssign::BCvt: {
assert(VA.getLocVT() == MVT::i64 || VA.getLocVT() == MVT::i128);
- assert(VA.getValVT().isVector() || VA.getValVT() == MVT::f64 ||
- VA.getValVT() == MVT::f128);
+ assert(VA.getValVT().isVector() || VA.getValVT() == MVT::f32 ||
+ VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::f128);
+ // For an f32 vararg we need to first promote it to an f64 and then
+ // bitcast it to an i64.
+ if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i64)
+ Value = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f64, Value);
MVT BitCastToType = VA.getValVT().isVector() && VA.getLocVT() == MVT::i64
? MVT::v2i64
: VA.getLocVT();
Index: llvm/lib/Target/SystemZ/SystemZCallingConv.td
===================================================================
--- llvm/lib/Target/SystemZ/SystemZCallingConv.td
+++ llvm/lib/Target/SystemZ/SystemZCallingConv.td
@@ -221,9 +221,10 @@
// XPLINK64 ABI compliant code widens integral types smaller than i64
// to i64 before placing the parameters either on the stack or in registers.
CCIfType<[i32], CCIfExtend<CCPromoteToType<i64>>>,
- // Promote f32 to f64 and bitcast to i64, if it needs to be passed in GPRS.
- CCIfType<[f32], CCIfNotFixed<CCPromoteToType<f64>>>,
- CCIfType<[f64], CCIfNotFixed<CCBitConvertToType<i64>>>,
+ // Promote f32 to f64 and bitcast to i64, if it needs to be passed in GPRs.
+ // Although we assign the f32 vararg to be bitcast, it will first be promoted
+ // to an f64 within convertValVTToLocVT().
+ CCIfType<[f32, f64], CCIfNotFixed<CCBitConvertToType<i64>>>,
// long double, can only be passed in GPR2 and GPR3, if available,
// hence R2Q
CCIfType<[f128], CCIfNotFixed<CCCustom<"CC_XPLINK64_Allocate128BitVararg">>>,
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