[PATCH] D128252: [AMDGPU] Lowering VGPR to SGPR copies to v_readfirstlane_b32 if profitable.

[Alexander via Phabricator via llvm-commits]

alex-t added a comment.

In D128252#3654433 <https://reviews.llvm.org/D128252#3654433>, @foad wrote:

> In D128252#3648385 <https://reviews.llvm.org/D128252#3648385>, @alex-t wrote:
>
>> In D128252#3644778 <https://reviews.llvm.org/D128252#3644778>, @foad wrote:
>>
>>> In future I would like VGPR-to-SGPR copies to be legal
>>
>> They are already legal.
>
> Currently `SIInstrInfo::copyPhysReg` does this:
>
>   if (RI.isSGPRClass(RC)) {
>     if (!RI.isSGPRClass(SrcRC)) {
>       reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
>       return;
>     }
>
> That is why I say they are illegal. I would like to change this, so that copyPhysReg will allow them and implement them by emitting readfirstlane.

OK.  You already can do this now. I have pointed you to the experimental branch on my github that propagates the DA information to MIR.
In this branch there is an assert if VGPR to SGPR copy defining instruction is uniform. I had to support a list of the exceptions for those instructions that a divergent but require SGPR operand. Not really a long list of them.
I passed through all the AMDGPU LIT tests w/o asserts.
For more information see https://github.com/alex-t/llvm-project/tree/dd_isel_exp: 850646bb02c204da602c7f4e654c7b65e59b6912
The branch is a pure draft for internal use. You may  be interested in the DA information propagated to MIR and the exception instruction list.

As for the -O0, the pass may be excluded as soon as I integrate part2 of this change that covers REG_SEQUENCE and PHIs


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128252/new/

https://reviews.llvm.org/D128252