[PATCH] D127392: [AggressiveInstCombine] Combine consecutive loads which are being merged to form a wider load.

[Biplob Mishra via Phabricator via llvm-commits]

bipmis added a comment.

In D127392#3653014 <https://reviews.llvm.org/D127392#3653014>, @spatel wrote:

> How does this code account for potential memory accesses between the loads that are getting combined?
>
>   define i16 @loadCombine_2consecutive_store_between(ptr %p) {
>     %p1 = getelementptr i8, ptr %p, i32 1
>     %l1 = load i8, ptr %p, align 2
>     store i8 42, ptr %p  ; this must happen after a combined load?
>     %l2 = load i8, ptr %p1
>   
>     %e1 = zext i8 %l1 to i16
>     %e2 = zext i8 %l2 to i16
>     %s2 = shl i16 %e2, 8
>     %o1 = or i16 %e1, %s2
>     ret i16 %o1
>   }

I should have mentioned. This being the base version have not enabled the same. Just targeting simple load scenarios in this patch. This was enabled in the the InstCombine patch.  The same will be enabled in the subsequent patches to handle memory access b/w loads.


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https://reviews.llvm.org/D127392