[llvm] ae15e6a - [LV] Pre-commit test case for D128523, NFC

[Mel Chen via llvm-commits]

Author: Mel Chen
Date: 2022-07-15T01:22:06-07:00
New Revision: ae15e6a952e88fe7c589f7206b392052e52dfa32

URL: https://github.com/llvm/llvm-project/commit/ae15e6a952e88fe7c589f7206b392052e52dfa32
DIFF: https://github.com/llvm/llvm-project/commit/ae15e6a952e88fe7c589f7206b392052e52dfa32.diff

LOG: [LV] Pre-commit test case for D128523, NFC

Added: 
    llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll b/llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
new file mode 100644
index 0000000000000..1c470a3d7ebbc
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll
@@ -0,0 +1,31 @@
+; REQUIRES: asserts
+; RUN: opt < %s -loop-vectorize -mtriple riscv64 -riscv-v-vector-bits-min=128 -mattr="+v" -debug-only=loop-vectorize -S 2>&1 | FileCheck %s
+
+; CHECK: LV: Loop hints: force=enabled
+; CHECK: LV: Scalar loop costs: 7.
+; CHECK: LV: Vector loop of width 2 costs: 4.
+; CHECK: LV: Vectorization seems to be not beneficial, but was forced by a user.
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+target triple = "riscv64-unknown-unknown"
+
+define i64 @foo(ptr nocapture noundef readonly %a, i64 noundef %N, i64 noundef %init) {
+entry:
+  br label %for.body
+
+for.body:                                         ; preds = %entry, %for.body
+  %i.06 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
+  %rd.05 = phi i64 [ %add, %for.body ], [ %init, %entry ]
+  %arrayidx = getelementptr inbounds i64, ptr %a, i64 %i.06
+  %0 = load i64, ptr %arrayidx, align 8
+  %add = add nsw i64 %0, %rd.05
+  %inc = add nuw i64 %i.06, 1
+  %exitcond.not = icmp eq i64 %inc, %N
+  br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
+
+for.end:                                          ; preds = %for.body
+  ret i64 %add
+}
+
+!0 = !{!0, !1}
+!1 = !{!"llvm.loop.vectorize.enable", i1 true}