[PATCH] D129715: [LoongArch] Heuristically load FP immediates by movgr2fr from materialized integer

Thu Jul 14 20:22:56 PDT 2022

xen0n added a comment.

In D129715#3653900 <https://reviews.llvm.org/D129715#3653900>, @gonglingqin wrote:

> In D129715#3653892 <https://reviews.llvm.org/D129715#3653892>, @xen0n wrote:
>
>> I don't know if you did the experiments thoroughly and found out 2 is the optimal threshold (on SPEC2006), or if it was just an arbitrary choice ("拍脑袋").
>>
>> You could mention how the threshold was chosen, in case it is indeed arbitrary but others wrongly assume it's something related to micro-architecture details, or empirically verified.
>
> I used 3A5000 on llvm13 to test materialized integer within 1,2 and 4 instructions.the results show that the performance is the best when using no more than 2 instructions. Maybe we should test the situation materialized integer within 3 instructions.

Could be better to find some time to upgrade your benchmarking environment for testing the actual main branch. ;-)

Regarding the actual benchmarks, yes I think testing the 3-instruction case could be useful. But again, it may not make a significant difference, since the IEEE-754 biased exponent is occupying the highest 12 bits (except the sign bit), all f64's with top 12 bits zeroed are denormals. And numbers whose binary representation have big "holes" of all-0s or 1s for their two "middle"  20-bit segments or lowest 12 bits are probably not commonly used in the wild, let alone being used as immediates. You could try benchmarking of course, but I doubt the result would be much different from the 2-insn case.

(The 4-insn case is useless and equivalent to unconditionally loading via integer immediates, because all 64-bit values can be loaded in 4 insns (`lu12i.w + ori + lu32i.d + lu52i.d`) in LA64, and in LA32 you need two pairs of materialization and GPR-FPR moves for the higher and lower 32 bits anyway.)

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