[llvm] 190518d - [X86] Use generic tuning for "x86-64" if "tune-cpu" is not specified
Phoebe Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 14 19:05:18 PDT 2022
Author: Phoebe Wang
Date: 2022-07-15T10:05:08+08:00
New Revision: 190518da4b6b3f4cfb4081b7e110d8a3b9080cc5
URL: https://github.com/llvm/llvm-project/commit/190518da4b6b3f4cfb4081b7e110d8a3b9080cc5
DIFF: https://github.com/llvm/llvm-project/commit/190518da4b6b3f4cfb4081b7e110d8a3b9080cc5.diff
LOG: [X86] Use generic tuning for "x86-64" if "tune-cpu" is not specified
This is an alternative to D129154. See discussions on https://discourse.llvm.org/t/fast-scalar-fsqrt-tuning-in-x86/63605
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D129647
Added:
llvm/test/CodeGen/X86/sqrt-fastmath-tunecpu-attr.ll
Modified:
llvm/lib/Target/X86/X86.td
llvm/lib/Target/X86/X86TargetMachine.cpp
llvm/test/CodeGen/X86/pow.ll
llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
llvm/test/CodeGen/X86/sqrt-fastmath.ll
llvm/test/CodeGen/X86/x86-cmov-converter.ll
llvm/test/DebugInfo/COFF/register-variables.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index a859176220c7c..fa0a6bd415dc0 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1277,7 +1277,7 @@ class ProcModel<string Name, SchedMachineModel Model,
// enabled. It has no effect on code generation.
// NOTE: As a default tuning, "generic" aims to produce code optimized for the
// most common X86 processors. The tunings might be changed over time. It is
-// recommended to use "x86-64" in lit tests for consistency.
+// recommended to use "tune-cpu"="x86-64" in function attribute for consistency.
def : ProcModel<"generic", SandyBridgeModel,
[FeatureX87, FeatureCX8, FeatureX86_64],
[TuningSlow3OpsLEA,
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index f4e25e4194db1..1de2a17259543 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -254,8 +254,12 @@ X86TargetMachine::getSubtargetImpl(const Function &F) const {
StringRef CPU =
CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
- StringRef TuneCPU =
- TuneAttr.isValid() ? TuneAttr.getValueAsString() : (StringRef)CPU;
+ // "x86-64" is a default target setting for many front ends. In these cases,
+ // they actually request for "generic" tuning unless the "tune-cpu" was
+ // specified.
+ StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString()
+ : CPU == "x86-64" ? "generic"
+ : (StringRef)CPU;
StringRef FS =
FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
diff --git a/llvm/test/CodeGen/X86/pow.ll b/llvm/test/CodeGen/X86/pow.ll
index 91c04be18c2b2..fc1593005debc 100644
--- a/llvm/test/CodeGen/X86/pow.ll
+++ b/llvm/test/CodeGen/X86/pow.ll
@@ -12,32 +12,8 @@ declare x86_fp80 @llvm.pow.f80(x86_fp80, x86_fp80)
define float @pow_f32_one_fourth_fmf_ieee(float %x) nounwind {
; CHECK-LABEL: pow_f32_one_fourth_fmf_ieee:
; CHECK: # %bb.0:
-; CHECK-NEXT: rsqrtss %xmm0, %xmm1
-; CHECK-NEXT: movaps %xmm0, %xmm3
-; CHECK-NEXT: mulss %xmm1, %xmm3
-; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; CHECK-NEXT: movaps %xmm3, %xmm4
-; CHECK-NEXT: mulss %xmm2, %xmm4
-; CHECK-NEXT: mulss %xmm1, %xmm3
-; CHECK-NEXT: movss {{.*#+}} xmm5 = mem[0],zero,zero,zero
-; CHECK-NEXT: addss %xmm5, %xmm3
-; CHECK-NEXT: mulss %xmm4, %xmm3
-; CHECK-NEXT: movaps {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
-; CHECK-NEXT: andps %xmm1, %xmm0
-; CHECK-NEXT: movss {{.*#+}} xmm4 = mem[0],zero,zero,zero
-; CHECK-NEXT: cmpltss %xmm4, %xmm0
-; CHECK-NEXT: andnps %xmm3, %xmm0
-; CHECK-NEXT: xorps %xmm3, %xmm3
-; CHECK-NEXT: rsqrtss %xmm0, %xmm3
-; CHECK-NEXT: andps %xmm0, %xmm1
-; CHECK-NEXT: mulss %xmm3, %xmm0
-; CHECK-NEXT: mulss %xmm0, %xmm2
-; CHECK-NEXT: mulss %xmm3, %xmm0
-; CHECK-NEXT: addss %xmm5, %xmm0
-; CHECK-NEXT: mulss %xmm2, %xmm0
-; CHECK-NEXT: cmpltss %xmm4, %xmm1
-; CHECK-NEXT: andnps %xmm0, %xmm1
-; CHECK-NEXT: movaps %xmm1, %xmm0
+; CHECK-NEXT: sqrtss %xmm0, %xmm0
+; CHECK-NEXT: sqrtss %xmm0, %xmm0
; CHECK-NEXT: retq
%r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01)
ret float %r
@@ -46,29 +22,8 @@ define float @pow_f32_one_fourth_fmf_ieee(float %x) nounwind {
define float @pow_f32_one_fourth_fmf_daz(float %x) #0 {
; CHECK-LABEL: pow_f32_one_fourth_fmf_daz:
; CHECK: # %bb.0:
-; CHECK-NEXT: rsqrtss %xmm0, %xmm1
-; CHECK-NEXT: movaps %xmm0, %xmm2
-; CHECK-NEXT: mulss %xmm1, %xmm2
-; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; CHECK-NEXT: movaps %xmm2, %xmm4
-; CHECK-NEXT: mulss %xmm3, %xmm4
-; CHECK-NEXT: mulss %xmm1, %xmm2
-; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; CHECK-NEXT: addss %xmm1, %xmm2
-; CHECK-NEXT: mulss %xmm4, %xmm2
-; CHECK-NEXT: xorps %xmm4, %xmm4
-; CHECK-NEXT: cmpeqss %xmm4, %xmm0
-; CHECK-NEXT: andnps %xmm2, %xmm0
-; CHECK-NEXT: xorps %xmm2, %xmm2
-; CHECK-NEXT: rsqrtss %xmm0, %xmm2
-; CHECK-NEXT: movaps %xmm0, %xmm5
-; CHECK-NEXT: mulss %xmm2, %xmm5
-; CHECK-NEXT: mulss %xmm5, %xmm3
-; CHECK-NEXT: mulss %xmm2, %xmm5
-; CHECK-NEXT: addss %xmm1, %xmm5
-; CHECK-NEXT: mulss %xmm3, %xmm5
-; CHECK-NEXT: cmpeqss %xmm4, %xmm0
-; CHECK-NEXT: andnps %xmm5, %xmm0
+; CHECK-NEXT: sqrtss %xmm0, %xmm0
+; CHECK-NEXT: sqrtss %xmm0, %xmm0
; CHECK-NEXT: retq
%r = call nsz ninf afn float @llvm.pow.f32(float %x, float 2.5e-01)
ret float %r
diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
index 07edf9c4117ea..73021fab9505c 100644
--- a/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
+++ b/llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll
@@ -5,6 +5,7 @@
; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=FAST-SCALAR,FAST-VECTOR
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=X86-64
define float @f32_no_daz(float %f) #0 {
; NHM-LABEL: f32_no_daz:
@@ -26,6 +27,11 @@ define float @f32_no_daz(float %f) #0 {
; FAST-SCALAR: # %bb.0:
; FAST-SCALAR-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
; FAST-SCALAR-NEXT: retq
+;
+; X86-64-LABEL: f32_no_daz:
+; X86-64: # %bb.0:
+; X86-64-NEXT: sqrtss %xmm0, %xmm0
+; X86-64-NEXT: retq
%call = tail call fast float @llvm.sqrt.f32(float %f) #2
ret float %call
}
@@ -82,6 +88,23 @@ define <4 x float> @v4f32_no_daz(<4 x float> %f) #0 {
; FAST-VECTOR: # %bb.0:
; FAST-VECTOR-NEXT: vsqrtps %xmm0, %xmm0
; FAST-VECTOR-NEXT: retq
+;
+; X86-64-LABEL: v4f32_no_daz:
+; X86-64: # %bb.0:
+; X86-64-NEXT: rsqrtps %xmm0, %xmm1
+; X86-64-NEXT: movaps %xmm0, %xmm2
+; X86-64-NEXT: mulps %xmm1, %xmm2
+; X86-64-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
+; X86-64-NEXT: mulps %xmm2, %xmm3
+; X86-64-NEXT: mulps %xmm1, %xmm2
+; X86-64-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; X86-64-NEXT: mulps %xmm3, %xmm2
+; X86-64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; X86-64-NEXT: movaps {{.*#+}} xmm1 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
+; X86-64-NEXT: cmpleps %xmm0, %xmm1
+; X86-64-NEXT: andps %xmm2, %xmm1
+; X86-64-NEXT: movaps %xmm1, %xmm0
+; X86-64-NEXT: retq
%call = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %f) #2
ret <4 x float> %call
}
@@ -153,6 +176,38 @@ define <8 x float> @v8f32_no_daz(<8 x float> %f) #0 {
; FAST-VECTOR: # %bb.0:
; FAST-VECTOR-NEXT: vsqrtps %ymm0, %ymm0
; FAST-VECTOR-NEXT: retq
+;
+; X86-64-LABEL: v8f32_no_daz:
+; X86-64: # %bb.0:
+; X86-64-NEXT: rsqrtps %xmm0, %xmm2
+; X86-64-NEXT: movaps %xmm0, %xmm4
+; X86-64-NEXT: mulps %xmm2, %xmm4
+; X86-64-NEXT: movaps {{.*#+}} xmm5 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
+; X86-64-NEXT: movaps %xmm4, %xmm3
+; X86-64-NEXT: mulps %xmm5, %xmm3
+; X86-64-NEXT: mulps %xmm2, %xmm4
+; X86-64-NEXT: movaps {{.*#+}} xmm6 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
+; X86-64-NEXT: addps %xmm6, %xmm4
+; X86-64-NEXT: mulps %xmm3, %xmm4
+; X86-64-NEXT: movaps {{.*#+}} xmm7 = [NaN,NaN,NaN,NaN]
+; X86-64-NEXT: andps %xmm7, %xmm0
+; X86-64-NEXT: movaps {{.*#+}} xmm2 = [1.17549435E-38,1.17549435E-38,1.17549435E-38,1.17549435E-38]
+; X86-64-NEXT: movaps %xmm2, %xmm3
+; X86-64-NEXT: cmpleps %xmm0, %xmm3
+; X86-64-NEXT: andps %xmm4, %xmm3
+; X86-64-NEXT: rsqrtps %xmm1, %xmm0
+; X86-64-NEXT: movaps %xmm1, %xmm4
+; X86-64-NEXT: mulps %xmm0, %xmm4
+; X86-64-NEXT: mulps %xmm4, %xmm5
+; X86-64-NEXT: mulps %xmm0, %xmm4
+; X86-64-NEXT: addps %xmm6, %xmm4
+; X86-64-NEXT: mulps %xmm5, %xmm4
+; X86-64-NEXT: andps %xmm7, %xmm1
+; X86-64-NEXT: cmpleps %xmm1, %xmm2
+; X86-64-NEXT: andps %xmm4, %xmm2
+; X86-64-NEXT: movaps %xmm3, %xmm0
+; X86-64-NEXT: movaps %xmm2, %xmm1
+; X86-64-NEXT: retq
%call = tail call fast <8 x float> @llvm.sqrt.v8f32(<8 x float> %f) #2
ret <8 x float> %call
}
@@ -179,6 +234,11 @@ define float @f32_daz(float %f) #1 {
; FAST-SCALAR: # %bb.0:
; FAST-SCALAR-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
; FAST-SCALAR-NEXT: retq
+;
+; X86-64-LABEL: f32_daz:
+; X86-64: # %bb.0:
+; X86-64-NEXT: sqrtss %xmm0, %xmm0
+; X86-64-NEXT: retq
%call = tail call fast float @llvm.sqrt.f32(float %f) #2
ret float %call
}
@@ -230,6 +290,21 @@ define <4 x float> @v4f32_daz(<4 x float> %f) #1 {
; FAST-VECTOR: # %bb.0:
; FAST-VECTOR-NEXT: vsqrtps %xmm0, %xmm0
; FAST-VECTOR-NEXT: retq
+;
+; X86-64-LABEL: v4f32_daz:
+; X86-64: # %bb.0:
+; X86-64-NEXT: rsqrtps %xmm0, %xmm1
+; X86-64-NEXT: movaps %xmm0, %xmm2
+; X86-64-NEXT: mulps %xmm1, %xmm2
+; X86-64-NEXT: movaps {{.*#+}} xmm3 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
+; X86-64-NEXT: mulps %xmm2, %xmm3
+; X86-64-NEXT: mulps %xmm1, %xmm2
+; X86-64-NEXT: addps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; X86-64-NEXT: mulps %xmm3, %xmm2
+; X86-64-NEXT: xorps %xmm1, %xmm1
+; X86-64-NEXT: cmpneqps %xmm1, %xmm0
+; X86-64-NEXT: andps %xmm2, %xmm0
+; X86-64-NEXT: retq
%call = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %f) #2
ret <4 x float> %call
}
@@ -292,6 +367,32 @@ define <8 x float> @v8f32_daz(<8 x float> %f) #1 {
; FAST-VECTOR: # %bb.0:
; FAST-VECTOR-NEXT: vsqrtps %ymm0, %ymm0
; FAST-VECTOR-NEXT: retq
+;
+; X86-64-LABEL: v8f32_daz:
+; X86-64: # %bb.0:
+; X86-64-NEXT: rsqrtps %xmm0, %xmm2
+; X86-64-NEXT: movaps %xmm0, %xmm3
+; X86-64-NEXT: mulps %xmm2, %xmm3
+; X86-64-NEXT: movaps {{.*#+}} xmm4 = [-5.0E-1,-5.0E-1,-5.0E-1,-5.0E-1]
+; X86-64-NEXT: movaps %xmm3, %xmm5
+; X86-64-NEXT: mulps %xmm4, %xmm5
+; X86-64-NEXT: mulps %xmm2, %xmm3
+; X86-64-NEXT: movaps {{.*#+}} xmm2 = [-3.0E+0,-3.0E+0,-3.0E+0,-3.0E+0]
+; X86-64-NEXT: addps %xmm2, %xmm3
+; X86-64-NEXT: mulps %xmm5, %xmm3
+; X86-64-NEXT: xorps %xmm5, %xmm5
+; X86-64-NEXT: cmpneqps %xmm5, %xmm0
+; X86-64-NEXT: andps %xmm3, %xmm0
+; X86-64-NEXT: rsqrtps %xmm1, %xmm3
+; X86-64-NEXT: movaps %xmm1, %xmm6
+; X86-64-NEXT: mulps %xmm3, %xmm6
+; X86-64-NEXT: mulps %xmm6, %xmm4
+; X86-64-NEXT: mulps %xmm3, %xmm6
+; X86-64-NEXT: addps %xmm2, %xmm6
+; X86-64-NEXT: mulps %xmm4, %xmm6
+; X86-64-NEXT: cmpneqps %xmm5, %xmm1
+; X86-64-NEXT: andps %xmm6, %xmm1
+; X86-64-NEXT: retq
%call = tail call fast <8 x float> @llvm.sqrt.v8f32(<8 x float> %f) #2
ret <8 x float> %call
}
diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath-tunecpu-attr.ll b/llvm/test/CodeGen/X86/sqrt-fastmath-tunecpu-attr.ll
new file mode 100644
index 0000000000000..99b45f83ac909
--- /dev/null
+++ b/llvm/test/CodeGen/X86/sqrt-fastmath-tunecpu-attr.ll
@@ -0,0 +1,85 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
+
+define float @f32_tune_nhm(float %f) #0 {
+; CHECK-LABEL: f32_tune_nhm:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rsqrtss %xmm0, %xmm1
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: mulss %xmm1, %xmm2
+; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; CHECK-NEXT: mulss %xmm2, %xmm3
+; CHECK-NEXT: mulss %xmm1, %xmm2
+; CHECK-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; CHECK-NEXT: mulss %xmm3, %xmm2
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: andnps %xmm2, %xmm0
+; CHECK-NEXT: retq
+ %call = tail call fast float @llvm.sqrt.f32(float %f)
+ ret float %call
+}
+
+define float @f32_no_tune(float %f) #1 {
+; CHECK-LABEL: f32_no_tune:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sqrtss %xmm0, %xmm0
+; CHECK-NEXT: retq
+ %call = tail call fast float @llvm.sqrt.f32(float %f)
+ ret float %call
+}
+
+define float @f32_tune_generic(float %f) #2 {
+; CHECK-LABEL: f32_tune_generic:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sqrtss %xmm0, %xmm0
+; CHECK-NEXT: retq
+ %call = tail call fast float @llvm.sqrt.f32(float %f)
+ ret float %call
+}
+
+define float @f32_tune_x86_64(float %f) #3 {
+; CHECK-LABEL: f32_tune_x86_64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: rsqrtss %xmm0, %xmm1
+; CHECK-NEXT: movaps %xmm0, %xmm2
+; CHECK-NEXT: mulss %xmm1, %xmm2
+; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; CHECK-NEXT: mulss %xmm2, %xmm3
+; CHECK-NEXT: mulss %xmm1, %xmm2
+; CHECK-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; CHECK-NEXT: mulss %xmm3, %xmm2
+; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: andnps %xmm2, %xmm0
+; CHECK-NEXT: retq
+ %call = tail call fast float @llvm.sqrt.f32(float %f)
+ ret float %call
+}
+
+define float @f32_tune_snb(float %f) #4 {
+; CHECK-LABEL: f32_tune_snb:
+; CHECK: # %bb.0:
+; CHECK-NEXT: sqrtss %xmm0, %xmm0
+; CHECK-NEXT: retq
+ %call = tail call fast float @llvm.sqrt.f32(float %f)
+ ret float %call
+}
+
+define float @f32_target_snb_tune_snb(float %f) #5 {
+; CHECK-LABEL: f32_target_snb_tune_snb:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
+; CHECK-NEXT: retq
+ %call = tail call fast float @llvm.sqrt.f32(float %f)
+ ret float %call
+}
+
+declare float @llvm.sqrt.f32(float)
+
+attributes #0 = { "target-cpu"="x86-64" "tune-cpu"="nehalem" }
+attributes #1 = { "target-cpu"="x86-64" }
+attributes #2 = { "target-cpu"="x86-64" "tune-cpu"="generic" }
+attributes #3 = { "target-cpu"="x86-64" "tune-cpu"="x86-64" }
+attributes #4 = { "target-cpu"="x86-64" "tune-cpu"="sandybridge" }
+attributes #5 = { "target-cpu"="sandybridge" "tune-cpu"="sandybridge" }
diff --git a/llvm/test/CodeGen/X86/sqrt-fastmath.ll b/llvm/test/CodeGen/X86/sqrt-fastmath.ll
index 2cbcd44fc08cc..e0c903d96f5c8 100644
--- a/llvm/test/CodeGen/X86/sqrt-fastmath.ll
+++ b/llvm/test/CodeGen/X86/sqrt-fastmath.ll
@@ -78,45 +78,13 @@ define float @finite_f32_estimate_ieee(float %f) #1 {
define float @finite_f32_estimate_ieee_ninf(float %f) #1 {
; SSE-LABEL: finite_f32_estimate_ieee_ninf:
; SSE: # %bb.0:
-; SSE-NEXT: rsqrtss %xmm0, %xmm1
-; SSE-NEXT: movaps %xmm0, %xmm2
-; SSE-NEXT: mulss %xmm1, %xmm2
-; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; SSE-NEXT: mulss %xmm2, %xmm3
-; SSE-NEXT: mulss %xmm1, %xmm2
-; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT: mulss %xmm3, %xmm2
-; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: andnps %xmm2, %xmm0
+; SSE-NEXT: sqrtss %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX1-LABEL: finite_f32_estimate_ieee_ninf:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm2
-; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: retq
-;
-; AVX512-LABEL: finite_f32_estimate_ieee_ninf:
-; AVX512: # %bb.0:
-; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
-; AVX512-NEXT: vandps %xmm2, %xmm0, %xmm2
-; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm0 * xmm1) + mem
-; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512-NEXT: vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %k1
-; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
-; AVX512-NEXT: retq
+; AVX-LABEL: finite_f32_estimate_ieee_ninf:
+; AVX: # %bb.0:
+; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT: retq
%call = tail call ninf afn float @__sqrtf_finite(float %f) #2
ret float %call
}
@@ -138,44 +106,13 @@ define float @finite_f32_estimate_daz(float %f) #4 {
define float @finite_f32_estimate_daz_ninf(float %f) #4 {
; SSE-LABEL: finite_f32_estimate_daz_ninf:
; SSE: # %bb.0:
-; SSE-NEXT: rsqrtss %xmm0, %xmm1
-; SSE-NEXT: movaps %xmm0, %xmm2
-; SSE-NEXT: mulss %xmm1, %xmm2
-; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; SSE-NEXT: mulss %xmm2, %xmm3
-; SSE-NEXT: mulss %xmm1, %xmm2
-; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT: mulss %xmm3, %xmm2
-; SSE-NEXT: xorps %xmm1, %xmm1
-; SSE-NEXT: cmpeqss %xmm1, %xmm0
-; SSE-NEXT: andnps %xmm2, %xmm0
+; SSE-NEXT: sqrtss %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX1-LABEL: finite_f32_estimate_daz_ninf:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm2
-; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2
-; AVX1-NEXT: vcmpeqss %xmm2, %xmm0, %xmm0
-; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: retq
-;
-; AVX512-LABEL: finite_f32_estimate_daz_ninf:
-; AVX512: # %bb.0:
-; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm2
-; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
-; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX512-NEXT: vmulss %xmm1, %xmm2, %xmm1
-; AVX512-NEXT: vxorps %xmm2, %xmm2, %xmm2
-; AVX512-NEXT: vcmpeqss %xmm2, %xmm0, %k1
-; AVX512-NEXT: vmovss %xmm2, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT: vmovaps %xmm1, %xmm0
-; AVX512-NEXT: retq
+; AVX-LABEL: finite_f32_estimate_daz_ninf:
+; AVX: # %bb.0:
+; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT: retq
%call = tail call ninf afn float @__sqrtf_finite(float %f) #2
ret float %call
}
@@ -221,45 +158,13 @@ define float @sqrtf_check_denorms(float %x) #3 {
define float @sqrtf_check_denorms_ninf(float %x) #3 {
; SSE-LABEL: sqrtf_check_denorms_ninf:
; SSE: # %bb.0:
-; SSE-NEXT: rsqrtss %xmm0, %xmm1
-; SSE-NEXT: movaps %xmm0, %xmm2
-; SSE-NEXT: mulss %xmm1, %xmm2
-; SSE-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
-; SSE-NEXT: mulss %xmm2, %xmm3
-; SSE-NEXT: mulss %xmm1, %xmm2
-; SSE-NEXT: addss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
-; SSE-NEXT: mulss %xmm3, %xmm2
-; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: andnps %xmm2, %xmm0
+; SSE-NEXT: sqrtss %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX1-LABEL: sqrtf_check_denorms_ninf:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm2
-; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
-; AVX1-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT: vmulss %xmm1, %xmm2, %xmm1
-; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: retq
-;
-; AVX512-LABEL: sqrtf_check_denorms_ninf:
-; AVX512: # %bb.0:
-; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX512-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
-; AVX512-NEXT: vandps %xmm2, %xmm0, %xmm2
-; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vfmadd213ss {{.*#+}} xmm1 = (xmm0 * xmm1) + mem
-; AVX512-NEXT: vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX512-NEXT: vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %k1
-; AVX512-NEXT: vmulss %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
-; AVX512-NEXT: retq
+; AVX-LABEL: sqrtf_check_denorms_ninf:
+; AVX: # %bb.0:
+; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT: retq
%call = tail call ninf afn float @__sqrtf_finite(float %x) #2
ret float %call
}
@@ -385,32 +290,13 @@ define float @f32_estimate(float %x) #1 {
define float @f32_estimate2(float %x) #5 {
; SSE-LABEL: f32_estimate2:
; SSE: # %bb.0:
-; SSE-NEXT: rsqrtss %xmm0, %xmm1
-; SSE-NEXT: mulss %xmm0, %xmm1
-; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: cmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: andnps %xmm1, %xmm0
+; SSE-NEXT: sqrtss %xmm0, %xmm0
; SSE-NEXT: retq
;
-; AVX1-LABEL: f32_estimate2:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
-; AVX1-NEXT: vmulss %xmm1, %xmm0, %xmm1
-; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT: retq
-;
-; AVX512-LABEL: f32_estimate2:
-; AVX512: # %bb.0:
-; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
-; AVX512-NEXT: vrsqrtss %xmm0, %xmm0, %xmm2
-; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm1
-; AVX512-NEXT: vcmpltss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %k1
-; AVX512-NEXT: vmulss %xmm2, %xmm0, %xmm0
-; AVX512-NEXT: vxorps %xmm1, %xmm1, %xmm1
-; AVX512-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
-; AVX512-NEXT: retq
+; AVX-LABEL: f32_estimate2:
+; AVX: # %bb.0:
+; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
+; AVX-NEXT: retq
%sqrt = tail call fast float @llvm.sqrt.f32(float %x)
ret float %sqrt
}
diff --git a/llvm/test/CodeGen/X86/x86-cmov-converter.ll b/llvm/test/CodeGen/X86/x86-cmov-converter.ll
index 03ae6fa698aef..0194c1aecc558 100644
--- a/llvm/test/CodeGen/X86/x86-cmov-converter.ll
+++ b/llvm/test/CodeGen/X86/x86-cmov-converter.ll
@@ -1057,5 +1057,5 @@ exit:
ret void
}
-attributes #0 = {"target-cpu"="x86-64"}
+attributes #0 = {"target-cpu"="x86-64" "tune-cpu"="x86-64"}
!0 = !{}
diff --git a/llvm/test/DebugInfo/COFF/register-variables.ll b/llvm/test/DebugInfo/COFF/register-variables.ll
index 62f5f5ef05844..6ac9a1cd6a9d2 100644
--- a/llvm/test/DebugInfo/COFF/register-variables.ll
+++ b/llvm/test/DebugInfo/COFF/register-variables.ll
@@ -209,7 +209,7 @@ declare void @putint(i32) #1
; Function Attrs: nounwind readnone
declare void @llvm.dbg.value(metadata, metadata, metadata) #2
-attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "tune-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind readnone }
attributes #3 = { nounwind }
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